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ADC11L066
11-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with
Internal Sample-and-Hold
General Description
Features
The ADC11L066 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 11-bit
digital words at 66 Megasamples per second (MSPS), minimum, with typical operation possible up to 80 MSPS. This
converter uses a differential, pipeline architecture with digital
error correction and an on-chip sample-and-hold circuit to
minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold
stage yields a full-power bandwidth of 450 MHz. Operating on
a single 3.3V power supply, this device consumes just
357 mW at 66 MSPS, including the reference current. The
Power Down feature reduces power consumption to just
50 mW.
The differential inputs provide a full scale input swing equal
to ±VREF with the possibility of a single-ended input. Full use
of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance, singleended reference input is converted on-chip to a differential
reference for use by the processing circuitry. Output data format is 11-bit offset binary.
This device is available in the 32-lead LQFP package and will
operate over the industrial temperature range of −40°C to
+85°C.
■
■
■
■
Single supply operation
Low power consumption
Power down mode
On-chip reference buffer
Key Specifications
■
■
■
■
■
■
■
■
■
■
Resolution
Conversion Rate
Full Power Bandwidth
DNL
INL
SNR (fIN = 10 MHz)
SFDR (fIN = 10 MHz)
Data Latency
Supply Voltage
Power Consumption, 66 MHz
11 Bits
66 MSPS
450 MHz
±0.2 LSB (typ)
±0.5 LSB (typ)
65 dB (typ)
78 dB (typ)
6 Clock Cycles
+3.3V ±300 mV
357 mW (typ)
Applications
■
■
■
■
■
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■
Ultrasound and Imaging
Instrumentation
Cellular Base Stations/Communications Receivers
Sonar/Radar
Wireless Local Loops
Data Acquisition Systems
DSP Front Ends
Connection Diagram
20050701
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation
200507
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ADC11L066 11-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold
May 13, 2009
ADC11L066
Ordering Information
Industrial (−40°C ≤ TA ≤ +85°C)
Package
ADC11L066CIVY
32 Pin LQFP
ADC11L066CIVYX
32 Pin LQFP Tape and Reel
Block Diagram
20050702
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2
ADC11L066
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
2
VIN+
3
VIN−
1
VREF
31
VRP
32
VRM
30
Analog signal Input pins. With a 1.0V reference voltage the
differential input signal level is 2.0 VP-P. The VIN- pin may be
connected to VCM for single-ended operation, but a differential input
signal is required for best performance.
Reference input. This pin should be bypassed to AGND with a 0.1
µF monolithic capacitor. VREF is 1.0V nominal and should be
between 0.8V and 1.5V.
These pins are high impedance reference bypass pins only.
Connect a 0.1 µF capacitor from each of these pins to AGND. DO
NOT connect anything else to these pins.
VRN
DIGITAL I/O
10
CLK
Digital clock input. The range of frequencies for this input is
10 MHz to 80 MHz (typical) with guaranteed performance at 66
MHz. The input is sampled on the rising edge of this input.
11
OE
OE is the output enable pin that, when low, enables the TRISTATE® data output pins. When this pin is high, the outputs are in
a high impedance state.
8
PD is the Power Down input pin. When high, this input puts the
converter into the power down mode. When this pin is low, the
converter is in the active mode.
PD
3
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ADC11L066
Pin No.
Symbol
Equivalent Circuit
Description
15–19, 22–
27
D0–D10
Digital data output pins that make up the 11-bit conversion results.
D0 is the LSB, while D10 is the MSB of the offset binary output
word.
5, 6, 29
VA
Positive analog supply pins. These pins should be connected to a
quiet +3.3V source and bypassed to AGND with 0.1 µF monolithic
capacitors located within 1 cm of these power pins, and with a 10
µF capacitor.
4, 7, 28
AGND
ANALOG POWER
The ground return for the analog supply.
DIGITAL POWER
13
VD
9, 12
DGND
21
20
Positive digital supply pin. This pin should be connected to the
same quiet +3.3V source as is VA and bypassed to DGND with a
0.1 µF monolithic capacitor in parallel with a 10 µF capacitor, both
located within 1 cm of the power pin.
The ground return for the digital supply.
VDR
Positive digital supply pin for the ADC11L066's output drivers. This
pin should be connected to a voltage source of +1.8V to VD and
bypassed to DR GND with a 0.1 µF monolithic capacitor. If the
supply for this pin is different from the supply used for VA and VD,
it should also be bypassed with a 10 µF tantalum capacitor. The
voltage at this pin should never exceed the voltage on VD by more
than 300 mV. All bypass capacitors should be located within 1 cm
of the supply pin.
DR GND
The ground return for the digital supply for the ADC11L066's output
drivers. This pin should be connected to the system digital ground,
but not be connected in close proximity to the ADC11L066's DGND
or AGND pins. See Section 5.0 (Layout and Grounding) for more
details.
TEST
This pin is internally tied to DGND. It may be connected to DGND,
or left floating.
OTHER
14
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4
Operating Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Temperature
VA, VD, VDR
|VA–VD|
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at TA = 25°C
ESD Susceptibility
Human Body Model (Note 5)
Machine Model (Note 5)
Soldering Temperature,
Infrared, 10 sec. (Note 6)
Storage Temperature
−40°C ≤ TA ≤ +85°C
+3.0V to +3.60V
+1.8V to VD
0.8V to 1.5V
−0.05V to (VD + 0.05V)
−0V to (VA − 0.5V)
0.5V to (VA - 1.5V)
Supply Voltage (VA, VD)
Output Driver Supply (VDR)
VREF Input
CLK, PD, OE
VIN Input
VCM
|AGND–DGND|
4.2V
Voltage on Any Pin
(Notes 1, 2)
≤ 100 mV
−0.3V to VA or VD
+0.3V
±25 mA
±50 mA
See (Note 4)
≤100 mV
2500V
250V
235°C
−65°C to +150°C
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V,
VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin.
Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (Notes 7, 8, 9, 10)
Symbol
Parameter
Typical
(Note 10)
Conditions
Limits
(Note 10)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
INL
Integral Non Linearity (Note 11)
DNL
Differential Non Linearity
±0.5
±0.2
Positive Error
GE
−0.5
Gain Error
Negative Error
−0.2
Offset Error (VIN+ = VIN−(
11
Bits
1.8
LSB (max)
−1.7
LSB (min)
0.6
LSB (max)
−0.8
LSB (min)
2.9
%FS (max)
−4.0
%FS (min)
4.8
%FS (max)
−4.1
%FS (min)
%FS (max)
−0.15
±1.3
Under Range Output Code
0
0
Over Range Output Code
2047
2047
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCM
Common Mode Input Voltage
CIN
VIN Input Capacitance (each pin to GND) VIN = 1.0 Vdc + 1 VP-P
VREF
(CLK LOW)
V (min)
V (max)
8
pF
7
pF
Reference Voltage (Note 13)
0.8
1.5
V (min)
V (max)
Reference Input Resistance
100
MΩ (min)
5
(CLK HIGH)
0.5
1.5
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ADC11L066
Absolute Maximum Ratings (Notes 1, 2)
ADC11L066
Symbol
Parameter
Typical
(Note 10)
Conditions
Limits
(Note 10)
Units
(Limits)
62.8
dB (min)
63.4
dB (min)
62.5
dB (min)
DYNAMIC CONVERTER CHARACTERISTICS
BW
Full Power Bandwidth
0 dBFS Input, Output at −3 dB
fIN = 10 MHz, Differential
VIN = −0.5 dBFS
450
85°C
25°C
−40°C
fIN = 25 MHz, Differential
VIN = −0.5 dBFS
SNR
Signal-to-Noise Ratio
fIN = 150 MHz, Differential
VIN = −6 dBFS
64
85°C
25°C
Signal-to-Noise & Distortion
fIN = 150 MHz, Differential
VIN = −6 dBFS
85°C
25°C
Effective Number of Bits
fIN = 150 MHz, Differential
VIN = −6 dBFS
85°C
25°C
2nd
Harm
fIN = 150 MHz, Differential
VIN = −6 dBFS
fIN = 240 MHz, Differential
VIN = −6 dBFS
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6
dB (min)
53.5
dB (min)
52.1
dB (min)
dB
62.1
dB (min)
62.4
dB (min)
61.2
dB (min)
dB
52.3
dB (min)
52.7
dB (min)
50.6
dB (min)
50
85°C
25°C
dB
10.02
10.31
−40°C
10.07
85°C
25°C
Bits
8.36
8.76
−40°C
8.46
85°C
−78
−40°C
Bits
−68.7
dB (max)
−69.5
dB (max)
−69.7
dB (max)
−86
85°C
25°C
Bits (min)
8.06
8.05
25°C
Bits(min)
9.80
10.18
fIN = 25 MHz, Differential
VIN = −0.5 dBFS
Second Harmonic Distortion
55
−40°C
fIN = 240 MHz, Differential
VIN = −6 dBFS
fIN = 10 MHz, Differential
VIN = −0.5 dBFS
52.8
63
fIN = 25 MHz, Differential
VIN = −0.5 dBFS
ENOB
64
−40°C
fIN = 240 MHz, Differential
VIN = −6 dBFS
fIN = 10 MHz, Differential
VIN = −0.5 dBFS
dB
52
fIN = 25 MHz, Differential
VIN = −0.5 dBFS
SINAD
56
−40°C
fIN = 240 MHz, Differential
VIN = −6 dBFS
fIN = 10 MHz, Differential
VIN = −0.5 dBFS
65
MHz
−67
−40°C
−62
dB
−60.6
dB (max)
−62.0
dB (max)
−58.3
dB (max)
dB
Parameter
Typical
(Note 10)
Conditions
fIN = 10 MHz, Differential
VIN = −0.5 dBFS
85°C
25°C
−40°C
fIN = 25 MHz, Differential
VIN = −0.5 dBFS
3rd Harm Third Harmonic Distortion
fIN = 150 MHz, Differential
VIN = −6 dBFS
85°C
25°C
Total Harmonic Distortion
fIN = 150 MHz, Differential
VIN = −6 dBFS
85°C
25°C
Spurious Free Dynamic Range
fIN = 150 MHz, Differential
VIN = −6 dBFS
fIN = 240 MHz, Differential
VIN = −6 dBFS
7
−74
−40°C
dB (max)
−76.8
dB (max)
−67.1
dB (max)
dB
−69.8
dB (max)
−69.0
dB (max)
−66.0
dB (max)
dB
−68.0
dB (max)
−67.0
dB (max)
−64.3
dB (max)
−73
85°C
25°C
−62
−40°C
dB
−56.6
dB (max)
−57.2
dB (max)
−54.1
dB (max)
−55
85°C
25°C
78
−40°C
fIN = 25 MHz, Differential
VIN = −0.5 dBFS
SFDR
−72.8
−74
fIN = 240 MHz, Differential
VIN = −6 dBFS
fIN = 10 MHz, Differential
VIN = −0.5 dBFS
−77
−40°C
fIN = 25 MHz, Differential
VIN = −0.5 dBFS
THD
Units
(Limits)
−80
fIN = 240 MHz, Differential
VIN = −6 dBFS
fIN = 10 MHz, Differential
VIN = −0.5 dBFS
−91
Limits
(Note 10)
dB
68.7
dB (min)
69.5
dB (min)
68.7
dB (min)
77
85°C
25°C
67
−40°C
62
dB
60.6
dB (min)
62.0
dB (min)
58.3
dB (min)
dB
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ADC11L066
Symbol
ADC11L066
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V,
VDR = +2.5V, PD = 0V, VREF = +1.0V, VCM = 1.0V, fCLK = 66 MHz, tr = tf = 2 ns, CL = 15 pF/pin.
Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (Notes 7, 8, 9, 10)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 10)
Units
(Limits)
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
VD = 3.3V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
VD = 3.3V
0.8
V (max)
IIN(1)
Logical “1” Input Current
VIN+, VIN− = 3.3V
10
µA
IIN(0)
Logical “0” Input Current
VIN+, VIN− = 0V
−10
µA
CIN
Digital Input Capacitance
5
pF
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
VOUT(1)
Logical “1” Output Voltage
IOUT = −0.5 mA
VDR − 0.18
V (min)
VOUT(0)
Logical “0” Output Voltage
IOUT = 1.6 mA
0.4
V (max)
IOZ
TRI-STATE Output Current
VOUT = 3.3V
100
nA
VOUT = 0V
−100
nA
+ISC
Output Short Circuit Source
Current
VOUT = 0V
−20
mA
−ISC
Output Short Circuit Sink Current
VOUT = 2.5V
20
mA
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
PD Pin = DGND, VREF = 1.0V
PD Pin = VDR
103
4
139
mA (max)
mA
ID
Digital Supply Current
PD Pin = DGND
PD Pin = VDR
5.3
2
6.2
mA (max)
mA
IDR
Digital Output Supply Current
PD Pin = DGND, (Note 14)
PD Pin = VDR
VA, VD or VDR), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. In the 32pin LQFP, θJA is 79°C/W, so PDMAX = 1,582 mW at 25°C and 823 mW at the maximum operating ambient temperature of 85°C. Note that the power consumption
of this device under normal operation will typically be about 612 mW (357 typical power consumption + 255 mW output loading with 250 MHz input). The values
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235°C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the
top of the package body above 183°C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220°C. Only one excursion
above 183°C is allowed per reflow cycle.
Note 7: The inputs are protected as shown below. Input voltages above VA or below GND will not damage this device, provided current is limited per (Note 3).
However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is 3.3V, the full-scale input
voltage must be ≤3.4V to ensure accurate conversions.
20050707
Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
Note 9: With the test condition for VREF = +1.0V (2 VP-P differential input), the 11-bit LSB is 488 µV.
Note 10: Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing
Quality Level).
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.
9
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ADC11L066
Note 13: Optimum dynamic performance will be obtained by keeping the reference input in the 0.8V to 1.5V range. The LM4051CIM3-ADJ or the LM4051CIM3-1.2
bandgap voltage reference is recommended for this application.
Note 14: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power
supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling
Note 15: Power consumption excludes output driver power. See (Note 14).
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample
is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at
every clock cycle, but the data lags the conversion by the
pipeline delay.
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 1½ LSB
below positive full scale.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure
of how well the ADC rejects a change in the power supply
voltage. For the ADC11L066, PSRR1 is the ratio of the
change in Full-Scale Error that results from a change in the
dc power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding upon the power supply
is rejected at the output.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or
SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics
but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not present
at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
Specification Definitions
APERTURE DELAY is the time after the rising edge of the
clock to when the input signal is acquired or held for conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
COMMON MODE VOLTAGE (VCM) is the d.c. potential
present at both signal inputs to the ADC.
CONVERSION LATENCY See PIPELINE DELAY.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital
waveform is high to the total time of one period. The specification here refers to the ADC clock input signal.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02
and says that the converter is equivalent to a perfect ADC of
this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Offset Error
INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative
full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The
deviation of any given code from this straight line is measured
from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC11L066 is guaranteed not
to have any missing codes.
NEGATIVE FULL SCALE ERROR is the difference between
the input voltage (VIN+ − VIN−) just causing a transition from
negative full scale to the first code and its ideal value of 0.5
LSB.
OFFSET ERROR is the input voltage that will cause a transition from a code of 010 1111 1111 to a code of 100 0000
0000.
OUTPUT DELAY is the time delay after the rising edge of the
clock before the data update is presented at the output pins.
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where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power in the first 9
harmonic frequencies.
SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input
frequency at the output and the power in its 2nd harmonic
level at the output.
THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the
input frequency at the output and the power in its 3rd harmonic
level at the output.
10
ADC11L066
Timing Diagram
20050709
Output Timing
Transfer Characteristic
20050710
FIGURE 1. Transfer Characteristic
11
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ADC11L066
Typical Performance Characteristics
VA = VD = 3.3V, VDR = 2.5V, fCLK = 66 MHz, fIN = 25 MHz, VREF =
1.0V, unless otherwise stated.
DNL
DNL vs. fCLK
200507e6
20050791
DNL vs. Clock Duty Cycle
DNL vs. Temperature
20050793
20050792
INL vs. fCLK
INL
200507e7
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20050794
12
ADC11L066
INL vs. Clock Duty Cycle
INL vs. Temperature
20050796
20050795
SNR vs. VA
SNR vs. VDR
20050797
20050798
SNR vs. VCM
SNR vs. fCLK
200507b2
200507b1
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ADC11L066
SNR vs. Clock Duty Cycle
SNR vs. VREF
200507b3
200507b4
SNR vs. Temperature
THD vs. VA
200507b5
200507b6
THD vs. VDR
THD vs. VCM
200507b7
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200507b8
14
ADC11L066
THD vs. fCLK
THD vs. Clock Duty Cycle
200507b9
200507c1
THD vs. VREF
THD vs. Temperature
200507c3
200507c2
SINAD vs. VA
SINAD vs. VDR
200507c5
200507c4
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ADC11L066
SINAD vs. VCM
SINAD vs. fCLK
200507c7
200507c6
SINAD vs. Clock Duty Cycle
SINAD vs. VREF
200507c8
200507c9
SINAD vs. Temperature
SFDR vs. VA
200507d1
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200507d2
16
ADC11L066
SFDR vs. VDR
SFDR vs. VCM
200507d4
200507d3
SFDR vs. fCLK
SFDR vs. Clock Duty Cycle
200507d6
200507d5
SFDR vs. VREF
SFDR vs. Temperature
200507d8
200507d7
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ADC11L066
Power Consumption vs. fCLK
tOD vs. VDR
200507d9
200507e1
Spectral Response @ 10 MHz Input, -0.5 dBFS
Spectral Response @ 25MHz Input, -0.5 dBFS
200507e4
200507e8
Spectral Response @ 50 MHz Input, -0.5 dBFS
Spectral Response @ 75 MHz Input, -0.5 dBFS
200507e9
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200507j0
18
Spectral Response @ 150 MHz Input, -6 dBFS
200507j1
200507j2
Spectral Response @ 240 MHz Input, -6 dBFS
200507e5
19
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ADC11L066
Spectral Response @ 100 MHz Input, -0.5 dBFS
ADC11L066
1.2 Reference Pins
The ADC11L066 is designed to operate with a 1.0V reference, but performs well with reference voltages in the range
of 0.8V to 1.5V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC11L066. Increasing the
reference voltage (and the input signal swing) beyond 1.5V
will degrade THD for a full-scale input. It is very important that
all grounds associated with the reference voltage and the input signal make connection to the analog ground plane at a
single point to minimize the effects of noise currents in the
ground path.
The ADC11L066 will perform well with reference voltages up
to 1.5V for full-scale input frequencies up to 10 MHz. However, more headroom is needed as the input frequency increases, so the maximum reference voltage (and input swing) will
decrease for higher full-scale input frequencies.
The three Reference Bypass Pins (VRP, VRM and VRN) are
made available for bypass purposes only. These pins should
each be bypassed to ground with a 0.1 µF capacitor. Smaller
capacitor values will allow faster recovery from the power
down mode, but may result in degraded noise performance.
DO NOT LOAD these pins. Loading any of these pins may
result in performance degradation.
The nominal voltages for the reference bypass pins are as
follows:
VRM = VA / 2
VRP = VRM + VREF / 2
VRN = VRM − VREF / 2
The VRM pin may be used as a common mode voltage source
(VCM) for the analog input pins as long as no d.c. current is
drawn from it. However, because the voltage at this pin is half
that of the VA supply pin, using these pins for a common mode
source will result in reduced input headroom (the difference
between the VA supply voltage and the peak signal voltage at
either analog input) and the possibility of reduced THD and
SFDR performance. For this reason, it is recommended that
VA always exceed VREF by at least 2 Volts. For high input frequencies it may be necessary to increase this headroom to
maintain THD and SFDR performance. Alternatively, use
VRN for a VCM source.
Functional Description
Operating on a single +3.3V supply, the ADC11L066 uses a
pipeline architecture and has error correction circuitry to help
ensure maximum performance.
Differential analog input signals are digitized to 11 bits. Each
analog input signal should have a peak-to-peak voltage equal
to the input reference voltage, VREF, be centered around a
common mode voltage, VCM and be 180° out of phase with
each other. Table 1 and Table 2 indicate the input to output
relationship of the ADC11L066. Biasing one input to VCM and
driving the other input with its full range signal results in a 6
dB reduction of the output range, limiting it to the range of ¼
to ¾ of the minimum output range obtainable if both inputs
were driven with complimentary signals. Section 1.3 explains
how to avoid this signal reduction.
TABLE 1. Input to Output Relationship–Differential Input
VIN+
VIN−
Output
VCM −0.5* VREF
VCM +0.5* VREF
000 0000 0000
VCM −0.25* VREF
VCM +0.25* VREF
010 0000 0000
VCM
VCM
100 0000 0000
VCM +0.25* VREF
VCM −0.25* VREF
110 0000 0000
VCM +0.5* VREF
VCM −0.5* VREF
111 1111 1111
TABLE 2. Input to Output Relationship–Single-Ended
Input
VIN+
VIN−
Output
VCM −VREF
VCM
000 0000 0000
VCM −0.5* VREF
VCM
010 0000 0000
VCM
VCM
100 0000 0000
VCM +0.5* VREF
VCM
110 0000 0000
VCM +VREF
VCM
111 1111 1111
The output word rate is the same as the clock frequency,
which can be between 10 MSPS and 80 MSPS (typical). The
analog input voltage is acquired at the rising edge of the clock
and the digital data for that sample is delayed by the pipeline
for 6 clock cycles.
A logic high on the power down (PD) pin reduces the converter power consumption to 50 mW.
1.3 Signal Inputs
The signal inputs are VIN+ and VIN−. The input signal, VIN, is
defined as
VIN = (VIN+) – (V−)
Applications Information
Figure 2 shows the expected input signal range.
Note that the nominal input common mode voltage is VREF
and the nominal input signals each run between the limits of
VREF/2 and 3VREF/2. The Peaks of the input signals should
never exceed the voltage described as
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC11L066:
3.0 V ≤ VA ≤ 3.6V
VD = VA
1.8V ≤ VDR ≤ VD
10 MHz ≤ fCLK ≤ 80 MHz
0.8V ≤ VREF ≤ 1.5V
0.5V ≤ VCM ≤ 1.5V
Peak Input Voltage = VA − 0.8
to maintain dynamic performance.
The ADC11L066 performs best with a differential input with
each input centered around a common mode voltage, VCM
(minimum of 0.5V). The peak-to-peak voltage swing at both
VIN+ and VIN− should not exceed the value of the reference
voltage or the output data will be clipped.
The two input signals should be exactly 180° out of phase
from each other and of the same amplitude. For single frequency (sine wave) inputs, angular errors result in a reduction
of the effective full scale input. For a complex waveform, however, angular errors will result in distortion.
1.1 Analog Inputs
The ADC11L066 has two analog signal inputs, VIN+ and VIN
−. These two pins form a differential input pair. There is one
reference input pin, VREF.
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20050711
FIGURE 2. Expected Input Signal Range
For angular deviations of up to 10 degrees from these two
signals being 180 out of phase with each other, the full scale
error in LSB can be described as approximately
EFS = dev1.79
Where dev is the angular difference between the two signals
having a 180° relative phase relationship to each other (see
Figure 2). Drive the analog inputs with a source impedance
less than 100Ω.
TABLE 3. Resistor values for Circuit of Figure 5
20050712
FIGURE 3. Angular Errors Between the Two Input Signals
Will Reduce the Output Level or Cause Distortion
For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage equal to the
input reference voltage, VREF, and be centered around VCM.
SIGNAL
RANGE
R1
R2
R3
R4
R5, R6
0 - 0.25V
open
124Ω
1500Ω
1000Ω
499Ω
1500Ω
499Ω
100Ω
698Ω
499Ω
0 - 0.5V
0Ω
0Ω
open
±0.5V
100Ω
698Ω
1.3.3 Input Common Mode Voltage
The input common mode voltage, VCM, should be in the range
of 0.5V to 1.5V and be of a value such that the peak excursions of the analog signal does not go more negative than
ground or more positive than 0.8 Volts below the VA supply
voltage. The nominal VCM should generally be about 1.0V, but
VRM or VRN can be used as a VCM source as long as no d.c.
current is drawn from either of these pins.
1.3.1 Single-Ended Operation
Single-ended performance is lower than with differential input
signals, so single-ended operation is not recommended.
However, if single-ended operation is required, one of the
analog inputs should be connected to the d.c. common mode
voltage of the driven input. The peak-to-peak differential input
signal should be twice the reference voltage to maximize SNR
and SINAD performance (Figure 2b).
For example, set VREF to 0.5V, bias VIN− to 1.0V and drive
VIN+ with a signal range of 0.5V to 1.5V.
Because very large input signal swings can degrade distortion
performance, better performance with a single-ended input
can be obtained by reducing the reference voltage while
maintaining a full-range output. Table 1 and Table 2 indicate
the input to output relationship of the ADC11L066.
2.0 DIGITAL INPUTS
Digital inputs are TTL/CMOS compatible and consist of CLK,
OE and PD.
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in the
range of 10 MHz to 80 MHz with rise and fall times of less than
2 ns. The trace carrying the clock signal should be as short
as possible and should not cross any other signal line, analog
or digital, not even at 90°.
The CLK signal also drives an internal state machine. If the
CLK is interrupted, or its frequency is too low, the charge on
internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the
lowest sample rate to 1 MSPS.
The duty cycle of the clock signal can affect the performance
of any A/D Converter. Because achieving a precise duty cycle
1.3.2 Driving the Analog Inputs
The VIN+ and the VIN− inputs of the ADC11L066 consist of an
analog switch followed by a switched-capacitor amplifier. The
capacitance seen at the analog input pins changes with the
clock level, appearing as 8 pF when the clock is low, and 7
pF when the clock is high.
As the internal sampling switch opens and closes, current
pulses occur at the analog input pins, resulting in voltage
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ADC11L066
spikes at the signal input pins. As a driving amplifier attempts
to counteract these voltage spikes, a damped oscillation may
appear at the ADC analog input. To help isolate the pulses at
the ADC input from the amplifier output, use RCs at the inputs,
as can be seen in Figure 4 and Figure 5. These components
should be placed close to the ADC inputs because the input
pins of the ADC is the most sensitive part of the system and
this is the last opportunity to filter that input.
Any amplifier driving the ADC11L066 input pins must be able
to react to the voltage spikes at the input and settle before the
sampling switch opens. The LMH6702 LMH6628, LMH6622
and the LMH6655 are good amplifiers for driving the ADC11L066.
For Nyquist applications the RC pole should be at the ADC
sample rate. The ADC input capacitance in the sample mode
should be considered when setting the RC pole. Setting the
pole in this manner will provide best SINAD performance.
To obtain best SNR performance, leave the RC values as
calculated. To obtain best SINAD and ENOB performance,
reduce the RC time constant until SNR and THD are numerically equal to each other. To obtain best distortion and SFDR
performance, eliminate the RC altogether.
For undersampling applications, the RC pole should be set at
about 1.5 to 2 times the maximum input frequency to maintain
a linear delay response.
A single-ended to differential conversion circuit is shown in
Figure 5. Table 3 gives resistor values for that circuit to provide input signals in a range of 1.0V ±0.5V at each of the
differential input pins of the ADC11L066.
ADC11L066
is difficult, the ADC11L066 is designed to maintain performance over a range of duty cycles. While it is specified and
performance is guaranteed with a 50% clock duty cycle, performance is typically maintained over a clock duty cycle range
of 40% to 60%.
The clock line should be series terminated at the clock source
in the characteristic impedance of that line if the clock line is
longer than
2.3 PD
The PD pin, when high, holds the ADC11L066 in a powerdown mode to conserve power when the converter is not
being used. The power consumption in this state is 50 mW
with a 66 MHz clock and 30 mW if the clock is stopped. The
output data pins are undefined in this mode. The data in the
pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the capacitors on pins 30, 31 and 32 and is about 300
ns with the recommended 0.1 µF on these pins. These capacitors loose their charge in the Power Down mode and must
be recharged by on-chip circuitry before conversions can be
accurate. Smaller capacitor values allow faster recovery from
the power down mode, but can result in a reduction in SNR,
SINAD and ENOB performance.
where tr is the clock rise time and tprop is the propagation rate
of the signal along the trace. For a typical board of FR-4 material, tPROP is about 150 ps/in, or 60 ps/cm.
The CLOCK pin may need to be a.c. terminated with a series
RC such that the resistor value is equal to the characteristic
impedance of the clock line and the capacitor value is
3.0 OUTPUTS
The ADC11L066 has 11 TTL/CMOS compatible Data Output
pins. The offset binary data is present at these outputs while
the OE and PD pins are low. While the tOD time provides information about output timing, a simple way to capture a valid
output is to latch the data on the rising edge of the conversion
clock (pin 10).
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through VDR and DR GND. These large charging current
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing, limiting output capacitance and careful attention
to the ground plane will reduce this problem. Additionally, bus
capacitance beyond the specified 15 pF/pin will cause tOD to
increase, making it difficult to properly latch the ADC output
data. The result could be an apparent reduction in dynamic
performance.
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connecting
buffers between the ADC outputs and any other circuitry
(74ACQ541, for example). Only one driven input should be
connected to each output pin. Additionally, inserting series
resistors of 100Ω at the digital outputs, close to the ADC pins,
will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise
result in performance degradation. See Figure 4.
While the ADC11L066 will operate with VDR voltages down to
1.8V, tOD increases with reduced VDR. Be careful of external
timing when using reduced VDR.
where "I" is the line length in inches and Zo is the characteristic
impedance of the clock line. This termination should be located as close as possible to, but within one centimeter of,
the ADC11L066 clock pin as shown in Figure 4. It should also
be located beyond the ADC clock pin as seen from the clock
source.
Take care to maintain a constant clock line impedance
throughout the length of the line and to properly terminate the
source end of the line with its characteristic impedance. Refer
to Application Note AN-905 for information on setting characteristic impedance.
2.2 OE
The OE pin, when high, puts the output pins into a high
impedance state. When this pin is low the outputs are in the
active state. The ADC11L066 will continue to convert whether
this pin is high or low, but the output can not be read while the
OE pin is high.
Since ADC noise increases with increased output capacitance at the digital output pins, do use the TRI-STATE outputs
of the ADC11L066 to drive a bus. Rather, each output pin
should be located close to and drive a single digital input pin.
To further reduce ADC noise, a 100 Ω resistor in series with
each ADC digital output pin, located close to their respective
pins, should be added to the circuit. See Section 3.0.
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ADC11L066
20050713
FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer
20050714
FIGURE 5. Differential Drive Circuit of Figure 4
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ADC11L066
20050715
FIGURE 6. Driving the Signal Inputs with a Transformer
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close proximity
to any of the ADC11L066's other ground pins.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated
from the digital circuitry, and to keep the clock line as short as
possible.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q
families. The worst noise generators are logic families that
draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T) families.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 47Ω to 100Ω
resistors in series with each data output line. Locate these
resistors as close to the ADC output pins as possible.
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor within a
centimeter of each power pin. Leadless chip capacitors are
preferred because they have low series inductance.
As is the case with all high-speed converters, the ADC11L066
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be kept below 100 mVP-P.
No pin should ever have a voltage on it that is in excess of the
supply voltages, not even on a transient basis. Be especially
careful of this during turn on and turn off of power.
The VDR pin provides power for the output drivers and may be
operated from a supply in the range of 1.8V to VD. This can
simplify interfacing to devices and systems operating with
supplies less than VD. DO NOT operate the VDR pin at a
voltage higher than VD.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate analog and digital areas of the board, with the ADC11L066
between these areas, is required to achieve specified performance.
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24
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
20050716
FIGURE 7. Example of a Suitable Layout
Generally, analog and digital lines should cross each other at
90° to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep clock lines as
short as possible and isolated from ALL other lines, including
other digital lines. Even the generally accepted 90° crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead
to degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in which
they are used. Inductors should not be placed side by side,
even with just a small part of their bodies beside each other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between
the converter's input pins and ground or to the reference input
pin and ground should be connected to a very clean point in
the ground plane.
Figure 7 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed in the analog area of the board. All digital
circuitry and I/O lines should be placed in the digital area of
the board. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground
should be connected together with short traces and enter the
ground plane at a single point. All ground connections should
have a low inductance path to ground.
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 8.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines.
Even lines with 90° crossings have capacitive coupling, so try
to avoid even these 90° crossings of the clock line.
20050717
FIGURE 8. Isolating the ADC Clock from other Circuitry
with a Clock Tree
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
pins). Exceeding these limits on even a transient basis may
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ADC11L066
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
ADC11L066
cause faulty or erratic operation. It is not uncommon for high
speed digital components (e.g., 74F and 74AC devices) to
exhibit overshoot or undershoot that goes above the power
supply or below ground. A resistor of about 50Ω to 100Ω in
series with any offending digital input, close to the signal
source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage, even
on a transient basis. Not even during power up or power
down.
Be careful not to overdrive the inputs of the ADC11L066 with
a device that is powered from supplies outside the range of
the ADC11L066 supply. Such practice may lead to conversion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current flows
through VDR and DR GND. These large charging current
spikes can couple into the analog circuitry, degrading dynamic performance. Adequate bypassing and maintaining separate analog and digital areas on the pc board will reduce this
problem.
Additionally, bus capacitance beyond the specified 15 pF/pin
will cause t OD to increase, making it difficult to properly latch
the ADC output data. The result could, again, be a reduction
in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved by
adding series resistors at each digital output, close to the ADC11L066, which reduces the energy coupled back into the
converter output pins by limiting the output current. A reasonable value for these resistors is 100Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the input
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alternates between 8 pF and 7 pF, depending upon the phase
of the clock. This dynamic load is more difficult to drive than
is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a
capacitor across the analog inputs (as shown in Figures 5,
6) will improve performance. The LMH6702, LMH6628,
LMH6622 and LMH6655 have been successfully used to
drive the analog inputs of the ADC11L066.
Also, it is important that the signals at the two inputs have
exactly the same amplitude and be exactly 180º out of phase
with each other. Board layout, especially equality of the length
of the two traces to the input pins, will affect the effective
phase between these two signals. Remember that an operational amplifier operated in the non-inverting configuration will
exhibit more time delay than will the same device operating
in the inverting configuration.
Operating with the reference pins outside of the specified
range. As mentioned in Section 1.2, VREF should be in the
range of
0.8V ≤ VREF ≤ 1.5V
Operating outside of these limits could lead to performance
degradation.
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a
reduction in SNR and SINAD performance.
26
ADC11L066
Physical Dimensions inches (millimeters) unless otherwise noted
32-Lead LQFP Package
Ordering Number ADC11L066CIVY
NS Package Number VBE32A
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ADC11L066 11-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold
Notes
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