ADS1230IPW

Burr Brown Products from Texas Instruments ADS1230 SBAS366 – OCTOBER 2006 20-Bit Analog-to-Digital Converter For Bridge Sensors FEATURES • • • • Complete Front-End for Bridge Sensor Onboard PGA with Gain of 64 or 128 Onboard Oscillator RMS Noise: 40nV at 10SPS (G = 128) 88nV at 80SPS (G = 128) 18-Bit Noise-Free Resolution Selectable 10SPS or 80SPS Data Rates Simultaneous 50Hz and 60Hz Rejection at 10SPS External Voltage Reference up to 5V for Ratiometric Measurements Simple, Pin-Driven Control Two-Wire Serial Digital Interface Tiny 16-pin TSSOP Package Supply Range: 2.7V to 5.3V –40°C to +85°C Temperature Range DESCRIPTION The ADS1230 is a precision 20-bit analog-to-digital converter (ADC). With an onboard low-noise programmable gain amplifier (PGA), onboard oscillator, and precision 20-bit delta-sigma ADC, the ADS1230 provides a complete front-end solution for bridge sensor applications including weigh scales, strain gauges, and pressure sensors. The low-noise PGA has a gain of 64 or 128, supporting a full-scale differential input of ±39mV or ±19.5mV, respectively. The delta-sigma ADC has 20-bit effective resolution and is comprised of a 3rd-order modulator and 4th-order digital filter. Two data rates are supported: 10SPS (with both 50Hz and 60Hz rejection) and 80SPS. The ADS1230 can be clocked by the internal oscillator or an external clock source. Offset calibration is performed on-demand, and the ADS1230 can be put in a low-power standby mode or shut off completely in power-down mode. All of the features of the ADS1230 are controlled by dedicated pins; there are no digital registers to program. Data are output over an easily-isolated serial interface that connects directly to the MSP430 and other microcontrollers. The ADS1230 is available in a TSSOP-16 package and is specified from –40°C to +85°C. • • • • • • • • • • • • • APPLICATIONS Weigh Scales Strain Gauges Pressure Sensors Industrial Process Control AVDD CAP REFP REFN DVDD Gain = 64 or 128 AINP PGA AINN DS ADC PDWN DRDY/DOUT SCLK Internal Oscillator SPEED AGND GAIN CAP CLKIN DGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated ADS1230 www.ti.com SBAS366 – OCTOBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) ADS1230 AVDD to AGND DVDD to DGND AGND to DGND Input Current Analog Input Voltage to AGND Digital Input Voltage to DGND Maximum Junction Temperature Operating Temperature Range Storage Temperature Range (1) –0.3 to +6 –0.3 to +6 –0.3 to +0.3 100, Momentary 10, Continuous –0.3 to AVDD + 0.3 –0.3 to DVDD + 0.3 +150 –40 to +85 –60 to +150 UNIT V V V mA mA V V °C °C °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 Submit Documentation Feedback ADS1230 www.ti.com SBAS366 – OCTOBER 2006 ELECTRICAL CHARACTERISTICS All specifications at TA = –40°C to +85°C, AVDD = DVDD = REFP = +5V, REFN = AGND, and Gain = 64, unless otherwise noted. ADS1230 PARAMETER Analog Inputs Full-Scale Input Voltage (AINP – AINN) Common-Mode Input Range Differential Input Current System Performance Resolution No Missing Codes Internal Oscillator, SPEED = High Data Rate Internal Oscillator, SPEED = Low External Oscillator, SPEED = High External Oscillator, SPEED = Low Digital Filter Settling Time Integral Nonlinearity (INL) Input Offset Error (1) Input Offset Drift Gain Error Gain Drift Internal Oscillator, fDATA = 10SPS Normal-Mode Rejection (2) Common-Mode Rejection Input-Referred Noise Power-Supply Rejection Voltage Reference Input Voltage Reference Input (VREF) Negative Reference Input (REFN) Positive Reference Input (REFP) Voltage Reference Input Current Digital VIH Logic Levels VIL VOH VOL Input Leakage External Clock Input Frequency (fCLKIN) Serial Clock Input Frequency (fSCLK) IOH = 1mA IOL = 1mA 0 < VIN < DVDD 0.2 4.9152 All digital inputs except CLKIN CLKIN 0.7 DVDD 0.7 DVDD DGND DVDD – 0.4 0.2 DVDD ±10 6 5 DVDD + 0.1 5.1 0.2 DVDD V V V V V µA MHz MHz VREF = REFP – REFN 1.5 AGND – 0.1 REFN + 1.5 10 AVDD AVDD + 0.1V REFP – 1.5 AVDD + 0.1 V V V nA External Oscillator, fDATA = 10SPS fIN = 50Hz or 60Hz, ±1Hz at DC, ∆VDD = 0.1V fDATA = 10SPS fDATA = 80SPS at DC, ∆VDD = 0.1V 90 Full Settling Differential Input, End-Point Fit, G = 64 Differential Input, End-Point Fit, G = 128 20 69.5 8.68 80 10 fCLK/61,440 fCLK/491,520 4 ±10 ±6 ±3 ±10 ±0.8 ±4 90 100 110 53 100 100 86.4 10.8 Bits SPS SPS SPS SPS Conversions ppm ppm ppm of FS nV/°C % ppm/°C dB dB dB nV, rms nV, rms dB AGND + 1.5V ±2 ±0.5VREF/PGA AVDD – 1.5V V V nA CONDITIONS MIN TYP MAX UNIT (1) (2) Offset calibration can minimize these errors to the level of noise at any temperature. Specification is assured by the combination of design and final production test. Submit Documentation Feedback 3 ADS1230 www.ti.com SBAS366 – OCTOBER 2006 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –40°C to +85°C, AVDD = DVDD = REFP = +5V, REFN = AGND, and Gain = 64, unless otherwise noted. ADS1230 PARAMETER Power Supply Power-Supply Voltage (AVDD, DVDD) Normal Mode, AVDD = 3V Analog Supply Current Normal Mode, AVDD = 5V Standby Mode Power-Down Normal Mode, DVDD = 3V Normal mode, DVDD = 5V Digital Supply Current Standby Mode, SCLK = High, DVDD = 3V Standby Mode, SCLK = High, DVDD = 5V Power-Down Normal Mode, AVDD = DVDD = 3V Power Dissipation, Total Normal Mode, AVDD = DVDD = 5V Standby Mode, AVDD = DVDD = 5V 2.7 900 900 0.1 0.1 60 95 45 65 0.2 2.9 5.0 0.3 4.5 7.7 0.4 5.3 1400 1400 1 1 100 140 65 80 V µA µA µA µA µA µA µA µA µA mW mW mW CONDITIONS MIN TYP MAX UNIT 4 Submit Documentation Feedback ADS1230 www.ti.com SBAS366 – OCTOBER 2006 PIN CONFIGURATION PW PACKAGE TSSOP-16 (Top View) DVDD DGND CLKIN GAIN CAP CAP AINP AINN 1 2 3 4 ADS1230 5 6 7 8 16 15 14 13 12 11 10 9 DRDY/DOUT SCLK PDWN SPEED AVDD AGND REFP REFN PIN DESCRIPTIONS NAME DVDD DGND CLKIN TERMINAL 1 2 3 ANALOG/DIGITAL INPUT/OUTPUT Digital Digital Digital/Digital Input DESCRIPTION Digital Power Supply: 2.7V to 5.3V Digital Ground External Clock Input: typically 4.9152MHz. Tie low to activate internal oscillator. PGA Gain Select GAIN 4 Digital Input GAIN 0 1 CAP CAP AINP AINN REFN REFP AGND AVDD 5 6 7 8 9 10 11 12 Analog Analog Analog Input Analog Input Analog Input Analog Input Analog Analog PGA 64 128 Gain Amp Bypass Capacitor Connection Gain Amp Bypass Capacitor Connection Positive Analog Input Negative Analog Input Negative Reference Input Positive Reference Input Analog Ground Analog Power Supply, 2.7V to 5.3V Data Rate Select: SPEED 13 Digital Input SPEED 0 1 DATA RATE 10SPS 80SPS PDWN SCLK 14 15 Digital Input Digital Input Power-Down: Holding this pin low powers down the entire converter and resets the ADC. Serial Clock: Clock out data on the rising edge. Also used to initiate Offset Calibration and Sleep modes. See the Offset Calibration, Standby Mode, and Standby Mode with Offset Calibration sections for more details. Dual-Purpose Output: DRDY/DOUT 16 Digital Output Data Ready: Indicates valid data by going low. Data Output: Outputs data, MSB first, on the first rising edge of SCLK. Submit Documentation Feedback 5 ADS1230 www.ti.com SBAS366 – OCTOBER 2006 NOISE PERFORMANCE The ADS1230 offers outstanding noise performance. Table 1 summarizes the typical noise performance with inputs shorted externally for different data rates and voltage reference values. The RMS and Peak-to-Peak noise are referred to the input. The effective number of bits (ENOB) is defined as: ENOB = ln (FSR/RMS noise)/ln(2) The Noise-Free Bits are defined as: Noise-Free Bits = ln (FSR/Peak-to-Peak Noise)/ln(2) Where: FSR (Full-Scale Range) = VREF/Gain. Table 1. Noise Performance for AVDD = 5V and VREF = 5V DATA RATE 10 80 (1) GAIN 64 128 64 128 RMS NOISE (nV) 53 40 100 88 PEAK-TO-PEAK NOISE (1) (nV) 290 198 480 480 ENOB (RMS) 20.5 19.8 19.5 18.7 NOISE-FREE BITS 18 17.5 17.3 16.3 Peak-to-peak data are based on direct measurement. Table 2. Noise Performance for AVDD = 3V and VREF = 3V DATA RATE 10 80 (1) GAIN 64 128 64 128 RMS NOISE (nV) 46 49 100 102 PEAK-TO-PEAK NOISE (1) (nV) 290 259 576 461 ENOB (RMS) 20.6 19.6 19.5 18.5 NOISE-FREE BITS 18 17.2 17 16.3 Peak-to-peak data are based on direct measurement. 6 Submit Documentation Feedback ADS1230 www.ti.com SBAS366 – OCTOBER 2006 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = DVDD = REFP = 5V, and REFN = AGND, unless otherwise noted. NOISE PLOT 4 PGA = 64 Data Rate = 10SPS 3 2 1 PGA = 64 Data Rate = 80SPS NOISE PLOT Output Code (LSB) Output Code (LSB) 0 200 400 600 800 1000 3 0 -1 -2 -3 -4 -5 2 1 0 Time (Reading Number) -6 0 200 400 600 800 1000 Time (Reading Number) Figure 1. NOISE HISTOGRAM 900 800 700 PGA = 64 Data Rate = 10SPS 400 350 300 PGA = 64 Data Rate = 80SPS Figure 2. NOISE HISTOGRAM Occurrence 500 400 300 200 100 0 1 2 Output Code (LSB) 3 Occurrence 600 250 200 150 100 50 0 -5 -4 -3 -2 -1 0 1 2 Output Code (LSB) Figure 3. NOISE PLOT 0 -1 PGA = 128 Data Rate = 10SPS 8 6 4 PGA = 128 Data Rate = 80SPS Figure 4. NOISE PLOT Output Code (LSB) -2 -3 -4 -5 -6 0 200 400 600 800 1000 Time (Reading Number) Output Code (LSB) 2 0 -2 -4 -6 -8 -10 0 200 400 600 800 1000 Time (Reading Number) Figure 5. Figure 6. Submit Documentation Feedback 7 ADS1230 www.ti.com SBAS366 – OCTOBER 2006 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DVDD = REFP = 5V, and REFN = AGND, unless otherwise noted. NOISE HISTOGRAM 500 450 400 350 PGA = 128 Data Rate = 10SPS 200 250 PGA = 128 Data Rate = 80SPS NOISE HISTOGRAM Occurrence 300 250 200 150 100 50 0 -5 -4 -3 -2 -1 0 Output Code (LSB) Occurrence 150 100 50 0 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 Output Code (LSB) Figure 7. OFFSET vs TEMPERATURE 1000 800 600 -0.03 -0.02 Figure 8. GAIN ERROR vs TEMPERATURE PGA = 64 Data Rate = 10SPS 200 0 -200 -400 -600 -800 PGA = 64 Data Rate = 10SPS -50 -25 0 25 50 75 100 Gain Error (%) 400 Offset (nV) -0.04 -0.05 -0.06 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure 9. NOISE vs INPUT SIGNAL 50 45 40 100 120 PGA = 64 Data Rate = 80SPS Figure 10. NOISE vs INPUT SIGNAL RMS Noise (nV) 30 25 20 15 10 5 0 -40 -30 -20 -10 0 VIN (mV) 10 20 30 40 PGA = 64 Data Rate = 10SPS RMS Noise (nV) 35 80 60 40 -40 -30 -20 -10 0 VIN (mV) 10 20 30 40 Figure 11. Figure 12. 8 Submit Documentation Feedback ADS1230 www.ti.com SBAS366 – OCTOBER 2006 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DVDD = REFP = 5V, and REFN = AGND, unless otherwise noted. INTEGRAL NONLINEARITY vs INPUT SIGNAL 10 +25°C 5 +70°C -20°C 0 +85°C -5 PGA = 64 Data Rate = 10SPS -10 -40 -30 -20 -10 0 VIN (mV) 10 20 30 40 -40°C -1.5 -2.0 PGA = 128 Data Rate = 10SPS -20 -10 1.0 -20°C 0.5 0 INTEGRAL NONLINEARITY vs INPUT SIGNAL INL (ppm) INL (ppm) -0.5 -40°C -1.0 +25°C +70°C 0 VIN (mV) 10 +85°C 20 Figure 13. ANALOG CURRENT vs TEMPERATURE (Normal Mode) 1200 1000 97 96 Figure 14. DIGITAL CURRENT vs TEMPERATURE (Normal Mode) Analog Current (mA) PGA = 64, 128 800 600 400 200 95 Digital Current (mA) 94 93 92 91 90 89 PGA = 64 -50 -25 0 25 50 75 100 PGA = 128 0 -50 -25 0 25 50 75 100 Temperature (°C) 88 Temperature (°C) Figure 15. DATA RATE vs TEMPERATURE 9.85 Figure 16. Data Rate (SPS) 9.80 9.75 9.70 -50 -25 0 25 50 75 100 Temperature (°C) Figure 17. Submit Documentation Feedback 9 ADS1230 www.ti.com SBAS366 – OCTOBER 2006 OVERVIEW The ADS1230 is a precision, 20-bit ADC that includes a low-noise PGA, internal oscillator, third-order delta-sigma (∆Σ) modulator, and fourth-order digital filter. The ADS1230 provides a complete front-end solution for bridge sensor applications such as weigh scales, strain guages, and pressure sensors. Clocking can be supplied by an external clock or by a precision internal oscillator. Data can be output at 10SPS for excellent 50Hz and 60Hz rejection, or at 80SPS when higher speeds are needed. The ADS1230 is easy to configure, and all digital control is accomplished through dedicated pins; there are no registers to program. A simple two-wire serial interface retrieves the data. 64) or 0mV to +19.5mV (Gain = 128). The inputs of the ADS1230 are protected with internal diodes connected to the power-supply rails. These diodes clamp the applied signal to prevent it from damaging the input circuitry. CAP 450W AINP 18pF A1 R RINT F1 Gain = 1 or 2 R1 RF2 A3 ADC RINT 450W AINN 18pF A2 ANALOG INPUTS (AINP, AINN) The input signal to be measured is applied to the input pins AINP and AINN. The ADS1230 accepts differential input signals, but can also measure unipolar signals. When measuring unipolar (or single-ended signals) with respect to ground, connect the negative input (AINN) to ground and connect the input signal to the positive input (AINP). Note that when the ADS1230 is configured this way, only half of the converter full-scale range is used, since only positive digital output codes are produced. CAP Figure 18. Simplified Diagram of the PGA Bypass Capacitor By applying a 0.1µF external capacitor (CEXT) across two capacitor pins combined with the internal 2kΩ resistor RINT (on-chip), a low-pass filter with a corner frequency of 720Hz is created to bandlimit the signal path before the modulator input. This low-pass filter serves two purposes. First, the input signal is bandlimited to prevent aliasing as well as to filter out the high-frequency noise. Second, it attenuates the chopping residue from the amplifier to improve temperature drift performance. It is not required to use high-quality capacitors (such as ceramic or tantalum capacitors) for a general application. However, high-quality capacitors such as poly are recommended for high-linearity applications. LOW-NOISE PGA The ADS1230 features a low-drift, low-noise PGA that provides a complete front-end solution for bridge sensors. A simplified diagram of the PGA is shown in Figure 18. It consists of two chopper-stabilized amplifiers (A1 and A2) and three accurately-matched resistors (R1, RF1, and RF2), which construct a differential front-end stage with a gain of 64, followed by gain stage A3 (Gain = 1 or 2). The PGA inputs are equipped with an EMI filter, as shown in Figure 18. The cutoff frequency of the EMI filter is 19.6MHz. By using AVDD as the reference input, the bipolar input ranges from –39mV to +39mV (Gain = 64) or –19.5mV to +19.5mV (Gain = 128), and the unipolar input ranges from 0mV to +39mV (Gain = 10 Submit Documentation Feedback ADS1230 www.ti.com SBAS366 – OCTOBER 2006 VOLTAGE REFERENCE INPUTS (REFP, REFN) The voltage reference used by the modulator is generated from the voltage difference between REFP and REFN: VREF = REFP – REFN. The reference inputs use a structure similar to that of the analog inputs. In order to increase the reference input impedance, a switching buffer circuitry is used to reduce the input equivalent capacitance. A simplified diagram of the circuitry on the reference inputs is shown in Figure 19. The switches and capacitors can be modeled with an effective impedance of: 1 Z EFF + 2f MODC BUF Where: fMOD = modulator sampling frequency (76.8kHz) CBUF = input capacitance of the buffer For the ADS1230: 1 Z EFF + + 200MW (2)(76.8kHz)(32.5fF) REFP REFN ESD diodes protect the reference inputs. To prevent these diodes from turning on, make sure the voltages on the reference pins do not go below GND by more than 100mV, and likewise, do not exceed AVDD by 100mV: GND – 100mV < (REFP or REFN) < AVDD + 100mV CLOCK SOURCES The ADS1230 can use an external clock source or internal oscillator to accommodate a wide variety of applications. Figure 20 shows the equivalent circuitry of the clock source. The CLK_DETECT block determines whether the crystal oscillator/external clock signal is applied to the CLKIN pin so that the internal oscillator is bypassed or activated. When the CLKIN pin frequency is above ~200kHz, the CLK_DETECT output goes low and shuts down the internal oscillator. When the CLKIN pin frequency is below ~200kHz, the CLK_DETECT output goes high and activates the internal oscillator. It is highly recommended to hard-wire the CLKIN pin to ground when the internal oscillator is chosen. CLKIN CLK_DETECT Internal Oscillator S0 S1 S MUX To ADC EN AVDD AVDD ESD Protection CBUF ZEFF = 200MW(1) Figure 20. Equivalent Circuitry of the Clock Source (1) fMOD = 76.8kHz Figure 19. Simplified Reference Input Circuitry An external clock may be used by driving the CLKIN pin directly. The Electrical Characteristics table shows the allowable frequency range. The clock input may be driven with 5V logic, regardless of the DVDD or AVDD voltage. Submit Documentation Feedback 11 ADS1230 www.ti.com SBAS366 – OCTOBER 2006 FREQUENCY RESPONSE The ADS1230 uses a sinc digital filter with the frequency response (fCLK = 4.9152MHz) shown in Figure 21. The frequency response repeats at multiples of the modulator sampling frequency of 76.8kHz. The overall response is that of a low-pass filter with a –3dB cutoff frequency of 3.32Hz with the SPEED pin tied low (10SPS data rate) and 11.64Hz with the SPEED pin tied high (80SPS data rate). 0 -20 -40 -60 fCLK = 4.9152MHz 0 Data Rate = 10SPS 4 -50 Gain (dB) -100 -150 0 10 20 30 40 50 (a) -50 Data Rate = 10SPS 60 70 80 90 100 Frequency (Hz) Gain (dB) -80 -100 -120 -140 -160 -200 0 38.4 Frequency (kHz) 76.8 Gain (dB) -180 -100 Figure 21. Frequency Response To help see the response at lower frequencies, Figure 22(a) illustrates the response out to 100Hz, when the data rate = 10SPS. Notice that signals at multiples of 10Hz are rejected, and therefore simultaneous rejection of 50Hz and 60Hz is achieved. The benefit of using a sinc filter is that every frequency notch has four zeros on the same location. This response, combined with the low drift internal oscillator, provides an excellent normal-mode rejection of line-cycle interference. Figure 22(b) shows the same plot, but zooms in on the 50Hz and 60Hz notches with the SPEED pin tied low (10SPS data rate). With only a ±3% variation of the internal oscillator, over 100dB of normal-mode rejection is achieved. 4 -150 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Frequency (Hz) (b) Figure 22. Frequency Response Out To 100Hz The ADS1230 data rate and frequency response scale directly with clock frequency. For example, if fCLK increases from 4.9152MHz to 6.144MHz when the SPEED pin is tied high, the data rate increases from 80SPS to 100SPS, while notches also increase from 80Hz to 100Hz. Note that these changes are only possible when the external clock source is applied. 12 Submit Documentation Feedback ADS1230 www.ti.com SBAS366 – OCTOBER 2006 SETTLING TIME In certain instances, large changes in input will require settling time. For example, an external multiplexer in front of the ADS1230 can put large changes in input voltage by simply switching the multiplexer input channels. Abrupt changes in the input will require four data conversion cycles to settle. When continuously converting, five readings may be necessary in order to settle the data. If the change in input occurs in the middle of the first conversion, four more full conversions of the fully-settled input are required to get fully-settled data. Discard the first four readings because they contain only partially-settled data. Figure 23 illustrates the settling time for the ADS1230 in Continuous Conversion mode. DATA FORMAT The ADS1230 outputs 20 bits of data in binary two’s complement format. The least significant bit (LSB) has a weight of 0.5VREF/(219 – 1). The positive full-scale input produces an output code of 7FFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 4 summarizes the ideal output codes for different input signals. The ADS1230 is a 20-bit ADC. After data conversion is completed, applying 20 SCLKs retrieves 20 bits of data (MSB first). However, if the SCLKs continue to be applied after 20 bits of data are retrieved, the DOUT pin outputs four 1s for the 21st through the 24th SCLK, as shown in Figure 24. Table 4. Ideal Output Code vs Input Signal(1) INPUT SIGNAL VIN (AINP – AINN) ≥ +0.5VREF/Gain (+0.5VREF /Gain)/(219– 0 (–0.5VREF/Gain)/(219– 1) ≤– 0.5VREF/Gain 1) IDEAL OUTPUT 7FFFFh 00001h 00000h FFFFFh 80000h DATA RATE The ADS1230 data rate is set by the SPEED pin, as shown in Table 3. When SPEED is low, the data rate is nominally 10SPS. This data rate provides the lowest noise, and also has excellent rejection of both 50Hz and 60Hz line-cycle interference. For applications requiring fast data rates, setting SPEED high selects a data rate of nominally 80SPS. Table 3. Data Rate Settings DATA RATE SPEED PIN 0 1 Internal Oscillator or 4.9152MHz Crystal 10SPS 80SPS External Oscillator fCLKIN / 491,520 fCLKIN / 61,440 (1) Excludes effects of noise, INL, offset, and gain errors. Abrupt Change in External VIN VIN Start of Conversion DRDY/DOUT Conversion Time 1st Conversion; includes unsettled VIN. 2nd Conversion; VIN settled, but digital filter unsettled. 3rd Conversion; VIN settled, but digital filter unsettled. 4th Conversion; VIN settled, but digital filter unsettled. 5th Conversion; VIN and digital filter both settled. Figure 23. Settling Time in Continuous Conversion Mode Data Data Ready MSB DRDY/DOUT 19 18 17 LSB 0 1 2 3 4 New Data Ready SCLK 1 2 3 20 21 22 23 24 Figure 24. Data Retrieval Format Submit Documentation Feedback 13 ADS1230 www.ti.com SBAS366 – OCTOBER 2006 DATA READY/DATA OUTPUT (DRDY/DOUT) This digital output pin serves two purposes. First, it indicates when new data are ready by going low. Afterwards, on the first rising edge of SCLK, the DRDY/DOUT pin changes function and begins outputting the conversion data, most significant bit (MSB) first. Data are shifted out on each subsequent SCLK rising edge. After all 20 bits have been retrieved, the pin can be forced high with an additional SCLK. It then stays high until new data are ready. This configuration is useful when polling on the status of DRDY/DOUT to determine when to begin data retrieval. DATA RETRIEVAL The ADS1230 continuously converts the analog input signal. To retrieve data, wait until DRDY/DOUT goes low, as shown in Figure 25. After DRDY/DOUT goes low, begin shifting out the data by applying SCLKs. Data are shifted out MSB first. It is not required to shift out all 20 bits of data, but the data must be retrieved before new data are updated (within tCONV) or else the data will be overwritten. Avoid data retrieval during the update period (tUPDATE). If 24 SCLKs have been applied, DRDY/DOUT will be high since the last four bits have been appended by '1'. However, if only 20 SCLKs have been applied, DRDY/DOUT remains at the state of the last bit shifted out until it is taken high (see tUPDATE), indicating that new data are being updated. To avoid having DRDY/DOUT remain in the state of the last bit, the 21st SCLK can be applied to force DRDY/DOUT high, as shown in Figure 26. This technique is useful when a host controlling the device is polling DRDY/DOUT to determine when data are ready. SERIAL CLOCK INPUT (SCLK) This digital input shifts serial data out with each rising edge. As with CLK, this input may be driven with 5V logic regardless of the DVDD or AVDD voltage. This input has built-in hysteresis, but care should still be taken to ensure a clean signal. Glitches or slow-rising signals can cause unwanted additional shifting. For this reason, it is best to make sure the rise and fall times of SCLK are both less than 50ns. 14 Submit Documentation Feedback ADS1230 www.ti.com SBAS366 – OCTOBER 2006 a) 20 Bits of Data Retrieval Data Ready MSB DRDY/DOUT 19 tPD tDS SCLK 1 18 17 Data New Data Ready LSB 0 tHT tSCLK 20 tSCLK tCONV tUPDATE b) 24 Bits of Data Retrieval Data Ready MSB DRDY/DOUT 19 tPD tDS SCLK 1 18 17 Data New Data Ready LSB 0 tHT tSCLK 20 tSCLK tCONV 21 22 23 24 tUPDATE 1 2 3 4 Figure 25. Data Retrieval Timing SYMBOL tDS tSCLK tPD tHT tUPDATE(1) tCONV(1) (1) DESCRIPTION DRDY/DOUT low to first SCLK rising edge SCLK positive or negative pulse width SCLK rising edge to new data bit valid: propagation delay SCLK rising edge to old data bit valid: hold time Data updating: no readback allowed Conversion time (1/data rate) SPEED = 1 SPEED = 0 0 39 12.5 100 MIN 0 100 50 TYP MAX UNITS ns ns ns ns µs ms ms Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Data Data Ready New Data Ready DRDY/DOUT 19 18 17 0 SCLK 1 20 21 21st SCLK to Force DRDY/DOUT High Figure 26. Data Retrieval with DRDY/DOUT Forced High Afterwards 15 Submit Documentation Feedback ADS1230 www.ti.com SBAS366 – OCTOBER 2006 OFFSET CALIBRATION Offset calibration can be initiated at any time to remove the ADS1230 inherited offset error. To initiate offset calibration, apply at least two additional SCLKs after retrieving 20 bits of data plus four bits of '1'. Figure 27 shows the timing pattern. The 25th SCLK keeps DRDY/DOUT high. The falling edge of the 26th SCLK begins the calibration cycle. Additional SCLK pulses may be sent after the 26th SCLK; however, activity on SCLK should be minimized during offset calibration for best results. During this time, the analog input pins are disconnected within the ADC and the appropriate signal is applied internally to perform the calibration. When the calibration is completed, DRDY/DOUT goes low, indicating that new data are ready. The first conversion after a calibration is fully settled and valid for use. The offset calibration takes exactly the same time as specified in (tCAL) immediately after the falling edge of the 26th SCLK. Data Ready After Calibration DRDY/DOUT 19 18 17 0 1 2 3 4 Calibration Begins 19 SCLK 1 20 21 22 23 24 25 26 tCAL Figure 27. Offset-Calibration Timing SYMBOL tCAL (1) (1) DESCRIPTION First data ready after calibration SPEED = 1 SPEED = 0 MIN 101.28 801.02 MAX 101.29 801.03 UNITS ms ms Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an internal oscillator is used. 16 Submit Documentation Feedback ADS1230 www.ti.com SBAS366 – OCTOBER 2006 STANDBY MODE Standby mode dramatically reduces power consumption by shutting down most of the circuitry. In Standby mode, the entire analog circuitry is powered down and only the clock source circuitry is awake to reduce the wake-up time from the Standby mode. To enter Standby mode, simply hold SCLK high after DRDY/DOUT goes low; see Figure 28. Standby mode can be initiated at any time during readback; it is not necessary to retrieve all 20 bits of data beforehand. When tSTANDBY has passed with SCLK held high, Standby mode activates. DRDY/DOUT stays high when Standby mode begins. SCLK must remain high to stay in Standby mode. To exit Standby mode (wakeup), set SCLK low. The first data after exiting Standby mode is valid. Standby Mode DRDY/DOUT 19 18 17 0 Data Ready Start Conversion 19 SCLK 1 tDSS 20 tSTANDBY tS_RDY Figure 28. Standby Mode Timing (can be used for single conversions) SYMBOL tDSS (1) tSTANDBY (1) tS_RDY (1) (1) DESCRIPTION SCLK high after DRDY/DOUT goes low to activate Standby mode Standby mode activation time Data ready after exiting Standby mode SPEED = 1 SPEED = 0 SPEED = 1 SPEED = 0 SPEED = 1 SPEED = 0 MIN 0 0 20 20 52.51 401.8 52.51 401.8 MAX 12.44 99.94 UNITS ms ms µs µs ms ms Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an internal oscillator is used. Submit Documentation Feedback 17 ADS1230 www.ti.com SBAS366 – OCTOBER 2006 STANDBY MODE WITH OFFSET-CALIBRATION Offset-calibration can be set to run immediately after exiting Standby mode. This option is useful when the ADS1230 is put in Standby mode for long periods of time, and offset-calibration is desired afterwards to compensate for temperature or supply voltage changes. To force an offset-calibration with Standby mode, shift 25 SCLKs and bring the SCLK pin high to enter Standby mode. Offset-calibration then begins after wake-up; Figure 29 shows the appropriate timing. Note the extra time needed after wake-up for calibration before data are ready. The first data after Standby mode with offset-calibration is fully settled and can be used right away. Data Ready After Calibration Standby Mode DRDY/DOUT 19 18 17 0 1 2 3 4 Begin Calibration 25 tSTANDBY tSC_RDY 19 SCLK 1 20 21 22 23 24 Figure 29. Standby Mode with Offset-Calibration Timing (can be used for single conversions) SYMBOL tSC_RDY (1) (1) DESCRIPTION Data ready after exiting Standby mode and calibration SPEED = 1 SPEED = 0 MIN 103 803 MAX 103 803 UNITS ms ms Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an internal oscillator is used. 18 Submit Documentation Feedback ADS1230 www.ti.com SBAS366 – OCTOBER 2006 POWER-DOWN MODE Power-Down mode shuts down the entire ADC circuitry and reduces the total power consumption close to zero. To enter Power-Down mode, simply hold the PDWN pin low. Power-Down mode also resets the entire circuitry to free the ADC circuitry from locking up to an unknown state. Power-Down mode can be initiated at any time during readback; it is not necessary to retrieve all 20 bits of data beforehand. Figure 30 shows the wake-up timing from Power-Down mode. Start Conversion Power-Down Mode tPDWN PDWN Data Ready CLK Source Wakeup DRDY/DOUT tWAKEUP SCLK tTS_RDY Figure 30. Wake-Up Timing from Power-Down Mode SYMBOL tWAKEUP tPDWN (1) (1) DESCRIPTION Wake-up time after Power-Down mode PDWN pulse width Internal clock External clock 26 MIN TYP 7.95 0.16 UNITS µs µs µs Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an internal oscillator is used. Submit Documentation Feedback 19 ADS1230 www.ti.com SBAS366 – OCTOBER 2006 APPLICATION EXAMPLES Weigh Scale System Figure 31 shows a typical ADS1230 hook-up as part of a weigh scale system. In this setup, the ADS1230 is configured at a 10SPS data rate. Note that the internal oscillator is used by grounding the CLKIN pin. The user can also apply a 4.9152MHz clock to the CLKIN pin. For a typical 2mV/V load cell, the maximum output signal is approximately 10mV for a single +5V excitation voltage. The ADS1230 can achieve 17.5 noise-free bits at 10SPS when PGA = 128. With the extra software filtering/averaging (typically done by a microprocessor), an extra bit can be expected. Noise−Free Counts + 2 BITEff FS LC FSAD Where: BITEFF = effective noise-free bits (17.5 + 1 bit from software filtering/averaging) FSLC = full-scale output of the load cell (10mV) FSAD = full-scale input of the ADS1230 (39mV, when PGA = 128) Therefore: Noise−Free Counts + 2 (17.5)1) 10mV + 95, 058 39mV With +5V supply voltage, 95,058 noise-free counts can be expected from the ADS1230. 2.7V to 5.3V 0.1mF 10 5 0.1mF 6 + ADS1230 7 8 AINP AINN GAIN CLKIN SPEED 9 REFN AGND 11 DGND 2, 4 GND 4 3 13 CAP 12 AVDD REFP CAP DRDY/DOUT SCLK PDWN 16 15 14 MSP430x4xx or Other Microprocessor 1 DVDD VDD Figure 31. Weigh Scale Application 20 Submit Documentation Feedback ADS1230 www.ti.com SBAS366 – OCTOBER 2006 SUMMARY OF SERIAL INTERFACE WAVEFORMS a) 20 Bits of Data Retrieval Data Ready MSB DRDY/DOUT 19 tPD tDS SCLK 1 tSCLK tCONV tSCLK 20 18 17 LSB 0 tHT tUPDATE Data New Data Ready b) 24 Bits of Data Retrieval Data Ready MSB DRDY/DOUT 19 tPD tDS SCLK 1 18 17 Data New Data Ready LSB 0 tHT tSCLK 20 tSCLK tCONV 21 22 23 24 tUPDATE 1 2 3 4 c) Data Retrieval with DRDY/DOUT Forced High Afterwards Data Ready Data New Data Ready DRDY/DOUT 19 18 17 0 SCLK 1 20 21 21st SCLK to Force DRDY/DOUT High d) Standby Mode/Single Conversions Standby Mode DRDY/DOUT 19 18 17 0 Data Ready Start Conversion 19 SCLK 1 tDSS 20 tSTANDBY tS_RDY Figure 32. Summary of Data Retrieval Waveforms Submit Documentation Feedback 21 ADS1230 www.ti.com SBAS366 – OCTOBER 2006 21st SCLK to Force DRDY/DOUT High a) Offset Calibration Timing DRDY/DOUT 19 18 17 0 1 2 3 4 Calibration Begins 19 Data Ready After Calibration SCLK 1 20 21 22 23 24 25 26 tCAL b) Standby Mode/Single Conversions DRDY/DOUT 19 18 17 0 Standby Mode Data Ready Start Conversion 19 SCLK 1 tDSS 20 tSTANDBY tS_RDY c) Standby Mode/Single Conversions with Offset Calibration DRDY/DOUT 19 18 17 0 1 2 3 4 Standby Mode Data Ready After Calibration Begin Calibration 25 tSTANDBY tSC_RDY 19 SCLK 1 20 21 22 23 24 Figure 33. Summary of Standby Mode and Calibration Waveforms 22 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 20-Nov-2006 PACKAGING INFORMATION Orderable Device ADS1230IPW ADS1230IPWR (1) Status (1) ACTIVE ACTIVE Package Type TSSOP TSSOP Package Drawing PW PW Pins Package Eco Plan (2) Qty 16 16 90 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,65 14 8 0,30 0,19 0,10 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0°– 8° 0,75 0,50 Seating Plane 1,20 MAX 0,15 0,05 0,10 PINS ** DIM A MAX 8 14 16 20 24 28 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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