ADS1230
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SBAS366B – OCTOBER 2006 – REVISED SEPTEMBER 2012
20-Bit Analog-to-Digital Converter
For Bridge Sensors
Check for Samples: ADS1230
FEATURES
DESCRIPTION
•
•
•
•
The ADS1230 is a precision 20-bit analog-to-digital
converter (ADC). With an onboard low-noise
programmable gain amplifier (PGA), onboard
oscillator, and precision 20-bit delta-sigma ADC, the
ADS1230 provides a complete front-end solution for
bridge sensor applications including weigh scales,
strain gauges, and pressure sensors.
1
2
•
•
•
•
•
•
•
•
•
Complete Front-End for Bridge Sensor
Onboard PGA with Gain of 64 or 128
Onboard Oscillator
RMS Noise:
40nV at 10SPS (G = 128)
88nV at 80SPS (G = 128)
18-Bit Noise-Free Resolution
Selectable 10SPS or 80SPS Data Rates
Simultaneous 50Hz and 60Hz Rejection at
10SPS
External Voltage Reference up to 5V for
Ratiometric Measurements
Simple, Pin-Driven Control
Two-Wire Serial Digital Interface
Tiny 16-pin TSSOP Package
Supply Range: 2.7V to 5.3V
–40°C to +85°C Temperature Range
APPLICATIONS
•
•
•
•
Weigh Scales
Strain Gauges
Pressure Sensors
Industrial Process Control
The low-noise PGA has a gain of 64 or 128,
supporting a full-scale differential input of ±39mV or
±19.5mV, respectively. The delta-sigma ADC has 20bit effective resolution and is comprised of a 3rdorder modulator and 4th-order digital filter. Two data
rates are supported: 10SPS (with both 50Hz and
60Hz rejection) and 80SPS. The ADS1230 can be
clocked by the internal oscillator or an external clock
source. Offset calibration is performed on-demand,
and the ADS1230 can be put in a low-power standby
mode or shut off completely in power-down mode.
All of the features of the ADS1230 are controlled by
dedicated pins; there are no digital registers to
program. Data are output over an easily-isolated
serial interface that connects directly to the MSP430
and other microcontrollers.
The ADS1230 is available in a TSSOP-16 package
and is specified from –40°C to +85°C.
AVDD
CAP
REFP REFN
DVDD
PDWN
Gain = 64 or 128
AINP
DRDY/DOUT
PGA
DS ADC
SCLK
AINN
SPEED
Internal
Oscillator
AGND
GAIN
CAP
CLKIN
DGND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2012, Texas Instruments Incorporated
ADS1230
SBAS366B – OCTOBER 2006 – REVISED SEPTEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
ADS1230
UNIT
AVDD to AGND
–0.3 to +6
V
DVDD to DGND
–0.3 to +6
V
AGND to DGND
–0.3 to +0.3
V
100, Momentary
mA
10, Continuous
mA
Analog Input Voltage to AGND
–0.3 to AVDD + 0.3
V
Digital Input Voltage to DGND
–0.3 to DVDD + 0.3
V
+150
°C
Operating Temperature Range
–40 to +85
°C
Storage Temperature Range
–60 to +150
°C
Input Current
Maximum Junction Temperature
(1)
2
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
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SBAS366B – OCTOBER 2006 – REVISED SEPTEMBER 2012
ELECTRICAL CHARACTERISTICS
All specifications at TA = –40°C to +85°C, AVDD = DVDD = REFP = +5V, REFN = AGND, and Gain = 64, unless otherwise noted.
ADS1230
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Analog Inputs
Full-Scale Input Voltage (AINP – AINN)
±0.5VREF/PGA
Common-Mode Input Range
AGND + 1.5V
Differential Input Current
V
AVDD – 1.5V
V
±2
nA
80
SPS
System Performance
Resolution
No Missing Codes
20
Internal Oscillator, SPEED = High
Internal Oscillator, SPEED = Low
Data Rate
Digital Filter Settling Time
Bits
10
SPS
External Oscillator, SPEED = High
fCLK/61,440
SPS
External Oscillator, SPEED = Low
fCLK/491,520
Full Settling
SPS
4
Conversions
Differential Input, End-Point Fit, G = 64
±10
Differential Input, End-Point Fit, G = 128
±6
ppm
±3
ppm of FS
Input Offset Drift
±10
nV/°C
Gain Error
±0.8
Integral Nonlinearity (INL)
Input Offset Error (1)
Gain Drift
Normal-Mode Rejection (2)
fIN = 50Hz or 60Hz ±1Hz,
fDATA = 10SPS
Common-Mode Rejection
at DC, AVDD = 0.1V
ppm/°C
80
90
dB
External Oscillator (3)
90
100
dB
fDATA = 80SPS
Power-Supply Rejection
%
±4
Internal Oscillator
fDATA = 10SPS
Input-Referred Noise
ppm
at DC, AVDD = 0.1V
110
dB
53
nV, rms
100
nV, rms
90
100
dB
1.5
AVDD
Voltage Reference Input
Voltage Reference Input (VREF)
AVDD + 0.1V
V
Negative Reference Input (REFN)
VREF = REFP – REFN
AGND – 0.1
REFP – 1.5
V
Positive Reference Input (REFP)
REFN + 1.5
AVDD + 0.1
Voltage Reference Input Current
V
10
nA
Digital
VIH
Logic Levels
All digital inputs except CLKIN
0.7 DVDD
DVDD + 0.1
V
CLKIN
0.7 DVDD
5.1
V
DGND
0.2 DVDD
V
VIL
VOH
IOH = 1mA
VOL
IOL = 1mA
Input Leakage
DVDD – 0.4
0 < VIN < DVDD
External Clock Input Frequency (fCLKIN)
V
μA
±10
0.2
Serial Clock Input Frequency (fSCLK)
(1)
(2)
(3)
V
0.2 DVDD
4.9152
6
MHz
5
MHz
Offset calibration can minimize these errors to the level of noise at any temperature.
Specification is assured by the combination of design and final production test.
External oscillator = 4.9152MHz.
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ADS1230
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = –40°C to +85°C, AVDD = DVDD = REFP = +5V, REFN = AGND, and Gain = 64, unless otherwise
noted.
ADS1230
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
5.3
V
Normal Mode, AVDD = 3V
900
1400
μA
Normal Mode, AVDD = 5V
900
1400
μA
Standby Mode
0.1
1
μA
Power-Down
0.1
1
μA
Normal Mode, DVDD = 3V
60
100
μA
Normal mode, DVDD = 5V
95
140
μA
Standby Mode, SCLK = High, DVDD = 3V
45
65
μA
Standby Mode, SCLK = High, DVDD = 5V
65
80
μA
Power-Down
0.2
Normal Mode, AVDD = DVDD = 3V
2.9
4.5
mW
Normal Mode, AVDD = DVDD = 5V
5.0
7.7
mW
Standby Mode, AVDD = DVDD = 5V
0.3
0.4
mW
Power Supply
Power-Supply Voltage (AVDD, DVDD)
Analog Supply Current
Digital Supply Current
Power Dissipation, Total
4
2.7
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μA
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SBAS366B – OCTOBER 2006 – REVISED SEPTEMBER 2012
PIN CONFIGURATION
PW PACKAGE
TSSOP-16
(Top View)
DVDD
1
16
DRDY/DOUT
DGND
2
15
SCLK
CLKIN
3
14
PDWN
GAIN
4
13
SPEED
ADS1230
CAP
5
12
AVDD
CAP
6
11
AGND
AINP
7
10
REFP
AINN
8
9
REFN
PIN DESCRIPTIONS
NAME
TERMINAL
ANALOG/DIGITAL
INPUT/OUTPUT
DVDD
1
Digital
Digital Power Supply: 2.7V to 5.3V
DGND
2
Digital
Digital Ground
CLKIN
3
Digital/Digital Input
DESCRIPTION
External Clock Input: typically 4.9152MHz. Tie low to activate internal oscillator.
PGA Gain Select
GAIN
4
Digital Input
GAIN
PGA
0
64
1
128
CAP
5
Analog
Gain Amp Bypass Capacitor Connection
CAP
6
Analog
Gain Amp Bypass Capacitor Connection
AINP
7
Analog Input
Positive Analog Input
AINN
8
Analog Input
Negative Analog Input
REFN
9
Analog Input
Negative Reference Input
REFP
10
Analog Input
Positive Reference Input
AGND
11
Analog
Analog Ground
AVDD
12
Analog
Analog Power Supply, 2.7V to 5.3V
Data Rate Select:
SPEED
DATA RATE
0
10SPS
1
80SPS
SPEED
13
Digital Input
PDWN
14
Digital Input
Power-Down: Holding this pin low powers down the entire converter and resets the ADC.
SCLK
15
Digital Input
Serial Clock: Clock out data on the rising edge. Also used to initiate Offset Calibration and Sleep
modes. See the Offset Calibration, Standby Mode, and Standby Mode with Offset Calibration sections
for more details.
DRDY/DOUT
16
Digital Output
Dual-Purpose Output:
Data Ready: Indicates valid data by going low.
Data Output: Outputs data, MSB first, on the first rising edge of SCLK.
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ADS1230
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NOISE PERFORMANCE
The ADS1230 offers outstanding noise performance. Table 1 summarizes the typical noise performance with
inputs shorted externally for different data rates and voltage reference values.
The RMS and Peak-to-Peak noise are referred to the input. The effective number of bits (ENOB) is defined as:
ENOB = ln (FSR/RMS noise)/ln(2)
The Noise-Free Bits are defined as:
Noise-Free Bits = ln (FSR/Peak-to-Peak Noise)/ln(2)
Where:
FSR (Full-Scale Range) = VREF/Gain.
Table 1. Noise Performance for AVDD = 5V and VREF = 5V
DATA RATE
10
80
(1)
GAIN
RMS NOISE
(nV)
PEAK-TO-PEAK NOISE (1)
(nV)
ENOB
(RMS)
NOISE-FREE BITS
64
53
290
20.5
18
128
40
198
19.8
17.5
64
100
480
19.5
17.3
128
88
480
18.7
16.3
Peak-to-peak data are based on direct measurement.
Table 2. Noise Performance for AVDD = 3V and VREF = 3V
DATA RATE
10
80
(1)
6
GAIN
RMS NOISE
(nV)
PEAK-TO-PEAK NOISE (1)
(nV)
ENOB
(RMS)
NOISE-FREE BITS
64
46
290
20.6
18
128
49
259
19.6
17.2
64
100
576
19.5
17
128
102
461
18.5
16.3
Peak-to-peak data are based on direct measurement.
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TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = DVDD = REFP = 5V, and REFN = AGND, unless otherwise noted.
NOISE PLOT
NOISE PLOT
3
PGA = 64
Data Rate = 10SPS
PGA = 64
Data Rate = 80SPS
2
1
3
Output Code (LSB)
Output Code (LSB)
4
2
1
0
-1
-2
-3
-4
-5
0
-6
0
200
400
600
800
1000
0
200
Figure 2.
NOISE HISTOGRAM
PGA = 64
Data Rate = 10SPS
350
PGA = 64
Data Rate = 80SPS
300
600
Occurrence
Occurrence
1000
400
700
500
400
300
250
200
150
100
200
50
100
0
0
1
2
3
-5
-4
-3
Output Code (LSB)
-2
-1
0
1
2
Output Code (LSB)
Figure 3.
Figure 4.
NOISE PLOT
NOISE PLOT
8
PGA = 128
Data Rate = 10SPS
PGA = 128
Data Rate = 80SPS
6
-1
4
Output Code (LSB)
Output Code (LSB)
800
Figure 1.
NOISE HISTOGRAM
0
600
Time (Reading Number)
900
800
400
Time (Reading Number)
-2
-3
-4
2
0
-2
-4
-6
-5
-8
-6
-10
0
200
400
600
800
1000
0
200
400
600
Time (Reading Number)
Time (Reading Number)
Figure 5.
Figure 6.
800
1000
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ADS1230
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = REFP = 5V, and REFN = AGND, unless otherwise noted.
NOISE HISTOGRAM
NOISE HISTOGRAM
500
250
PGA = 128
Data Rate = 10SPS
450
PGA = 128
Data Rate = 80SPS
400
200
Occurrence
Occurrence
350
300
250
200
150
100
150
100
50
50
0
0
-5
-4
-3
-2
0
-1
-7 -6 -5 -4 -3 -2 -1 0
Output Code (LSB)
Figure 8.
OFFSET
vs
TEMPERATURE
GAIN ERROR
vs
TEMPERATURE
-0.02
800
600
Gain Error (%)
Offset (nV)
200
0
-200
5
6
7
PGA = 64
Data Rate = 10SPS
-0.04
PGA = 64
Data Rate = 10SPS
-0.06
-800
-50
0
-25
25
50
75
100
-50
0
-25
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 9.
Figure 10.
NOISE
vs
INPUT SIGNAL
NOISE
vs
INPUT SIGNAL
50
120
PGA = 64
Data Rate = 80SPS
45
40
100
35
RMS Noise (nV)
RMS Noise (nV)
4
-0.05
-400
30
25
20
15
80
60
10
PGA = 64
Data Rate = 10SPS
0
40
-40
-30
-20
-10
0
10
20
30
40
-40
VIN (mV)
-30
-20
-10
0
10
20
30
40
VIN (mV)
Figure 11.
8
3
-0.03
400
5
2
Figure 7.
1000
-600
1
Output Code (LSB)
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DVDD = REFP = 5V, and REFN = AGND, unless otherwise noted.
INTEGRAL NONLINEARITY
vs
INPUT SIGNAL
INTEGRAL NONLINEARITY
vs
INPUT SIGNAL
10
1.0
-20°C
+25°C
5
0
-20°C
INL (ppm)
INL (ppm)
0.5
+70°C
0
+85°C
-0.5
-40°C
-1.0
+25°C
-5
-1.5
PGA = 64
Data Rate = 10SPS
PGA = 128
Data Rate = 10SPS
-40°C
-10
+70°C
+85°C
-2.0
-40
-30
-20
-10
0
10
20
30
40
-20
0
-10
VIN (mV)
10
20
VIN (mV)
Figure 13.
Figure 14.
ANALOG CURRENT
vs
TEMPERATURE
(Normal Mode)
DIGITAL CURRENT
vs
TEMPERATURE
(Normal Mode)
97
1200
96
95
PGA = 64, 128
Digital Current (mA)
Analog Current (mA)
1000
800
600
400
94
93
92
PGA = 128
91
90
200
89
PGA = 64
88
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 15.
Figure 16.
DATA RATE
vs
TEMPERATURE
Data Rate (SPS)
9.85
9.80
9.75
9.70
-50
-25
0
25
50
75
100
Temperature (°C)
Figure 17.
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ADS1230
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OVERVIEW
The ADS1230 is a precision, 20-bit ADC that includes
a low-noise PGA, internal oscillator, third-order deltasigma (ΔΣ) modulator, and fourth-order digital filter.
The ADS1230 provides a complete front-end solution
for bridge sensor applications such as weigh scales,
strain guages, and pressure sensors.
Clocking can be supplied by an external clock or by a
precision internal oscillator. Data can be output at
10SPS for excellent 50Hz and 60Hz rejection, or at
80SPS when higher speeds are needed. The
ADS1230 is easy to configure, and all digital control
is accomplished through dedicated pins; there are no
registers to program. A simple two-wire serial
interface retrieves the data.
input ranges from 0mV to +39mV (Gain = 64) or 0mV
to +19.5mV (Gain = 128). The inputs of the ADS1230
are protected with internal diodes connected to the
power-supply rails. These diodes clamp the applied
signal to prevent it from damaging the input circuitry.
CAP
450W
18pF
A1
R
Gain = 1 or 2
F1
R1
A3
RF2
ADC
RINT
ANALOG INPUTS (AINP, AINN)
A2
450W
The input signal to be measured is applied to the
input pins AINP and AINN. The ADS1230 accepts
differential input signals, but can also measure
unipolar signals. When measuring unipolar (or singleended signals) with respect to ground, connect the
negative input (AINN) to ground and connect the
input signal to the positive input (AINP). Note that
when the ADS1230 is configured this way, only half
of the converter full-scale range is used, since only
positive digital output codes are produced.
LOW-NOISE PGA
The ADS1230 features a low-drift, low-noise PGA
that provides a complete front-end solution for bridge
sensors. A simplified diagram of the PGA is shown in
Figure 18. It consists of two chopper-stabilized
amplifiers (A1 and A2) and three accurately-matched
resistors (R1, RF1, and RF2), which construct a
differential front-end stage with a gain of 64, followed
by gain stage A3 (Gain = 1 or 2). The PGA inputs are
equipped with an EMI filter, as shown in Figure 18.
The cutoff frequency of the EMI filter is 19.6MHz. By
using AVDD as the reference input, the bipolar input
ranges from –39mV to +39mV (Gain = 64) or
–19.5mV to +19.5mV (Gain = 128), and the unipolar
10
RINT
AINP
AINN
18pF
CAP
Figure 18. Simplified Diagram of the PGA
Bypass Capacitor
By applying a 0.1μF external capacitor (CEXT) across
two capacitor pins combined with the internal 2kΩ
resistor RINT (on-chip), a low-pass filter with a corner
frequency of 720Hz is created to bandlimit the signal
path before the modulator input. This low-pass filter
serves two purposes. First, the input signal is
bandlimited to prevent aliasing as well as to filter out
the high-frequency noise. Second, it attenuates the
chopping residue from the amplifier to improve
temperature drift performance. It is not required to
use high-quality capacitors (such as ceramic or
tantalum capacitors) for a general application.
However, high-quality capacitors such as poly are
recommended for high-linearity applications.
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VOLTAGE REFERENCE INPUTS
(REFP, REFN)
The voltage reference used by the modulator is
generated from the voltage difference between REFP
and REFN: VREF = REFP – REFN. The reference
inputs use a structure similar to that of the analog
inputs. In order to increase the reference input
impedance, a switching buffer circuitry is used to
reduce the input equivalent capacitance. The
reference drift and noise impact ADC performance. In
order to achieve best results, pay close attention to
the reference noise and drift specifications. A
simplified diagram of the circuitry on the reference
inputs is shown in Figure 19. The switches and
capacitors can be modeled approximately using an
effective impedance of:
1
Z EFF +
2f MODC BUF
Where:
fMOD = modulator sampling frequency (76.8kHz)
CBUF = input capacitance of the buffer
ESD diodes protect the reference inputs. To prevent
these diodes from turning on, make sure the voltages
on the reference pins do not go below GND by more
than 100mV, and likewise, do not exceed AVDD by
100mV:
GND – 100mV < (REFP or REFN) < AVDD + 100mV
CLOCK SOURCES
The ADS1230 can use an external clock source or
internal oscillator to accommodate a wide variety of
applications. Figure 20 shows the equivalent circuitry
of the clock source. The CLK_DETECT block
determines whether the crystal oscillator/external
clock signal is applied to the CLKIN pin so that the
internal oscillator is bypassed or activated. When the
CLKIN pin frequency is above ~200kHz, the
CLK_DETECT output goes low and shuts down the
internal oscillator. When the CLKIN pin frequency is
below ~200kHz, the CLK_DETECT output goes high
and activates the internal oscillator. It is highly
recommended to hard-wire the CLKIN pin to ground
when the internal oscillator is chosen.
For the ADS1230:
1
Z EFF +
+ 500MW
(2)(76.8kHz)(13fF)
CLKIN
REFP
CLK_DETECT
REFN
Internal
Oscillator
S0
S1
MUX
AVDD
AVDD
EN
S
To ADC
ESD
Protection
CBUF
ZEFF = 500MW(1)
(1) fMOD = 76.8kHz
Figure 19. Simplified Reference Input Circuitry
Figure 20. Equivalent Circuitry of the Clock
Source
An external clock may be used by driving the CLKIN
pin directly. The Electrical Characteristics table shows
the allowable frequency range. The clock input may
be driven with 5V logic, regardless of the DVDD or
AVDD voltage.
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FREQUENCY RESPONSE
0
Data Rate = 10SPS
4
-50
Gain (dB)
The ADS1230 uses a sinc digital filter with the
frequency response (fCLK = 4.9152MHz) shown in
Figure 21. The frequency response repeats at
multiples of the modulator sampling frequency of
76.8kHz. The overall response is that of a low-pass
filter with a –3dB cutoff frequency of 3.32Hz with the
SPEED pin tied low (10SPS data rate) and 11.64Hz
with the SPEED pin tied high (80SPS data rate).
-100
0
fCLK = 4.9152MHz
-20
-150
0
-40
20
30
40
50
60
70
80
90
100
Frequency (Hz)
-60
Gain (dB)
10
(a)
-80
-100
-50
-120
Data Rate = 10SPS
-140
-180
-200
0
38.4
76.8
Frequency (kHz)
Gain (dB)
-160
-100
Figure 21. Frequency Response
To help see the response at lower frequencies,
Figure 22(a) illustrates the response out to 100Hz,
when the data rate = 10SPS. Notice that signals at
multiples of 10Hz are rejected, and therefore
simultaneous rejection of 50Hz and 60Hz is achieved.
The benefit of using a sinc4 filter is that every
frequency notch has four zeros on the same location.
This response, combined with the low drift internal
oscillator, provides an excellent normal-mode
rejection of line-cycle interference.
Figure 22(b) shows the same plot, but zooms in on
the 50Hz and 60Hz notches with the SPEED pin tied
low (10SPS data rate). With only a ±3% variation of
the internal oscillator, over 100dB of normal-mode
rejection is achieved.
12
-150
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Frequency (Hz)
(b)
Figure 22. Frequency Response Out To 100Hz
The ADS1230 data rate and frequency response
scale directly with clock frequency. For example, if
fCLK increases from 4.9152MHz to 6.144MHz when
the SPEED pin is tied high, the data rate increases
from 80SPS to 100SPS, while notches also increase
from 80Hz to 100Hz. Note that these changes are
only possible when the external clock source is
applied.
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SETTLING TIME
DATA FORMAT
In certain instances, large changes in input will
require settling time. For example, an external
multiplexer in front of the ADS1230 can put large
changes in input voltage by simply switching the
multiplexer input channels. Abrupt changes in the
input will require four data conversion cycles to settle.
When continuously converting, five readings may be
necessary in order to settle the data. If the change in
input occurs in the middle of the first conversion, four
more full conversions of the fully-settled input are
required to get fully-settled data. Discard the first four
readings because they contain only partially-settled
data. Figure 23 illustrates the settling time for the
ADS1230 in Continuous Conversion mode.
The ADS1230 outputs 20 bits of data in binary two’s
complement format. The least significant bit (LSB)
has a weight of 0.5VREF/(219 – 1). The positive fullscale input produces an output code of 7FFFFh and
the negative full-scale input produces an output code
of 800000h. The output clips at these codes for
signals exceeding full-scale. Table 4 summarizes the
ideal output codes for different input signals.
The ADS1230 is a 20-bit ADC. After data conversion
is completed, applying 20 SCLKs retrieves 20 bits of
data (MSB first). However, if the SCLKs continue to
be applied after 20 bits of data are retrieved, the
DOUT pin outputs four 1s for the 21st through the
24th SCLK, as shown in Figure 24.
DATA RATE
Table 4. Ideal Output Code vs Input Signal
The ADS1230 data rate is set by the SPEED pin, as
shown in Table 3. When SPEED is low, the data rate
is nominally 10SPS. This data rate provides the
lowest noise, and also has excellent rejection of both
50Hz and 60Hz line-cycle interference. For
applications requiring fast data rates, setting SPEED
high selects a data rate of nominally 80SPS.
Table 3. Data Rate Settings
INPUT SIGNAL VIN
(AINP – AINN)
IDEAL OUTPUT
≥ +0.5VREF/Gain
7FFFFh
19
– 1)
00001h
0
00000h
(–0.5VREF/Gain)/(219 – 1)
FFFFFh
≤ –0.5VREF/Gain
80000h
(+0.5VREF/Gain)/(2
(1)
Excludes effects of noise, INL, offset, and
gain errors.
DATA RATE
SPEED
PIN
Internal Oscillator
or 4.9152MHz Crystal
External
Oscillator
0
10SPS
fCLKIN / 491,520
1
80SPS
fCLKIN / 61,440
Abrupt Change in External VIN
VIN
2nd Conversion;
VIN settled, but
digital filter
unsettled.
1st Conversion;
includes
unsettled VIN.
Start of
Conversion
DRDY/DOUT
4th Conversion;
VIN settled, but
digital filter
unsettled.
3rd Conversion;
VIN settled, but
digital filter
unsettled.
5th Conversion;
VIN and digital
filter both
settled.
Conversion
Time
Figure 23. Settling Time in Continuous Conversion Mode
Data
New Data Ready
Data Ready
MSB
DRDY/DOUT
SCLK
LSB
19
18
1
2
17
3
0
20
1
21
2
22
4
3
23
24
Figure 24. Data Retrieval Format
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ADS1230
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DATA READY/DATA OUTPUT (DRDY/DOUT)
DATA RETRIEVAL
This digital output pin serves two purposes. First, it
indicates when new data are ready by going low.
Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins
outputting the conversion data, most significant bit
(MSB) first. Data are shifted out on each subsequent
SCLK rising edge. After all 20 bits have been
retrieved, the pin can be forced high with an
additional SCLK. It then stays high until new data are
ready. This configuration is useful when polling on the
status of DRDY/DOUT to determine when to begin
data retrieval.
The ADS1230 continuously converts the analog input
signal. To retrieve data, wait until DRDY/DOUT goes
low, as shown in Figure 25. After DRDY/DOUT goes
low, begin shifting out the data by applying SCLKs.
Data are shifted out MSB first. It is not required to
shift out all 20 bits of data, but the data must be
retrieved before new data are updated (within tCONV)
or else the data will be overwritten. Avoid data
retrieval during the update period (tUPDATE). If 24
SCLKs have been applied, DRDY/DOUT will be high
since the last four bits have been appended by '1'.
However, if only 20 SCLKs have been applied,
DRDY/DOUT remains at the state of the last bit
shifted out until it is taken high (see tUPDATE),
indicating that new data are being updated. To avoid
having DRDY/DOUT remain in the state of the last
bit, the 21st SCLK can be applied to force
DRDY/DOUT high, as shown in Figure 26. This
technique is useful when a host controlling the device
is polling DRDY/DOUT to determine when data are
ready.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising
edge. This input has built-in hysteresis, but care
should still be taken to ensure a clean signal. Glitches
or slow-rising signals can cause unwanted additional
shifting. For this reason, it is best to make sure the
rise and fall times of SCLK are both less than 50ns.
14
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Data
a) 20 Bits of Data Retrieval
New Data Ready
Data Ready
MSB
DRDY/DOUT
LSB
19
17
18
0
tPD
tHT
tDS
tSCLK
tUPDATE
1
SCLK
20
tSCLK
tCONV
Data
b) 24 Bits of Data Retrieval
Data Ready
New Data Ready
MSB
DRDY/DOUT
LSB
19
18
17
0
4
tHT
tPD
tDS
tUPDATE
tSCLK
1
SCLK
3
2
1
20
21
22
23
24
tSCLK
tCONV
Figure 25. Data Retrieval Timing
SYMBOL
tDS
tSCLK
DESCRIPTION
MIN
DRDY/DOUT low to first SCLK rising edge
SCLK positive or negative pulse width
SCLK rising edge to new data bit valid: propagation delay
tHT
SCLK rising edge to old data bit valid: hold time
0
Data updating: no readback allowed
39
tCONV
(1)
MAX
Conversion time (1/data rate)
UNITS
ns
100
tPD
tUPDATE
TYP
0
ns
50
ns
ns
μs
SPEED = 1
12.5
ms
SPEED = 0
100
ms
Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period.
Data
Data Ready
New Data Ready
DRDY/DOUT
19
18
17
1
SCLK
0
20
21
21st SCLK to Force DRDY/DOUT High
Figure 26. Data Retrieval with DRDY/DOUT Forced High Afterwards
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ADS1230
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OFFSET CALIBRATION
During this time, the analog input pins are
disconnected within the ADC and the appropriate
signal is applied internally to perform the calibration.
When the calibration is completed, DRDY/DOUT
goes low, indicating that new data are ready. The first
conversion after a calibration is fully settled and valid
for use. The offset calibration takes exactly the same
time as specified in (tCAL) immediately after the falling
edge of the 26th SCLK.
Offset calibration can be initiated at any time to
remove the ADS1230 inherited offset error. To initiate
offset calibration, apply at least two additional SCLKs
after retrieving 20 bits of data plus four bits of '1'.
Figure 27 shows the timing pattern. The 25th SCLK
keeps DRDY/DOUT high. The falling edge of the 26th
SCLK begins the calibration cycle. Additional SCLK
pulses may be sent after the 26th SCLK; however,
activity on SCLK should be minimized during offset
calibration for best results.
Data Ready After Calibration
DRDY/DOUT
19
18
17
0
1
2
3
19
4
Calibration Begins
SCLK
20
1
21
22
23
24
25
26
tCAL
Figure 27. Offset-Calibration Timing
SYMBOL
tCAL
(1)
16
(1)
DESCRIPTION
First data ready after calibration
MIN
MAX
UNITS
SPEED = 1
101.28
101.29
ms
SPEED = 0
801.02
801.03
ms
Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
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STANDBY MODE
When tSTANDBY has passed with SCLK held high,
Standby mode activates. DRDY/DOUT stays high
when Standby mode begins. SCLK must remain high
to stay in Standby mode. To exit Standby mode
(wakeup), set SCLK low. The first data after exiting
Standby mode is valid.
Standby
mode
dramatically
reduces
power
consumption by shutting down most of the circuitry. In
Standby mode, the entire analog circuitry is powered
down and only the clock source circuitry is awake to
reduce the wake-up time from the Standby mode. To
enter Standby mode, simply hold SCLK high after
DRDY/DOUT goes low; see Figure 28. Standby mode
can be initiated at any time during readback; it is not
necessary to retrieve all 20 bits of data beforehand.
Data Ready
Standby Mode
DRDY/DOUT
SCLK
19
18
17
0
1
Start Conversion
19
20
tDSS
tSTANDBY
tS_RDY
Figure 28. Standby Mode Timing (can be used for single conversions)
SYMBOL
tDSS
(1)
tSTANDBY
tS_RDY
(1)
(1)
(1)
DESCRIPTION
MIN
MAX
UNITS
SCLK high after DRDY/DOUT goes low SPEED = 1
to activate Standby mode
SPEED = 0
0
12.44
ms
0
99.94
ms
SPEED = 1
20
SPEED = 0
20
SPEED = 1
52.51
52.51
ms
SPEED = 0
401.8
401.8
ms
Standby mode activation time
Data ready after exiting Standby mode
μs
μs
Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
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ADS1230
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STANDBY MODE WITH OFFSETCALIBRATION
To force an offset-calibration with Standby mode, shift
25 SCLKs and bring the SCLK pin high to enter
Standby mode. Offset-calibration then begins after
wake-up; Figure 29 shows the appropriate timing.
Note the extra time needed after wake-up for
calibration before data are ready. The first data after
Standby mode with offset-calibration is fully settled
and can be used right away.
Offset-calibration can be set to run immediately after
exiting Standby mode. This option is useful when the
ADS1230 is put in Standby mode for long periods of
time, and offset-calibration is desired afterwards to
compensate for temperature or supply voltage
changes.
Standby
Mode
DRDY/DOUT
SCLK
19
18
17
0
1
20
1
21
2
22
3
23
Begin
Calibration
4
24
Data Ready
After Calibration
19
25
tSTANDBY
tSC_RDY
Figure 29. Standby Mode with Offset-Calibration Timing (can be used for single conversions)
SYMBOL
tSC_RDY
(1)
18
(1)
DESCRIPTION
Data ready after exiting Standby mode
and calibration
MIN
MAX
UNITS
SPEED = 1
103
103
ms
SPEED = 0
803
803
ms
Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
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SBAS366B – OCTOBER 2006 – REVISED SEPTEMBER 2012
POWER-UP SEQUENCE
blank
When powering up the ADS1230, AVDD and DVDD
must be powered up before the PDWN pin goes high,
as shown in Figure 30. If PDWN is not controlled by a
microprocessor, a simple RC delay circuit must be
implemented, as shown in Figure 31.
AVDD
DVDD
PDWN
³ 10ms
POWER-DOWN MODE
Power-Down mode shuts down the entire ADC
circuitry and reduces the total power consumption
close to zero. To enter Power-Down mode, simply
hold the PDWN pin low. Power-Down mode also
resets the entire circuitry to free the ADC circuitry
from locking up to an unknown state. Power-Down
mode can be initiated at any time during readback; it
is not necessary to retrieve all 20 bits of data
beforehand. Figure 32 shows the wake-up timing
from Power-Down mode.
Figure 30. Power-Up Timing Sequence
DVDD(1)
1.2kW
2.2nF
blank
Connect to
ADS1230
PDWN pin
NOTE: (1) AVDD must be powered up at least 10ms
before PDWN goes high.
blank
blank
Figure 31. RC Delay Circuit
Start
Conversion
Power-Down Mode
tPDWN
Data Ready
CLK Source
Wakeup
PDWN
DRDY/DOUT
tTS_RDY
tWAKEUP
SCLK
Figure 32. Wake-Up Timing from Power-Down Mode
SYMBOL
tWAKEUP
tPDWN
(1)
(1)
DESCRIPTION
Wake-up time after Power-Down
mode
MIN
TYP
UNITS
Internal clock
7.95
μs
External clock
0.16
μs
PDWN pulse width
26
μs
Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
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ADS1230
SBAS366B – OCTOBER 2006 – REVISED SEPTEMBER 2012
www.ti.com
FS
ǒFS
Ǔ
APPLICATION EXAMPLES
LC
Noise−Free Counts + ǒ2 BITEffǓ
Weigh Scale System
Figure 33 shows a typical ADS1230 hook-up as part
of a weigh scale system. In this setup, the ADS1230
is configured at a 10SPS data rate. Note that the
internal oscillator is used by grounding the CLKIN pin.
The user can also apply a 4.9152MHz clock to the
CLKIN pin. For a typical 2mV/V load cell, the
maximum output signal is approximately 10mV for a
single +5V excitation voltage. The ADS1230 can
achieve 17.5 noise-free bits at 10SPS when
PGA
=
128.
With
the
extra
software
filtering/averaging
(typically
done
by
a
microprocessor), an extra bit can be expected.
AD
Where:
BITEFF = effective noise-free bits (17.5 + 1 bit
from software filtering/averaging)
FSLC = full-scale output of the load cell (10mV)
FSAD = full-scale input of the ADS1230 (39mV,
when PGA = 128)
Therefore:
With +5V supply voltage, 95,058 noise-free counts
can be expected from the ADS1230.
2.7V to 5.3V
3V
0.1mF
12
1
AVDD
10
5
CAP
DRDY/DOUT
6
SCLK
CAP
+
ADS1230
7
8
VDD
DVDD
REFP
0.1mF
-
Ǔ
ǒ
Noise−Free Counts + ǒ2 (17.5)1)Ǔ 10mV + 95, 058
39mV
PDWN
16
15
14
MSP430x4xx
or Other
Microprocessor
AINP
AINN
GAIN
CLKIN
SPEED
4
3
13
9
REFN
AGND
11
GND
DGND
2, 4
Figure 33. Weigh Scale Application
20
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SBAS366B – OCTOBER 2006 – REVISED SEPTEMBER 2012
SUMMARY OF SERIAL INTERFACE WAVEFORMS
Data
a) 20 Bits of Data Retrieval
New Data Ready
Data Ready
MSB
DRDY/DOUT
LSB
19
17
18
0
tPD
tHT
tDS
tSCLK
tUPDATE
1
SCLK
20
tSCLK
tCONV
Data
b) 24 Bits of Data Retrieval
Data Ready
New Data Ready
MSB
DRDY/DOUT
LSB
19
18
0
17
3
2
1
4
tHT
tPD
tDS
tUPDATE
tSCLK
1
SCLK
20
21
22
23
24
tSCLK
tCONV
c) Data Retrieval with DRDY/DOUT Forced High Afterwards
Data
Data Ready
New Data Ready
DRDY/DOUT
19
18
17
0
1
SCLK
20
21
21st SCLK to Force DRDY/DOUT High
d) Standby Mode/Single Conversions
Data Ready
Standby Mode
DRDY/DOUT
SCLK
19
18
17
1
0
Start Conversion
19
20
tDSS
tSTANDBY
tS_RDY
Figure 34. Summary of Data Retrieval Waveforms
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ADS1230
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21st SCLK to Force DRDY/DOUT High
Data Ready After Calibration
a) Offset Calibration Timing
DRDY/DOUT
18
19
17
0
1
2
3
19
4
Calibration Begins
1
SCLK
21
20
22
23
24
25
26
tCAL
b) Standby Mode/Single Conversions
DRDY/DOUT
19
SCLK
18
17
0
1
Start Conversion
tSTANDBY
tS_RDY
Standby
Mode
c) Standby Mode/Single Conversions with Offset Calibration
SCLK
19
19
20
tDSS
DRDY/DOUT
Data Ready
Standby Mode
18
1
17
0
20
1
21
2
22
3
23
Begin
Calibration
4
24
Data Ready
After Calibration
19
25
tSTANDBY
tSC_RDY
Figure 35. Summary of Standby Mode and Calibration Waveforms
22
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SBAS366B – OCTOBER 2006 – REVISED SEPTEMBER 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2007) to Revision B
•
Page
Deleted "Not recommended for new design" watermark from entire document ................................................................... 1
Changes from Original (October 2006) to Revision A
Page
•
Deleted min and max values for Data Rate Internal Oscillator ............................................................................................. 3
•
Changed Normal Mode Rejection format and added min values ......................................................................................... 3
•
Changed Voltage Reference Input section ......................................................................................................................... 11
•
Changed Figure 19 ............................................................................................................................................................. 11
•
Deleted second sentence of Serial Clock Input (SCLK) section ........................................................................................ 14
•
Added Power-Up Sequence section with new text and two new figures (Figure 30 and Figure 31) ................................. 19
•
Changed Figure 33 ............................................................................................................................................................. 20
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ADS1230IPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1230
Samples
ADS1230IPWG4
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1230
Samples
ADS1230IPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1230
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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