ADS1259QPWRQ1

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software ADS1259-Q1 SLASE20 – MARCH 2014 ADS1259-Q1 Automotive, 14.4-kSPS, 24-Bit Analog-to-Digital Converter With Integrated Low-Drift Reference 1 Features 3 Description • • The ADS1259-Q1 is a precision, low-drift, 24-bit, analog-to-digital converter (ADC). The device can perform conversions at data rates up to 14.4 kSPS with high resolution and is therefore ideally suited to measure rapidly changing signals that have a wide dynamic range. An integrated low-noise, low-drift 2.5-V reference eliminates the need for an external voltage reference, thus reducing system cost and component count. 1 • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified with the Following Results: – Temperature Grade 1: –40°C to 125°C – HBM ESD Classification 2 – CDM ESD Classification C4B Programmable Data Rates: 10 SPS to 14.4 kSPS Single-Cycle Settling Digital Filter High Performance: – 21.3 ENOB at 1.2 kSPS – INL: 3 ppm – Offset Drift: 0.05 μV/°C – Gain Drift: 0.5 ppm/°C Internal Reference: 2.5 V, 10 ppm/°C Drift Internal 2% Accurate Oscillator Input Signal Out-of-Range Detection Optional Checksum and Redundant Data-Read Capability to Augment Data Integrity SPI™-Compatible Interface, Mode 1 Analog Supply: 5 V or ±2.5 V Digital Supply: 2.7 V to 5 V The converter uses a fourth-order, inherently stable, delta-sigma (ΔΣ) modulator that provides outstanding noise performance and linearity. The device can use the integrated oscillator, an external crystal, or an external clock as the ADC clock source. A fast-responding input overrange detector flags the conversion data if an input overrange event occurs. To augment data integrity in noisy automotive environments the ADS1259-Q1 offers an optional checksum byte and a redundant conversion dataread capability. The ADS1259-Q1 consumes 13 mW during operation and less than 25 μW when powered down. TI offers the ADS1259-Q1 device in a TSSOP-20 package with full specification from –40°C to 125°C. Device Information 2 Applications • • ORDER NUMBER Automotive Power Train Electrical Vehicles ADS1259QPWRQ1 PACKAGE TSSOP (20) BODY SIZE 6,5 mm × 4,4 mm Space Space Space ADS1259-Q1 Simplified Block Diagram AVDD AINP REFP REFN DS Modulator AINN REFOUT SYNCOUT DVDD 2.5-V Reference fCLK / 8 Clock Generator Programmable Digital Filter Calibration Engine START DRDY SCLK DIN DOUT CS ADS1259-Q1 AVSS XTAL2 RESET/PWDN Control and Serial Interface Out-of-Range Detection XTAL1/CLKIN DGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS1259-Q1 SLASE20 – MARCH 2014 www.ti.com Table of Contents 1 2 3 4 5 6 Features ................................................................. Applications .......................................................... Description ............................................................ Revision History ................................................... Terminal Configuration and Functions ............... Specifications ........................................................ 6.4 Thermal Information ................................................. 5 6.5 Electrical Characteristics .......................................... 6 1 1 1 2 3 4 7 8 6.1 Absolute Maximum Ratings ..................................... 4 6.2 Handling Ratings ...................................................... 4 6.3 Recommended Operating Conditions ...................... 5 9 Residue .................................................................. 7 Device Documentation and Support ................... 8 8.1 Trademarks .............................................................. 8 8.2 Electrostatic Discharge Caution ............................... 8 8.3 Glossary ................................................................... 8 Mechanical, Packaging, and Orderable Information ............................................................ 9 4 Revision History 2 DATE REVISION NOTES March 2014 * Initial release Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: ADS1259-Q1 ADS1259-Q1 www.ti.com SLASE20 – MARCH 2014 5 Terminal Configuration and Functions 20-Terminal TSSOP PW Package (Top View) AINP 1 20 AVDD AINN 2 19 AVSS RESET/PWDN 3 18 REFN START 4 17 REFP SYNCOUT 5 16 REFOUT CS 6 15 DVDD SCLK 7 14 DGND DIN 8 13 BYPASS DOUT 9 12 XTAL2 DRDY 10 11 XTAL1/CLKIN Terminal Functions TERMINAL NO. (1) TYPE NAME DESCRIPTION 1 AINP Analog input Positive analog input 2 AINN Analog input Negative analog input 3 RESET/PWDN Digital input Reset or power down; reset is active-low; hold low for power down. 4 START Digital input Start conversions, active-high 5 SYNCOUT 6 CS Digital input SPI chip-select, active-low 7 SCLK Digital input SPI clock input 8 DIN Digital input SPI data input 9 DOUT Digital output SPI data output 10 DRDY Digital output Data-ready output, active-low 11 XTAL1/CLKIN 12 XTAL2 Digital External crystal2, otherwise no connection 13 BYPASS Analog Core voltage bypass. Connect a 1-µF capacitor to DGND. 14 DGND Digital Digital ground 15 DVDD Digital Digital power supply 16 REFOUT 17 REFP Analog input Positive reference input. Connect a 1-µF capacitor, CREFIN, to REFN. (1) 18 REFN Analog input Negative reference input (1) 19 AVSS Analog Negative analog power supply and negative internal reference output 20 AVDD Analog Positive analog power supply Digital output Digital input Analog output Sync clock output (f(CLK) / 8) Internal oscillator: DGND External clock: clock input Crystal oscillator: external crystal1 Positive internal reference output. Connect a 1-µF capacitor, CREFOUT, to AVSS. Leave unused reference inputs unconnected or tie to AVDD. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: ADS1259-Q1 3 ADS1259-Q1 SLASE20 – MARCH 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating ambient temperature range (unless otherwise noted) MIN MAX AVDD to AVSS –0.3 7 UNIT V AVSS to DGND –2.8 0.3 V DVDD to DGND –0.3 7 V Analog input voltage AINN, AINP, REFN, REFP AVSS – 0.3 AVDD + 0.3 V Digital input voltage CS, DIN, RESET/PDWN, SCLK, START, XTAL1/CLKIN DGND – 0.3 DVDD + 0.3 V Input current, continuous Any terminal except supply terminals –10 10 mA –40 150 °C Operating junction temperature, TJ (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) (1) (2) 4 MIN MAX UNIT –60 150 °C Human-body model (HBM) ESD stress voltage (2) –2 2 kV Charged-device model (CDM) ESD stress voltage (2) –1 1 kV Electrostatic discharge (ESD) to measure device sensitivity or immunity to damage caused by assembly-line electrostatic discharges into the device. Meets or exceeds the passing level per AEC-Q100. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: ADS1259-Q1 ADS1259-Q1 www.ti.com SLASE20 – MARCH 2014 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY Analog power supply Digital power supply AVDD to AVSS 4.75 5.0 5.25 V AVSS to DGND –2.6 –2.5 0 V DVDD to DGND 2.7 3.3 5.25 V ANALOG INPUTS Absolute input voltage AINP or AINN AVSS – 0.1 AVDD + 0.1 V Differential input voltage (1) V(IN) = (V(AINP) – V(AINN)) –Vref Vref V Reference input voltage Vref = (V(REFP) – V(REFN)) 0.5 2.5 AVDD – AVSS + 0.2 V Absolute negative reference voltage REFN AVSS – 0.1 AVSS REFP – 0.5 V Absolute positive reference voltage REFP REFN + 0.5 AVSS + 2.5 AVDD + 0.1 V 2 7.3728 8 MHz Frequency 0.1 7.3728 8 MHz Duty cycle 40% VOLTAGE REFERENCE INPUTS EXTERNAL CLOCK SOURCES (f(CLK)) Crystal oscillator Frequency External clock 60% DIGITAL INPUTS High-level input voltage, VIH Low-level input voltage, VIL 0.8 DVDD DVDD V DGND 0.2 DVDD V –40 125 °C TEMPERATURE RANGE Operating ambient temperature, TA (1) Excluding the effects of offset and gain error. 6.4 Thermal Information THERMAL METRIC (1) PW (20 TERMINALS) UNIT 86.9 °C/W 21 °C/W RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance 39.1 °C/W ψJT Junction-to-top characterization parameter 0.8 °C/W ψJB Junction-to-board characterization parameter 38.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: ADS1259-Q1 5 ADS1259-Q1 SLASE20 – MARCH 2014 www.ti.com 6.5 Electrical Characteristics Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, external f(CLK) = 7.3728 MHz, external Vref = 2.5 V, and f(DATA) = 60 SPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Differential input impedance 120 kΩ Common-mode input impedance 500 kΩ SYSTEM PERFORMANCE Resolution (no missing codes) 24 Data rate, f(DATA) 10 Noise (input referred) Shorted inputs, See SBAS424 for more information. Integral nonlinearity, INL Best-fit method Offset voltage (input referred) ±3 10 ppm –250 ±40 250 μV 0.05 0.25 μV/°C ±0.05% 0.5% TA = –40°C to 125°C –0.5% Gain error after calibration (1) Gain drift μVRMS 0.7 μV ±1 Gain error (2) SPS –10 Offset voltage after calibration (1) Offset drift Bits 14,400 ±0.0002% TA = –40°C to 125°C 0.5 Normal-mode rejection ratio, NMRR 2.5 ppm/°C See SBAS424. Common-mode rejection ratio, CMRR 60 Hz, ac (3) 100 120 dB AVDD, AVSS power-supply rejection ratio, PSRR 60 Hz, ac (3) 85 95 dB DVDD power supply-rejection ratio, PSRR 60 Hz, ac (3) 85 110 dB OUT-OF-RANGE DETECTION Threshold level AVSS + 150 mV ≤ V(AINP), V(AINN) ≤ AVDD – 150 mV ±105 %FSR Threshold level accuracy AVSS + 150 mV ≤ V(AINP), V(AINN) ≤ AVDD – 150 mV ±0.5 %FSR AVSS ≤ V(REFP) , V(REFN) ≤ AVDD 350 nA 0.2 nA/°C VOLTAGE REFERENCE INPUTS Average reference input current Average reference input current drift INTERNAL VOLTAGE REFERENCE Reference output voltage V(REFOUT) = (REFOUT – AVSS) Accuracy TA = 25°C Temperature drift TA = –40°C to 125°C 2.5 –0.4% Drive current (sink and source) 10 –10 Load regulation V 0.4% 40 10 ±0.001% settling, CREFIN = 1 μF, CREFOUT = 1 μF Long-term stability 0 to 1000 hours Thermal hysteresis mA μV/mA 10 Turn-on settling time ppm/°C 1 s 70 ppm 30 ppm CLOCK SOURCE (f(CLK)) Internal oscillator frequency 7.3728 Internal oscillator accuracy External crystal oscillator start-up time (4) –2% 18-pF load capacitors ±0.2% MHz 2% 20 ms DIGITAL INPUTS AND OUTPUTS (DVDD = 2.7 V to 5.25 V) High-level output voltage, VOH Low-level output voltage, VOL IOH = 1 mA 0.8 DVDD V IOH = 8 mA 0.75 DVDD IOL = 1 mA 0.2 DVDD V IOL = 8 mA 0.2 DVDD Input hysteresis Input leakage (1) (2) (3) (4) 6 0.1 0 < V(DIGITAL INPUT) < DVDD –10 V 10 μA Calibration accuracy is on the level of noise (signal and ADC), reduced by the effect of 16-reading averaging. Excludes internal reference error. f(DATA) = 14.4 kSPS. Placing a notch of the digital filter at 60 Hz (setting f(DATA) = 10 SPS or 60 SPS) further improves the commonmode rejection and power-supply rejection of this input frequency. External crystal start-up time can vary with crystal manufacturer and over temperature. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: ADS1259-Q1 ADS1259-Q1 www.ti.com SLASE20 – MARCH 2014 Electrical Characteristics (continued) Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, external f(CLK) = 7.3728 MHz, external Vref = 2.5 V, and f(DATA) = 60 SPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX Operating (internal reference enabled) 2.3 5 Standby mode (internal reference enabled) 200 Standby mode (internal reference disabled) 1 Power-down mode 1 UNIT POWER SUPPLY Absolute analog supply current (AVDD, AVSS) Digital supply current (DVDD) Power dissipation (5) μA Operating (internal oscillator (5)) 500 700 Standby mode (internal oscillator) 160 300 1 10 Operating (internal reference enabled, internal oscillator) 13 28 Standby mode (internal reference enabled, internal oscillator) 1.5 Standby mode (internal reference disabled, internal oscillator) 0.5 Power-down mode 10 Power-down mode (external CLKIN, SCLK stopped, digital inputs maintained at VIH or VIL voltage levels) mA μA mW μW Internal oscillator current: 40 µA (typ.) 7 Residue See SBAS424 for any information on the ADS1259-Q1 device that is not covered in the foregoing sections. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: ADS1259-Q1 7 ADS1259-Q1 SLASE20 – MARCH 2014 www.ti.com 8 Device Documentation and Support 8.1 Trademarks SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. 8.2 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions. 8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: ADS1259-Q1 ADS1259-Q1 www.ti.com SLASE20 – MARCH 2014 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: ADS1259-Q1 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1259QPWRQ1 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AD1259Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of