ADS1292IPBSR

Order Now Product Folder Support & Community Tools & Software Technical Documents ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 ADS129x Low-Power, 2-Channel, 24-Bit Analog Front-End for Biopotential Measurements 1 Features 3 Description • The ADS1291, ADS1292, and ADS1292R are multichannel, simultaneous sampling, 24-bit, deltasigma (ΔΣ) analog-to-digital converters (ADCs) with a built-in programmable gain amplifier (PGA), internal reference, and an onboard oscillator. 1 • • • • • • • • • • • • • Two low-noise PGAs and two high-resolution ADCs (ADS1292 and ADS1292R) Low power: 335 μW/channel Input-referred noise: 8 μVPP (150-Hz BW, G = 6) Input bias current: 200 pA Data rate: 125 SPS to 8 kSPS CMRR: 120 dB Programmable gain: 1, 2, 3, 4, 6, 8, or 12 Supplies: unipolar or bipolar – Analog: 2.7 V to 5.25 V – Digital: 1.7 V to 3.6 V Built-in right leg drive amplifier, lead-off detection, test signals Integrated respiration impedance measurement (ADS1292R) Built-in oscillator and reference Flexible power-down, standby mode SPI™-compatible serial interface Operating temperature range: –40°C to +85°C 2 Applications • • Medical instrumentation (ECG) including: – Patient monitoring: Holter, event, stress, and vital signs including ECG, AED, and telemedicine – Personal care and fitness monitors (heart rate, respiration, and ECG) High-precision, simultaneous, multichannel data acquisition Simplified Block Diagram With high levels of integration and exceptional performance, the ADS1291, ADS1292, and ADS1292R enable the creation of scalable medical instrumentation systems at significantly reduced size, power, and overall cost. The ADS1291, ADS1292, and ADS1292R have a flexible input multiplexer per channel that can be independently connected to the internally-generated signals for test, temperature, and lead-off detection. Additionally, any configuration of input channels can be selected for derivation of the right leg drive (RLD) output signal. The ADS1291, ADS1292, and ADS1292R operate at data rates up to 8 kSPS. Leadoff detection can be implemented internal to the device, using the device internal excitation current sink or source. The ADS1292R version includes a fully integrated respiration impedance measurement function. The devices are packaged in a 5-mm × 5-mm, 32-pin thin quad flat pack (TQFP) and a 4-mm x 4-mm, 32pin quad flat pack with no leads (VQFN). Operating temperature is specified from –40°C to +85°C. Device Information(1) PART NUMBER ADS129x PACKAGE BODY SIZE (NOM) TQFP (32) 5.00 mm × 5.00 mm VQFN (32) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. REF Test Signals and Monitors The ADS1291, ADS1292, and ADS1292R incorporate all features commonly required in portable, low-power medical electrocardiogram (ECG), sports, and fitness applications. Reference SPI SPI (ADS1292R) INPUTS RESP DEMOD CLK A1 ADC1 Oscillator MUX Control GPIO AND CONTROL ADC2 A2 To Channel ¼ (ADS1292R) RESP MOD ¼ RESP RLD 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 1 1 1 2 4 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Timing Requirements .............................................. 11 Typical Characteristics ............................................ 12 7 Parameter Measurement Information ................ 15 8 Detailed Description ............................................ 18 7.1 Noise Measurements .............................................. 15 8.1 Overview ................................................................. 18 8.2 Functional Block Diagram ....................................... 18 8.3 Feature Description................................................. 19 8.4 Device Functional Modes........................................ 41 8.5 Programming........................................................... 41 8.6 Register Maps ......................................................... 51 9 Application and Implementation ........................ 62 9.1 Application Information............................................ 62 9.2 Typical Application ................................................. 62 10 Power Supply Recommendations ..................... 65 10.1 Power-Up Sequencing .......................................... 65 11 Layout................................................................... 66 11.1 Layout Guidelines ................................................. 66 11.2 Layout Example .................................................... 69 12 Device and Documentation Support ................. 70 12.1 12.2 12.3 12.4 12.5 12.6 Related Links ........................................................ Receiving Notification of Documentation Updates Support Resources ............................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 70 70 70 70 70 70 13 Mechanical, Packaging, and Orderable Information ........................................................... 70 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (September 2012) to Revision C Page • Added Device Information table, ESD Ratings table, title to page 1 figure, Recommended Operating Conditions table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Changed CMRR value from 105 dB to 120 dB in Features section ...................................................................................... 1 • Changed Application section ................................................................................................................................................. 1 • Changed QFN to VQFN throughout document ..................................................................................................................... 1 • Added thermal pad data to RDM pin out package drawing .................................................................................................. 4 • Changed Pin Functions title from Pin Assignments, changed Terminal column header to Pin, and corrected format to show both package options ................................................................................................................................................ 4 • Changed function and description of RESP_MODN/IN3N and RESP_MODP/IN3P pins, changed function of RLDOUT pin from Analog input to Analog output, and added Thermal Pad row to Pin Assignments table.......................... 4 • Deleted Family and Ordering Information table...................................................................................................................... 6 • Changed CMRR parameter values from –105 dB to 105 dB (minimum) and from –120 dB to 120 dB (typical) in Electrical Characteristics table ............................................................................................................................................... 7 • Changed Noise Measurements section: deleted SNR equation, changed DYN RANGE and EFF RESOL column headers in section tables...................................................................................................................................................... 15 • Added last sentence to Internal Respiration Circuitry with External Clock (ADS1292R) section......................................... 39 • Changed denominator of equation 10 ................................................................................................................................. 41 • Changed first paragraph of Data Output (DOUT) section .................................................................................................... 42 • Changed RDATAC Usage figure.......................................................................................................................................... 48 • Changed RDATA Usage figure ............................................................................................................................................ 49 • Changed ADS1292R Application section to fulfill Typical Application section ..................................................................... 62 2 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 Changes from Revision A (March 2012) to Revision B Page • Added QFN package to device graphic.................................................................................................................................. 1 • Added QFN pin out drawing ................................................................................................................................................... 4 • Changed AVSS to DGND row in Absolute Maximum Ratings table ...................................................................................... 6 • Changed parameters of Supply Current (RLD Amplifier Turned Off) section in Electrical Characteristics table................. 10 • Changed description of bit 6 in LOFF_STATUS: Lead-Off Status register .......................................................................... 59 Changes from Original (December 2011) to Revision A Page • Changed device graphic......................................................................................................................................................... 1 • Changed device status from Mixed Status to Production Data.............................................................................................. 1 • Changed second Features bullet............................................................................................................................................ 1 • Updated Family and Ordering Information table .................................................................................................................... 6 • Moved ADS1292R to production status ................................................................................................................................. 6 • Deleted footnote 2 from Family and Ordering Information table ............................................................................................ 6 • Changed values of AVDD to AVSS and DVDD to DGND rows in Absolute Maximum Ratings table ................................... 6 • Changed Operating temperature range parameter in Absolute Maximum Ratings table ...................................................... 6 • Changed DC Channel Performance, INL parameter test conditions in Electrical Characteristics table ................................ 7 • Changed AC Channel Performance, SNR and THD parameters test conditions in Electrical Characteristics table ............. 7 • Added third Channel Performance, THD parameter row to Electrical Characteristics table .................................................. 7 • Added Digital Filter section to Electrical Characteristics table ............................................................................................... 8 • Deleted Right Leg Drive Amplifier, Quiescent power consumption parameter test condition from Electrical Characteristics table ............................................................................................................................................................... 8 • Changed Respiration, Impedance measurement noise parameter test conditions in Electrical Characteristics table .......... 8 • Changed Respiration, Maximum modulator current parameter in Electrical Characteristics table ........................................ 8 • Changed Power-Supply Requirements, Digital supply parameter in Electrical Characteristics table .................................... 9 • Changed first IDVDD Supply Current, Normal mode parameter test conditions in Electrical Characteristics table................ 10 • Changed 3-V Power Dissipation, Quiescent power dissipation, per channel parameter typical specifications in Electrical Characteristics table ............................................................................................................................................. 10 • Added CFILTER to Typical Characteristics conditions............................................................................................................. 12 • Updated Figure 5.................................................................................................................................................................. 12 • Updated Figure 9 and Figure 12 .......................................................................................................................................... 12 • Changed description of CHnSET setting in Supply Measurements (MVDDP, MVDDN) section......................................... 21 • Changed second paragraph of PGA Settings and Input Range section .............................................................................. 23 • Changed description of PD_REFBUF bit in the Reference section ..................................................................................... 27 • Updated second column title in Table 9 ............................................................................................................................... 28 • Updated Figure 33................................................................................................................................................................ 30 • Updated Figure 42................................................................................................................................................................ 38 • Added description of Figure 43, Figure 43, and Table 12 to Internal Respiration Circuitry with External Clock (ADS1292R) section ............................................................................................................................................................. 39 • Updated description of DOUT and DRDY in RDATAC: Read Data Continuous section ..................................................... 48 • Updated RLD_STAT in address 08h of Table 16................................................................................................................. 51 • Changed description of bit 1 in CONFIG2: Configuration Register 2................................................................................... 53 • Changed descriptions of bits[3:0] in CH2SET: Channel 2 Settings ..................................................................................... 56 • Updated Figure 70 and Figure 71 ........................................................................................................................................ 64 • Updated Figure 73 and added footnote 1............................................................................................................................. 67 • Updated Figure 74 and added footnote 1............................................................................................................................. 68 Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 3 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 5 Pin Configuration and Functions RESP_MODN/IN3N RESP_MODP/IN3P RLDOUT RLDIN/RLDREF RLDINV VCAP2 GPIO1/RCLK1 GPIO2/RCLK2 25 GPIO2/RCLK2 RSM Package 32-Pin VQFN Top View 26 GPIO1/RCLK1 27 VCAP2 28 RLDINV 29 RLDIN/RLDREF 30 RLDOUT 31 RESP_MODP/IN3P 32 RESP_MODN/IN3N PBS Package 32-Pin TQFP Top View 32 31 30 29 28 27 26 25 2 23 DVDD 3 22 DRDY IN1N 3 22 DRDY IN1P 4 21 DOUT IN1P 4 21 DOUT IN2N 5 20 SCLK IN2N 5 20 SCLK IN2P 6 19 DIN IN2P 6 19 DIN PGA2N 7 18 CS PGA2N 7 18 CS PGA2P 8 17 CLK PGA2P 8 17 CLK 10 11 12 13 14 15 16 VCAP1 AVDD AVSS CLKSEL PWDN/RESET START 9 VREFN Thermal Pad, Must Be Connected To AVSS VREFP VREFP START 16 PGA1P IN1N PWDN/RESET 15 DGND CLKSEL 14 24 23 DVDD AVSS 13 1 2 AVDD 12 PGA1N PGA1P VCAP1 11 24 DGND VREFN 10 1 9 PGA1N Pin Functions PIN NO. FUNCTION DESCRIPTION PBS (TQFP) RSM (VQFN) 1 PGA1N PGA1N Analog output PGA1 inverting output 2 PGA1P PGA1P Analog output PGA1 noninverting output 3 IN1N (1) IN1N (1) Analog input Differential analog negative input 1 4 IN1P (1) IN1P (1) Analog input Differential analog positive input 1 5 IN2N (1) IN2N (1) Analog input Differential analog negative input 2 6 IN2P (1) IN2P (1) Analog input Differential analog positive input 2 7 PGA2N PGA2N Analog output PGA2 inverting output 8 PGA2P PGA2P Analog output PGA2 noninverting output 9 VREFP VREFP Analog input/output Positive reference voltage 10 VREFN VREFN Analog input Negative reference voltage; must be connected to AVSS 11 VCAP1 VCAP1 — 12 AVDD AVDD Supply Analog supply 13 AVSS AVSS Supply Analog ground 14 CLKSEL CLKSEL Digital input Master clock select 15 PWDN/RESET PWDN/RESET Digital input Power-down or system reset; active low 16 START START Digital input Start conversion 17 CLK CLK Digital input Master clock input 18 CS CS Digital input Chip select 19 DIN DIN Digital input SPI data in (1) 4 Analog bypass capacitor Connect unused analog inputs to AVDD. Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 Pin Functions (continued) PIN NO. PBS (TQFP) RSM (VQFN) FUNCTION DESCRIPTION 20 SCLK SCLK Digital input SPI clock 21 DOUT DOUT Digital output SPI data out 22 DRDY DRDY Digital output Data ready; active low 23 DVDD DVDD Supply Digital power supply 24 DGND DGND Supply Digital ground General-purpose I/O 2 or resp clock 2 (ADS1292R) General-purpose I/O 1 or resp clock 1 (ADS1292R) 25 GPIO2/RCLK2 GPIO2/RCLK2 Digital input/output 26 GPIO1/RCLK1 GPIO1/RCLK1 Digital input/output 27 VCAP2 VCAP2 — 28 RLDINV RLDINV Analog input Analog bypass capacitor Right leg drive inverting input; connect to AVDD if not used 29 RLDIN/ RLDREF RLDIN/ RLDREF Analog input Right leg drive input to MUX or RLD amplifier noninverting input; connect to AVDD if not used Right leg drive output 30 RLDOUT RLDOUT Analog output 31 RESP_MODP/ IN3P (1) RESP_MODP/ IN3P (1) Analog output/input P-side respiration excitation signal for respiration (analog output) or auxiliary input 3P (analog input) 32 RESP_MODN/ IN3N (1) RESP_MODN/ IN3N (1) Analog output/input N-side respiration excitation signal for respiration (analog output) or auxiliary input 3N (analog input) — Pad — Power Pad Thermal pad; must be connected to AVSS Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 5 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX AVDD to AVSS –0.3 5.5 V DVDD to DGND –0.3 3.9 V AVSS to DGND UNIT –3 0.2 V Analog input to AVSS AVSS – 0.3 AVDD + 0.3 V Digital input to DVDD DVSS – 0.3 DVDD + 0.3 Input current to any pin except supply pins Input current Momentary ±100 Continuous ±10 Operating temperature range (1) mA mA –40 +85 °C 150 °C –60 +150 °C Maximum junction temperature (TJ) Storage temperature, Tstg V ±10 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD Analog power supply, AVDD to AVSS 2.7 5 5.25 V DVDD Digital power supply, DVDD to DGND 1.7 3 3.6 V V TA Analog input voltage AVSS AVDD Digital input voltage DVSS DVDD V –40 85 °C Operating ambient temperature 6.4 Thermal Information ADS1291, ADS1292, ADS1292R THERMAL METRIC (1) PBS (TQFP) RSM (VQFN) UNIT 32 PINS 32 PINS RθJA Junction-to-ambient thermal resistance 68.4 33.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 25.9 36.4 °C/W RθJB Junction-to-board thermal resistance 30.5 25.2 °C/W ψJT Junction-to-top characterization parameter 0.5 0.2 °C/W ψJB Junction-to-board characterization parameter 24.3 7.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 2.2 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 6.5 Electrical Characteristics minimum and maximum specifications apply from –40°C to +85°C; typical specifications are at +25°C; all specifications are at DVDD = 1.8 V, AVDD – AVSS = 3 V (1), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF (2), and gain = 6 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale differential input voltage (AINP – AINN) ±VREF / gain V See the Input Common-Mode Range subsection of the PGA Settings and Input Range section Input common-mode range Input capacitance 20 TA = +25°C, input = 1.5 V Input bias current (PGA chop = 8 kHz) TA = –40°C to +85°C, input = 1.5 V DC input impedance pA ±1 Chop rates other than 8 kHz No pull-up or pull-down current source pF ±200 nA See Pace Detect section 1000 MΩ Current source lead-off detection (nA), AVSS + 0.3 V < AIN < AVDD – 0.3 V 500 MΩ Current source lead-off detection (µA), AVSS + 0.6 V < AIN < AVDD – 0.6 V 100 MΩ PGA PERFORMANCE Gain settings 1, 2, 3, 4, 6, 8, 12 With a 4.7-nF capacitor on PGA output (see PGA Settings and Input Range section for details) Bandwidth 8.5 kHz ADC PERFORMANCE Resolution 24 Data rate fCLK = 512 kHz Bits 125 8000 SPS CHANNEL PERFORMANCE (DC Performance) Input-referred noise Gain = 6 (3), 10 seconds of data 8 Gain = 6, 256 points, 0.5 seconds of data 8 Gain settings other than 6, data rates other than 500 SPS Integral nonlinearity μVPP 11 μVPP See Noise Measurements section Full-scale with gain = 6, best fit 2 Offset error ppm ±100 Offset error drift μV 2 Offset error with calibration μV/°C 15 Gain error Excluding voltage reference error Gain drift Excluding voltage reference drift ±0.1 Gain match between channels μV ±0.2 % of FS 2 ppm/°C 0.2 % of FS CHANNEL PERFORMANCE (AC performance) CMRR Common-mode rejection ratio fCM = 50 Hz and 60 Hz (4) 120 dB PSRR Power-supply rejection ratio fPS = 50 Hz and 60 Hz 90 dB Crosstalk fIN = 50 Hz and 60 Hz –120 dB Signal-to-noise ratio fIN = 10 Hz input, gain = 6 107 dB 10 Hz, –0.5 dBFs, CFILTER = 4.7nF –104 dB 100 Hz, –0.5 dBFs, CFILTER = 4.7nF –95 dB ADS1292R channel 1, 10 Hz, –0.5 dBFS, CFILTER = 47 nF –82 dB SNR THD (1) (2) (3) (4) Total harmonic distortion 105 Performance is applicable for 5-V operation as well. Production testing for limits is performed at 3 V. CFILTER is the capacitor accross the PGA outputs; see the PGA Settings and Input Range section for details. Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with input shorted (without electrode resistance) over a 10-second interval. CMRR is measured with a common-mode signal of AVSS + 0.3 V to AVDD – 0.3 V. The values indicated are the minimum of the two channels. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 7 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Electrical Characteristics (continued) minimum and maximum specifications apply from –40°C to +85°C; typical specifications are at +25°C; all specifications are at DVDD = 1.8 V, AVDD – AVSS = 3 V(1), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF(2), and gain = 6 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL FILTER –3-dB bandwidth Digital filter settling 0.262 fDR Full setting Hz 4 Conversions RIGHT LEG DRIVE (RLD) AMPLIFIER RLD integrated noise BW = 150 Hz 1.4 GBP Gain bandwidth product 50 kΩ || 10 pF load, gain = 1 100 kHz SR Slew rate 50 kΩ || 10 pF load, gain = 1 0.07 V/μs THD Total harmonic distortion fIN = 100 Hz, gain = 1 CMIR Common-mode input range Common-mode resistor matching ISC μVRMS –85 AVSS + 0.3 Internal 200-kΩ resistor matching Short-circuit current dB AVDD – 0.3 V 0.1 % 1.1 mA 5 μA Quiescent power consumption LEAD-OFF DETECT Frequency Current See Register Map section for settings 0, fDR / 4 kHz ILEAD_OFF [1:0] = 00 6 nA ILEAD_OFF [1:0] = 01 22 nA ILEAD_OFF [1:0] = 10 6 μA ILEAD_OFF [1:0] = 11 22 μA Current accuracy ±10 % Comparator threshold accuracy ±10 mV RESPIRATION (ADS1292R) Frequency Internal source 32, 64 External source Phase shift See Register Map section for settings Impedance range IRESP = 30 µA Impedance measurement noise 0.05-Hz to 2-Hz brick wall filter, 32-kHz modulation clock, phase = 112.5, using IRESP = 30 µA with 2-kΩ baseline load, gain = 4 Maximum modulator current Using Internal reference 32 0 kHz 64 kHz 112.5 168.75 Degrees 2000 10,000 Ω 40 mΩPP 100 μA EXTERNAL REFERENCE Reference input voltage VREFN Negative input VREFP Positive input 3-V supply VREF = (VREFP – VREFN) 2 2.5 VDD – 0.3 V 5-V supply VREF = (VREFP – VREFN) 2 4 VDD – 0.3 V AVSS AVSS + 2.5 Input impedance 8 Submit Documentation Feedback 120 V V kΩ Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 Electrical Characteristics (continued) minimum and maximum specifications apply from –40°C to +85°C; typical specifications are at +25°C; all specifications are at DVDD = 1.8 V, AVDD – AVSS = 3 V(1), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF(2), and gain = 6 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL REFERENCE Output voltage Output current drive Register bit CONFIG2.VREF_4V = 0 2.42 Register bit CONFIG2.VREF_4V = 1 4.033 V 100 µA Available for external use VREF accuracy V ±0.5 Internal reference drift –40°C ≤ TA ≤ +85°C Start-up time Settled to 0.2% with 10-µF capacitor on VREFP pin % 45 ppm/°C 100 ms 20 µA Analog supply reading error 1 % Digital supply reading error 1 % From power-supply ramp after power-on reset (POR) to DRDY low 32 ms From power-down mode to DRDY low 10 ms From STANDBY mode to DRDY low 10 ms 1% accuracy 0.5 s TA = +25°C 145 mV 490 μV/°C Quiescent current consumption SYSTEM MONITORS Device wake up VCAP1 settling time Temperature sensor reading Voltage Coefficient TEST SIGNAL Signal frequency See Register Map section for settings Signal voltage See Register Map section for settings At dc and 1 Hz Accuracy Hz ±1 mV ±2 % CLOCK Internal oscillator clock frequency Nominal frequency Internal clock accuracy 512 kHz TA = +25°C ±0.5 –40°C ≤ TA ≤ +85°C ±1.5 Internal oscillator start-up time 32 Internal oscillator power consumption External clock input frequency % % μs 30 μW CLKSEL pin = 0, CLK_DIV = 0 485 512 562.5 kHz CLKSEL pin = 0, CLK_DIV = 1 1.94 2.048 2.25 MHz DIGITAL INPUT/OUTPUT VIH DVDD = 1.8 V to 3.6 V 0.8 DVDD DVDD + 0.1 V VIL DVDD = 1.8 V to 3.6 V –0.1 0.2 DVDD V VIH DVDD = 1.7 V to 1.8 V DVDD – 0.2 VIL Logic level V DVDD = 1.7 V to 1.8 V 0.2 VOH DVDD = 1.7 V to 3.6 V IOH = –500 μA VOL DVDD = 1.7 V to 3.6 V IOL = +500 μA IIN Input current 0 V < VDigitalInput < DVDD 0.9 DVDD V V –10 0.1 DVDD V +10 μA POWER-SUPPLY REQUIREMENTS AVDD Analog supply AVDD – AVSS 2.7 3 5.25 V DVDD Digital supply DVDD – DGND 1.7 1.8 3.6 V 3.6 V AVDD – DVDD –2.1 Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 9 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Electrical Characteristics (continued) minimum and maximum specifications apply from –40°C to +85°C; typical specifications are at +25°C; all specifications are at DVDD = 1.8 V, AVDD – AVSS = 3 V(1), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF(2), and gain = 6 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT (RLD Amplifier Turned Off) IAVDD ADS1292 and ADS1292R AVDD – AVSS = 3 V 205 μA AVDD – AVSS = 5 V 250 μA IDVDD ADS1292 and ADS1292R DVDD = 3.3 V 75 μA DVDD = 1.8 V 32 μA POWER DISSIPATION (Analog Supply = 3 V, RLD Amplifier Turned Off) Quiescent power dissipation Normal mode 670 Standby mode 160 Normal mode 450 Standby mode 160 µW ADS1292R Normal mode 335 µW ADS1292 Normal mode 335 µW ADS1291 Normal mode 450 µW Normal mode 1300 µW Standby mode 340 µW Normal mode 950 µW Standby mode 340 µW ADS1292R Normal mode 670 µW ADS1292 Normal mode 670 µW ADS1291 Normal mode 860 µW DVDD = 1.8 V 1 µW DVDD = 3.3 V 4 µW DVDD = 1.8 V 5 µW DVDD = 3.3 V 10 µW ADS1292 and ADS1292R ADS1291 Quiescent power dissipation, per channel 740 µW µW 495 µW POWER DISSIPATION (Analog Supply = 5 V, RLD Amplifier Turned Off) Quiescent power dissipation ADS1292 and ADS1292R ADS1291 Quiescent power dissipation, per channel POWER DISSIPATION IN POWER-DOWN MODE Analog supply = 3 V Analog supply = 5 V TEMPERATURE 10 Specified temperature range –40 +85 °C Operating temperature range –40 +85 °C Storage temperature range –60 +150 °C Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 6.6 Timing Requirements specifications apply from –40°C to +85°C; load on DOUT = 20 pF || 100 kΩ 2.7 V ≤ DVDD ≤ 3.6 V MIN tCLK MAX MIN MAX UNIT Master clock period (CLK_DIV bit of LOFF_STAT register = 0) 1775 2170 1775 2170 ns Master clock period (CLK_DIV bit of LOFF_STAT register = 1) 444 542 444 542 ns tCSSC CS low to first SCLK, setup time tSCLK tSPWH, L NOM 1.7 V ≤ DVDD ≤ 2 V NOM 6 17 ns SCLK period 50 66.6 ns SCLK pulse width, high and low 15 25 ns tDIST DIN valid to SCLK falling edge: setup time 10 10 ns tDIHD Valid DIN after SCLK falling edge: hold time 10 tDOPD SCLK rising edge to DOUT valid tCSH CS high pulse tCSDOD CS low to DOUT driven tSCCS Eighth SCLK falling edge to CS high tSDECODE Command decode time 4 tCSDOZ CS high to DOUT Hi-Z 11 ns 12 22 ns 2 2 tCLKs 10 20 ns 3 3 tCLKs 4 tCLKs 10 20 ns tCLK CLK tCSSC tSCLK SCLK 1 tCSH tSDECODE CS tSPWL tSPWH 3 2 tDIHD tDIST 8 1 2 tSCCS 3 8 tDOPD DIN tCSDOZ tCSDOD Hi-Z Hi-Z DOUT NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1. Serial Interface Timing Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 11 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 6.7 Typical Characteristics at TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS, external clock = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF, and gain = 6 (unless otherwise noted) 4 1200 1000 2 1 Occurences Input−Referred Noise (µV) 3 0 −1 800 600 400 −2 200 −3 Peak−to−Peak Over 10 seconds = 8 µV G001 4 3 3.5 2 2.5 1 1.5 0 0.5 −1 −0.5 0 10 −2 8 −1.5 6 Time (sec) −3 4 −2.5 2 −4 0 −3.5 −4 Input−Referred Noise (µV) G002 Figure 2. Input-Referred Noise Figure 3. Noise Histogram −95 Common−Mode Rejection Ratio (dB) Internal Reference (V) 2.424 2.422 2.42 2.418 2.416 −40 −15 10 35 Temperature (°C) 60 −105 −110 −115 Gain = 1 Gain = 2 Gain = 3 Gain = 4 Gain = 6 Gain = 8 Gain = 12 −120 −125 −130 −135 85 Data Rate = 8 kSPS AIN = AVDD − 0.3 V to AVSS + 0.3 V −100 10 Figure 4. Internal Reference vs Temperature 1k G004 Figure 5. CMRR vs Frequency 0.7 2.5 0.6 0.5 Leakage Current (nA) 2 Leakage Current (nA) 100 Frequency (Hz) G003 64 kHz Chop Rate 32 kHz Chop Rate 0.4 0.3 8 kHz Chop Rate 0.2 1.5 AVDD = 3 V, Chop = 8 k AVDD = 3 V, Chop = 32 k AVDD = 3 V, Chop = 64 k AVDD = 5 V, Chop = 8 k AVDD = 5 V, Chop = 32 k AVDD = 5 V, Chop =64 k 1 0.5 0.1 0 0 0.5 1 1.5 2 Input Signal (V) 2.5 Figure 6. Leakage Current vs Input Voltage 12 Submit Documentation Feedback 3 0 −40 −15 G030 10 35 Temperature (°C) 60 85 G006 Figure 7. Leakage Current vs Temperature Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 Typical Characteristics (continued) at TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS, external clock = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF, and gain = 6 (unless otherwise noted) −55 Data Rate = 8 kSPS, −0.5 dBFS Data Rate = 8 kSPS, −0.5 dBFS 110 −65 100 −75 THD (dB) Power Supply Rejection Ratio (dB) 120 90 80 70 Gain = 1 Gain = 2 Gain = 3 Gain = 4 60 50 10 −85 Gain = 1 Gain = 2 Gain = 3 Gain = 4 Gain = 6 Gain = 8 Gain = 12 −95 −105 Gain = 6 Gain = 8 Gain = 12 −115 100 Frequency (Hz) −125 1k 10 Figure 8. PSRR vs Frequency Integral Nonlinearity (ppm) 2 1 2 0 −2 −40 °C −20 °C 0 °C 25 °C −4 0 2 4 6 PGA Gain 8 10 −1 12 G009 Figure 10. INL vs PGA Gain 40 °C 50 °C 70 °C 85 °C −0.5 0 0.5 Input Range (Normalized to Full−Scale) 1 G010 Figure 11. INL vs Temperature 0 0 PGA Gain = 1 Input = 10Hz, −0.5 dBFS THD = −103 dB SNR =117 dB Data Rate =500 sps −40 −60 −80 −100 −120 −40 −60 −80 −100 −140 −120 −160 −140 0 50 100 150 Frequency (Hz) 200 PGA Gain = 1 Input = 10Hz, −0.5 dBFS THD = −101 dB SNR = 80 dB Data Rate = 8 ksps −20 Amplitude (dBFS) −20 Amplitude (dBFS) G008 4 3 −180 1k Figure 9. THD vs Frequency 4 Integral Nonlinearity (ppm) 100 Frequency (Hz) G007 250 −160 0 1000 G011 Figure 12. THD FFT Plot (60-Hz Signal) Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R 2000 Frequency (Hz) 3000 4000 G012 Figure 13. FFT Plot (60-Hz Signal) Submit Documentation Feedback 13 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Typical Characteristics (continued) at TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS, external clock = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF, and gain = 6 (unless otherwise noted) 300 60 Data from 96 devices, Two lots 250 Number of Bins Offset (uV) 200 150 100 40 20 50 G013 0.6 0.5 0.4 0.3 0.2 0.1 0 12 0 10 −0.1 6 8 PGA Gain (dB) −0.2 4 −0.3 2 −0.4 0 −0.5 0 Error (%) G014 Figure 14. Offset vs PGA Gain (Absolute Value) Figure 15. Test Signal Amplitude Accuracy 140 120 Data from 96 devices, Two Lots 120 Data from 125 devices, Two lots Current Setting = 24 nA Figure 16. Lead-Off Comparator Threshold Accuracy Submit Documentation Feedback 2.5 2 Error in Current Magnitude (nA) G015 14 1.5 Threshold Error (mV) 1 −2 12 10 8 6 4 2 0 −2 −4 0 −6 0 −8 20 −10 20 0.5 40 0 40 60 −0.5 60 80 −1 80 −1.5 Number of Bins Number of Bins 100 100 G016 Figure 17. Lead-Off Current Source Accuracy Distribution Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 7 Parameter Measurement Information 7.1 Noise Measurements The ADS1291, ADS1292, and ADS1292R noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the programmable gain amplifier (PGA) value reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals. Table 1 through Table 8 summarize the ADS1291, ADS1292, and ADS1292R noise performance. The data are representative of typical noise performance at TA = +25°C. The data shown are the result of averaging the readings from multiple devices and are measured with the inputs shorted together. For the shown data rates, the ratio is approximately 6.6. Table 1 through Table 8 show measurements taken with an internal reference. The data are also representative of the ADS1291, ADS1292, and ADS1292R noise performance when using a low-noise external reference such as the REF5025. In Table 1 through Table 8, µVRMS and µVPP are measured values. Effective resolution (EFF RESOL) and dynamic range (DYN RANGE) are calculated with Equation 1 and Equation 2. § 2 u VREF · Effective Resolution = log2 ¨ ¸ © Gain u VRMS ¹ Dynamic Range 20 u log10 (1) VREF 2 u VRMS _ Noise u Gain (2) Table 1. Input-Referred Noise (μVRMS / μVPP) 3-V Analog Supply and 2.42-V Reference (1) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) μVRMS μVPP DYN RANGE EFF RESOL ENOB μVRMS μVPP DYN RANGE EFF RESOL ENOB 000 125 32.75 1.5 10.3 121.0 18.83 20.10 0.8 5.6 120.0 18.71 19.94 001 250 65.5 2.2 14.4 117.8 18.34 19.58 1.2 7.5 117.1 18.29 19.46 010 500 131 3.0 18.9 115.1 17.95 19.11 1.7 10.9 113.9 17.75 18.91 011 1000 262 4.6 30.8 111.3 17.25 18.49 2.5 15.6 110.6 17.23 18.37 100 2000 524 10.1 99 104.5 15.57 17.36 5.3 48 104.0 15.60 17.28 101 4000 1048 55.2 563 89.7 13.06 14.91 26.0 265 90.3 13.14 15.00 110 8000 2096 287.3 2930 75.4 10.68 12.53 144.1 1470 75.4 10.67 12.52 111 NA NA — — — — — — — — — — (1) PGA GAIN = 1 PGA GAIN = 2 At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table. Table 2. Input-Referred Noise (μVRMS / μVPP) 3-V Analog Supply and 2.42-V Reference (1) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) μVRMS μVPP DYN RANGE EFF RESOL ENOB μVRMS μVPP DYN RANGE EFF RESOL ENOB 000 125 32.75 0.6 4.1 119.2 18.58 19.80 0.5 3.4 117.9 18.42 19.58 001 250 65.5 0.9 5.5 115.9 18.15 19.26 0.8 5.0 114.8 17.88 19.07 010 500 131 1.3 7.7 113.0 17.67 18.77 1.1 6.6 111.9 17.47 18.59 011 1000 262 1.9 12.0 109.5 17.02 18.19 1.6 10.3 108.7 16.83 18.06 100 2000 524 3.7 31 103.7 15.65 17.23 2.9 23 103.2 15.69 17.14 101 4000 1048 17.0 173 90.5 13.18 15.03 12.2 124 90.8 13.24 15.09 110 8000 2096 91.9 937 75.8 10.74 12.59 66.8 681 76.1 10.78 12.63 111 NA NA — — — — — — — — — — (1) PGA GAIN = 3 PGA GAIN = 4 At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 15 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Table 3. Input-Referred Noise (μVRMS / μVPP) 3-V Analog Supply and 2.42-V Reference (1) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) μVRMS μVPP DYN RANGE EFF RESOL ENOB μVRMS μVPP DYN RANGE EFF RESOL ENOB 000 125 32.75 0.5 3.0 115.9 18.04 19.26 0.4 2.6 114.0 17.82 18.94 001 250 65.5 0.7 4.1 112.8 17.58 18.73 0.6 3.9 111.0 17.22 18.44 010 500 131 0.9 5.6 109.9 17.14 18.25 0.8 5.5 108.0 16.75 17.93 011 1000 262 1.3 8.7 106.8 16.49 17.73 1.2 7.6 104.9 16.26 17.42 100 2000 524 2.2 16 102.1 15.64 16.96 2.0 14 100.7 15.36 16.72 101 4000 1048 7.5 77 91.5 13.34 15.19 5.5 56 91.7 13.39 15.24 110 8000 2096 42.7 436 76.4 10.84 12.69 31.3 319 76.6 10.88 12.73 111 NA NA — — — — — — — — — — (1) PGA GAIN = 6 PGA GAIN = 8 At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table. Table 4. Input-Referred Noise (μVRMS / μVPP) 3-V Analog Supply and 2.42-V Reference (1) (1) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 12 μVRMS μVPP DYN RANGE EFF RESOL ENOB 000 125 32.75 0.4 2.5 111.3 17.31 18.48 001 250 65.5 0.5 3.5 108.4 16.81 18.01 010 500 131 0.8 5.0 105.0 16.29 17.44 011 1000 262 1.1 6.9 102.1 15.82 16.97 100 2000 524 1.7 11 98.6 15.21 16.38 101 4000 1048 3.5 36 92.0 13.44 15.29 110 8000 2096 20.1 205 76.9 10.93 12.78 111 NA NA — — — — — At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table. Table 5. Input-Referred Noise (μVRMS / μVPP) 5-V Analog Supply and 4.033-V Reference (1) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) μVRMS μVPP DYN RANGE EFF RESOL ENOB μVRMS μVPP DYN RANGE EFF RESOL ENOB 000 125 32.75 1.6 10.2 124.9 19.58 20.75 0.9 5.4 124.3 19.50 20.65 001 250 65.5 2.2 13.3 122.3 19.20 20.31 1.2 8.1 121.3 18.91 20.15 010 500 131 3.1 18.9 119.3 18.69 19.82 1.7 10.6 118.2 18.52 19.63 011 1000 262 4.9 31.9 115.2 17.94 19.14 2.7 17.9 114.4 17.77 19.00 100 2000 524 15.5 167 105.2 15.55 17.48 7.5 80 105.5 15.62 17.53 101 4000 1048 89.6 959 90.0 13.03 14.95 45.0 481 89.9 13.02 14.94 110 8000 2096 460.1 4923 75.8 10.67 12.59 229.0 2450 75.8 10.67 12.59 111 NA NA — — — — — — — — — — (1) 16 PGA GAIN = 1 PGA GAIN = 2 At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table. Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 Table 6. Input-Referred Noise (μVRMS / μVPP) 5-V Analog Supply and 4.033-V Reference (1) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) μVRMS μVPP DYN RANGE EFF RESOL ENOB μVRMS μVPP DYN RANGE EFF RESOL ENOB 000 125 32.75 0.6 4.2 123.4 19.28 20.50 0.5 3.6 122.3 19.08 20.32 001 250 65.5 0.9 5.7 120.7 18.82 20.04 0.7 4.8 119.5 18.66 19.86 010 500 131 1.3 8.4 117.3 18.27 19.49 1.1 7.4 116.2 18.04 19.31 011 1000 262 2.0 13.3 113.5 17.62 18.85 1.6 11.0 112.7 17.48 18.72 100 2000 524 5.1 53 105.3 15.61 17.49 3.9 38 105.2 15.67 17.47 101 4000 1048 28.7 307 90.3 13.08 15.00 20.7 222 90.6 13.14 15.06 110 8000 2096 149.3 1598 76.0 10.70 12.62 111.8 1196 76.0 10.71 12.63 111 NA NA — — — — — — — — — — (1) PGA GAIN = 3 PGA GAIN = 4 At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table. Table 7. Input-Referred Noise (μVRMS / μVPP) 5-V Analog Supply and 4.033-V Reference (1) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) μVRMS μVPP DYN RANGE EFF RESOL ENOB μVRMS μVPP DYN RANGE EFF RESOL ENOB 000 125 32.75 0.5 3.0 120.4 18.78 19.99 0.4 2.7 118.5 18.48 19.68 001 250 65.5 0.6 4.0 117.5 18.36 19.52 0.6 3.8 115.7 18.01 19.21 010 500 131 0.9 6.0 114.3 17.75 18.99 0.8 5.3 112.8 17.53 18.74 011 1000 262 1.4 8.8 110.8 17.20 18.41 1.2 8.1 109.5 16.92 18.19 100 2000 524 2.8 24 104.6 15.74 17.38 2.3 18 103.6 15.73 17.22 101 4000 1048 13.3 142 91.0 13.20 15.12 9.3 100 91.5 13.29 15.21 110 8000 2096 71.5 765 76.4 10.77 12.69 52.3 560 76.6 10.80 12.72 111 NA NA — — — — — — — — — — (1) PGA GAIN = 6 PGA GAIN = 8 At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table. Table 8. Input-Referred Noise (μVRMS / μVPP) 5-V Analog Supply and 4.033-V Reference (1) (1) DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 12 μVRMS μVPP DYN RANGE EFF RESOL ENOB 000 125 32.75 0.4 2.6 115.7 17.96 19.21 001 250 65.5 0.5 3.4 112.9 17.59 18.75 010 500 131 0.8 5.2 109.8 16.96 18.24 011 1000 262 1.1 6.9 106.6 16.56 17.70 100 2000 524 1.9 14 101.9 15.57 16.83 101 4000 1048 5.9 63 92.0 13.37 15.29 110 8000 2096 33.8 362 76.9 10.85 12.77 111 NA NA — — — — — At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 17 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8 Detailed Description 8.1 Overview The ADS1291, ADS1292, and ADS1292R are low-power, multichannel, simultaneously-sampling, 24-bit deltasigma (ΔΣ) analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These devices integrate various electrocardiogram (ECG)-specific functions that make them well-suited for scalable ECG, sports, and fitness applications. The devices can also be used in high-performance, multichannel data acquisition systems by powering down the ECG-specific circuitry. The ADS1291, ADS1292, and ADS1292R have a highly programmable multiplexer that allows for temperature, supply, input short, and RLD measurements. Additionally, the multiplexer allows any of the input electrodes to be programmed as the patient reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 3, 4, 6, 8, and 12). The ADCs in the device offer data rates from 125 SPS to 8 kSPS. Communication to the device is accomplished using an SPI-compatible interface. The device provides two general-purpose I/O (GPIO) pins for general use. Multiple devices can be synchronized using the START pin. The internal reference can be programmed to either 2.42 V or 4.033 V. The internal oscillator generates a 512kHz clock. The versatile right leg drive (RLD) block allows the user to choose the average of any combination of electrodes to generate the patient drive signal. Lead-off detection can be accomplished either by using an external pull-up or pull-down resistor or the device internal current source or sink. An internal ac lead-off detection feature is also available. Apart from the above features, the ADS1292R provides options for internal respiration circuitry. Functional Block Diagram shows a block diagram for the ADS1291, ADS1292, and ADS1292R. 8.2 Functional Block Diagram AVDD VCAP1 Power-Supply Signal RESP_EN Temperature Sensor Input PGA1P PGA1N VREFP VCAP2 VREFN DVDD Reference RESP DEMOD1 (ADS1292R) Test Signal DRDY Lead-Off Excitation Source SPI IN1P EMI Filter CLKSEL DS ADC1 PGA1 IN1N IN2P Oscillator EMI Filter IN2N GPIO2/ RCLK RESP_MODP/ IN3P DS ADC2 PGA2 RESP_MODN/ IN3N RESP PWDN/ RESET START (AVDD + AVSS)/2 Resp Mod (ADS1292R) AVSS 18 CLK GPIO1/ RCLK Control MUX CS SCLK DIN DOUT RLD Amplifier RLDIN/ RLDREF Submit Documentation Feedback RLD OUT RLD INV PGA2N PGA2P DGND Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.3 Feature Description This section contains details of the ADS1291, ADS1292, and ADS1292R internal functional elements. The analog blocks are discussed first followed by the digital interface. Blocks implementing ECG-specific functions are covered in the end. Throughout this document, fCLK denotes the signal frequency at the CLK pin, tCLK denotes the signal period of the CLK pin, fDR denotes the output data rate, tDR denotes the output data time period, and fMOD denotes the frequency at which the modulator samples the input. 8.3.1 EMI Filter An RC filter at the input acts as an electromagnetic interference (EMI) filter on channels 1 and 2. The –3-dB filter bandwidth is approximately 3 MHz. 8.3.2 Input Multiplexer The ADS1291, ADS1292, and ADS1292R input multiplexers are very flexible and provide many configurable signal-switching options. Figure 18 shows the multiplexer for the ADS1291, ADS1292, and ADS1292R. Note that TESTP, TESTM, and RLDIN/RLDREF are common to both channels. INP and INN are separate for each of the three pins. This flexibility allows for significant device and sub-system diagnostics, calibration, and configuration. Switch settings for each channel are selected by writing the appropriate values to the CH1SET or CH2SET register (see the CH1SET and CH2SET Registers in the Register Maps section for details). More details of the ECG-specific features of the multiplexer are discussed in the Input Multiplexer subsection of the ECG-Specifc Functions. 8.3.2.1 Device Noise Measurements Setting CHnSET[3:0] = 0001 sets the common-mode voltage of (VREFP + VREFN) / 2 to both inputs of the channel. This setting can be used to test the inherent noise of the device in the user system. 8.3.2.2 Test Signals (TestP and TestN) Setting CHnSET[3:0] = 0101 provides internally-generated test signals for use in sub-system verification at power-up. This functionality allows the entire signal chain to be tested out. Although the test signals are similar to the CAL signals described in the IEC60601-2-51 specification, this feature is not intended for use in compliance testing. Test signals are controlled through register settings (see the CONFIG2: Configuration Register 2 subsection in the Register Maps section for details). INT_TEST enables the test signal and TEST_FREQ controls switching at the required frequency. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 19 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Feature Description (continued) INT_TEST Device MUX1[3:0] = 0101 TESTP TEMPP MVDDP MUX1[3:0] = 0100 MUX1[3:0] = 0011 From LOFFP MUX1[3:0] = 0000 IN2P To PGA2_INP MUX1[3:0] = 0110 or MUX1[3:0] = 1000 MUX1[3:0] = 0001 MUX1[3:0] = 0010 EMI Filter VREFP + VREFN 2 MUX1[3:0] = 0111 or MUX1[3:0] = 1000 MUX1[3:0] = 0001 MUX1[3:0] = 0000 IN2N From LOFFN RLD_REF MVDDN TEMPN INT_TEST TESTM RLDIN/ RLDREF To PGA2_INN MUX1[3:0] = 0010 MUX1[3:0] = 1001 MUX1[3:0] = 0011 MUX1[3:0] = 0100 MUX1[3:0] = 1001 MUX1[3:0] = 0101 INT_TEST MUX1[3:0] = 0101 TESTP TEMPP MVDDP MUX1[3:0] = 0100 MUX1[3:0] = 0011 From LOFFP MUX1[3:0] = 0000 IN1P To PGA1_INP MUX1[3:0] = 0111 or MUX1[3:0] = 1000 MUX1[3:0] = 0001 MUX1[3:0] = 0010 EMI Filter VREFP + VREFN 2 MUX1[3:0] = 0110 or MUX1[3:0] = 1000 MUX1[3:0] = 0001 MUX1[3:0] = 0000 IN1N From LOFFN RLD_REF MVDDN TEMPN RESP MOD INT_TEST TESTM To PGA1_INN MUX1[3:0] = 0010 MUX1[3:0] = 1001 MUX1[3:0] = 0011 MUX1[3:0] = 0100 MUX1[3:0] = 1001 MUX1[3:0] = 0101 RESP_MODP/IN3P RESP_MODN/IN3N NOTE: MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN) section. Figure 18. Input Multiplexer Block for Both Channels 20 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 Feature Description (continued) 8.3.2.3 Auxiliary Differential Input (RESP_MODN/IN3N, RESP_MODN/IN3P) In applications where the respiration modulator output is not used, the RESP_MODN/IN3N and RESP_MODN/IN3P signals can be used as a third multiplexed differential input channel. These inputs can be multiplexed to either of the ADC channels. 8.3.2.4 Temperature Sensor (TEMPP, TEMPN) The ADS1291, ADS1292, and ADS1292R contain an on-chip temperature sensor. This sensor uses two internal diodes with one diode having a current density 16x that of the other, as shown in Figure 19. The difference in diode current densities yields a difference in voltage that is proportional to absolute temperature. Temperature Sensor Monitor AVDD 1x 2x To MUX TEMPP To MUX TEMPN 8x 1x AVSS Figure 19. Temperature Sensor Measurement in the Input As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device temperature tracks the PCB temperature closely. Note that self-heating of the ADS1291, ADS1292, and ADS1292R causes a higher reading than the temperature of the surrounding PCB. The scale factor of Equation 3 converts the temperature reading to °C. Before using this equation, the temperature reading code must first be scaled to μV. Temperature (°C) = Temperature Reading (mV) - 145,300 mV 490 mV/°C + 25°C (3) 8.3.2.5 Supply Measurements (MVDDP, MVDDN) Setting CHnSET[3:0] = 0011 sets the channel inputs to different supply voltages of the device. For channel 1 (MVDDP – MVDDN) is [0.5(AVDD + AVSS)]; for channel 2 (MVDDP – MVDDN) is DVDD / 4. Note that to avoid saturating the PGA while measuring power supplies, the gain must be set to '1'. 8.3.2.6 Lead-Off Excitation Signals (LoffP, LoffN) The lead-off excitation signals are fed into the multiplexer before the switches. The comparators that detect the lead-off condition are also connected to the multiplexer block before the switches. For a detailed description of the lead-off block, refer to the Lead-Off Detection subsection in the ECG-Specific Functions section. 8.3.2.7 Auxiliary Single-Ended Input The RLDIN/RLDREF pin is primarily used for routing the right leg drive signal to any of the electrodes in case the right leg drive electrode falls off. However, the RLDIN/RLDREF pin can be used as a multiple single-ended input channel. The signal at the RLDIN/RLDREF pin can be measured with respect to the midsupply [(AVDD + AVSS) / 2]. This measurement is done by setting the channel multiplexer setting MUXn[3:0] to '0010' in the CH1SET and CH2SET registers. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 21 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Feature Description (continued) 8.3.3 Analog Input The ADS1291, ADS1292, and ADS1292R analog input is fully differential. Assuming PGA = 1, the differential input (INP – INN) can span between –VREF to +VREF. Note that the absolute range for INP and INN must be between AVSS – 0.3 V and AVDD + 0.3 V. Refer to Table 10 for an explanation of the correlation between the analog input and the digital codes. There are two general methods of driving the ADS1291, ADS1292, and ADS1292R analog input: single-ended or differential, as shown in Figure 20 and Figure 21. Note that INP and INN are 180°C out-of-phase in the differential input method. When the input is single-ended, the INN input is held at the common-mode voltage, preferably at mid-supply. The INP input swings around the same common voltage and the peak-to-peak amplitude is (common-mode + 1/2 VREF) and (common-mode – 1/2 VREF). When the input is differential, the common-mode is given by (INP + INN) / 2. Both INP and INN inputs swing from (commonmode + 1/2 VREF to common-mode – 1/2 VREF). For optimal performance, it is recommended that the ADS1291, ADS1292, and ADS1292R be used in a differential configuration. -1/2 VREF to +1/2 VREF VREF Peak-to-Peak Device Device Common Voltage Common Voltage Single-Ended Input VREF Peak-to-Peak Differential Input Figure 20. Methods of Driving the ADS1291, ADS1292, and ADS1292R: Single-Ended or Differential CM + 1/2 VREF +1/2 VREF INP CM Voltage -1/2 VREF INN = CM Voltage CM - 1/2 VREF t Single-Ended Inputs INP CM + 1/2 VREF +VREF CM Voltage CM - 1/2 VREF INN -VREF t Differential Inputs (INP) + (INN) , Common-Mode Voltage (Single-Ended Mode) = INN. 2 Input Range (Differential Mode) = (AINP - AINN) = 2 VREF. Common-Mode Voltage (Differential Mode) = Figure 21. Using the ADS1291, ADS1292, and ADS1292R in Single-Ended and Differential Input Modes 22 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.3.4 PGA Settings and Input Range The PGA is a differential input or differential output amplifier, as shown in Figure 22. It has seven gain settings (1, 2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CH1SET and CH2SET Registers in the Register Map section for details). The ADS1291, ADS1292, and ADS1292R have CMOS inputs and hence have negligible current noise. From MuxP RS = 2 kW PGA1P PgaP CP1 R2 150 kW R1 60 kW (for Gain = 6) R2 150 kW CFILTER 4.7 nF RS = 2 kW PgaN PGA1N From MuxN CP2 Figure 22. PGA Implementation The PGA resistor string that implements the gain has 360 kΩ of resistance for a gain of 6. This resistance provides a current path across the outputs of the PGA in the presence of a differential input signal. This current is in addition to the quiescent current specified for the device in the presence of a differential signal at the input. The PGA output is filtered by an RC filter before it goes to the ADC. The filter is formed by an internal resistor RS = 2 kΩ and an external capacitor CFILTER (4.7 nF, typical). This filter acts as an anti-aliasing filter with the –3-dB bandwidth of 8.4 kHz. The internal RS resistor is accurate to 15% so actual bandwidth will vary. This RC filter also suppresses the glitch at the PGA output caused by ADC sampling. The minimum value of CEXT that can be used is 4 nF. A larger value CFILTER capacitor can be used for increased attenuation at higher frequencies for anti-aliasing purposes. If channel 1 of the ADS1292R is used for respiration measurement, then a 4.7-nF external capacitor is recommended. The tradeoff is that a larger capacitor value gives degraded THD performance. See Figure 23 for a diagram explaining the THD versus CFILTER value for a 10-Hz input signal. −85 THD (dB) −90 −95 −100 −105 5 10 15 CFILTER (nF) 20 25 G025 Figure 23. THD versus CFILTER Value Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 23 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Special care must be taken in PCB layout to minimize the parasitic capacitance CP1 / CP2. The absolute value of these capacitances must be less than 20 pF. Ideally, CFILTER should be placed right at the pins to minimize these capacitors. Mismatch between these capacitors will lead to CMRR degradation. Assuming everything else is perfectly matched, the 60-Hz CMRR as a function of this mismatch is given by Equation 4. Gain CMRR = 20log 2p ´ 2e3 ´ DCP ´ 60 (4) where ΔCP = CP1 – CP2 For example, a mismatch of 20 pF with a gain of 6 limits the CMRR to 112 dB. If ΔCP is small, then the CMRR is limited by the PGA itself and is as specified in the Electrical Characteristics table. The PGA are chopped internally at either 8, 32, or 64 kSPS, as determined by the CHOP bits (see the RLD_SENS: Right Leg Drive Sense Selection register, bits[7:6]). The digital decimation filter filters out the chopping ripple in the normal path so the chopping ripple is not a concern. If PGA output is used for hardware PACE detection, the chopping ripple must be filtered. First-order filtering is provided by the RC filter at the PGA output. Additional filtering may be needed to suppress the chopping ripple. If the PGA output is routed to other circuitry, a 20-kΩ series resistance must be added in the path near the CFILTER capacitor. The routing should be matched to maintain the CMRR performance. 8.3.4.1 Input Common-Mode Range The usable input common-mode range of the front end depends on various parameters, including the maximum differential input signal, supply voltage, and PGA gain. Equation 5 describes this range. æ Gain ´ VMAX _ DIFF ö æ Gain ´ VMAX _ DIFF ö AVDD - 0.2 V - çç ÷÷ > CM > AVSS + 0.2 V + çç ÷÷ 2 2 è ø è ø where: VMAX_DIFF = maximum differential signal at the input of the PGA CM = common-mode range (5) For example: If VDD = 3 V, gain = 6, and VMAX_DIFF = 350 mV Then 1.25 V < CM < 1.75 V 8.3.4.2 Input Differential Dynamic Range The differential (INP – INN) signal range depends on the analog supply and reference used in the system. Equation 6 shows this range. VREF ±VREF 2 VREF Max (INP - INN) < ; Full-Scale Range = = Gain Gain Gain (6) The 3-V supply, with a reference of 2.42 V and a gain of 6 for ECGs, is optimized for power with a differential input signal of approximately 300 mV. For higher dynamic range, a 5-V supply with a reference of 4.033 V (set by the VREF_4V bit of the CONFIG2 register) can be used to increase the differential dynamic range. 24 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.3.4.3 ADC ΔΣ Modulator Power Spectral Density (dB) Each channel of the ADS1291, ADS1292, and ADS1292R has a 24-bit ΔΣ ADC. This converter uses a secondorder modulator optimized for low-power applications. The modulator samples the input signal at the rate of fMOD = fCLK / 4 or fCLK / 16, as determined by the CLK_DIV bit. In both cases, the sampling clock has a typical value of 128 kHz. As in the case of any ΔΣ modulator, the ADS1291, ADS1292, and ADS1292R noise is shaped until fMOD / 2, as shown in Figure 24. The on-chip digital decimation filters explained in the Digital Decimation Filter section can be used to filter out the noise at higher frequencies. These on-chip decimation filters also provide antialias filtering. This feature of the ΔΣ converters drastically reduces the complexity of analog antialiasing filters that are typically needed with nyquist ADCs. 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 0.001 0.01 0.1 Normalized Frequency (fIN/fMOD) 1 G001 Figure 24. Power Spectral Density (PSD) of a ΔΣ Modulator (4-Bit Quantizer) 8.3.5 Digital Decimation Filter The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rates. Higher data rates are typically used in ECG applications for implement software pace detection and ac lead-off detection. The digital filter on each channel consists of a third-order sinc filter. The decimation ratio on the sinc filters can be adjusted by the DR bits in the CONFIG1 register (see the Register Map section for details). This setting is a global setting that affects all channels and, therefore, in a device all channels operate at the same data rate. 8.3.5.1 Sinc Filter Stage (sinx / x) The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of fMOD. The sinc filter attenuates the high-frequency noise of the modulator, then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the converter. Equation 7 shows the scaled Z-domain transfer function of the sinc filter. ½H(z)½ = 1 - Z-N 3 1 - Z-1 (7) The frequency domain transfer function of the sinc filter is shown in Equation 8. 3 sin H(f) = Npf fMOD N ´ sin pf fMOD where: N = decimation ratio (8) Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 25 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 0 0 -20 -0.5 -40 -1 Gain (dB) Gain (dB) The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has infinite attenuation. Figure 25 shows the sinc filter frequency response and Figure 26 shows the sinc filter roll-off. With a step change at input, the filter takes 3 tDR to settle. After a START signal rising edge, the filter takes tSETTLE time to give the first data output. The filter settling times at various data rates are discussed in the START subsection of the SPI Interface section. Figure 27 and Figure 28 show the filter transfer function until fMOD / 2 and fMOD / 16, respectively, at different data rates. Figure 29 shows the transfer function extended until 4 fMOD. It can be seen that the ADS1291, ADS1292, and ADS1292R passband repeats itself at every fMOD. The input R-C anti-aliasing filters in the system should be chosen such that any interference in frequencies around multiples of fMOD are attenuated sufficiently. -60 -80 -1.5 -2 -100 -2.5 -120 -3 -140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 0.05 0.1 Figure 25. Sinc Filter Frequency Response 0 DR[2:0] = 000 0.25 0.3 0.35 DR[2:0] = 000 -20 DR[2:0] = 110 -40 DR[2:0] = 110 -40 Gain (dB) Gain (dB) 0.2 Figure 26. Sinc Filter Roll-Off 0 -20 0.15 Normalized Frequency (fIN/fDR) Normalized Frequency (fIN/fDR) -60 -80 -60 -80 -100 -100 -120 -120 -140 -140 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.01 Normalized Frequency (fIN/fMOD) Figure 27. Transfer Function of On-Chip Decimation Filters Until fMOD / 2 10 0.02 0.03 0.04 0.05 0.06 0.07 Normalized Frequency (fIN/fMOD) DR[2:0] = 110 Figure 28. Transfer Function of On-Chip Decimation Filters Until fMOD / 16 DR[2:0] = 000 -10 Gain (dB) -30 -50 -70 -90 -110 -130 0 0.5 1 1.5 2 2.5 3 3.5 4 Normalized Frequency (fIN/fMOD) Figure 29. Transfer Function of On-Chip Decimation Filters Until 4fMOD for DR[2:0] = 000 and DR[2:0] = 110 26 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.3.6 Reference Figure 30 shows a simplified block diagram of the ADS1291, ADS1292, and ADS1292R internal reference. The reference voltage is generated with respect to AVSS. The VREFN pin must always be connected to AVSS. 1 mF VCAP1 (1) R1 2.42 V or 4.033 V Bandgap VREFP (1) R3 10 mF R2 0.1 mF (1) VREFN AVSS To ADC Reference Inputs (1) For VREF = 2.42 V: R1 = 100 kΩ, R2 = 200 kΩ, and R3 = 200 kΩ. For VREF = 4.033 V: R1 = 84 kΩ, R2 = 120 kΩ, and R3 = 280 kΩ. Figure 30. Internal Reference The external band-limiting capacitors determine the amount of reference noise contribution. For high-end ECG systems, the capacitor values should be chosen such that the bandwidth is limited to less than 10 Hz so that the reference noise does not dominate the system noise. When using a 3-V analog supply, the internal reference must be set to 2.42 V. In case of a 5-V analog supply, the internal reference can be set to 4.033 V by setting the VREF_4V bit in the CONFIG2 register. Alternatively, the internal reference buffer can be powered down and VREFP can be applied externally. Figure 31 shows a typical external reference drive circuitry. Power-down is controlled by the PD_REFBUF bit in the CONFIG2 register. This power-down is also used to share internal references when two devices are cascaded. By default the device wakes up in external reference mode. 100 kW 10 pF +5 V 0.1 mF 100 W +5 V VIN 10 mF OUT 22 mF REF5025 TRIM To VREFP Pin OPA211 100 W 0.1 mF 100 mF 22 mF Figure 31. External Reference Driver Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 27 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.3.7 Clock The ADS1291, ADS1292, and ADS1292R provide two different methods for device clocking: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. Over the specified temperature range the accuracy varies; see the Electrical Characteristics. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit. The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG2 register enables and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 9. The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that during power-down the external clock be shut down to save power. Table 9. CLKSEL Pin and CLK_EN Bit CLKSEL PIN CONFIG2.CLK_EN BIT CLOCK SOURCE CLK PIN STATUS 0 X External clock Input: external clock 1 0 Internal clock oscillator 3-state 1 1 Internal clock oscillator Output: internal clock oscillator The ADS1291, ADS1292, and ADS1292R have the option to choose between two different external clock frequencies (512 kHz or 2.048 MHz). This frequency is selected by setting the CLK_DIV bit (bit 6) in the LOFF_STAT register. The modulator must be clocked at 128 kHz, regardless of the external clock frequency. Figure 32 shows the relationship between the external clock (fCLK) and the modulator clock (fMOD). The default mode of operation is fCLK = 512 kHz. The higher frequency option has been provided to allow the SPI to run at a higher speed. SCLK can be only twice the speed of fCLK during a register read or write, see section on sending multi-byte commands. Having the 2.048 MHz option allows for register read and writes to be performed at SCLK speeds up to 4.096 MHz. fCLK Frequency Divider Divide-By-4 fMOD Frequency Divider Divide-By-16 CLK_DIV (Bit 6 of LOFF_STAT Register) Figure 32. Relationship Between External Clock (fCLK) and Modulator Clock (fMOD) 28 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.3.8 Data Format The ADS1291, ADS1292, and ADS1292R outputs 24 bits of data per channel in binary twos complement format, MSB first. The LSB has a weight of VREF / (223 – 1). A positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 10 summarizes ideal output codes for different input signals. All 24 bits toggle when the analog input is at positive or negative full-scale. Table 10. Ideal Output Code versus Input Signal (1) INPUT SIGNAL, VIN (AINP – AINN) IDEAL OUTPUT CODE (1) ≥ VREF 7FFFFFh +VREF / (223 – 1) 000001h 0 000000h –VREF / (223 – 1) FFFFFFh ≤ –VREF (223 / 223 – 1) 800000h Excludes effects of noise, linearity, offset, and gain error. 8.3.9 Multiple Device Configuration The ADS1291, ADS1292, and ADS1292R are designed to provide configuration flexibility when multiple devices are used in a system. The serial interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one additional chip select signal per device, multiple devices can be connected together. The number of signals needed to interface n devices is 3 + n. The right leg drive amplifiers can be daisy-chained as explained in the RLD Configuration with Multiple Devices subsection of the ECG-Specific Functions section. To use the internal oscillator in a daisy-chain configuration, one of the devices must be set as the master for the clock source with the internal oscillator enabled (CLKSEL pin = 1) and the internal oscillator clock brought out of the device by setting the CLK_EN register bit to '1'. This master device clock is used as the external clock source for the other devices. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 29 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com When using multiple devices, the devices can be synchronized with the START signal. The delay from START to the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more details on the settling times). Figure 33 shows the behavior of two devices when synchronized with the START signal. Device1 START START1 CLK DRDY DRDY1 CLK Device2 START2 DRDY DRDY2 CLK CLK Note 1 START DRDY1 Note 2 DRDY2 (1) Start pulse must be at least one tMOD cycle wide. (2) Settling time number uncertainty is one tMOD cycle. Figure 33. Synchronizing Multiple Converters 8.3.9.1 Standard Mode Figure 34 shows a configuration with two devices cascaded together. One of the devices is an ADS1292R (twochannel with RESP) and the other is an ADS1292 (two-channel). Together, they create a system with four channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure allows the other device to take control of the DOUT bus. START (1) CLK START CLK DRDY CS INT GPO0 GPO1 ADS1292 (Device 0) SCLK SCLK DIN MOSI DOUT MISO Host Processor START CLK DRDY CS SCLK ADS1292R (Device 1) DIN DOUT Figure 34. Multiple Device Configurations 30 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.3.10 ECG-Specific Functions 8.3.10.1 Input Multiplexer (Rerouting the Right Leg Drive Signal) The input multiplexer has ECG-specific functions for the right leg drive signal. The RLD signal is available at the RLDOUT pin once the appropriate channels are selected for RLD derivation, feedback elements are installed external to the chip, and the loop is closed. This signal can be fed after filtering or fed directly into the RLDIN pin, as shown in Figure 35. This RLDIN signal can be multiplexed into any one of the input electrodes by setting the MUX bits of the appropriate channel set registers to '0110' for P-side or '0111' for N-side. Figure 35 shows the RLD signal generated from channel 1 and routed to the N-side of channel 2. This feature can be used to dynamically change the electrode that is used as the reference signal to drive the patient body. Note that the corresponding channel cannot be used and can be powered down. RLD1P = 1 IN1P EMI Filter PGA1 RLD1N = 1 MUX1[3:0] = 0000 IN1N RLD2P = 0 IN2P EMI Filter PGA2 RLD2N = 0 MUX1[3:0] = 0111 IN2N RLDREF_INT = 1 (AVDD + AVSS) MUX 2 RLDREF_INT = 0 RLD_AMP ADS1292R RLDIN/RLDREF RLDOUT Filter or Feedthrough 1M RLDINV (1) 1.5 nF(1) (1) Typical values for example only. Figure 35. Example RLDOUT Signal Configured to be Routed to IN2N Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 31 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.3.10.1.1 Input Multiplexer (Measuring the Right Leg Drive Signal) The RLDOUT signal can also be routed to a channel (that is not used for the calculation of RLD) for measurement. Figure 36 shows the register settings to route the RLDIN signal to channel 2. The measurement is done with respect to the voltage (AVDD + AVSS) / 2. This feature is useful for debugging purposes during product development. RLD1P = 1 IN1P EMI Filter PGA1 RLD1N = 1 MUX1[3:0] = 0000 IN1N RLD2P = 0 IN2P EMI Filter PGA2 MUX1[3:0] = 0010 IN2N RLD2N = 0 RLDREF_INT = 1 (AVDD + AVSS) 2 MUX MUX1[3:0] = 0010 RLDREF_INT = 0 RLD_AMP Device RLDIN/RLDREF RLDOUT 1M Filter or Feedthrough RLDINV (1) 1.5 nF(1) (1) Typical values for example only. Figure 36. RLDOUT Signal Configured to be Read Back by Channel 2 32 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.3.10.2 Lead-Off Detection Patient electrode impedances are known to decay over time. It is necessary to continuously monitor these electrode connections to verify a suitable connection is present. The ADS1291, ADS1292, and ADS1292R leadoff detection functional block provides significant flexibility to the user to choose from various lead-off detection strategies. Though called lead-off detection, this is in fact an electrode-off detection. The basic principle is to inject an excitation signal and measure the response to find out if the electrode is off. As shown in the lead-off detection functional block diagram in Figure 37, this circuit provides two different methods of determining the state of the patient electrode. The methods differ in the frequency content of the excitation signal. Lead-off can be selectively done on a per channel basis using the LOFF_SENS register. Also, the internal excitation circuitry can be disabled and just the sensing circuitry can be enabled. Patient Skin, Electrode Contact Model Patient Protection Resistor 47 nF 51 k IN1P_OFF/ IN2P_OFF 30 k VINP 51 k EMI Filter 30 k LOFF1P/ LOFF2P 47 nF 47 nF 51 k VINN PGA LOFF1N/ LOFF2N AVDD AVSS To ADC IN1N_OFF/ IN2N_OFF 4-Bit DAC COMP_TH[2:0] 30 k RLD OUT NOTE: The RP value must be selected in order to be below the maximum allowable current flow into a patient (in accordance with the relevant specification the latest revision of IEC 60601). Figure 37. Lead-Off Detection Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 33 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.3.10.2.1 DC Lead-Off In this method, the lead-off excitation is with a dc signal. The dc excitation signal can be chosen from either an external pull-up or pull-down resistor or a current source or sink, as shown in Figure 38. One side of the channel is pulled to supply and the other side is pulled to ground. The internal current source and current sink can be swapped by setting the FLIP1 and FLIP2 bits in the LOFF_SENS register. In case of current source or sink, the magnitude of the current can be set by using the ILEAD_OFF[1:0] bits in the LOFF register. The current source or sink gives larger input impedance compared to the 10-MΩ pull-up or pull-down resistor. AVDD AVDD Device Device 10 MW INP INP PGA INN PGA INN 10 MW a) External Pull-Up/Pull-Down Resistors b) Input Current Source Figure 38. DC Lead-Off Excitation Options Sensing of the response can be done either by looking at the digital output code from the device or by monitoring the input voltages with an on-chip comparator. If either of the electrodes is off, the pull-up resistors and the pulldown resistors saturate the channel. By looking at the output code it can be determined that either the P-side or the N-side is off. To pinpoint which one is off, the comparators must be used. The input voltage is also monitored using a comparator and a 4-bit digital-to-analog converter (DAC) whose levels are set by the COMP_TH[2:0] bits in the LOFF register. The output of the comparators are stored in the LOFF_STAT register. These two registers are available as a part of the output data stream. (See the Data Output Protocol (DOUT) subsection of the SPI Interface section.) If dc lead-off is not used, the lead-off comparators can be powered down by setting the PD_LOFF_COMP bit in the CONFIG2 register. An example procedure to turn on dc lead-off is given in the Lead-Off section. 8.3.10.2.2 AC Lead-Off In this method, an out-of-band ac signal is used for excitation. The ac signal is generated by alternatively providing an internal current source and current sink at the input with a fixed frequency. The excitation frequency is a function of the output data rate and is fDR / 4. This out-of-band excitation signal is passed through the channel and measured at the output. Sensing of the ac signal is done by passing the signal through the channel to digitize it and measure at the output. The ac excitation signals are introduced at a frequency that is above the band of interest, generating an out-of-band differential signal that can be filtered out separately and processed. By measuring the magnitude of the excitation signal at the output spectrum, the lead-off status can be calculated. Therefore, the ac lead-off detection can be accomplished simultaneously with the ECG signal acquisition. 34 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.3.10.2.3 RLD Lead-Off The ADS1291, ADS1292, and ADS1292R provide two modes for determining whether the RLD is correctly connected: • RLD lead-off detection during normal operation • RLD lead-off detection during power-up The following sections provide details of the two modes of operation. RLD Lead-Off Detection During Normal Operation During normal operation, the ADS1291, ADS1292, and ADS1292R RLD lead-off at power-up function cannot be used because it is necessary to power off the RLD amplifier. RLD Lead-Off Detection At Power-Up This feature is included in the ADS1291, ADS1292, and ADS1292R for use in determining whether the right leg electrode is suitably connected. At power-up, the ADS1291, ADS1292, and ADS1292R provides a procedure to determine the RLD electrode connection status using a current sink, as shown in Figure 39. The reference level of the comparator is set to determine the acceptable RLD impedance threshold. Patient Skin, Electrode Contact Model Patient Protection Resistor To ADC input (through VREF connection to any of the channels). 47 nF 51 k RLD_STAT 30 k RLD_LOFF_SENS AVSS NOTE: The RP value must be selected in order to be below the maximum allowable current flow into a patient (in accordance with the relevant specification the latest revision of IEC 60601). Figure 39. RLD Lead-Off Detection at Power-Up When the RLD amplifier is powered on, the current source has no function. Only the comparator can be used to sense the voltage at the output of the RLD amplifier. The comparator thresholds are set by the same LOFF[7:5] bits used to set the thresholds for other negative inputs. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 35 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.3.10.2.4 Right Leg Drive (RLD DC Bias Circuit) The right leg drive (RLD) circuitry is used as a means to counter the common-mode interference in a ECG system as a result of power lines and other sources, including fluorescent lights. The RLD circuit senses the common-mode of a selected set of electrodes and creates a negative feedback loop by driving the body with an inverted common-mode signal. The negative feedback loop restricts the common-mode movement to a narrow range, depending on the loop gain. Stabilizing the entire loop is specific to the individual user system based on the various poles in the loop. The ADS1291, ADS1292, and ADS1292R integrates the muxes to select the channel and an operational amplifier. All the amplifier terminals are available at the pins, allowing the user to choose the components for the feedback loop. The circuit shown in Figure 40 shows the overall functional connectivity for the RLD bias circuit. The reference voltage for the right leg drive can be chosen to be internally generated (AVDD + AVSS) / 2 or it can be provided externally with a resistive divider. The selection of an internal versus external reference voltage for the RLD loop is defined by writing the appropriate value to the RLDREF_INT bit in the RESP2 register. From MUX1P RLD1P 400 k PGA1P 150 k RLD2P 400 k PGA2P 60 k 150 k From MUX1N From MUX2P 150 k 60 k 400 k PGA1N RLD1N 150 k 400 k PGA2N From MUX2N RLD2N RLDINV (1) CEXT 1.5 nF (1) REXT 1M RLDOUT RLD Amp (AVDD + AVSS) 2 RLDREF_INT RLDIN/RLDREF RLDREF_INT To MUX (1) Typical values. Figure 40. RLD Channel Selection If the RLD function is not used, the amplifier can be powered down using the PDB_RLD bit. This bit is also used in daisy-chain mode to power-down all but one of the RLD amplifiers. The functionality of the RLDIN pin is explained in the Input Multiplexer section. 36 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.3.10.2.4.1 RLD Configuration With Multiple Devices RLDIN/ RLDREF RLD OUT Power-Down (AVDD+AVSS) 2 RLDIN/ RLDREF RLD OUT Device N VA1 RLDINV VA2 To Input MUX (AVDD+AVSS) 2 To Input MUX To Input MUX Figure 41 shows multiple devices connected to an RLD. Device 2 VA1 VA2 RLDINV RLDIN/ RLDREF (AVDD+AVSS) 2 Device 1 VA1 RLD OUT REXT VA2 RLDINV CEXT Figure 41. RLD Connection for Multiple Devices 8.3.10.3 PACE Detect The ADS1291 and ADS1292 provide flexibility for PACE detection by using an external hardware. The external hardware approach is made possible by bringing out the output of the PGA at pins: PGA1P, PGA1N and PGA2P, PGA2N. External hardware circuitry can be used to detect the presence of the pulse. The output of the PACE detection logic can then be fed into the device through one of the GPIO pins. The GPIO data are transmitted through the SPI port and loaded 2 tCLKs before DRDY goes low. When in pace detection mode, the chopping ripple can interfere with pace detect in hardware. It is therefore preffered to chop thee PGA at a higher frequency (32 kHz or 64 kHz). The RC filter at the PGA output, suppresses this ripple to a reasonable level. Additionally, suppression can be obtained with an additional RC stage. The trade-off with chopping the PGA at a higher frequency is an increase in the input bias current. Figure 6 shows bias current versus input voltage for three different chop frequencies. 8.3.10.4 Respiration The ADS1292R provides two options for respiration: internal respiration with external clock and internal respiration with internal clock, as shown in Table 11. Table 11. Respiration Control RESP_CTRL DESCRIPTION 0 Internal respiration with internal clock 1 Internal respiration with external clock Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 37 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.3.10.4.1 Internal Respiration Circuitry With Internal Clock (ADS1292R) This mode is set by RESP_CTRL = 0. Figure 42 shows a block diagram of the internal respiration circuitry. The internal modulation and demodulator circuitry can be selectively used. The modulation block is controlled by the RESP_MOD_EN bit and the demodulation block is controlled by the RESP_DEMOD_EN bit. The modulation signal is a square wave of the magnitude VREFP – AVSS. When the internal modulation circuitry is used, the output of the modulation circuitry is available at the RESP_MODP and RESP_MODM pins of the device. This availability allows custom filtering to be added to the square wave modulation signal. In this mode, GPIO1 and GPIO2 can be used for other purposes. The modulation frequency of the respiration circuit is set by the RESP_FREQ bits. CLK (512 kHz) CLK GEN RESP_FREQ RESP_MOD_EN RESP_MODP VREFP RESP_CTRL Modulation Block RESP_MODN RESP_MOD_EN AVSS I/O RESP_CTRL RESP_MOD_CLK I/O GPIO1 I/O GPIO2 IN1P EMI Filter VBIAS MUX Ch1 PGA Ch1 ADC Demodulation Block IN1N RESP_DEMOD_EN PGA1P PGA1N 47 nF Figure 42. Internal Respiration Timing Diagram 38 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.3.10.4.2 Internal Respiration Circuitry With External Clock (ADS1292R) This mode is set by RESP_CTRL = 1. In this mode GPIO1 and GPIO2 are automatically configured as inputs. GPIO1 and GPIO2 cannot be used for other purposes. The signals must be provided as described in Figure 43. An external, synchronous master clock (CLK) is required for this mode in order to operate. (Modulation Clock) GPIO1 tPHASE tBLKDLY (Blocking Signal) GPIO2 Figure 43. Internal Respiration (RESP_CTRL = 1) Timing Diagram Table 12. Timing Characteristics for Figure 43 (1) 1.65 V ≤ DVDD ≤ 3.6 V PARAMETER MIN tPHASE Respiration phase delay tBLKDLY Modulation clock rising edge to XOR signal (1) TYP 0 MAX 168.75 0 UNIT Degrees 5 ns Specifications apply from –40°C to +85°C. 8.3.11 Setting the Device for Basic Data Capture This section outlines the procedure to configure the device in a basic state and capture data. This procedure is intended to put the device in a data sheet condition to check if the device is working properly in the user's system. It is recommended that this procedure be followed initially to get familiar with the device settings. Once this procedure has been verified, the device can be configured as needed. For details on the timings for commands refer to the appropriate sections in the data sheet. Also, some sample programming codes are added for the ECG-specific functions. Figure 44 details a flow chart of the configuration procedure. 8.3.11.1 Lead-Off Sample code to set dc lead-off with current source or sink resistors on all channels WREG LOFF 10h // Comparator threshold at 95% and 5%, current source or sink resistor // DC lead-off WREG CONFIG2 E0h // Turn-on dc lead-off comparators WREG LOFF_SENS 0Fh // Turn on both P- and N-side of all channels for lead-off sensing Observe the status bits of the output data stream to monitor lead-off status. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 39 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Analog/Digital Power-Up Set CLKSEL Pin = 0 and Provide External Clock fCLK = 512 kHz Yes // Follow Power-Up Sequencing External Clock No Set CLKSEL Pin = 1 and Wait for Oscillator to Wake Up // If START is Tied High, After This Step // DRDY Toggles at fMOD/256 Set PWDN/RESET = 1 Wait for 1 s for Power-On Reset // Delay for Power-On Reset and Oscillator Start-Up Issue Reset Pulse, Wait for 18 tCLKs Set PDB_REFBUF = 1 and Wait for Internal Reference To Settle // Activate DUT //CS can be Either Tied Permanently Low // Or Selectively Pulled Low Before Sending // Commands or Reading/Sending Data From/To Device Send SDATAC Command // Device Wakes Up in RDATAC Mode, so Send // SDATAC Command so Registers can be Written SDATAC External Reference // If Using Internal Reference, Send This Command -- WREG CONFIG2 A0h No Yes Write Certain Registers, Including Input Short // DRATE = 500 SPS WREG CONFIG1 02h // Set All Channels to Input Short WREG CHnSET 01h Set START = 1 // Activate Conversion // After This Point DRDY Should Toggle at // fCLK Review RDATAC // Put the Device Back in RDATAC Mode RDATAC Capture Data and Check Noise Set Test Signals Capture Data and Test Signals // Look for DRDY and Issue 24 + n 24 SCLKs // Activate a (1 mV VREF/2.4) Square-Wave Test Signal // On All Channels SDATAC WREG CONFIG2 A3h WREG CHnSET 05h RDATAC // Look for DRDY and Issue 24 + n 24 SCLKs Figure 44. Initial Flow at Power-Up 40 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.4 Device Functional Modes The ADS1291, ADS1292, and ADS1292R can be used in different functional modes, as a single device in a system, or as multiple devices in a system. The ADS1291, ADS1292, and ADS1292R are designed to provide configuration flexibility when multiple devices are used in a system, as explained in the Multiple Device Configuration section. In terms of data conversion, the device can operate in continuous mode as explained in the Continuous mode section, or in single-shot mode as explained in the Single-shot mode section. 8.5 Programming 8.5.1 SPI Interface The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads conversion data, reads and writes registers, and controls ADS1291, ADS1292, and ADS1292R operation. The DRDY output is used as a status signal to indicate when data are ready. DRDY goes low when new data are available. 8.5.1.1 Chip Select (CS) CS selects the ADS1291, ADS1292, and ADS1292R for SPI communication. CS must remain low for the entire duration of the serial communication. After the serial communication is finished, always wait four or more tCLK cycles before taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored, and DOUT enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is high or low. 8.5.1.2 Serial Clock (SCLK) SCLK is the serial peripheral interface (SPI) serial clock. SCLK is used to shift commands in and shift data out from the device. The serial clock features a Schmitt-triggered input and clocks data on the DIN and DOUT pins into and out of the ADS1291, ADS1292, and ADS1292R. Even though the input has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally forcing a clock event. The absolute maximum SCLK limit is specified in the Serial Interface Timing table. When shifting in commands with SCLK, make sure that the entire set of SCLKs is issued to the device. Failure to do so could result in the device serial interface being placed into an unknown state, requiring CS to be taken high to recover. For a single device, the minimum speed needed for the SCLK depends on the number of channels, number of bits of resolution, and output data rate. (For multiple cascaded devices, see the Cascade Mode subsection of the Multiple Device Configuration section.) The minimum speed can be calculated with Equation 9. tDR - 4 tCLK tSCLK < 72 (2 x 24 bits +STATUS) (9) For example, if the ADS1292R is used in a 500-SPS mode (2 channels, 24-bit resolution), the minimum SCLK speed is approximately 36 kHz. Data retrieval can be done either by putting the device in RDATAC mode or by issuing a RDATA command for data on demand. The above SCLK rate limitation applies to RDATAC. For the RDATA command, the limitation applies if data must be read in between two consecutive DRDY signals. Equation 9 assumes that there are no other commands issued in between data captures. SCLK can only be twice the speed of fCLK during register reads and writes. For faster SPI interface, use fCLK = 2.048 MHz and set the CLK_DIV register bit (in the LOFF_STAT register) to '1'. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 41 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Programming (continued) 8.5.1.3 Data Input (DIN) The data input pin (DIN) is used along with SCLK to communicate with the ADS1291, ADS1292, and ADS1292R (opcode commands and register data). The device latches data on DIN on the SCLK falling edge. 8.5.1.4 Data Output (DOUT) The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS1291, ADS1292, and ADS1292R. The START pin must transition from low to high before the data output pin can generate any data. Data on DOUT are shifted out on the SCLK rising edge. DOUT goes to a high-impedance state when CS is high. Figure 45 shows the data output protocol for the ADS1292 and ADS1292R. DRDY CS SCLK DOUT STAT CH1 CH2 24-Bit 24-Bit 24-Bit DIN Figure 45. SPI Bus Data Output for the ADS1292 and ADS1292R (Two Channels) 8.5.1.5 Data Retrieval Data retrieval can be accomplished in one of two methods. The read data continuous command (see the RDATAC: Read Data Continuous section) can be used to set the device in a mode to read the data continuously without sending opcodes. The read data command (see the RDATA: Read Data section) can be used to read just one data output from the device (see the SPI Command Definitions section for more details). The conversion data are read by shifting data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the entire read operation. The number of bits in the data output depends on the number of channels and the number of bits per channel. For the ADS1292R, the number of data outputs is (24 status bits + 24 bits × 2 channels) = 72 bits. The format of the 24 status bits is: (1100 + LOFF_STAT[4:0] + GPIO[1:0] + 13 '0's). The data format for each channel data is twos complement, MSB first. When channels are powered down using user register settings, the corresponding channel output is set to '0'. However, the sequence of channel outputs remains the same. The ADS1291, ADS1292, and ADS1292R also provide a multiple readback feature. Data can be read out multiple times by simply giving more SCLKs, in which case the MSB data byte repeats after reading the last byte. 8.5.1.6 Data Ready (DRDY) DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the data ready signal. The behavior of DRDY is determined by whether the device is in RDATAC mode or the RDATA command is being used to read data on demand. (See the RDATAC: Read Data Continuous and RDATA: Read Data subsections of the SPI Command Definitions section for further details). When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY without data corruption. The START pin or the START command is used to place the device either in normal data capture mode or pulse data capture mode. 42 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 Programming (continued) Figure 46 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an ADS1291, ADS1292, and ADS1292R with a selected data rate that gives 24-bit resolution). DOUT is latched out at the SCLK rising edge. DRDY is pulled high at the SCLK falling edge. Note that DRDY goes high on the first SCLK falling edge regardless of the status of CS and regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin. DRDY Bit 71 DOUT Bit 70 Bit 69 SCLK Figure 46. DRDY with Data Retrieval (CS = 0) 8.5.1.7 GPIO The ADS1291, ADS1292, and ADS1292R have a total of two general-purpose digital input/output (GPIO) pins available in the normal mode of operation. The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC bits register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits, the data returned are the logic level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a write to the GPIOD bit sets the output value. If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on or after a reset. Figure 47 shows the GPIO port structure. The pins should be shorted to DGND with a series resistor if not used. GPIO Data (read) GPIO Pin GPIO Data (write) GPIO Control Figure 47. GPIO Port Pin 8.5.1.8 Power-Down and Reset (PWDN/RESET) The PWDN/RESET pins are shared. If PWDN/RESET is held low for longer than 29 fMOD clock cycles, the device is powered down. The implementation is such that the device is always reset when PWDN/RESET makes a transition from high to low. If the device is powered down it is reset first and then if 210 clock elapses it is powered down. Hence, all registers must be rewritten after power up. There are two methods to reset the ADS1291, ADS1292, and ADS1292R: pull the PWDN/RESET pin low, or send the RESET opcode command. When using the PWDN/RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the PWDN/RESET pin back high. The RESET command takes effect on the eighth SCLK falling edge of the opcode command. On reset it takes 18 tCLK cycles to complete initialization of the configuration registers to the default states and start the conversion cycle. Note that an internal RESET is automatically issued to the digital filter whenever the CONFIG1, RESP1, and RESP2 registers are set to a new value with a WREG command. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 43 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Programming (continued) 8.5.1.9 START The START pin must be set high or the START command sent to begin conversions. When START is low or if the START command has not been sent, the device does not issue a DRDY signal (conversions are halted). When using the START opcode to control conversion, hold the START pin low. The ADS1291, ADS1292, and ADS1292R feature two modes to control conversion: continuous mode and single-shot mode. The mode is selected by SINGLE_SHOT (bit 7 of the CONFIG1 register). In multiple device configurations the START pin is used to synchronize devices (see the Multiple Device Configuration subsection of the SPI Interface section for more details). 8.5.1.10 Settling Time The settling time (tSETTLE) is the time it takes for the converter to output fully settled data when the START signal is pulled high. Once START is pulled high, DRDY is also pulled high. The next DRDY falling edge indicates that data are ready. Figure 48 shows the timing diagram and Table 13 shows the settling time for different data rates. The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 register). Refer to Table 10 for the settling time as a function of tMOD. Note that when START is held high and there is a step change in the input signal, it takes 3 tDR for the filter to settle to the new value. Settled data are available on the fourth DRDY pulse. Settling time number uncertainty is one tMOD cycle. Therefore, it is recommended to add one tMOD cycle delay before issuing SCLK to retrieve data. tSETTLE START Pin or START Opcode DIN tDR 4 / fCLK DRDY (1) Settling time uncertainty is one tMOD cycle. Figure 48. Settling Time Table 13. Settling Time for Different Data Rates (1) (2) 44 DR[2:0] SETTLING TIME (1) UNIT (2) 000 4100 tMOD 001 2052 tMOD 010 1028 tMOD 011 516 tMOD 100 260 tMOD 101 132 tMOD 110 68 tMOD 111 — — Settling time uncertainty is one tMOD cycle. tMOD = 4 tCLK for CLK_DIV = 0 and tMOD = 16 tCLK for CLK_DIV = 1. Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.5.1.11 Continuous Mode Conversions begin when the START pin is taken high or when the START opcode command is sent. As seen in Figure 49, the DRDY output goes high when conversions are started and goes low when data are ready. Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted. When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to complete. Figure 50 and Table 14 show the required DRDY timing to the START pin and the START and STOP opcode commands when controlling conversions in this mode. To keep the converter running continuously, the START pin can be permanently tied high. Note that when switching from pulse mode to continuous mode, the START signal is pulsed or a STOP command must be issued, followed by a START command. This conversion mode is ideal for applications that require a fixed continuous stream of conversions results. START Pin or or (1) DIN (1) START Opcode STOP Opcode tDR tSETTLE DRDY (1) START and STOP opcode commands take effect on the seventh SCLK falling edge. Figure 49. Continuous Conversion Mode tSDSU DRDY and DOUT tDSHD START Pin or STOP Opcode (1) STOP(1) STOP(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission. Figure 50. START to DRDY Timing Table 14. Timing Characteristics for Figure 50 (1) MIN UNIT tSDSU START pin low or STOP opcode to DRDY setup time to halt further conversions PARAMETER 8 tMOD tDSHD START pin low or STOP opcode to complete current conversion 8 tMOD (1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 45 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.5.1.12 Single-Shot Mode The single-shot mode is enabled by setting the SINGLE_SHOT bit in the CONFIG1 register to '1'. In single-shot mode, the ADS1291, ADS1292, and ADS1292R perform a single conversion when the START pin is taken high or when the START opcode command is sent. As seen in Figure 50, when a conversion is complete, DRDY goes low and further conversions are stopped. Regardless of whether the conversion data are read or not, DRDY remains low. To begin a new conversion, take the START pin low and then back high, or transmit the START opcode again. When switching from continuous mode to pulse mode, make sure the START signal is pulsed or issue a STOP command followed by a START command. This conversion mode is provided for applications that require non-standard or non-continuous data rates. Issuing a START command or toggling the START pin high resets the digital filter, effectively dropping the data rate by a factor of four. Note that this mode leaves the system more susceptible to aliasing effects, requiring more complex analog anti-aliasing filters at the inputs. Loading on the host processor increases because it must toggle the START pin or send a START command to initiate a new conversion cycle. START tSETTLE 4 / fCLK Data Updating 4 / fCLK DRDY Figure 51. DRDY with No Data Retrieval in Single-Shot Mode 46 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.5.2 SPI Command Definitions The ADS1291, ADS1292, and ADS1292R provide flexible configuration control. The opcode commands summarized in Table 15 control and configure the ADS1291, ADS1292, and ADS1292R operation. The opcode commands are stand-alone, except for the register read and register write operations that require a second command byte plus data. CS can be taken high or held low between opcode commands but must stay low for the entire command operation (especially for multi-byte commands). System opcode commands and the RDATA command are decoded by the ADS1291, ADS1292, and ADS1292R on the seventh SCLK falling edge. The register read and write opcodes are decoded on the eighth SCLK falling edge. Be sure to follow SPI timing requirements when pulling CS high after issuing a command. Table 15. Command Definitions COMMAND DESCRIPTION FIRST BYTE SECOND BYTE System Commands WAKEUP Wake-up from standby mode 0000 0010 (02h) STANDBY Enter standby mode 0000 0100 (04h) RESET Reset the device 0000 0110 (06h) START Start or restart (synchronize) conversions 0000 1000 (08h) STOP Stop conversion 0000 1010 (0Ah) OFFSETCAL Channel offset calibration 0001 1010 (1Ah) Data Read Commands RDATAC Enable Read Data Continuous mode. This mode is the default mode at power-up. (1) 0001 0000 (10h) SDATAC Stop Read Data Continuously mode 0001 0001 (11h) RDATA Read data by command; supports multiple read back. 0001 0010 (12h) Register Read Commands RREG Read n nnnn registers starting at address r rrrr 001r rrrr (2xh) (2) 000n nnnn (2) WREG Write n nnnn registers starting at address r rrrr 010r rrrr (4xh) (2) 000n nnnn (2) (1) (2) When in RDATAC mode, the RREG command is ignored. n nnnn = number of registers to be read or written – 1. For example, to read or write three registers, set n nnnn = 0 (0010). r rrrr = starting register address for read and write opcodes. 8.5.2.1 WAKEUP: Exit STANDBY Mode This opcode exits the low-power standby mode; see the STANDBY: Enter STANDBY Mode subsection of the SPI Command Definitions section. Time is required when exiting standby mode (see the Electrical Characteristics for details). There are no restrictions on the SCLK rate for this command and it can be issued any time. Any following command must be sent after 4 tCLK cycles. 8.5.2.2 STANDBY: Enter STANDBY Mode This opcode command enters the low-power standby mode. All parts of the circuit are shut down except for the reference section. The standby mode power consumption is specified in the Electrical Characteristics. There are no restrictions on the SCLK rate for this command and it can be issued any time. Do not send any other command other than the wakeup command after the device enters the standby mode. 8.5.2.3 RESET: Reset Registers to Default Values This command resets the digital filter cycle and returns all register settings to the default values. See the Reset (RESET) subsection of the SPI Interface section for more details. There are no restrictions on the SCLK rate for this command and it can be issued any time. It takes 9 fMOD cycles to execute the RESET command. Avoid sending any commands during this time. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 47 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.5.2.4 START: Start Conversions This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the START command is immediately followed by a STOP command then have a gap of 4 tCLK cycles between them. When the START opcode is sent to the device, keep the START pin low until the STOP command is issued. (See the START subsection of the SPI Interface section for more details.) There are no restrictions on the SCLK rate for this command and it can be issued any time. 8.5.2.5 STOP: Stop Conversions This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP command is sent, the conversion in progress completes and further conversions are stopped. If conversions are already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command and it can be issued any time. 8.5.2.6 OFFSETCAL: Channel Offset Calibration This command is used to cancel the channel offset. The CALIB_ON bit in the RESP2 register must be set to '1' before issuing this command. OFFSETCAL must be executed every time there is a change in the PGA gain settings. 8.5.2.7 RDATAC: Read Data Continuous This opcode enables the output of conversion data on each DRDY without the need to issue subsequent read data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The read data continuous mode is the device default mode; the device defaults to this mode on power-up. RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a SDATAC command must be issued before any other commands can be sent to the device. There is no restriction on the SCLK rate for this command. However, the subsequent data retrieval SCLKs or the SDATAC opcode command should wait at least 4 tCLK cycles. RDATAC timing is shown in Figure 52. As Figure 52 shows, there is a keep out zone of 4 tCLK cycles around the DRDY pulse where this command cannot be issued in. To retrieve data from the device after RDATAC command is issued, make sure either the START pin is high or the START command is issued. Figure 52 shows the recommended way to use the RDATAC command. RDATAC is ideally-suited for applications such as data loggers or recorders where registers are set once and do not need to be re-configured. START DRDY tUPDATE (1) CS SCLK RDATAC Opcode DIN Hi-Z DOUT STATUS Word + Channel Data (up to 72 bits) (1) Next Data tUPDATE = 4 x tCLK. Do not read data during this time. Figure 52. RDATAC Usage 48 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.5.2.8 SDATAC: Stop Read Data Continuous This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this command, but the following command must wait for 4 tCLK cycles. 8.5.2.9 RDATA: Read Data Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode). There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent commands or data retrieval SCLKs. To retrieve data from the device after RDATA command is issued, make sure either the START pin is high or the START command is issued. When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY without data corruption. Figure 53 shows the recommended way to use the RDATA command. RDATA is best suited for ECG- and EEG-type systems where register setting must be read or changed often between conversion cycles. START DRDY CS SCLK RDATA Opcode DIN RDATA Opcode Hi-Z DOUT STATUS Word + Channel Data (up to 72 bits) Figure 53. RDATA Usage 8.5.2.10 Sending Multi-Byte Commands The ADS1291, ADS1292, and ADS1292R serial interface decodes commands in bytes and requires 4 tCLK cycles to decode and execute. Therefore, when sending multi-byte commands, a 4 tCLK period must separate the end of one byte (or opcode) and the next. Assume CLK is 512 kHz, then tSDECODE (4 tCLK) is 7.8125 µs. When SCLK is 16 MHz, one byte can be transferred in 500 ns. This byte-transfer time does not meet the tSDECODE specification; therefore, a delay must be inserted so the end of the second byte arrives 7.3125 µs later. If SCLK is 1 MHz, one byte is transferred in 8 µs. Because this transfer time exceeds the tSDECODE specification, the processor can send subsequent bytes without delay. In this later scenario, the serial port can be programmed to move from single-byte transfer per cycle to multiple bytes. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 49 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.5.2.11 RREG: Read From Register This opcode reads register data. The Register Read command is a two-byte opcode followed by the output of the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to read – 1. First opcode byte: 001r rrrr, where r rrrr is the starting register address. Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1. The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 54. When the device is in read data continuous mode it is necessary to issue a SDATAC command before the RREG command can be issued. The RREG command can be issued at any time. However, because this command is a multi-byte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for the entire command. CS 1 9 17 25 SCLK DIN OPCODE 1 OPCODE 2 REG DATA DOUT REG DATA + 1 Figure 54. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register) (OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001) 8.5.2.12 WREG: Write to Register This opcode writes register data. The Register Write command is a two-byte opcode followed by the input of the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to write – 1. First opcode byte: 010r rrrr, where r rrrr is the starting register address. Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1. After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 55. The WREG command can be issued at any time. However, because this command is a multi-byte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for the entire command. CS 1 9 17 25 SCLK DIN OPCODE 1 OPCODE 2 REG DATA 1 REG DATA 2 DOUT Figure 55. WREG Command Example: Write Two Registers Starting from 00h (ID Register) (OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001) 50 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.6 Register Maps Table 16 describes the various ADS1291, ADS1292, and ADS1292R registers. Table 16. Register Assignments ADDRESS REGISTER RESET VALUE (Hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 XX REV_ID7 REV_ID6 REV_ID5 1 0 0 REV_ID1 REV_ID0 0 DR2 DR1 DR0 Device Settings (Read-Only Registers) 00h ID Global Settings Across Channels 01h CONFIG1 02 SINGLE_ SHOT 0 0 0 02h CONFIG2 80 1 PDB_LOFF_ COMP PDB_REFBUF VREF_4V CLK_EN 0 INT_TEST TEST_FREQ 03h LOFF 10 COMP_TH2 COMP_TH1 COMP_TH0 1 ILEAD_OFF1 ILEAD_OFF0 0 FLEAD_OFF Channel-Specific Settings 04h CH1SET 00 PD1 GAIN1_2 GAIN1_1 GAIN1_0 MUX1_3 MUX1_2 MUX1_1 MUX1_0 05h CH2SET 00 PD2 GAIN2_2 GAIN2_1 GAIN2_0 MUX2_3 MUX2_2 MUX2_1 MUX2_0 06h RLD_SENS 00 CHOP1 CHOP0 PDB_RLD RLD_LOFF_ SENS RLD2N RLD2P RLD1N RLD1P 07h LOFF_SENS 00 0 0 FLIP2 FLIP1 LOFF2N LOFF2P LOFF1N LOFF1P 08h LOFF_STAT 00 0 CLK_DIV 0 RLD_STAT IN2N_OFF IN2P_OFF IN1N_OFF IN1P_OFF 00 RESP_ DEMOD_EN1 RESP_MOD_ EN RESP_PH3 RESP_PH2 RESP_PH1 RESP_PH0 1 RESP_CTRL GPIO and Other Registers 09h RESP1 0Ah RESP2 02 CALIB_ON 0 0 0 0 RESP_FREQ RLDREF_INT 1 0Bh GPIO 0C 0 0 0 0 GPIOC2 GPIOC1 GPIOD2 GPIOD1 Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 51 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.6.1 User Register Description 8.6.1.1 ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h) This register is programmed during device manufacture to indicate device characteristics. Figure 56. ID: ID Control Register (Factory-Programmed, Read-Only) 7 REV_ID7 6 REV_ID6 5 REV_ID5 4 1 3 0 2 0 1 REV_ID1 0 REV_ID0 Table 17. ID: ID Control Register (Factory-Programmed, Read-Only) Field Descriptions Bits[7:5] REV_ID[7:5]: Revision identification 000 = Reserved 001 = Reserved 010 = ADS1x9x device 011 = ADS1292R device 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved Bit 4 Reads high Bits[3:2] Reads low Bits[1:0] REV_ID[1:0]: Revision identification 00 01 10 11 = ADS1191 = ADS1192 = ADS1291 = ADS1292 and ADS1292R 8.6.1.2 CONFIG1: Configuration Register 1 (address = 01h) This register configures each ADC channel sample rate. Figure 57. CONFIG1: Configuration Register 1 7 SINGLE_SHOT 6 0 5 0 4 0 3 0 2 DR2 1 DR1 0 DR0 Table 18. CONFIG1: Configuration Register 1 Field Descriptions Bit 7 SINGLE_SHOT: Single-shot conversion This bit sets the conversion mode 0 = Continuous conversion mode (default) 1 = Single-shot mode Bits[6:3] Must be set to '0' Bits[2:0] DR[2:0]: Channel oversampling ratio These bits determine the oversampling ratio of both channel 1 and channel 2. (1) 52 DATA RATE (1) BIT OVERSAMPLING RATIO 000 fMOD / 1024 125 SPS 001 fMOD / 512 250 SPS 010 fMOD / 256 500 SPS (default) 011 fMOD / 128 1 kSPS 100 fMOD / 64 2 kSPS 101 fMOD / 32 4 kSPS 110 fMOD / 16 8 kSPS 111 Do not use Do not use fCLK = 512 kHz and CLK_DIV = 0 or fCLK = 2.048 MHz and CLK_DIV = 1. Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.6.1.3 CONFIG2: Configuration Register 2 (address = 02h) This register configures the test signal, clock, reference, and LOFF buffer. Figure 58. CONFIG2: Configuration Register 2 7 1 6 PDB_LOFF_ COMP 5 4 3 2 1 0 PDB_REFBUF VREF_4V CLK_EN 0 INT_TEST TEST_FREQ Table 19. CONFIG2: Configuration Register 2 Field Descriptions Bit 7 Must be set to '1' Bit 6 PDB_LOFF_COMP: Lead-off comparator power-down This bit powers down the lead-off comparators. 0 = Lead-off comparators disabled (default) 1 = Lead-off comparators enabled Bit 5 PDB_REFBUF: Reference buffer power-down This bit powers down the internal reference buffer so that the external reference can be used. 0 = Reference buffer is powered down (default) 1 = Reference buffer is enabled Bit 4 VREF_4V: Enables 4-V reference This bit chooses between 2.42-V and 4.033-V reference. 0 = 2.42-V reference (default) 1 = 4.033-V reference Bit 3 CLK_EN: CLK connection This bit determines if the internal oscillator signal is connected to the CLK pin when an internal oscillator is used. 0 = Oscillator clock output disabled (default) 1 = Oscillator clock output enabled Bit 2 Must be set to '0' Bit 1 INT_TEST: Test signal selection This bit determines whether the test signal is turned on or off. 0 = Off (default) 1 = On; amplitude = ±(VREFP – VREFN) / 2400 Bit 0 TEST_FREQ: Test signal frequency This bit determines the test signal frequency. 0 = At dc (default) 1 = Square wave at 1 Hz Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 53 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.6.1.4 LOFF: Lead-Off Control Register (address = 03h) This register configures the lead-off detection operation. Figure 59. LOFF: Lead-Off Control Register 7 COMP_TH2 6 COMP_TH1 5 COMP_TH0 4 1 3 ILEAD_OFF1 2 ILEAD_OFF0 1 0 0 FLEAD_OFF Table 20. LOFF: Lead-Off Control Register Field Descriptions Bits[7:5] COMP_TH[2:0]: Lead-off comparator threshold These bits determine the lead-off comparator threshold. See the Lead-Off Detection subsection of the ECG-Specific Functions section for a detailed description. Comparator positive side 000 = 95% (default) 001 = 92.5% 010 = 90% 011 = 87.5% 100 = 85% 101 = 80% 110 = 75% 111 = 70% Comparator negative side 000 = 5% (default) 001 = 7.5% 010 = 10% 011 = 12.5% 100 = 15% 101 = 20% 110 = 25% 111 = 30% Bit 4 Must be set to '1' Bits[3:2] ILEAD_OFF[1:0]: Lead-off current magnitude These bits determine the magnitude of current for the current lead-off mode. 00 = 6 nA (default) 01 = 22 nA 10 = 6 µA 11 = 22 µA Bit 1 Must be set to '0' Bit 0 FLEAD_OFF: Lead-off frequency This bit selects ac or dc lead-off. 0 = At dc lead-off detect (default) 1 = At ac lead-off detect at fDR / 4 (500 Hz for an 2-kHz output rate) 54 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.6.1.5 CH1SET: Channel 1 Settings (address = 04h) This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer section for details. Figure 60. CH1SET: Channel 1 Settings 7 PD1 6 GAIN1_2 5 GAIN1_1 4 GAIN1_0 3 MUX1_3 2 MUX1_2 1 MUX1_1 0 MUX1_0 Table 21. CH1SET: Channel 1 Settings Field Descriptions Bit 7 PD1: Channel 1 power-down 0 = Normal operation (default) 1 = Channel 1 power-down (1) Bits[6:4] GAIN1[2:0]: Channel 1 PGA gain setting These bits determine the PGA gain setting for channel 1. 000 = 6 (default) 001 = 1 010 = 2 011 = 3 100 = 4 101 = 8 110 = 12 Bits[3:0] MUX1[3:0]: Channel 1 input selection These bits determine the channel 1 input selection. 0000 = Normal electrode input (default) 0001 = Input shorted (for offset measurements) 0010 = RLD_MEASURE 0011 = MVDD (2) for supply measurement 0100 = Temperature sensor 0101 = Test signal 0110 = RLD_DRP (positive input is connected to RLDIN) 0111 = RLD_DRM (negative input is connected to RLDIN) 1000 = RLD_DRPM (both positive and negative inputs are connected to RLDIN) 1001 = Route IN3P and IN3N to channel 1 inputs 1010 = Reserved (1) (2) When powering down channel 1, make sure the input multiplexer is set to input short configuration. Bits[3:0] = 001. For channel 1, (MVDDP – MVDDN) is [0.5(AVDD + AVSS)]; for channel 2, (MVDDP – MVDDN) is DVDD / 4. Note that to avoid saturating the PGA while measuring power supplies, the gain must be set to '1'. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 55 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.6.1.6 CH2SET: Channel 2 Settings (address = 05h) This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer section for details. Figure 61. CH2SET: Channel 2 Settings 7 PD2 6 GAIN2_2 5 GAIN2_1 4 GAIN2_0 3 MUX2_3 2 MUX2_2 1 MUX2_1 0 MUX2_0 Table 22. CH2SET: Channel 2 Settings Field Descriptions Bit 7 PD2: Channel 2 power-down 0 = Normal operation (default) 1 = Channel 2 power-down (1) Bits[6:4] GAIN2[2:0]: Channel 2 PGA gain setting These bits determine the PGA gain setting for channel 2. 000 = 6 (default) 001 = 1 010 = 2 011 = 3 100 = 4 101 = 8 110 = 12 Bits[3:0] MUX2[3:0]: Channel 2 input selection These bits determine the channel 2 input selection. 0000 = Normal electrode input (default) 0001 = Input shorted (for offset measurements) 0010 = RLD_MEASURE 0011 = VDD / 2 for supply measurement 0100 = Temperature sensor 0101 = Test signal 0110 = RLD_DRP (positive input is connected to RLDIN) 0111 = RLD_DRM (negative input is connected to RLDIN) 1000 = RLD_DRPM (both positive and negative inputs are connected to RLDIN) 1001 = Route IN3P and IN3N to channel 2 inputs 1010 = Reserved (1) 56 When powering down channel 2 and for ADS1291, make sure the input multiplexer is set to input short configuration. Bits[3:0] = 001. Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.6.1.7 RLD_SENS: Right Leg Drive Sense Selection (address = 06h) This register controls the selection of the positive and negative signals from each channel for right leg drive derivation. See the Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for details. Figure 62. RLD_SENS: Right Leg Drive Sense Selection 7 6 5 CHOP1 CHOP0 PDB_RLD 4 RLD_LOFF_ SENS 3 2 1 0 RLD2N RLD2P RLD1N RLD1P Table 23. RLD_SENS: Right Leg Drive Sense Selection Field Descriptions Bits[7:6] CHOP[1:0]: Chop frequency These bits determine PGA chop frequency 00 = fMOD / 16 01 = Reserved 10 = fMOD / 2 11 = fMOD / 4 Bit 5 PDB_RLD: RLD buffer power This bit determines the RLD buffer power state. 0 = RLD buffer is powered down (default) 1 = RLD buffer is enabled Bit 4 RLD_LOFF_SENSE: RLD lead-off sense function This bit enables the RLD lead-off sense function. 0 = RLD lead-off sense is disabled (default) 1 = RLD lead-off sense is enabled Bit 3 RLD2N: Channel 2 RLD negative inputs This bit controls the selection of negative inputs from channel 2 for right leg drive derivation. 0 = Not connected (default) 1 = RLD connected to IN2N Bit 2 RLD2P: Channel 2 RLD positive inputs This bit controls the selection of positive inputs from channel 2 for right leg drive derivation. 0 = Not connected (default) 1 = RLD connected to IN2P Bit 1 RLD1N: Channel 1 RLD negative inputs This bit controls the selection of negative inputs from channel 1 for right leg drive derivation. 0 = Not connected (default) 1 = RLD connected to IN1N Bit 0 RLD1P: Channel 1 RLD positive inputs This bit controls the selection of positive inputs from channel 1 for right leg drive derivation. 0 = Not connected (default) 1 = RLD connected to IN1P Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 57 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.6.1.8 LOFF_SENS: Lead-Off Sense Selection (address = 07h) This register selects the positive and negative side from each channel for lead-off detection. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details. Note that the LOFF_STAT register bits should be ignored if the corresponding LOFF_SENS bits are set to '1'. Figure 63. LOFF_SENS: Lead-Off Sense Selection 7 0 6 0 5 FLIP2 4 FLIP1 3 LOFF2N 2 LOFF2P 1 LOFF1N 0 LOFF1P Table 24. LOFF_SENS: Lead-Off Sense Selection Field Descriptions Bits[7:6] Must be set to '0' Bit 5 FLIP2: Current direction selection This bit controls the direction of the current used for lead-off derivation for channel 2. 0 = Disabled (default) 1 = Enabled Bit 4 FLIP1: Current direction selection This bit controls the direction of the current used for lead-off derivation for channel 1. 0 = Disabled (default) 1 = Enabled Bit 3 LOFF2N: Channel 2 lead-off detection negative inputs This bit controls the selection of negative input from channel 2 for lead-off detection. 0 = Disabled (default) 1 = Enabled Bit 2 LOFF2P: Channel 2 lead-off detection positive inputs This bit controls the selection of positive input from channel 2 for lead-off detection. 0 = Disabled (default) 1 = Enabled Bit 1 LOFF1N: Channel 1 lead-off detection negative inputs This bit controls the selection of negative input from channel 1 for lead-off detection. 0 = Disabled (default) 1 = Enabled Bit 0 LOFF1P: Channel 1 lead-off detection positive inputs This bit controls the selection of positive input from channel 1 for lead-off detection. 0 = Disabled (default) 1 = Enabled 58 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.6.1.9 LOFF_STAT: Lead-Off Status (address = 08h) This register stores the status of whether the positive or negative electrode on each channel is on or off. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details. Ignore the LOFF_STAT values if the corresponding LOFF_SENS bits are not set to '1'. '0' is lead-on (default) and '1' is lead-off. When the LOFF_SENS bits[3:0] are '0', the LOFF_STAT bits should be ignored. Figure 64. LOFF_STAT: Lead-Off Status 7 6 5 0 CLK_DIV 0 4 RLD_STAT (read only) 3 IN2N_OFF (read only) 2 IN2P_OFF (read only) 1 IN1N_OFF (read only) 0 IN1P_OFF (read only) Table 25. LOFF_STAT: Lead-Off Status Field Descriptions Bit 7 Must be set to '0' Bit 6 CLK_DIV : Clock divider selection This bit sets the modultar divider ratio between fCLK and fMOD. Two external clock values are supported: 512 kHz and 2.048 MHz. 0 = fMOD = fCLK / 4 (default, use when fCLK = 512 kHz) 1 = fMOD = fCLK / 16 (use when fCLK = 2.048 MHz) Bit 5 Must be set to '0' Bit 4 RLD_STAT: RLD lead-off status This bit determines the status of RLD. 0 = RLD is connected (default) 1 = RLD is not connected Bit 3 IN2N_OFF: Channel 2 negative electrode status This bit determines if the channel 2 negative electrode is connected or not. 0 = Connected (default) 1 = Not connected Bit 2 IN2P_OFF: Channel 2 positive electrode status This bit determines if the channel 2 positive electrode is connected or not. 0 = Connected (default) 1 = Not connected Bit 1 IN1N_OFF: Channel 1 negative electrode status This bit determines if the channel 1 negative electrode is connected or not. 0 = Connected (default) 1 = Not connected Bit 0 IN1P_OFF: Channel 1 positive electrode status This bit determines if the channel 1 positive electrode is connected or not. 0 = Connected (default) 1 = Not connected Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 59 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 8.6.1.10 RESP1: Respiration Control Register 1 (address = 09h) This register controls the respiration functionality. This register applies to the ADS1292R version only. For the ADS1291 and ADS1292 devices, 02h must be written to the RESP1 register. Figure 65. RESP1: Respiration Control Register 1 7 RESP_ DEMOD_EN1 6 RESP_MOD_ EN 5 4 3 2 1 0 RESP_PH3 RESP_PH2 RESP_PH1 RESP_PH0 1 RESP_CTRL Table 26. RESP1: Respiration Control Register 1 Field Descriptions Bit 7 RESP_DEMOD_EN1: Enables respiration demodulation circuitry This bit enables and disables the demodulation circuitry on channel 1. 0 = RESP demodulation circuitry turned off (default) 1 = RESP demodulation circuitry turned on Bit 6 RESP_MOD_EN: Enables respiration modulation circuitry This bit enables and disables the modulation circuitry on channel 1. 0 = RESP modulation circuitry turned off (default) 1 = RESP modulation circuitry turned on Bits[5:2] RESP_PH[3:0]: Respiration phase (1) These bits control the phase of the respiration demodulation control signal. RESP_PH[3:0] RESP_CLK = 32kHz RESP_CLK = 64 kHz 0000 0° (default) 0° (default) 0001 11.25° 22.5° 0010 22.5° 45° 0011 33.75° 67.5° 0100 45° 90° 0101 56.25° 112.5° 0110 67.5° 135° 0111 78.75° 157.5° 1000 90° Not available 1001 101.25° Not available 1010 112.5° Not available 1011 123.75° Not available 1100 135° Not available 1101 146.25° Not available 1110 157.5° Not available 1111 168.75° Not available Bit 1 Must be set to '1' Bit 0 RESP_CTRL: Respiration control This bit sets the mode of the respiration circuitry. 0 = Internal respiration with internal clock 1 = Internal respiration with external clock (1) 60 The RESP_PH3 bit is ignored when RESP_CLK = 64 kHz. Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 8.6.1.11 RESP2: Respiration Control Register 2 (address = 0Ah) This register controls the respiration and calibration functionality. Figure 66. RESP2: Respiration Control Register 2 7 CALIB_ON 6 0 5 0 4 0 3 0 2 RESP_FREQ 1 RLDREF_INT 0 1 Table 27. RESP2: Respiration Control Register 2 Field Descriptions Bit 7 CALIB_ON: Calibration on This bit is used to enable offset calibration. 0 = Off (default) 1 = On Bits[6:3] Must be '0' Bit 2 RESP_FREQ: Respiration control frequency (ADS1292R only) This bit controls the respiration control frequency when RESP_CTRL = 0. This bit must be written with '1' for the ADS1291 and ADS1292. 0 = 32 kHz (default) 1 = 64 kHz Bit 1 RLDREF_INT: RLDREF signal This bit determines the RLDREF signal source. 0 = RLDREF signal fed externally 1 = RLDREF signal (AVDD – AVSS) / 2 generated internally (default) Bit 0 Must be set to '1' 8.6.1.12 GPIO: General-Purpose I/O Register (address = 0Bh) This register controls the GPIO pins. Figure 67. GPIO: General-Purpose I/O Register 7 0 6 0 5 0 4 0 3 GPIOC2 2 GPIOC1 1 GPIOD2 0 GPIOD1 Table 28. GPIO: General-Purpose I/O Register Field Descriptions Bits[7:4] Must be '0' Bits[3:2] GPIOC[2:1]: GPIO 1 and 2 control These bits determine if the corresponding GPIOD pin is an input or output. 0 = Output 1 = Input (default) Bits[1:0] GPIOD[2:1]: GPIO 1 and 2 data These bits are used to read and write data to the GPIO ports. When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the GPIOD has no effect. GPIO is not available in certain respiration modes. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 61 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The ADS1291, ADS1292, and ADS1292R incorporate all features commonly required in a low-power medical electrocardiogram (ECG) application. The ADS1291, ADS1292, and ADS1292R have a flexible input multiplexer per channel that can be independently connected to the internally-generated signals for test, temperature, and lead-off detection. Additionally, any configuration of input channels can be selected for derivation of the right leg drive (RLD) output signal. Lead-off detection can be implemented internal to the device, using the device internal excitation current sink or source. The ADS1292R version includes a fully integrated respiration impedance measurement function. 9.2 Typical Application A typical application for the ADS1292R is the acquisition of ECG signals in combination with a respiration impedance measurement. The ADS1292R channel 1 with respiration enabled mode cannot be used to acquire ECG signals. If the right arm (RA) and left arm (LA) leads are intended to measure respiration and ECG signals, the two leads can be wired into channel 1 for respiration and channel 2 for ECG signals, as shown in Figure 68. R6 10 MW AVDD R5 10 MW AVSS C2 0.1 mF IN1P C1 2.2 nF C3 2.2 nF ADS1292R R2 40.2 kW RESP_MODP Left Arm Lead IN2P IN2N RESP_MODN Right Arm Lead C6 0.1 mF R4 10 MW C4 2.2 nF R1 40.2 kW C5 2.2 nF AVDD R3 10 MW IN1N AVSS NOTE: Patient and input protection circuitry not shown. Figure 68. Typical Respiration Circuitry 62 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 Typical Application (continued) 9.2.1 Design Requirements This design requires the measurement of respiration and ECG signals on the right arm (RA) and left arm (LA) with very low noise. Standard requirements are respiration impedance values ranging from 2 kΩ to 15 kΩ, modulation clock frequencies of 32 kHz or 64 kHz, and noise levels of less than 10 µV. 9.2.2 Detailed Design Procedure Figure 69 shows a respiration test circuit. Figure 70 and Figure 71 plot noise on channel 1 for the ADS1292R as baseline impedance, gain, and phase are swept. The x-axis is the baseline impedance, normalized to a 30-µA modulation current (as shown in Equation 10). RACTUAL ´ IACTUAL RNORMALIZED = 30 mA where: RACTUAL is the baseline body impedance IACTUAL is the modulation current, as calculated by (VREFP – AVSS) divided by the impedance of the modulation circuit (10) For example, if modulation frequency = 32 kHz, RACTUAL = 3 kΩ, IACTUAL = 50 µA, and RNORMALIZED = (3 kΩ × 50 µA) / 29 µA = 5.1 kΩ. Referring to Figure 70 and Figure 71, it can be noted that gain = 4 and phase = 112.5° yield the best performance at 4.6 µVPP. Low-pass filtering this signal with a high-order 2-Hz cutoff can reduce the noise to less than 1200 nVPP. The impedance resolution is 1200 nVPP / 30 µA = 40 mΩ. When the modulation frequency is 32 kHz, gains of 3 and 4 and phase of 112.5° and 135° are recommended. When the modulation frequency is 64 kHz, gains of 2 and 3 and phase of 135° and 157° are recommended for best performance. Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 63 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Typical Application (continued) 9.2.3 Application Curves Figure 70 and Figure 71 show the results for the respiration test circuit of Figure 69 by plotting noise on channel 1 for the ADS1292R as baseline impedance, gain, and phase are swept. The x-axis is the baseline impedance, normalized to a 30-µA modulation current (as shown in Equation 10). 10 ADS1292R RESP_MODP RBASELINE = 2.21 kW RESP_MODN R2 40.2 kW Channel 1 Noise (µV) IN1P R2 40.2 kW 9 Data Rate = 125Hz Respiration Modulation Clock = 32kHz 8 7 6 5 4 PGA=3, PHASE = 112.5 PGA = 4, PHASE = 112.5 PGA = 3, PHASE = 135 PGA = 4, PHASE = 135 3 2 1 2.2 IN1N Channel 1 Noise (µV) Figure 69. Respiration Noise Test Circuit 5.2 8.2 11.2 14.2 Normalized Baseline Respiration Impedance (kΩ) G058 Figure 70. Channel 1 Noise versus Impedance for 32-kHz Modulation Clock and Phase (BW = 32 Hz, Respiration Modulation Clock = 32 kHz) 15 Data Rate = 125Hz 14 Respiration Modulation Clock = 64kHz 13 12 11 10 9 8 7 6 5 PGA=2, PHASE = 135 4 PGA = 3, PHASE = 135 3 PGA = 2, PHASE = 157.5 2 PGA = 3, PHASE = 157.5 1 2.2 7.2 12.2 15 Normalized Baseline Respiration Impedance (kΩ) G059 Figure 71. Channel 1 Noise versus Impedance for 64-kHz Modulation Clock and Phase (BW = 32 Hz, Respiration Modulation Clock = 64 kHz) 64 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 10 Power Supply Recommendations The nominal performance of the device is specified with an analog supply voltage AVDD of 3 V and an internal reference voltage VREFP of 2.42 V. The device also operates using power supplies at the AVDD pin from 2.7 V to 5.5 V with excellent performance. Parameters that can vary significantly with operating voltage and reference voltage are listed in the Typical Characteristics section. 10.1 Power-Up Sequencing Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals should remain low until the power supplies have stabilized, as shown in Figure 72. At this time, begin supplying the master clock signal to the CLK pin. Wait for time tPOR, then transmit a RESET pulse. After releasing RESET, the configuration register must be programmed, see the CONFIG1: Configuration Register 1 subsection of the Register Map section for details. The power-up sequence timing is shown in Table 29. tPOR Power Supplies tRST RESET Start Using the Device 18 tCLK Figure 72. Power-Up Timing Diagram Table 29. Power-Up Sequence Timing PARAMETER MIN tPOR Wait after power-up until reset tRST Reset low width TYP MAX UNIT 212 tMOD 1 tMOD Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 65 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 11 Layout 11.1 Layout Guidelines Attention to good layout practices is always recommended. For best operational performance of the device, use good PCB layout practices. Noise propagates into analog circuitry through the power pins of the circuit as a whole and of the device. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications. To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in parallel with the noisy trace. Place the external components as close to the device as possible. Keep the traces as short as possible. 11.1.1 PCB Layout 11.1.1.1 Power Supplies and Grounding The ADS1291, ADS1292, and ADS1292R have two supplies: AVDD and DVDD. AVDD should be as quiet as possible. AVDD provides the supply to the charge pump block and has transients at fCLK. It is important to eliminate noise from AVDD that is non-synchronous with the ADS1291, ADS1292, and ADS1292R operation. Each ADS1291, ADS1292, and ADS1292R supply should be bypassed with 10-μF and a 0.1-μF solid ceramic capacitors. It is recommended that placement of the digital circuits (such as the DSP, microcontrollers, and FPGAs) in the system is done such that the return currents on those devices do not cross the ADS1291, ADS1292, and ADS1292R analog return path. The ADS1291, ADS1292, and ADS1292R can be powered from unipolar or bipolar supplies. The capacitors used for decoupling can be of the surface-mount, low-cost, low-profile multi-layer ceramic type. In most cases the VCAP1 capacitor can also be a multi-layer ceramic, but in systems where the board is subjected to high or low frequency vibration, it is recommend that a non-ferroelectric capacitor such as a tantalum or class 1 capacitor (for example, C0G or NPO) be installed. EIA class 2 and class 3 dielectrics (such as X7R, X5R, X8R, and such) are ferroelectric. The piezoelectric property of these capacitors can appear as electrical noise coming from the capacitor. When using internal reference, noise on the VCAP1 node results in performance degradation. 66 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 Layout Guidelines (continued) 11.1.1.1.1 Connecting the Device to Unipolar (+3 V or +1.8 V) Supplies Figure 73 shows the ADS1291, ADS1292, and ADS1292R connected to a unipolar supply. In this example, the analog supply (AVDD) is referenced to analog ground (AVSS) and the digital supply (DVDD) is referenced to digital ground (DGND). +1.8 V +3 V 0.1 mF 1 mF DVDD AVDD VREFP VREFN 4.7 nF 1 mF 0.1 mF 0.1 mF 10 mF PGA1N (1) VCAP1 PGA1P VCAP2 Device PGA2N 4.7 nF PGA2P AVSS DGND 1 mF 1 mF NOTE: Place the capacitors for supply, reference, VCAP1, and VCAP2 as close to the package as possible. (1) When using the ADS1292R and the channel 1 respiration function, this capacitor must be 47 nF. Figure 73. Single-Supply Operation Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 67 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com Layout Guidelines (continued) 11.1.1.1.2 Connecting the Device to Bipolar (±1.5 V or 1.8 V) Supplies Figure 74 illustrates the ADS1291, ADS1292, and ADS1292R connected to a bipolar supply. In this example, the analog supplies connect to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the digital supply (DVDD) is referenced to the device digital ground return (DGND). +1.5 V +1.8 V 1 mF 0.1 mF 0.1 mF DVDD AVDD VREFP VREFN 4.7 nF (1) 4.7 nF 1 mF 10 mF 0.1 mF PGA1N -1.5 V PGA1P PGA2N VCAP1 Device VCAP2 PGA2P AVSS DGND 1 mF 1 mF 1 mF 0.1 mF -1.5 V NOTE: Place the capacitors for supply, reference, VCAP1, and VCAP2 as close to the package as possible. (1) When using the ADS1292R and the channel 1 respiration function, this capacitor must be 47 nF. Figure 74. Bipolar Supply Operation 11.1.1.2 Shielding Analog Signal Paths As with any precision circuit, careful PCB layout ensures the best performance. It is essential to make short, direct interconnections and avoid stray wiring capacitance—particularly at the analog input pins and AVSS. These analog input pins are high-impedance and extremely sensitive to extraneous noise. The AVSS pin should be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding. Leakage currents between the PCB traces can exceed the ADS1291, ADS1292, and ADS1292R input bias current if shielding is not implemented. Digital signals should be kept as far as possible from the analog input signals on the PCB. 68 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R ADS1291, ADS1292, ADS1292R www.ti.com SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 11.2 Layout Example CAP and power supply decoupling capacitors close to pins 25: GPIO2/ RCLK2 26: GPIO1/ RCLK1 27: VCAP2 28: RLDINV 29: RLDIN/ RLDREF 30: RLDOUT Via to ground plane or pour 31:RESP_MODP/ IN3P Via to corresponding voltage plane or pour 32:RESP_MODN/ IN3N +3.3 V 1: PGA1N 24: DGND 2: PGA1P 23: DVDD 3: IN1N 22: DRDY +1.8 V 4: IN1P 21: DOUT Device 5: IN2N 20: SCLK 6 IN2P 19: DIN 7: PGA2N 18: CS 8: PGA2P 17: CLK 16: START 15: PWDN/RESET 14: CLKSEL 13: AVSS 12: AVDD 11: VCAP1 10: VREFN 9: VREFP Inputs filtered with differential capacitors Long digital input lines terminated with resistors to prevent reflection +3 V CAP and power supply decoupling capacitors close to pins Figure 75. Example PCB Layout for Single-Supply Operation Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R Submit Documentation Feedback 69 ADS1291, ADS1292, ADS1292R SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 www.ti.com 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 30. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADS1291 Click here Click here Click here Click here Click here ADS1292 Click here Click here Click here Click here Click here ADS1292R Click here Click here Click here Click here Click here 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks E2E is a trademark of Texas Instruments. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 70 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS1291IPBS ACTIVE TQFP PBS 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1291 ADS1291IPBSR ACTIVE TQFP PBS 32 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1291 ADS1291IRSMR ACTIVE VQFN RSM 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 1291 ADS1291IRSMT ACTIVE VQFN RSM 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 1291 ADS1292IPBS ACTIVE TQFP PBS 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1292 ADS1292IPBSR ACTIVE TQFP PBS 32 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1292 ADS1292IRSMR ACTIVE VQFN RSM 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 1292 ADS1292IRSMT ACTIVE VQFN RSM 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 1292 ADS1292RIPBS ACTIVE TQFP PBS 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 1292R ADS1292RIPBSR ACTIVE TQFP PBS 32 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 1292R ADS1292RIRSMR ACTIVE VQFN RSM 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 1292R ADS1292RIRSMT ACTIVE VQFN RSM 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 1292R (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of