ADS131M08IPBSR

ADS131M08 ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 www.ti.com ADS131M08 8-Channel, Simultaneously-Sampling, 24-Bit, Delta-Sigma ADC 1 Features 3 Description • • • • The ADS131M08 is a eight-channel, simultaneouslysampling, 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) that offers wide dynamic range, low power, and energy-measurement-specific features, making the device an excellent fit for energy metering, power metrology, and circuit breaker applications. The ADC inputs can be directly interfaced to a resistordivider network or a power transformer to measure voltage or to a current transformer or a Rogowski coil to measure current. • • • • • • • • • • • • • 8 simultaneously sampling differential inputs Programmable data rate up to 32 kSPS Programmable gain up to 128 Noise performance: – 102-dB dynamic range at gain = 1, 4 kSPS – 80-dB dynamic range at gain = 64, 4 kSPS Total harmonic distortion: –100 dB High-impedance inputs for direct sensor connection: – Input impedance 330-kΩ for gains of 1, 2, and 4 – Input impedance ≥ 1-MΩ for gains of 8, 16, 32, 64, and 128 Programmable channel-to-channel phase delay calibration: – 244-ns resolution, 8.192-MHz fCLKIN Current-detect mode allows for extremely low power tamper detection Fast startup: first data within 0.5 ms of supply ramp Integrated negative charge pump allows input signals below ground Crosstalk between channels: –120 dB Low-drift internal voltage reference Cyclic redundancy check (CRC) on communications and register map 2.7-V to 3.6-V analog and digital supplies Low power consumption: 6.0 mW at 3-V AVDD and DVDD Packages: 32-pin TQFP or 32-pin WQFN Operating temperature range: –40°C to +125°C 2 Applications • • • • • • Electricity meters: commercial and residential Circuit breakers Protection relays Power quality meters Battery test equipment Battery management systems The individual ADC channels can be independently configured depending on the sensor input. A lownoise, programmable gain amplifier (PGA) provides gains ranging from 1 to 128 to amplify low-level signals. Additionally, this device integrates channel-tochannel phase calibration and offset and gain calibration registers to help remove signal-chain errors. A low-drift, 1.2-V reference is integrated into the device reducing printed circuit board (PCB) area. Optional cyclic redundancy checks (CRCs) on the data input, data output, and register map maintain communication integrity. The complete analog front-end (AFE) is offered in a 32-pin TQFP package or a leadless 32-pin WQFN package and is specified over the industrial temperature range of –40°C to +125°C. Device Information (1) PART NUMBER ADS131M08 (1) PACKAGE BODY SIZE (NOM) TQFP (32) 5.00 mm × 5.00 mm WQFN (32) 4.00 mm × 4.00 mm For all available packages, see the orderable addendum at the end of the data sheet. AVDD DVDD REFIN SW AIN0P + AIN0N ± Channel 0 '6 ADC 1.2-V Reference Phase Shift & Digital Filter Gain & Offset Calibration SYNC / RESET Channel 0 CS AINnP Channels 1-6 AINnN SCLK + + + ± ++ ± + ± ± ± ± '6 ADC '6 ADC '6 ADC '6 ADC '6 '6ADC ADC Phase Shift & Phase Shift & PhaseFilter Shift & Digital PhaseFilter Shift & Digital PhaseFilter Shift & Digital PhaseFilter Shift & Digital Digital Filter Digital Filter Gain & Offset Gain & Offset Gain & Offset Calibration Gain & Offset Calibration Gain & Offset Calibration Gain & Offset Calibration Calibration Calibration Control & Serial Interface DIN DOUT DRDY Channels 1-6 AIN7P + AIN7N ± '6 ADC Channel 7 Phase Shift & Digital Filter Gain & Offset Calibration Clock Generation Channel 7 AGND XTAL1 / CLKIN XTAL2 DGND Simplified Block Diagram An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2021 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: ADS131M08 1 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................4 6 Specifications.................................................................. 6 6.1 Absolute Maximum Ratings ....................................... 6 6.2 ESD Ratings .............................................................. 6 6.3 Recommended Operating Conditions ........................7 6.4 Thermal Information ...................................................7 6.5 Electrical Characteristics ............................................8 6.6 Timing Requirements ............................................... 10 6.7 Switching Characteristics .........................................10 6.8 Timing Diagrams....................................................... 11 6.9 Typical Characteristics.............................................. 13 7 Parameter Measurement Information.......................... 18 7.1 Noise Measurements................................................ 18 8 Detailed Description......................................................19 8.1 Overview................................................................... 19 8.2 Functional Block Diagram......................................... 19 8.3 Feature Description...................................................20 8.4 Device Functional Modes..........................................31 8.5 Programming............................................................ 37 8.6 Registers...................................................................47 9 Application and Implementation.................................. 89 9.1 Application Information............................................. 89 9.2 Typical Application.................................................... 96 10 Power Supply Recommendations............................103 10.1 CAP Pin Behavior................................................. 103 10.2 Power-Supply Sequencing....................................103 10.3 Power-Supply Decoupling.....................................103 11 Layout......................................................................... 104 11.1 Layout Guidelines................................................. 104 11.2 Layout Example.................................................... 105 12 Device and Documentation Support........................106 12.1 Documentation Support........................................ 106 12.2 Receiving Notification of Documentation Updates106 12.3 Support Resources............................................... 106 12.4 Trademarks........................................................... 106 12.5 Electrostatic Discharge Caution............................106 12.6 Glossary................................................................106 13 Mechanical, Packaging, and Orderable Information.................................................................. 106 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2019) to Revision B (February 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document .................1 • Added gain of 128 to High impedance inputs bullet........................................................................................... 1 • Added Protection relays and Power quality meters to Applications section....................................................... 1 • Changed Applications section ........................................................................................................................... 1 • Changed WQFN package from preview to active ..............................................................................................1 • Removed capacitor recommendation for REFIN pin in Pin Functions table ......................................................4 • Corrected analog input pin numbering in Pin Functions table ........................................................................... 4 • Added thermal pad to pinout diagram ................................................................................................................4 • Added Differential input voltage range using external reference........................................................................ 7 • Added long-term reference and gain error drift in WQFN package in Electrical Characteristics table............... 8 • Changed tsu(SY) parameter description in Timing Requirements table............................................................. 10 • Changed SPI Timing Diagram and SYNC/RESET Timing Requirements figures............................................ 11 • Added typical characteristics plots....................................................................................................................13 • Removed recommendation for decoupling capacitor when using internal reference....................................... 21 • Changed Clocking and Power Modes section.................................................................................................. 22 • Changed description of modulator frequency and added fMOD equation in ΔΣ Modulator section................... 22 • Changed Digital Filter section...........................................................................................................................22 • Changed Digital Filter Implementation title and section ...................................................................................23 • Updated description of the test signal derived from the internal reference.......................................................26 • Updated description of the test signal derived from the internal reference.......................................................26 • Changed communication cyclic redundancy check (CRC) seed value............................................................ 29 • Added DRDY transitions in Power-Up and Reset section................................................................................ 31 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 www.ti.com • • • • • • • • • • • • • ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Moved Fast Startup Behavior section to Device Functional Modes section, and changed values for wait time delays in text and figures.................................................................................................................................. 32 Added global-chop mode block diagram, global-chop mode conversion timing diagram, and Equation 9 ......33 Changed Standby Mode section ......................................................................................................................34 Deleted comments about MOSI, MISO, slave, and master.............................................................................. 37 Added description for new conversions when reading data in the Data Ready (DRDY) section......................37 Added second paragraph to SPI Communication Frames section .................................................................. 38 Changed Register Map table............................................................................................................................ 47 Changed description sentence for each register section..................................................................................47 Added pullup resistor option for DRDY in the Unused Inputs and Outputs section..........................................89 Changed root cause description in Troubleshooting section ........................................................................... 95 Added reference to TIDA-010037 design guide in Typical Application section................................................ 96 Changed discussion of burden resistor in Current Measurement Front-End section ...................................... 98 Added ADC energy metrology library software to Related Documents ......................................................... 106 Changes from Revision * (October 2019) to Revision A (December 2019) Page • Changed document status from advance information to production data ......................................................... 1 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 3 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 AIN1P AIN1N AIN0N AIN0P AGND NC DVDD DGND 5 Pin Configuration and Functions 32 31 30 29 28 27 26 25 AIN2P 1 24 CAP AIN2N 2 23 XTAL1/CLKIN AIN3N 3 22 XTAL2 AIN3P 4 21 DIN AIN4P 5 20 DOUT AIN4N 6 19 SCLK AIN5N 7 18 DRDY AIN5P 8 17 CS 16 SYNC/RESET 15 AVDD 14 REFIN 13 AGND 12 AIN7P 11 AIN7N 10 AIN6N AIN6P 9 AIN1P AIN1N AIN0N AIN0P AGND NC DVDD DGND Figure 5-1. PBS Package, 32-Pin TQFP, Top View 32 31 30 29 28 27 26 25 AIN3N 3 22 XTAL2 AIN3P 4 Exposed Thermal Pad on Underside 21 DIN AIN4P 5 Connect to AGND 20 DOUT AIN4N 6 19 SCLK AIN5N 7 18 DRDY AIN5P 8 17 CS 9 10 11 12 13 14 15 16 SYNC/RESET XTAL1/CLKIN AVDD 23 REFIN 2 AGND AIN2N AIN7P CAP AIN7N 24 AIN6N 1 AIN6P AIN2P Figure 5-2. RSN Package, 32-Pin WQFN, Top View 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Table 5-1. Pin Functions PIN NAME DESCRIPTION(1) I/O NO. WQFN TQFP AGND 13, 28 13, 28 Supply AIN0N 30 30 Analog input Negative analog input 0 AIN0P 29 29 Analog input Positive analog input 0 AIN1N 31 31 Analog input Negative analog input 1 AIN1P 32 32 Analog input Positive analog input 1 AIN2N 2 2 Analog input Negative analog input 2 AIN2P 1 1 Analog input Positive analog input 2 AIN3N 3 3 Analog input Negative analog input 3 AIN3P 4 4 Analog input Positive analog input 3 AIN4N 6 6 Analog input Negative analog input 4 AIN4P 5 5 Analog input Positive analog input 4 AIN5N 7 7 Analog input Negative analog input 5 AIN5P 8 8 Analog input Positive analog input 5 AIN6N 10 10 Analog input Negative analog input 6 AIN6P 9 9 Analog input Positive analog input 6 Analog ground AIN7N 11 11 Analog input Negative analog input 7 AIN7P 12 12 Analog input Positive analog input 7 AVDD 15 15 Supply CAP 24 24 Analog output CS 17 17 Digital input DGND 25 25 Supply DIN 21 21 Digital input DOUT 20 20 Digital output Serial data output DRDY 18 18 Digital output Data ready; active low DVDD 26 26 Supply NC 27 27 — REFIN 14 14 Analog input External reference voltage input. (2) SCLK 19 19 Digital input Serial data clock SYNC/RESET 16 16 Digital input Conversion synchronization or system reset; active low XTAL1/CLKIN 23 23 Digital input Master clock input, or crystal oscillator input XTAL2 22 22 Digital output — — Thermal pad (1) (2) (3) Analog supply. Connect a 1-µF capacitor to AGND. Digital low-dropout (LDO) regulator output. Connect a 220-nF capacitor to DGND. Chip select; active low Digital ground Serial data input Digital I/O supply. Connect a 1-µF capacitor to DGND. Leave unconnected or connect to AGND Crystal oscillator excitation(3) Thermal pad; connect to AGND See the Unused Inputs and Outputs section for details on how to connect unused pins. Do not place any capacitance on REFIN if the current-detect mode is used. See the Clocking and Power Modes section for more information regarding synchronization and how to implement the clocking scheme for optimized device performance. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 5 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 6 Specifications 6.1 Absolute Maximum Ratings See (1) Power-supply voltage MIN MAX AVDD to AGND –0.3 3.9 AGND to DGND –0.3 0.3 DVDD to DGND –0.3 3.9 DVDD to DGND, CAP tied to DVDD –0.3 2.2 UNIT V CAP to DGND –0.3 2.2 AINxP, AINxN AGND – 1.6 AVDD + 0.3 V Reference input voltage REFIN AGND – 0.3 AVDD + 0.3 V Digital input voltage CS, XTAL1/CLKIN, DIN, SCLK, SYNC/RESET, XTAL2 DGND – 0.3 DVDD + 0.3 V Input current Continuous, all pins except power-supply pins –10 10 –60 150 Analog input voltage Temperature (1) Junction, TJ 150 Storage, Tstg mA °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. 6.2 ESD Ratings VALUE V(ESD) (1) (2) 6 Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX AVDD to AGND, normal operating modes 2.7 3.0 3.6 AVDD to AGND, standby and current-detect modes 2.4 3.0 3.6 AGND to DGND –0.3 0 0.3 DVDD to DGND 2.7 3.0 3.6 1.65 1.8 2 UNIT POWER SUPPLY Analog power supply Digital power supply DVDD to DGND, DVDD shorted to CAP (digital LDO bypassed) V V ANALOG INPUTS(1) VAINxP, VAINxN Absolute input voltage VIN Differential input voltage Gain = 1, 2, or 4 AGND – 1.3 AVDD Gains = 8, 16, 32, 64 or 128 AGND – 1.3 AVDD – 1.8 Using internal reference, VIN = VAINxP - VAINxN –VREF / Gain VREF / Gain Using external reference, VIN = VAINxP - VAINxN – 0.96 × VREF / Gain 0.96 × VREF / Gain V V V VOLTAGE REFERENCE INPUT VREFIN Reference input voltage 1.1 1.25 1.3 High-resolution mode, Gain = 1 or 2 0.3 8.192 8.4 EXTERNAL CLOCK SOURCE fCLKIN External clock frequency High-resolution mode, Gain > 2 0.3 8.192 8.2 Low-power mode 0.3 4.096 4.15 Very-low-power mode 0.3 2.048 2.08 40 50 60 % DGND DVDD V –40 125 °C Duty cycle MHz DIGITAL INPUTS Input voltage TEMPERATURE RANGE TA (1) Operating ambient temperature The subscript "x" signifies the channel. For example, the positive analog input to channel 0 is named AIN0P. See the Pin Configurations and Functions section for the pin names. 6.4 Thermal Information ADS131M08 THERMAL METRIC(1) RSN (WQFN) PBS (TQFP) 32 PINS 32 PINS 33.7 81.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26.5 26.0 °C/W RθJB Junction-to-board thermal resistance 13.4 32.7 °C/W ΨJT Junction-to-top characterization parameter 0.3 1.1 °C/W ΨJB Junction-to-board characterization parameter 13.4 32.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 4.1 N/A °C/W RθJA (1) Junction-to-ambient thermal resistance UNIT For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 7 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 6.5 Electrical Characteristics minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, gain = 1, all channels enabled, global-chop mode disabled, using internal reference with 100-nF tied to REFIN pin, and internal oscillator disabled (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Zin Differential input impedance Gain = 1, 2, or 4 Ib Input bias current Gain = 8, 16, 32, 64, or 128, inputs shorted to ground 330 kΩ ±1 µA/V ADC CHARACTERISTICS Resolution 24 Gain settings fDATA Data rate Startup time Bits 1, 2, 4, 8, 16, 32, 64, 128 High-resolution mode, fCLKIN = 8.192 MHz 250 32k Low-power mode, fCLKIN = 4.096 MHz 125 16k Very low-power mode, fCLKIN = 2.048 MHz 62.5 8k Measured from supplies at 90% to first DRDY falling edge SPS 0.5 ms 7.5 ppm of FSR ADC PERFORMANCE INL Integral nonlinearity (best fit) Offset error (input referred) Offset drift ±240 Global-chop mode 215 Global-chop mode ±0.3% Excluding voltage reference error, gain = 1 Long-term gain drift CMRR PSRR Common-mode rejection ratio Power-supply rejection ratio Input referred noise 5 Including internal voltage reference error, gain = 1 10 Including internal voltage reference error, gain = 32 15 1000 hours at 85°C, including internal voltage reference error, TQFP package 385 1000 hours at 85°C, including internal voltage reference error, WQFN package 90 100 fCM = 50 Hz or 60 Hz 94 AVDD at DC 80 DVDD at DC 100 AVDD supply, fPS = 50 Hz or 60 Hz 78 DVDD supply, fPS = 50 Hz or 60 Hz 90 5.4 During fast startup 1500 99 Dynamic range Gain = 64 Crosstalk fIN = 50 Hz or 60 Hz 102 80 All other gain settings Submit Document Feedback 20 ppm/°C ppm At dc Gain = 1 8 nV/°C 105 Gain error Gain drift µV ±32 dB dB µVRMS dB See Table 7-1 –120 dB Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 6.5 Electrical Characteristics (continued) minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, gain = 1, all channels enabled, global-chop mode disabled, using internal reference with 100-nF tied to REFIN pin, and internal oscillator disabled (unless otherwise noted). PARAMETER SNR Signal-to-noise ratio TEST CONDITIONS MIN TYP fIN = 50 Hz or 60 Hz, gain = 1, VIN = –0.5 dBFS, normalized 101 fIN = 50 Hz or 60 Hz, gain = 64, VIN = –0.5 dBFS, normalized 80 MAX UNIT dB THD Total harmonic distortion fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS –100 dB SFDR Spurious-free dynamic range fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS 103 dB 1.2 V INTERNAL VOLTAGE REFERENCE VREF Internal reference voltage Accuracy TA = 25°C ±0.1% Temperature drift Long-term reference drift 8 1000 hours at 85°C, TQFP package 340 1000 hours at 85°C, WQFN package 70 20 ppm/°C ppm DIGITAL INPUTS/OUTPUTS VIL Logic input level, low VIH Logic input level, high VOL Logic output level, low DGND 0.8 DVDD IOL = –1 mA VOH Logic output level, high IOH = 1 mA IIN Input current DGND < VDigital Input < DVDD 0.2 DVDD V DVDD V 0.2 DVDD V 1 µA 0.8 DVDD V –1 POWER SUPPLY IAVDD Analog supply current High-resolution mode 6.5 7.7 Low-power mode 3.4 4.1 Very low-power mode 1.9 2.3 Current-detect mode IDVDD Digital supply current(1) PD (1) Power dissipation 1.8 Standby mode 0.35 High-resolution mode 0.66 0.9 Low-power mode 0.35 0.47 Very low-power mode 0.18 0.3 Current-detect mode 0.115 Standby mode mA 1.1 High-resolution mode 21.5 Low-power mode 11.3 Very low-power mode 6.2 Current-detect mode 5.8 Standby mode 4.4 µA mA µA mW µW Currents measured with SPI idle and oscillator disabled. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 9 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 6.6 Timing Requirements over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted) MIN NOM MAX UNIT(1) 1.65 V ≤ DVDD ≤ 2.0 V tw(CLL) Pulse duration, CLKIN low 49 ns tw(CLH) Pulse duration, CLKIN high 49 ns tc(SC) SCLK period 64 ns tw(SCL) Pulse duration, SCLK low 32 ns tw(SCH) Pulse duration, SCLK high 32 ns td(CSSC) Delay time, first SCLK rising edge after CS falling edge 16 ns td(SCCS) Delay time, CS rising edge after final SCLK falling edge 10 ns tw(CSH) Pulse duration, CS high 20 ns tsu(DI) Setup time, DIN valid before SCLK falling egde 5 ns th(DI) Hold time, DIN valid after SCLK falling edge 10 ns tw(RSL) Pulse duration, SYNC/RESET low to generate device reset tw(SYL) Pulse duration, SYNC/RESET low for synchronization tsu(SY) Setup time, SYNC/RESET valid before CLKIN rising edge 2048 tCLKIN 1 2047 tCLKIN 10 ns 2.7 V ≤ DVDD ≤ 3.6 V tw(CLL) Pulse duration, CLKIN low 49 ns tw(CLH) Pulse duration, CLKIN high 49 ns tc(SC) SCLK period 40 ns tw(SCL) Pulse duration, SCLK low 20 ns tw(SCH) Pulse duration, SCLK high 20 ns td(CSSC) Delay time, first SCLK rising edge after CS falling edge 16 ns td(SCCS) Delay time, CS rising edge after final SCLK falling edge 10 ns tw(CSH) Pulse duration, CS high 15 ns tsu(DI) Setup time, DIN valid before SCLK falling egde 5 ns th(DI) Hold time, DIN valid after SCLK falling edge 10 ns tw(RSL) Pulse duration, SYNC/RESET low to generate device reset tw(SYL) Pulse duration, SYNC/RESET low for synchronization tsu(SY) Setup time, SYNC/RESET valid before CLKIN rising edge (1) 2048 tCLKIN 1 2047 10 tCLKIN ns tCLKIN = 1/fCLKIN 6.7 Switching Characteristics over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT(1) 1.65 V ≤ DVDD ≤ 2.0 V tp(CSDO) Propagation delay time, CS falling edge to DOUT driven 50 ns tp(SCDO) Progapation delay time, SCLK rising edge to valid new DOUT 32 ns tp(CSDOZ) Propagation delay time, CS rising edge to DOUT high impedace 75 ns tw(DRH) Pulse duration, DRDY high 4 tCLKIN tw(DRL) Pulse duration, DRDY low 4 tCLKIN SPI timeout tPOR 10 Power-on-reset time 32768 Measured from supplies at 90% to first DRDY rising edge Submit Document Feedback tCLKIN 250 μs Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 6.7 Switching Characteristics (continued) over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted) PARAMETER tREGACQ TEST CONDITIONS MIN TYP Register default acquisition time MAX 5 UNIT(1) µs 2.7 V ≤ DVDD ≤ 3.6 V tp(CSDO) Propagation delay time, CS falling edge to DOUT driven 50 ns tp(SCDO) Progapation delay time, SCLK rising edge to valid new DOUT 20 ns tp(CSDOZ) Propagation delay time, CS rising edge to DOUT high impedace 75 ns tw(DRH) Pulse duration, DRDY high 4 tCLKIN tw(DRL) Pulse duration, DRDY low 4 tCLKIN SPI timeout 32768 tPOR Power-on-reset time tREGACQ Register default acquisition time (1) tCLKIN Measured from supplies at 90% to first DRDY rising edge 250 μs 5 µs tCLKIN = 1/fCLKIN 6.8 Timing Diagrams tw(CLH) tw(CLL) CLKIN tw(DRL) DRDY tw(DRH) § CS tw(SCL) td(CSSC) td(SCCS) tc(SC) tw(SCH) tw(CSH) § SCLK tsu(DI) th(DI) § § DIN tp(CSDO) tp(SCDO) MSB - 1 tw(CSDOZ) § § MSB DOUT LSB + 1 LSB SPI settings are CPOL = 0 and CPHA = 1. CS transitions must take place when SCLK is low. Figure 6-1. SPI Timing Diagram § CLKIN tsu(SY) tw(SYL) tw(RSL) § SYNC/RESET Figure 6-2. SYNC/RESET Timing Requirements Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 11 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Supplies 90% tPOR DRDY Figure 6-3. Power-On-Reset Timing 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 6.9 Typical Characteristics at TA = 25°C, AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, gain = 1 with global-chop mode disabled, using internal reference with 100-nF tied to REFIN pin, and internal oscillator disabled (unless otherwise noted) 350 HR Mode LP Mode VLP Mode Input Offset Current (nA) 300 250 200 150 100 50 0 8 16 32 Gain 64 128 Gains of 8, 16, 32, 64, and 128 only Figure 6-5. Input Impedance vs Gain Figure 6-4. Input Offset Current vs Gain 350 Input Offset Voltage (PV) 300 250 200 150 100 50 0 1 2 4 8 16 32 64 128 Gain 30 units, channel 1 Figure 6-7. Input Offset Voltage vs Gain Figure 6-6. Startup Time Histogram 182.5 Input Offset Voltage (PV) 180 177.5 175 172.5 170 167.5 165 162.5 160 157.5 -40 -20 0 20 40 60 80 Temperature (qC) 100 120 140 Includes internal reference error Figure 6-8. Input Offset Voltage vs Temperature Figure 6-9. Gain Error vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 13 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 6.9 Typical Characteristics (continued) at TA = 25°C, AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, gain = 1 with global-chop mode disabled, using internal reference with 100-nF tied to REFIN pin, and internal oscillator disabled (unless otherwise noted) 12 units, all channels 12 units, all channels Figure 6-10. Long-Term Gain Drift (TQFP Package) Figure 6-11. Long-Term Gain Drift (WQFN Package) 12 units, all channels Figure 6-13. DC CMRR vs Temperature Figure 6-12. Gain Error vs Humidity 120 105 110 DC AVDD PSRR (dB) AC CMRR (dB) 104 103 102 101 100 2.7 90 80 70 2.8 2.9 3 3.1 3.2 3.3 AVDD Voltage (V) Figure 6-14. AC CMRR vs AVDD 14 100 3.4 3.5 3.6 60 -40 -20 0 20 40 60 80 Temperature (qC) 100 120 140 Figure 6-15. DC AVDD PSRR vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 6.9 Typical Characteristics (continued) at TA = 25°C, AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, gain = 1 with global-chop mode disabled, using internal reference with 100-nF tied to REFIN pin, and internal oscillator disabled (unless otherwise noted) 110 DC DVDD PSRR (dB) 108 106 104 102 100 -40 -20 0 20 40 60 80 Temperature (qC) 100 120 140 Figure 6-17. Noise vs Temperature Figure 6-16. DC DVDD PSRR vs Temperature Gain = 1, inputs shorted Gain = 1, inputs shorted Figure 6-18. Single Device Noise Histogram at 4 kSPS Figure 6-19. Single Device Noise Histogram at 32 kSPS 110 HR Mode LP Mode VLP Mode Dynamic Range (dB) 100 90 80 70 60 1 2 4 8 16 32 64 128 Gain Figure 6-20. Dynamic Range vs Gain Across Power Modes Figure 6-21. Dynamic Range vs Gain Across Channels Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 15 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 6.9 Typical Characteristics (continued) at TA = 25°C, AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, gain = 1 with global-chop mode disabled, using internal reference with 100-nF tied to REFIN pin, and internal oscillator disabled (unless otherwise noted) -140 120 110 90 -130 80 70 Crosstalk (dB) Dynamic Range (dB) 100 OSR 128 256 512 1024 2048 4096 8192 16384 60 50 40 30 20 10 -110 0 1 2 -120 4 8 16 32 64 128 Gain -100 0 1 3 4 Channel 5 Figure 6-22. Dynamic Range vs Gain Across OSR Figure 6-23. Crosstalk vs Channel Figure 6-24. THD vs Gain Figure 6-25. THD vs AVDD 6 7 32 units 32 units Figure 6-26. Long-Term Reference Drift (TQFP Package) 16 2 Figure 6-27. Long-Term Reference Drift (WQFN Package) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 6.9 Typical Characteristics (continued) at TA = 25°C, AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, gain = 1 with global-chop mode disabled, using internal reference with 100-nF tied to REFIN pin, and internal oscillator disabled (unless otherwise noted) 32 units Figure 6-29. Internal Reference Voltage Temperature Drift Figure 6-28. Reference Error vs Humidity 7 10 HR Mode LP Mode VLP Mode 6 AVDD Current (mA) AVDD Current (mA) 8 6 4 5 4 3 2 2 HR Mode LP Mode VLP Mode 1 0 1 2 4 8 16 32 64 Gain Figure 6-30. AVDD Current vs Gain 128 0 0 1 2 3 4 5 6 Frequency (MHz) 7 8 9 Figure 6-31. AVDD Current vs CLKIN Frequency 700 DVDD Current (PA) 600 500 400 300 200 HR Mode LP Mode VLP Mode 100 0 0 1 2 3 4 5 Frequency (MHz) 6 7 8 8.5 Figure 6-32. DVDD Current vs CLKIN Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 17 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 7 Parameter Measurement Information 7.1 Noise Measurements Adjust the data rate and gain to optimize the ADS131M08 noise performance. When averaging is increased by reducing the data rate, noise drops correspondingly. Table 7-1 summarizes the ADS131M08 noise performance using the 1.2-V internal reference and a 3.0-V analog power supply. The data are representative of typical noise performance at TA = 25°C when fCLKIN = 8.192 MHz. The modulator clock frequency fMOD = fCLKIN / 2. The data shown are typical input-referred noise results with the analog inputs shorted together and taking an average of multiple readings across all channels. A minimum 1 second of consecutive readings are used to calculate the RMS noise for each reading. Table 7-2 shows the dynamic range and effective resolution calculated from the noise data. Equation 1 calculates dynamic range. Equation 2 calculates effective resolution. In each case, VREF corresponds to the internal 1.2-V reference, or the voltage on the REFIN pin if the external reference is used. In global-chop mode, noise is improved by a factor of √ 2. The noise performance scales with the OSR and gain settings, but is independent from the configured power mode. Thus, the device exhibits the same noise performance in different power modes when selecting the same OSR and gain settings. However, the data rate at the OSR settings scales based on the applied clock frequency for the different power modes. § · VREF Dynamic Range = 20 u log ¨ ¸¸ ¨ 2 u Gain u V RMS ¹ © (1) § 2 u VREF · Effective Resolution = log2 ¨ ¸ © Gain u VRMS ¹ (2) Table 7-1. Noise (µVRMS) at TA = 25°C GAIN OSR DATA RATE (kSPS), fCLKIN = 8.192 MHz 1 2 4 8 16 32 64 128 16384 0.25 1.90 1.69 1.56 0.95 0.64 0.42 0.42 0.42 8192 0.5 2.39 2.13 2.13 1.29 0.86 0.57 0.57 0.57 4096 1 3.38 2.99 2.88 1.74 1.17 0.77 0.77 0.77 2048 2 4.25 3.91 3.79 2.27 1.52 1.00 1.00 1.00 1024 4 5.35 4.68 4.52 2.70 1.82 1.20 1.20 1.20 512 8 7.56 6.62 6.37 3.82 2.55 1.69 1.69 1.69 256 16 10.68 9.56 9.09 5.42 3.63 2.39 2.39 2.40 128 32 21.31 15.26 13.52 7.89 5.21 3.41 3.42 3.42 64 128 Table 7-2. Dynamic Range (Effective Resolution) at TA = 25°C 18 GAIN OSR DATA RATE (kSPS), fCLKIN = 8.192 MHz 1 2 16384 0.25 113 (20.3) 8192 0.5 111 (19.9) 4096 1 2048 2 1024 512 4 8 108 (19.4) 103 (18.6) 101 (18.3) 98 (17.8) 96 (17.5) 90 (16.5) 84 (15.4) 106 (19.1) 100 (18.1) 98 (17.8) 96 (17.4) 93 (17.0) 87 (16.0) 81 (15.0) 108 (19.4) 103 (18.6) 97 (17.7) 96 (17.4) 93 (17.0) 91 (16.6) 85 (15.6) 79 (14.6) 106 (19.1) 101 (18.2) 95 (17.3) 93 (17.0) 91 (16.6) 88 (16.2) 82 (15.2) 76 (14.2) 4 104 (18.8) 99 (18.0) 93 (17.0) 92 (16.8) 89 (16.3) 87 (15.9) 81 (14.9) 75 (13.9) 8 101 (18.3) 96 (17.5) 90 (16.5) 89 (16.3) 86 (15.8) 84 (15.4) 78 (14.4) 72 (13.4) 256 16 98 (17.8) 93 (16.9) 87 (16.0) 86 (15.8) 83 (15.3) 81 (14.9) 75 (13.9) 69 (12.9) 128 32 92 (16.8) 89 (16.3) 84 (15.4) 83 (15.2) 80 (14.8) 78 (14.4) 72 (13.4) 65 (12.4) Submit Document Feedback 16 32 Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8 Detailed Description 8.1 Overview The ADS131M08 is a low-power, eight-channel, simultaneously sampling, 24-bit, delta-sigma (ΔΣ) analog-todigital converter (ADC) with a low-drift internal reference voltage. The dynamic range, size, feature set, and power consumption are optimized for cost-sensitive applications requiring simultaneous sampling. The ADS131M08 requires both analog and digital supplies. The analog power supply (AVDD – AGND) can operate between 2.7 V and 3.6 V. An integrated negative charge pump allows absolute input voltages as low as 1.3 V below AGND, which enables measurements of input signals varying around ground with a single-ended power supply. The digital power supply (DVDD – DGND) accepts both 1.8-V and 3.3-V supplies. The device features a programmable gain amplifier (PGA) with gains up to 128. An integrated input precharge buffer enabled at gains greater than 4 ensures high input impedance at high PGA gain settings. The ADC receives its reference voltage from an integrated 1.2-V reference. The device allows differential input voltages as large as the reference. Three power-scaling modes allow designers to trade power consumption for ADC dynamic range. Each channel on the ADS131M08 contains a digital decimation filter that demodulates the output of the ΔΣ modulators. The filter enables data rates as high as 32 kSPS per channel in high-resolution mode. The relative phase of the samples can be configured between channels, thus enabling an accurate compensation for the sensor phase response. Offset and gain calibration registers can be programmed to automatically adjust output samples for measured offset and gain errors. The Functional Block Diagram provides a detailed diagram of the ADS131M08. The device communicates via a serial programming interface (SPI)-compatible interface. Several SPI commands and internal registers control the operation of the ADS131M08. Other devices can be added to the same SPI bus by adding discrete CS control lines. The SYNC/RESET pin can be used to synchronize conversions between multiple ADS131M08 devices as well as to maintain synchronization with external events. 8.2 Functional Block Diagram AVDD DVDD REFIN SW AIN0P + AIN0N ± Channel 0 '6 ADC 1.2-V Reference Phase Shift & Digital Filter Gain & Offset Calibration SYNC / RESET Channel 0 CS AINnP Channels 1-6 AINnN SCLK + + + ± ++ ± + ± ± ± ± '6 ADC '6 ADC '6 ADC '6 ADC '6 '6ADC ADC Phase Shift & Phase Shift & PhaseFilter Shift & Digital PhaseFilter Shift & Digital PhaseFilter Shift & Digital PhaseFilter Shift & Digital Digital Filter Digital Filter Gain & Offset Gain & Offset Gain & Offset Calibration Gain & Offset Calibration Gain & Offset Calibration Gain & Offset Calibration Calibration Calibration Control & Serial Interface DIN DOUT DRDY Channels 1-6 AIN7P + AIN7N ± '6 ADC Channel 7 Phase Shift & Digital Filter Gain & Offset Calibration Clock Generation Channel 7 AGND XTAL1 / CLKIN XTAL2 DGND Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 19 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.3 Feature Description 8.3.1 Input ESD Protection Circuitry Basic electrostatic discharge (ESD) circuitry protects the ADS131M08 inputs from ESD and overvoltage events in conjunction with external circuits and assemblies. Figure 8-1 depicts a simplified representation of the ESD circuit. The protection for input voltages exceeding AVDD can be modeled as a simple diode. AVDD AINnP To analog inputs AINnN AVDD Figure 8-1. Input ESD Protection Circuitry The ADS131M08 has an integrated negative charge pump that allows for input voltages below AGND with a unipolar supply. Consequently, shunt diodes between the inputs and AGND cannot be used to clamp excessive negative input voltages. Instead, the same diode that clamps overvoltage is used to clamp undervoltage at its reverse breakdown voltage. Take care to prevent input voltages or currents from exceeding the limits provided in the Absolute Maximum Ratings table. 8.3.2 Input Multiplexer Each channel of the ADS131M08 has a dedicated input multiplexer. The multiplexer controls which signals are routed to the ADC channels. Configure the input multiplexer using the MUXn[1:0] bits in the CHn_CFG register. The input multiplexer allows the following inputs to be connected to the ADC channel: • The analog input pins corresponding to the given channel • AGND, which is helpful for offset calibration • Positive DC test signal • Negative DC test signal See the Internal Test Signals section for more information about the test signals. Figure 8-2 shows a diagram of the input multiplexer on the ADS131M08. MUXn[1:0] = 00 SW To Positive PGA Input AINnP MUXn[1:0] = 10 SW MUXn[1:0] = 11 SW + DC Test Signal ± AGND SW SW MUXn[1:0] = 01 SW SW SW MUXn[1:0] = 01 MUXn[1:0] = 10 AINnN To Negative PGA Input MUXn[1:0] = 00 Figure 8-2. Input Multiplexer 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.3.3 Programmable Gain Amplifier (PGA) Each channel of the ADS131M08 features an integrated programmable gain amplifier (PGA) that provides gains of 1, 2, 4, 8, 16, 32, 64, and 128. The gains for all channels are individually controlled by the PGAGAINn bits for each channel in the GAIN1 register. Varying the PGA gain scales the differential full-scale input voltage range (FSR) of the ADC. Equation 3 describes the relationship between FSR and gain. Equation 3 uses the internal reference voltage, 1.2 V, as the scaling factor without accounting for gain error caused by tolerance in the reference voltage. FSR = ±1.2 V / Gain (3) Table 8-1 shows the corresponding full-scale ranges for each gain setting, assuming the internal reference is used. Table 8-1. Full-Scale Range GAIN SETTING FSR 1 ±1.2 V 2 ±600 mV 4 ±300 mV 8 ±150 mV 16 ±75 mV 32 ±37.5 mV 64 ±18.75 mV 128 ±9.375 mV The input impedance of the PGA dominates the input impedance characteristics of the ADS131M08. The PGA input impedance for gain settings up to 4 behaves according to Equation 4 without accounting for device tolerance and change over temperature. Minimize the output impedance of the circuit that drives the ADS131M08 inputs to obtain the best possible gain error, INL, and distortion performance. 330 kΩ × 4.096 MHz / fMOD (4) where: • fMOD is the ΔΣ modulator frequency, fCLKIN / 2 The device uses an input precharge buffer for PGA gain settings of 8 and higher. The input impedance at these gain settings is very high. Specifying the input bias current for these gain settings is therefore more useful. A plot of input bias current for the high gain settings is provided in Figure 6-5. 8.3.4 Voltage Reference The ADS131M08 has two reference voltage options: the internal reference and an external reference. The internal reference uses a low-drift band-gap voltage to supply the reference for the ADC. The internal reference has a nominal voltage of 1.2 V, allowing the differential input voltage to swing from –1.2 V to 1.2 V. The reference circuitry starts up very quickly to accommodate the fast-startup feature of this device. The device waits until after the reference circuitry is fully settled before generating conversion data. Do not place any capacitance on the REFIN pin if the current-detect mode is used. See the Current-Detect Mode section for more details about the current-detect mode. The device also allows for an external reference voltage, which can be input at the REFIN pin. The nominal external reference voltage is 1.25 V. The full-scale range of the ADC is 1.2 V / gain when the reference voltage is 1.25 V. The ADC full-scale range maintains the ratio of 1.2 to 1.25 for all recommended reference voltages. For example, the ADC full-scale range is 1.248 V / gain if 1.3 V is applied to the REFIN pin instead of the nominal 1.25 V. The startup time for the external reference is governed by the external circuitry. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 21 ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 www.ti.com 8.3.5 Clocking and Power Modes The master clock can either be sourced externally to the CLKIN pin or generated internally using the onboard oscillator that requires a crystal connected between the XTAL1/CLKIN and XTAL2 pins. For optimal performance, the modulator sampling clock must be synchronous with the serial data clock (SCLK). The modulator sampling clock is derived from the master clock, which means the master clock must be synchronous with SCLK. Therefore, for best performance, supply a master clock to CLKIN and make sure data retrieval is synchronous to the clock signal at CLKIN. When not in use, turn the internal oscillator off to save power. The PWR[1:0] bits in the CLOCK register allow the device to be configured in one of three power modes: highresolution (HR) mode, low-power (LP) mode, and very low-power (VLP) mode. Changing the PWR[1:0] bits scales the internal bias currents to achieve the expected power levels. The external clock frequency must follow the guidance provided in the Recommended Operating Conditions table corresponding to the intended power mode in order for the device to perform according to the specification. 8.3.6 ΔΣ Modulator The ADS131M08 uses a delta-sigma (ΔΣ) modulator to convert the analog input voltage to a one's density modulated digital bit-stream. The ΔΣ modulator oversamples the input voltage at a frequency many times greater than the output data rate. The modulator frequency, fMOD, of the ADS131M08 is equal to half the master clock frequency, that is, fMOD = fCLKIN / 2. The output of the modulator is fed back to the modulator input through a digital-to-analog converter (DAC) as a means of error correction. This feedback mechanism shapes the modulator quantization noise in the frequency domain to make the noise more dense at higher frequencies and less dense in the band of interest. The digital decimation filter following the ΔΣ modulator significantly attenuates the out-of-band modulator quantization noise, allowing the device to provide excellent dynamic range. 8.3.7 Digital Filter The ΔΣ modulator bit-stream feeds into a digital filter. The digital filter is a linear phase, finite impulse response (FIR), low-pass sinc-type filter that attenuates the out-of-band quantization noise of the ΔΣ modulator. The digital filter demodulates the output of the ΔΣ modulator by averaging. The data passing through the filter is decimated and downsampled, to reduce the rate at which data come out of the modulator (fMOD) to the output data rate (fDATA). The decimation factor is defined as per Equation 5 and is called the oversampling ratio (OSR). OSR = fMOD / fDATA (5) The OSR is configurable and set by the OSR[2:0] bits in the CLOCK register. There are OSR settings in the ADS131M08, allowing different data rate settings for any given master clock frequency. Table 8-2 lists the OSR settings and their corresponding output data rates for the nominal CLKIN frequencies mentioned. The OSR determines the amount of averaging of the modulator output in the digital filter and therefore also the filter bandwidth. The filter bandwidth directly affects the noise performance of the ADC because lower bandwidth results in lower noise whereas higher bandwidth results in higher noise. See Table 7-1 for the noise specifications for various OSR settings. 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Table 8-2. OSR Settings and Data Rates for Nominal Master Clock Frequencies POWER MODE NOMINAL MASTER CLOCK FREQUENCY HR fMOD 8.192 MHz LP 4.096 MHz 4.096 MHz VLP 2.048 MHz 2.048 MHz 1.024 MHz OSR OUTPUT DATA RATE 128 32 kSPS 256 16 kSPS 512 8 kSPS 1024 4 kSPS 2048 2 kSPS 4096 1 kSPS 8192 500 SPS 16384 250 SPS 128 16 kSPS 256 8 kSPS 512 4 kSPS 1024 2 kSPS 2048 1 kSPS 4096 500 SPS 8192 250 SPS 16384 125 SPS 128 8 kSPS 256 4 kSPS 512 2 kSPS 1024 1 kSPS 2048 500 SPS 4096 250 SPS 8192 125 SPS 16384 62.5 SPS 8.3.7.1 Digital Filter Implementation Figure 8-3 shows the digital filter implementation of the ADS131M08. The modulator bit-stream feeds two parallel filter paths, a sinc3 filter, and a fast-settling filter path. PHASEx[9:0] OSR[2:0] Phase Delay Sinc3 Regular Filter Modulator Bitstream Power-up or Reset 0 MUX Fast-Settling Filter 265 ” 1024 Sinc1 Averager (OSR>1024) OSR[2:0] 1 0 MUX Global Chop Logic Calibration Logic, Gain scaling 1 PGA_GAINx[2:0] OSR = 1024 Figure 8-3. Digital Filter Implementation 8.3.7.1.1 Fast-Settling Filter At power-up or after a device reset, the ADS131M08 selects the fast-settling filter to allow for settled output data generation with minimal latency. The fast-settling filter has the characteristic of a first-order sinc filter (sinc1). After two conversions, the device switches to and remains in the sinc3 filter path until the next time the device is reset or powered cycled. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 23 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 The fast-settling filter exhibits wider bandwidth and less stop-band attenuation than the sinc3 filter. Consequently, the noise performance when using the fast-settling filter is not as high as with the sinc3 filter. The first two samples available from the ADS131M08 after a supply ramp or reset have the noise performance and frequency response corresponding to the fast-settling filter as specified in the Electrical Characteristics table, whereas subsequent samples have the noise performance and frequency response consistent with the sinc3 filter. See the Fast Startup Behavior section for more details regarding the fast startup capabilities of the ADS131M08. 8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter The ADS131M08 selects the sinc3 filter path two conversion after power-up or device reset. For OSR settings of 128 to 1024 the sinc3 filter output directly feeds into the global-chop and calibration logic. For OSR settings of 2048 and higher the sinc3 filter is followed by a sinc1 filter. As shown in Table 8-3, the sinc3 filter operates at a fixed OSR of 1024 in this case while the sinc1 filter implements the additional OSRs of 2 to 16. That means when an OSR of 4096 (for example) is selected, the sinc3 filter operates at an OSR of 1024 and the sinc1 filter at an OSR of 4. The filter has infinite attenuation at integer multiples of the data rate except for integer multiples of fMOD. Like all digital filters, the digital filter response of the ADS131M08 repeats at integer multiples of the modulator frequency, fMOD. The data rate and filter notch frequencies scale with fMOD. When possible, plan frequencies for unrelated periodic processes in the application for integer multiples of the data rate such that any parasitic effect they have on data acquisition is effectively cancelled by the notches of the digital filter. Avoid frequencies near integer multiples of fMOD whenever possible because tones in these bands can alias to the band of interest. The sinc3 and sinc3 + sinc1 filters for a given channel require time to settle after a channel is enabled, the channel multiplexer or gain setting is changed, or a resynchronization event occurs. See the Synchronization section for more details on resynchronization. Table 8-3 lists the settling times of the sinc3 and sinc3 + sinc1 filters for each OSR setting. The ADS131M08 does not gate unsettled data. Therefore, the host must account for the filter settling time and disregard unsettled data if any are read. The data at the next DRDY falling edge after the filter settling time listed in Table 8-3 has expired can be considered fully settled. Table 8-3. Digital Filter Startup Times After Power-Up or Resynchronization OSR (OVERALL) OSR (SINC3) OSR (SINC1) SETTLING TIME (tCLKIN) 128 128 N/A 856 256 256 N/A 1112 512 512 N/A 1624 1024 1024 N/A 2648 2048 1024 2 4696 4096 1024 4 8792 8192 1024 8 16984 16384 1024 16 33368 8.3.7.2 Digital Filter Characteristic Equation 6 calculates the z-domain transfer function of a sinc3 filter that is used for OSRs of 1024 and lower. 3 H z 1 N1 Z N Z 1 (6) where N is the OSR. Equation 7 calculates the transfer function of a sinc3 filter in terms of the continuous-time frequency parameter f. 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Npf fMOD sin ½H(f)½ = N ´ sin 3 pf fMOD (7) where N is the OSR. Figure 8-4 through Figure 8-7 show the digital filter response of the fast-settling filter and the sinc3 filter for OSRs of 1024 and lower. Figure 8-6 and Figure 8-7 show the digital filter response of the sinc3 + sinc1 filter for an OSR of 4096. 0 0 -20 -1.5 -3 Magnitude (dB) Magnitude (dB) -40 -60 -80 -100 -4.5 -6 -7.5 -9 -120 -10.5 Fast-settling filter Sinc3 filter -140 0 1 2 3 Frequency (fIN/fDATA) 4 0 5 Figure 8-4. Fast-Settling and Sinc3 Digital Filter Response 0 0.1 0.2 0.3 Frequency (fIN/fDATA) 0.4 0.5 Figure 8-5. Fast-Settling and Sinc3 Digital Filter Response, Pass-Band Detail 0 Sinc3 filter (1024) Sinc3 + Sinc1 filter -20 Fast-settling filter Sinc3 filter -12 -2 Magnitude (dB) Magnitude (dB) -40 -60 -80 -100 -4 -6 -8 -10 -120 -140 0 1 2 3 4 5 6 7 8 Frequency (fIN/fDATA) 9 10 11 12 Figure 8-6. Digital Filter Response for OSR = 1024 and OSR = 4096 Sinc3 filter (1024) Sinc3 + Sinc1 filter -12 0 0.1 0.2 0.3 Frequency (fIN/fDATA) 0.4 0.5 Figure 8-7. Digital Filter Response for OSR = 1024 and OSR = 4096, Pass-Band Detail 8.3.8 DC Block Filter The ADS131M08 includes an optional high-pass filter to eliminate any systematic offset or low-frequency noise. The filter is enabled by writing any value in the DCBLOCK[3:0] bits in the CD_TH_LSB register besides 0h. The DC block filter can be enabled and disabled on a channel-by-channel basis by the DCBLKn_DIS bit in the CHn_CFG register for each respective channel. Figure 8-8 shows the topology of the DC block filter. Coefficient a represents a register configurable value that configures the cutoff frequency of the filter. The cutoff frequency is configured using the DCBLOCK[3:0] bits in the CD_TH_LSB register. Table 8-4 describes the characteristics of the filter for various DCBLOCK[3:0] settings. The data provided in Table 8-4 is provided for an 8.192-MHz CLKIN frequency and a 4-kSPS data rate. The frequency response of the filter response scales directly with the frequency of CLKIN and the data rate. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 25 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Input 1Å z-1 1-z-1 a 2 Output ÅD Figure 8-8. DC Block Filter Topology Table 8-4. DC Block Filter Characteristics DCBLOCK[3:0] a COEFFICIENT –3-dB CORNER(1) 0h (1) PASS-BAND ATTENUATION(1) 50 Hz 60 Hz SETTLING TIME (Samples) SETTLED >99% FULLY SETTLED DC block filter disabled 1h 1/4 181 Hz 11.5 dB 10.1 dB 17 88 2h 1/8 84.8 Hz 5.89 dB 4.77 dB 36 187 3h 1/16 41.1 Hz 2.24 dB 1.67 dB 72 387 4h 1/32 20.2 Hz 657 mdB 466 mdB 146 786 5h 1/64 10.0 Hz 171 mdB 119 mdB 293 1585 6h 1/128 4.99 Hz 43.1 mdB 29.9 mdB 588 3182 7h 1/256 2.49 Hz 10.8 mdB 7.47 mdB 1178 6376 8h 1/512 1.24 Hz 2.69 mdB 1.87 mdB 2357 12764 9h 1/1024 622 mHz 671 µdB 466 µdB 4714 25540 Ah 1/2048 311 mHz 168 µdB 116 µdB 9430 51093 Bh 1/4096 155 mHz 41.9 µdB 29.1 µdB 18861 102202 Ch 1/8192 77.7 mHz 10.5 µdB 7.27 µdB 37724 204447 Dh 1/16384 38.9 mHz 2.63 µdB 1.82 µdB 75450 409156 Eh 1/32768 19.4 mHz 655 ndB 455 ndB 150901 820188 Fh 1/65536 9.70 mHz 164 ndB 114 ndB 301803 1627730 Values given are for a 4-kSPS data rate with a 8.192-MHz CLKIN frequency. 8.3.9 Internal Test Signals The ADS131M08 features an internal analog test signal that is useful for troubleshooting and diagnosis. A positive or negative DC test signal can be applied to the channel inputs through the input multiplexer. The multiplexer is controlled through the MUXn[1:0] bits in the CHn_CFG register. The test signals are created by internally dividing the internal reference voltage. The same signal is shared by all channels. The test signal is nominally 2 / 15 × VREF. The test signal automatically adjusts its voltage level with the gain setting such that the ADC always measures a signal that is 2 / 15 × VDiff Max. For example, at a gain of 1, this voltage equates to 160 mV. At a gain of 2, this voltage is 80 mV. 8.3.10 Channel Phase Calibration The ADS131M08 allows fine adjustment of the sample phase between channels through the use of channel phase calibration. This feature is helpful when different channels are measuring the outputs of different types of sensors that have different phase responses. For example, in power metrology applications, voltage can be measured by a voltage divider, whereas current is measured using a current transformer that exhibits a phase difference between its input and output signals. The differences in phase between the voltage and current measurement must be compensated to measure the power and related parameters accurately. The phase setting of the different channels is configured by the PHASEn[9:0] bits in the CHn_CFG register corresponding to the channel whose phase adjustment is desired. The register value is a 10-bit two's complement value corresponding to the number of modulator clock cycles of phase offset compared to a reference phase of 0 degrees. 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 The mechanism for achieving phase adjustment derives from the ΔΣ architecture. The ΔΣ modulator produces samples continuously at the modulator frequency, fMOD. These samples are filtered and decimated to the output data rate by the digital filter. The ratio between fMOD and the data rate is the oversampling ratio (OSR). Each conversion result corresponds to an OSR number of modulator samples provided to the digital filter. When the different channels of the ADS131M08 have no programmed phase offset between them, the modulator clock cycles corresponding to the conversion results of the different channels are aligned in the time domain. Figure 8-9 depicts an example scenario where the voltage input to channel 1 has no phase offset from channel 0. Sample Period CH0 Input CH1 Input Figure 8-9. Two Channel Outputs With Equal Phase Settings However, the sample period of one channel can be shifted with respect to another. If the inputs to both channels are sinusoids of the same frequency and the samples for these channels are retrieved by the host at the same time, the effect is that the phase of the channel with the modified sample period appears shifted. Figure 8-10 depicts how the period corresponding to the samples are shifted between channels. Figure 8-11 illustrates how the samples appear as having generated a phase shift when they are retrieved by the host. Sample Period CH0 Input CH1 Input Sample Period Offset Figure 8-10. Channel 1 With a Positive Sample Phase Shift With Respect to Channel 0 CH0 Output CH1 Output Figure 8-11. Channels 1 and 0 From the Perspective of the Host Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 27 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 The valid setting range is from –OSR / 2 to (OSR / 2) – 1, except for OSRs greater than 1024, where the phase calibration setting is limited to –512 to 511. If a value outside of –OSR / 2 and (OSR / 2) – 1 is programmed, the device internally clips the value to the nearest limit. For example, if the OSR setting is programmed to 128 and the PHASEn[9:0] bits are programmed to 0001100100b corresponding to 100 modulator clock cycles, the device sets the phase of the channel to 63 because that value is the upper limit of phase calibration for that OSR setting. Table 8-5 gives the range of phase calibration settings for various OSR settings. Table 8-5. Phase Calibration Setting Limits for Different OSR Settings OSR SETTING PHASE OFFSET RANGE (tMOD) PHASEn[9:0] BITS RANGE 128 –64 to 63 11 1100 0000b to 00 0011 1111b 256 –128 to 127 11 1000 0000b to 00 0111 1111b 512 –256 to 255 11 0000 0000b to 00 1111 1111b 1024 –512 to 511 10 0000 0000b to 01 1111 1111b 2048 –512 to 511 10 0000 0000b to 01 1111 1111b 4096 –512 to 511 10 0000 0000b to 01 1111 1111b 8192 –512 to 511 10 0000 0000b to 01 1111 1111b 16384 –512 to 511 10 0000 0000b to 01 1111 1111b Follow these steps to create a phase shift larger than half the sample period for OSRs less than 2048: • Create a phase shift corresponding to an integer number of sample periods by modifying the indices between channel data in software • Use the phase calibration function of the ADS131M08 to create the remaining fractional sample period phase shift For example, to create a phase shift of 2.25 samples between channels 0 and 1, create a phase shift of two samples by aligning sample N in the channel 0 output data stream with sample N+2 in the channel 1 output data stream in the host software. Make the remaining 0.25 sample adjustment using the ADS131M08 phase calibration function. The phase calibration settings of the channels affect the timing of the data-ready interrupt signal, DRDY. See the Data Ready (DRDY) section for more details regarding how phase calibration affects the DRDY signal. 8.3.11 Calibration Registers The calibration registers allow for the automatic computation of calibrated ADC conversion results from preprogrammed values. The host can rely on the device to automatically correct for system gain and offset after the error correction terms are programmed into the corresponding device registers. The measured calibration coefficients must be store in external non-volatile memory and programmed into the registers each time the ADS131M08 powers up because the ADS131M08 registers are volatile. The offset calibration registers are used to correct for system offset error, otherwise known as zero error. Offset error corresponds to the ADC output when the input to the system is zero. The ADS131M08 corrects for offset errors by subtracting the contents of the OCALn[23:0] register bits in the CHn_OCAL_MSB and CHn_OCAL_LSB registers from the conversion result for that channel before being output. There are separate CHn_OCAL_MSB and CHnOCAL_LSB registers for each channel, which allows separate offset calibration coefficients to be programmed for each channel. The contents of the OCALn[23:0] bits are interpreted by the device as 24-bit two's complement values, which is the same format as the ADC data. The gain calibration registers are used to correct for system gain error. Gain error corresponds to the deviation of gain of the system from its ideal value. The ADS131M08 corrects for gain errors by multiplying the ADC conversion result by the value given by the contents of the GCALn[23:0] register bits in the CHn_GCAL_MSB and CHn_GCAL_LSB registers before being output. There are separate CHn_GCAL_MSB and CHn_GCAL_LSB registers for each channel, which allows separate gain calibration coefficients to be programmed for each channel. The contents of the GCALn[23:0] bits are interpreted by the device as 24-bit unsigned values corresponding to linear steps ranging from gains of 0 to 2 – (1 / 223). Table 8-6 describes the relationship between the GCALn[23:0] bit values and the gain calibration factor. 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Table 8-6. GCALn[23:0] Bit Mapping GCALn[23:0] VALUE GAIN CALIBRATION FACTOR 000000h 0 000001h 1.19 × 10–7 800000h 1 FFFFFEh 2 – 2.38 × 10–7 FFFFFFh 2 – 1.19 × 10–7 The calibration registers do not need to be enabled because they are always in use. The OCALn[23:0] bits have a default value of 000000h resulting in no offset correction. Similarly, the GCALn[23:0] bits default to 800000h resulting in a gain calibration factor of 1. Figure 8-12 depicts a block diagram illustrating the mechanics of the calibration registers on one channel of the ADS131M08. Digital Filter û Modulator To Interface Å 1 OCALn[23:0] 223 GCALn[23:0] Figure 8-12. Calibration Block Diagram 8.3.12 Communication Cyclic Redundancy Check (CRC) The ADS131M08 features a cyclic redundancy check (CRC) engine on both input and output data to mitigate SPI communication errors. The CRC word is 16 bits wide for either input or output CRC. Coverage includes all words in the SPI frame where the CRC is enabled, including padded bits in a 32-bit word size. CRC on the SPI input is optional and can be enabled and disabled by writing the RX_CRC_EN bit in the MODE register. Input CRC is disabled by default. When the input CRC is enabled, the device checks the provided input CRC against the CRC generated based on the input data. A CRC error occurs if the CRC words do not match. The device does not execute any commands, except for the WREG command, if the input CRC check fails. A WREG command always executes even when the CRC check fails. The device sets the CRC_ERR bit in the STATUS register for all cases of a CRC error. The response on the output in the SPI frame following the frame where the CRC error occurred is that of a NULL command, which means the STATUS register plus the conversion data are output in the following SPI frame. The CRC_ERR bit is cleared when the STATUS register is output. The output CRC cannot be disabled and always appears at the end of the output frame. The host can ignore the data if the output CRC is not used. There are two types of CRC polynomials available: CCITT CRC and ANSI CRC (CRC-16). The CRC setting determines the algorithm for both the input and output CRC. The CRC type is programmed by the CRC_TYPE bit in the MODE register. Table 8-7 lists the details of the two CRC types. The seed value of the CRC calculation is FFFFh. Table 8-7. CRC Types CRC TYPE CCITT CRC ANSI CRC POLYNOMIAL x16 + x12 + x5 BINARY POLYNOMIAL +1 0001 0000 0010 0001 x16 + x15 + x2 + 1 1000 0000 0000 0101 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 29 ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 www.ti.com 8.3.13 Register Map CRC The ADS131M08 performs a CRC on its own register map as a means to check for unintended changes to the registers. Enable the register map CRC by setting the REG_CRC_EN bit in the MODE register. When enabled, the device constantly calculates the register map CRC using each bit in the writable register space. The register addresses covered by the register map CRC on the ADS131M08 are 02h through 30h. The CRC is calculated beginning with the MSB of register 02h and ending with the LSB of register 30h using the polynomial selected in the CRC_TYPE bit in the MODE register. The calculated CRC is a 16-bit value and is stored in the REGMAP_CRC register. The calculation is done using one register map bit per CLKIN period and constantly checks the result against the previous calculation. The REG_MAP bit in the STATUS register is set to flag the host if the register map CRC changes, including changes resulting from register writes. The bit is cleared by reading the STATUS register, or by the STATUS register being output as a response to the NULL command. 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.4 Device Functional Modes Figure 8-13 shows a state diagram depicting the major functional modes of the ADS131M08 and the transitions between them. POR, pin reset, or RESET command Reset complete Reset STANDBY Standby Mode Continuous Conversion Mode WAKEUP && GC_EN STANDBY Current detection complete GC_EN WAKEUP && GC_EN GC_EN SYNC Current Detect Mode Global-Chop Mode Figure 8-13. State Diagram Depicting Device Functional Modes 8.4.1 Power-Up and Reset The ADS131M08 is reset in one of three ways: by a power-on reset (POR), by the SYNC/RESET pin, or by a RESET command. After a reset occurs, the configuration registers are reset to the default values and the device begins generating conversion data as soon as a valid MCLK is provided. In all three cases a low to high transition on the DRDY pin indicates that the SPI interface is ready for communication. The device ignores any SPI communication before this point. 8.4.1.1 Power-On Reset Power-on reset (POR) is the reset that occurs when a valid supply voltage is first applied. The POR process requires tPOR from when the supply voltages reach 90% of their nominal value. Internal circuitry powers up and the registers are set to their default state during this time. The DRDY pin transitions from low to high immediately after tPOR indicating the SPI interface is ready for communication. The device ignores any SPI communication before this point. 8.4.1.2 SYNC/RESET Pin The SYNC/RESET pin is an active low, dual-function pin that generates a reset if the pin is held low longer than tw(RSL). The device maintains a reset state until SYNC/RESET is returned high. The host must wait for at least tREGACQ after SYNC/RESET is brought high or for the DRDY rising edge before communicating with the device. Conversion data are generated immediately after the registers are reset to their default values, as described in the Fast Startup Behavior section. 8.4.1.3 RESET Command The ADS131M08 can be reset via the SPI RESET command (0011h). The device communicates in frames of a fixed length. See the SPI Communication Frames section for details regarding SPI data framing on the ADS131M08. The RESET command occurs in the first word of the data frame, but the command is not latched by the device until the entire frame is complete. After the response completes channel data and CRC words are Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 31 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 clocked out. Terminating the frame early causes the RESET command to be ignored. Ten words are required to complete a frame on the ADS131M08. A reset occurs immediately after the command is latched. The host must wait for tREGACQ before communicating with the device to ensure the registers have assumed their default settings. Conversion data are generated immediately after the registers are reset to their default values, as described in the Fast Startup Behavior section. 8.4.2 Fast Startup Behavior The ADS131M08 begins generating conversion data shortly after startup as soon as a valid CLKIN signal is provided to the ΔΣ modulators. The fast startup feature is useful for applications such as circuit breakers powered from the mains that require a fast determination of the input voltage soon after power is applied to the device. Fast startup is accomplished via two mechanisms. First, the device internal power-supply circuitry is designed specifically to enable fast startup. Second, the digital decimation filter dynamically switches from a fastsettling filter to a sinc3 filter when the sinc3 filter has had time to settle. After the supplies are ramped to 90% of their final values, the device requires tPOR for the internal circuitry to settle. The end of tPOR is indicated by a transition of DRDY from low to high. The transition of DRDY from low to high also indicates the SPI interface is ready to accept commands. The ΔΣ modulators of the ADS131M08 require CLKIN to toggle after tPOR to begin working. The modulators begin sampling the input signal after an initial wait time delay of (256 + 44) × tMOD when CLKIN begins toggling. Therefore, provide a valid clock signal on CLKIN as soon as possible after the supply ramp to achieve the fastest possible startup time. The data generated by the ΔΣ modulators are fed to the digital filter blocks. The data are provided to both the fast-settling filter and the sinc3 filter paths. The fast-settling filter requires only one data rate period to provide settled data. Meanwhile, the sinc3 filter requires three data rate periods to settle. The fast-settling filter generates the output data for the two interim ADC output samples indicated by DRDY transitioning from high to low while the sinc3 filter is settling. The device disables the fast-settling filter and provides conversion data from the sinc3 filter path for the third and following samples. Figure 8-14 shows the behavior of the fast-startup feature when using an external clock that is provided to the device right after the supplies have ramped. Table 8-8 shows the values for the various startup and settling times relevant to the device startup. Supplies 90% tSETTLE3 tPOR tDATA tSETTLE1 tDATA DRDY Fast-settling filter data ... CLKIN Sinc3 filter data Fast-settling filter data ... ... Sinc3 filter data ... Figure 8-14. Fast Startup Behavior and Settling Times Table 8-8. Fast Startup Settling Times for Default OSR = 1024 PARAMETER VALUE (DETAILS) (tMOD) VALUE (tMOD) VALUE AT fCLKIN = 8.192 MHz (ms) tDATA = 1/fDATA 1024 1024 0.250 tSETTLE1 256 + 44 + 1024 1324 0.323 tSETTLE3 256 + 44 + 3 x 1024 3372 0.823 The fast-settling filter provides conversion data that are significantly noisier than the data that comes from the sinc3 filter path, but allows the device to provide settled conversion data during the longer settling time of the more accurate sinc3 digital filter. If the level of precision provided by the fast-settling filter is insufficient even for 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 the first samples immediately following startup, ignore the first two instances of DRDY toggling from high to low and begin collecting data on the third instance. The startup process following a RESET command or a pin reset using the SYNC/RESET pin is similar to what occurs after power up. However there is no tPOR in the case of a command or pin reset because the supplies are already ramped. After reset, the device waits for the initial wait time delay of (256 + 44) × tMOD before providing modulator samples to the two digital filters. The fast-settling filter is enabled for the first two output samples. 8.4.3 Conversion Modes There are two ADC conversion modes on the ADS131M08: continuous-conversion and global-chop mode. Continuous-conversion mode is a mode where ADC conversions are generated constantly by the ADC at a rate defined by fMOD / OSR. Global-chop mode differs from continuous-conversion mode because global-chop periodically chops (or swaps) the inputs, which reduces system offset errors at the cost of settling time between the points when the inputs are swapped. In either continuous-conversion or global-chop mode, there are three power modes that provide flexible options to scale power consumption with bandwidth and dynamic range. The Power Modes section discusses these power modes in further detail. 8.4.3.1 Continuous-Conversion Mode Continuous-conversion mode is the mode in which ADC data are generated constantly at the rate of fMOD / OSR. New data are indicated by a DRDY falling edge at this rate. Continuous-conversion mode is intended for measuring AC signals because this mode allows for higher output data rates than global-chop mode. 8.4.3.2 Global-Chop Mode The ADS131M08 incorporates a global-chop mode option to reduce offset error and offset drift inherent to the device due to mismatch in the internal circuitry to very low levels. When global-chop mode is enabled by setting the GC_EN bit in the GLOBAL_CHOP_CFG register, the device uses the conversion results from two consecutive internal conversions taken with opposite input polarity to cancel the device offset voltage. Conversion n is taken with normal input polarity. The device then reverses the internal input polarity for conversion n + 1. The average of two consecutive conversions (n and n + 1, n + 1 and n + 2 and so on) yields the final offset compensated result. Figure 8-15 shows a block diagram of the global-chop mode implementation. The combined PGA and ADC internal offset voltage is modeled as VOFS. Only this device inherent offset voltage is reduced by global-chop mode. Offset in the external circuitry connected to the analog inputs is not affected by global-chop mode. GC_EN Chop Switch VOFS + Digital Filter ADC AINnP PGA ADC Global-Chop Mode Control Conversion Output AINnN Figure 8-15. Global-Chop Mode Implementation The conversion period in global-chop mode differs from the conversion time when global-chop mode is disabled (tDATA = OSR x tMOD). Figure 8-16 shows the conversion timing for an ADC channel using global-chop mode. Global-chop delay Modulator sampling Conversion start xx Sampling n Data not settled Data not settled Sampling n Swap inputs, digital filter reset xx Sampling n tGC_FIRST CONVERSION Sampling n+1 Data not settled Data not settled Sampling n+1 st nd 1 global-chop conversion result Sampling n+1 x 2 global-chop conversion result Sampling n+2 Sampling n+2 tGC_CONVERSION Sampling n+2 Sampling n+3 x x ADC overhead Sampling n+3 Sampling n+3 tDATA Figure 8-16. Conversion Timing With Global-Chop Mode Enabled Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 33 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Every time the device swaps the input polarity, the digital filter is reset. The ADC then always takes three internal conversions to produce one settled global-chop conversion result. The ADS131M08 provides a programmable delay (tGC_DLY) between the end of the previous conversion period and the beginning of the subsequent conversion period after the input polarity is swapped. This delay is to allow for external input circuitry to settle because the chopping switches interface directly with the analog inputs. The GC_DLY[3:0] bits in the GLOBAL_CHOP_CFG register configure the delay after chopping the inputs. The global-chop delay is selected in terms of modulator clock periods from 2 to 65,536 x tMOD. The effective conversion period in global-chop mode follows Equation 8. A DRDY falling edge is generated each time a new global-chop conversion becomes available to the host. The conversion process of all ADC channels in global-chop mode is restarted in the following two conditions so that all channels start sampling at the same time: • Falling edge of SYNC/RESET pin • Change of OSR setting The conversion period of the first conversion after the ADC channels have been reset is considerably longer than the conversion period of all subsequent conversions mentioned in Equation 8, because the device first needs to perform two fully settled internal conversions with the input polarity swapped. The conversion period for the first conversion in global-chop mode follows Equation 9. tGC_CONVERSION = tGC_DLY + 3 × OSR x tMOD (8) tGC_FIRST_CONVERSION = tGC_DLY + 3 × OSR x tMOD + tGC_DLY + 3 × OSR x tMOD + 44 x tMOD (9) Using global-chop mode reduces the ADC noise shown in Table 7-1 at a given OSR by a factor of √2 because two consecutive internal conversions are averaged to yield one global-chop conversion result. The DC test signal cannot be measured in global-chop mode. Phase calibration is automatically disabled in global-chop mode. 8.4.4 Power Modes In both continuous-conversion and global-chop mode, there are three selectable power modes that allow scaling of power with bandwidth and performance: high-resolution (HR) mode, low-power (LP) mode, and very-lowpower (VLP) mode. The mode is selected by the PWR[1:0] bits in the CLOCK register. See the Recommended Operating Conditions table for restrictions on the CLKIN frequency for each power mode. 8.4.5 Standby Mode Standby mode is a low-power state in which all channels are disabled, and the reference and other nonessential circuitry are powered down. This mode differs from completely powering down the device because the device retains its register settings. Enter standby mode by sending the STANDBY command (0022h). Stop toggling CLKIN when the device is in standby mode to minimize device power consumption. Exit standby mode by sending the WAKEUP command (0033h). After exiting standby mode, the modulators begin sampling the input signal after a modulator settling time of 8 × tMOD when CLKIN begins toggling. 8.4.6 Current-Detect Mode Current-detect mode is a special mode that is helpful for applications requiring tamper detection when the equipment is in a low-power state. In this mode, the ADS131M08 collects a configurable number of samples at a nominal data rate of 2.7 kSPS and compares the absolute value of the results to a programmable threshold. If a configurable number of results exceed the threshold, the host is notified via a DRDY falling edge and the device returns to standby mode. Enter current-detect mode by providing a negative pulse on SYNC/RESET with a pulse duration less than tw(RSL) when in standby mode. Current-detect mode can only be entered from standby mode. The device uses a limited power operating mode to generate conversions in current-detect mode. The conversion results are only used for comparison by the internal digital threshold comparator and are not accessible by the host. The device uses an internal oscillator that enables the device to capture the data without the use of the external clock input. Do not toggle CLKIN when in current-detect mode to minimize device power 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 www.ti.com ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 consumption. Do not place a capacitor on the REFIN pin if current-detect mode is used. Capacitance on this pin requires time to start up, and the resulting ADC conversions generated during current-detect mode are not valid when the voltage on the REFIN pin is charging. Current-detect mode is configured in the CFG, THRSHLD_MSB, and THRSHLD_LSB registers. Enable and disable current-detect mode by toggling the CD_EN bit in the CFG register. The THRSHLD_MSB and THRSHLD_LSB registers contain the CD_THRSH[23:0] bits that represent the digital comparator threshold value during current detection. The number of samples used for current detection are programmed by the CD_LEN[2:0] bits in the CFG register. The number of samples used for current detection range from 128 to 3584. The programmable values in CD_NUM[2:0] configure the number of samples that must exceed the threshold for a detection to occur. The purpose of requiring multiple samples for detection is to control noisy values that may exceed the threshold, but do not represent a high enough power level to warrant action by the host. In summary, the conversion result must exceed the value programmed in CD_THRSH[23:0] a number of times as represented by the value stored in CD_NUM[2:0]. The device can be configured to notify the host based on any of the results from either individual channels , all channels, or any combination of channels. The CD_ALLCH bit in the CFG register determines how many channels are required to exceed the programmed thresholds to trigger a current detection. When the bit is 1, all enabled channels are required to meet the current detection requirements in order for the host to be notified. If the bit is 0, any enabled channel triggers a current detection notification if the requirements are met. Enable and disable channels using the CHn_EN bits in the CLK register to control which combination of channels must meet the requirements to trigger a current-detection notification. Figure 8-17 illustrates a flow chart depicting the current-detection process on the ADS131M08. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 35 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Continuous-Conversion Mode No WAKEUP Command STANDBY Command? Yes Standby Mode No SYNC Asserted? Yes Current-Detect Mode Yes Samples Collected = CD_LEN? No Measurement > CD_THRSHLD? No Yes Increment threshold counter Threshold counter > CD_NUM? No Yes No Assert DRDY CD_ALLCH? Yes Yes Current detected on all enabled channels? No Figure 8-17. Current-Detect Mode Flow Chart 36 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 www.ti.com ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.5 Programming 8.5.1 Interface The ADS131M08 uses an SPI-compatible interface to configure the device and retrieve conversion data. The device always acts as an SPI slave; SCLK and CS are inputs to the interface. The interface operates in SPI mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, the SCLK idles low and data are launched or changed only on SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. The interface is full-duplex, meaning data can be sent and received simultaneously by the interface. The device includes the typical SPI signals: SCLK, CS, DIN (MOSI), and DOUT (MISO). In addition, there are two other digital pins that provide additional functionality. The DRDY pin serves as a flag to the host to indicate new conversion data are available. The SYNC/RESET pin is a dual-function pin that allows synchronization of conversions to an external event and allows for a hardware device reset. 8.5.1.1 Chip Select (CS) The CS pin is an active low input signal that selects the device for communication. The device ignores any communication and DOUT is high impedance when CS is held high. Hold CS low for the duration of a communication frame to ensure proper communication. The interface is reset each time CS is taken high. 8.5.1.2 Serial Data Clock (SCLK) The SCLK pin is an input that serves as the serial clock for the interface. Output data on the DOUT pin transition on the rising edge of SCLK and input data on DIN are latched on the falling edge of SCLK. 8.5.1.3 Serial Data Input (DIN) The DIN pin is the serial data input pin for the device. Serial commands are shifted in through the DIN pin by the device with each SCLK falling edge when the CS pin is low. 8.5.1.4 Serial Data Output (DOUT) The DOUT pin is the serial data output pin for the device. The device shifts out command responses and ADC conversion data serially with each rising SCLK edge when the CS pin is low. This pin assumes a highimpedance state when CS is high. 8.5.1.5 Data Ready (DRDY) The DRDY pin is an active low output that indicates when new conversion data are ready in conversion mode or that the requirements are met for current detection when in current-detect mode. Connect the DRDY pin to a digital input on the host to trigger periodic data retrieval in conversion mode. The timing of DRDY with respect to the sampling of a given channel on the ADS131M08 depends on the phase calibration setting of the channel and the state of the DRDY_SEL[1:0] bits in the MODE register. Setting the DRDY_SEL[1:0] bits to 00b configures DRDY to assert when the channel with the largest positive phase calibration setting, or the most lagging, has a new conversion result. When the bits are 01b, the device asserts DRDY each time any channel data are ready. Finally, setting the bits to either 10b or 11b configures the device to assert DRDY when the channel with the most negative phase calibration setting, or the most leading, has new conversion data. Changing the DRDY_SEL[1:0] bits has no effect on DRDY behavior in global-chop mode because phase calibration is automatically disabled in global-chop mode. The timing of the first DRDY assertion after channels are enabled or after a synchronization pulse is provided depends on the phase calibration setting. If the channel that causes DRDY to assert has a phase calibration setting less than zero, the first DRDY assertion can be less than one sample period from the channel being enabled or the occurrence of the synchronization pulse. However, DRDY asserts in the next sample period if the phase setting puts the output timing too close to the beginning of the sample period. Table 8-9 lists the phase calibration setting boundary at which DRDY either first asserts within a sample period, or in the next sample period. If the setting for the channel configured to control DRDY assertion is greater than the value listed in Table 8-9 for each OSR, DRDY asserts for the first time within a sample period of the channel being enabled or the synchronization pulse. If the phase setting value is equal to or more negative than the Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 37 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 value in Table 8-9, DRDY asserts in the following sample period. See the Synchronization section for more information about synchronization. Table 8-9. Phase Setting First DRDY Assertion Boundary OSR PHASE SETTING BOUNDARY PHASEn[9:0] BIT SETTING BOUNDARY 128 –19 3EDh 256 –83 3ADh 512 –211 32Dh 1024 –467 22Dh >1024 None N/A The DRDY_HIZ bit in the MODE register configures the state of the DRDY pin when deasserted. By default the bit is 0b, meaning the pin is actively driven high using a push-pull output stage. When the bit is 1b, DRDY behaves like an open-drain digital output. Use a 100-kΩ pullup resistor to pull the pin high when DRDY is not asserted. The DRDY_FMT bit in the MODE register determines the format of the DRDY signal. When the bit is 0b, new data are indicated by DRDY changing from high to low and remaining low until either all of the conversion data are shifted out of the device, or remaining low and going high briefly before the next time DRDY transitions low. When the DRDY_FMT bit is 1b, new data are indicated by a short negative pulse on the DRDY pin. If the host does not read conversion data after the DRDY pulse when DRDY_FMT is 1b, the device skips a conversion result and does not provide another DRDY pulse until the second following instance when data are ready because of how the pulse is generated. See the Collecting Data for the First Time or After a Pause in Data Collection section for more information about the behavior of DRDY when data are not consistently read. The DRDY pulse is blocked when new conversions complete while conversion data are read. Therefore, avoid reading ADC data during the time where new conversions complete in order to achieve consistent DRDY behavior. 8.5.1.6 Conversion Synchronization or System Reset (SYNC/RESET) The SYNC/RESET pin is a multi-function digital input pin that serves primarily to allow the host to synchronize conversions to an external process or to reset the device. See the Synchronization section for more details regarding the synchronization function. See the SYNC/RESET Pin section for more details regarding how the device is reset. 8.5.1.7 SPI Communication Frames SPI communication on the ADS131M08 is performed in frames. Each SPI communication frame consists of several words. The word size is configurable as either 16 bits, 24 bits, or 32 bits by programming the WLENGTH[1:0] bits in the MODE register. The ADS131M08 implements a timeout feature for the SPI communication. Enable or disable the timeout using the TIMEOUT bit in the MODE register. When enabled, the entire SPI frame (first SCLK to last SCLK) must complete within 215 CLKIN cycles otherwise the SPI will reset. This feature is provided as a means to recover SPI synchronization for cases where CS is tied low. The interface is full duplex, meaning that the interface is capable of transmitting data on DOUT while simultaneously receiving data on DIN. The input frame that the host sends on DIN always begins with a command. The first word on the output frame that the device transmits on DOUT always begins with the response to the command that was written on the previous input frame. The number of words in a command depends on the command provided. For most commands, there are ten words in a frame. On DIN, the host provides the command, the command CRC if input CRC is enabled or a word of zeros if input CRC is disabled, and eight additional words of zeros. Simultaneously on DOUT, the device outputs the response from the previous frame command, eight words of ADC data representing the eight ADC channels, and a CRC word. Figure 8-18 illustrates a typical command frame structure. 38 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 DRDY CS SCLK DIN DOUT Hi-Z Command CRC Response Channel 0 Data Channel 1 Data Channel 2 Data Channel 7 Data CRC Hi-Z Command CRC Response Channel 0 Data Figure 8-18. Typical Communication Frame There are some commands that require more than ten words. In the case of a read register (RREG) command where more than a single register is read, the response to the command contains the acknowledgment of the command followed by the register contents requested, which may require a larger frame depending on how many registers are read. See the RREG (101a aaaa annn nnnn) section for more details on the RREG command. In the case of a write register (WREG) command where more than a single register is written, the frame extends to accommodate the additional data. See the WREG (011a aaaa annn nnnn) section for more details on the WREG command. See the Commands section for a list of all valid commands and their corresponding responses on the ADS131M08. Under special circumstances, a data frame can be shortened by the host. See the Short SPI Frames section for more information about artificially shortening communication frames. 8.5.1.8 SPI Communication Words An SPI communication frame with the ADS131M08 is made of words. Words on DIN can contain commands, register settings during a register write, or a CRC of the input data. Words on DOUT can contain command responses, register settings during a register read, ADC conversion data, or CRC of the output data. Words can be 16, 24, or 32 bits. The word size is configured by the WLENGTH[1:0] bits in the MODE register. The device defaults to a 24-bit word size. Commands, responses, CRC, and registers always contain 16 bits of actual data. These words are always most significant bit (MSB) aligned, and therefore the least significant bits (LSBs) are zero-padded to accommodate 24- or 32-bit word sizes. ADC conversion data are nominally 24 bits. The ADC truncates its eight LSBs when the device is configured for 16-bit communication. There are two options for 32-bit communication available for ADC data that are configured by the WLENGTH[1:0] bits in the MODE register. Either the ADC data can be LSB padded with zeros or the data can be MSB sign extended. 8.5.1.9 ADC Conversion Data The device provides conversion data for each channel at the data rate. The time when data are available relative to DRDY asserting is determined by the channel phase calibration setting and the DRDY_SEL[1:0] bits in the MODE register when in continuous-conversion mode. All data are available immediately following DRDY assertion in global-chop mode. The conversion status of all channels is available as the DRDY[7:0] bits in the STATUS register. The STATUS register content is automatically output as the response to the NULL command. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 39 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Conversion data are 24 bits. The data LSBs are truncated when the device operates with a 16-bit word size. The LSBs are zero padded or the MSBs sign extended when operating with a 32-bit word size depending on the setting of the WLENGTH[1:0] bits in the MODE register. Data are given in binary two's complement format. Use Equation 10 to calculate the size of one code (LSB). 1 LSB = (2.4 / Gain) / 224 = +FSR / 223 (10) A positive full-scale input VIN ≥ +FSR – 1 LSB = 1.2 / Gain – 1 LSB produces an output code of 7FFFFFh and a negative full-scale input (VIN ≤ –FSR = –1.2 / Gain) produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale. Table 8-10 summarizes the ideal output codes for different input signals. Table 8-10. Ideal Output Code versus Input Signal INPUT SIGNAL, VIN = VAINP – VAINN IDEAL OUTPUT CODE ≥ FSR (223 – 1) / 223 7FFFFFh 223 FSR / 000001h 0 000000h –FSR / 223 FFFFFFh ≤ –FSR 800000h Figure 8-19 shows the mapping of the analog input signal to the output codes. 7FFFFFh 000001h 000000h FFFFFFh ¼ Output Code ¼ 7FFFFEh 800001h 800000h ¼ -FS 2 23 FS ¼ Input Voltage VIN -1 -FS 2 0 23 2 23 FS 2 -1 23 Figure 8-19. Code Transition Diagram 8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection Take special precaution when collecting data for the first time or when beginning to collect data again after a pause. The internal mechanism that outputs data contains a first-in-first-out (FIFO) buffer that can store two samples of data per channel at a time. The DRDY flag for each channel in the STATUS register remains set until both samples for each channel are read from the device. This condition is not obvious under normal circumstances when the host is reading each consecutive sample from the device. In that case, the samples are cleared from the device each time new data are generated so the DRDY flag for each channel in the STATUS register is cleared with each read. However, both slots of the FIFO are full if a sample is missed or if data are not read for a period of time. Either strobe the SYNC/RESET pin to re-synchronize conversions and clear the FIFOs, or quickly read two data packets when data are read for the first time or after a gap in reading data. This process ensures predictable DRDY pin behavior. See the Synchronization section for information about the synchronization feature. These methods do not need to be employed if each channel data was read for each output data period from when the ADC was enabled. 40 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Figure 8-20 depicts an example of how to collect data after a period of the ADC running, but where no data are being retrieved. In this instance, the SYNC/RESET pin is used to clear the internal FIFOs and realign the ADS131M08 output data with the host. Time where data is not being read DRDY SYNC / RESET SYNC Pulse CS SCLK DOUT Data Data Hi-Z CRC Status Data CRC Figure 8-20. Collecting Data After a Pause in Data Collection Using the SYNC/RESET Pin Another functionally equivalent method for clearing the FIFO after a pause in collecting data is to begin by reading two samples in quick succession. Figure 8-21 depicts this method. This example shows when the DRDY_FMT bit in the MODE register is set to 0b indicating DRDY is a level output. There is a very narrow pulse on DRDY immediately after the first set of data are shifted out of the device. This pulse may be too narrow for some microcontrollers to detect. Therefore, do not rely upon this pulse but instead immediately read out the second data set after the first data set. The host operates synchronous to the device after the second word is read from the device. Time where data is not being read Narrow DRDY Pulse DRDY CS SCLK DOUT Data Data CRC Hi-Z Status Data CRC Status Data CRC Data is read a second time Figure 8-21. Collecting Data After a Pause in Data Collection by Reading Data Twice 8.5.1.10 Commands Table 8-11 contains a list of all valid commands, a short description of their functionality, their binary command word, and the expected response that appears in the following frame. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 41 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Table 8-11. Command Definitions COMMAND DESCRIPTION NULL No operation RESET Reset the device 0000 0000 0001 0001 1111 1111 0010 1000 Place the device into standby mode 0000 0000 0010 0010 0000 0000 0010 0010 WAKEUP Wake the device from standby mode to conversion mode 0000 0000 0011 0011 0000 0000 0011 0011 Lock the interface such that only the NULL, UNLOCK, and RREG commands are valid 0000 0101 0101 0101 0000 0101 0101 0101 Unlock the interface after the interface is locked 0000 0110 0101 0101 0000 0110 0101 0101 dddd dddd dddd dddd or 111a aaa annn nnnn (1) UNLOCK (2) RESPONSE STATUS register STANDBY LOCK (1) COMMAND WORD 0000 0000 0000 0000 RREG Read nnn nnnn plus 1 registers beginning at address a aaaa a 101a aaaa annn nnnn WREG Write nnn nnnn plus 1 registers beginning at address a aaaa a 011a aaaa annn nnnn 010a aaaa ammm mmmm (2) When nnn nnnn is 0, the response is the requested register data dddd dddd dddd dddd. When nnn nnnn is greater than 0, the response begins with 111a aaaa annn nnnn, followed by the register data. In this case mmm mmmm represents the number of registers that are actually written minus one. This value may be less than nnn nnnn in some cases. 8.5.1.10.1 NULL (0000 0000 0000 0000) The NULL command is the no-operation command that results in no registers read or written, and the state of the device remains unchanged. The intended use case for the NULL command is during ADC data capture. The command response for the NULL command is the contents of the STATUS register. Any invalid command also gives the NULL response. 8.5.1.10.2 RESET (0000 0000 0001 0001) The RESET command resets the ADC to its register defaults. The command is latched by the device at the end of the frame. A reset occurs immediately after the command is latched. The host must wait for tREGACQ after reset before communicating with the device to ensure the registers have assumed their default settings. The device sends an acknowledgment of FF28h when the ADC is properly RESET. The device responds with 0011h if the command word is sent but the frame is not completed and therefore the device is not reset. See the RESET Command section for more information regarding the operation of the reset command. Figure 8-22 illustrates a properly sent RESET command frame. CS SCLK DIN RESET CRC RESET command latched here x5 DOUT Hi-Z Response 'RQ¶W &DUH 'RQ¶W &DUH 'RQ¶W &DUH Hi-Z Figure 8-22. RESET Command Frame 42 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 www.ti.com ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.5.1.10.3 STANDBY (0000 0000 0010 0010) The STANDBY command places the device in a low-power standby mode. The command is latched by the device at the end of the frame. The device enters standby mode immediately after the command is latched. See the Standby Mode section for more information. This command has no effect if the device is already in standby mode. 8.5.1.10.4 WAKEUP (0000 0000 0011 0011) The WAKEUP command returns the device to conversion mode from standby mode. This command has no effect if the device is already in conversion mode. 8.5.1.10.5 LOCK (0000 0101 0101 0101) The LOCK command locks the interface, preventing the device from accidentally latching unwanted commands that can change the state of the device. When the interface is locked, the device only responds to the NULL, RREG, and UNLOCK commands. The device continues to output conversion data even when locked. 8.5.1.10.6 UNLOCK (0000 0110 0110 0110) The UNLOCK command unlocks the interface if previously locked by the LOCK command. 8.5.1.10.7 RREG (101a aaaa annn nnnn) The RREG is used to read the device registers. The binary format of the command word is 101a aaaa annn nnnn, where a aaaa a is the binary address of the register to begin reading and nnn nnnn is the unsigned binary number of consecutive registers to read minus one. There are two cases for reading registers on the ADS131M08. When reading a single register (nnn nnnn = 000 0000b), the device outputs the register contents in the command response word of the following frame. If multiple registers are read using a single command (nnn nnnn > 000 0000b), the device outputs the requested register data sequentially in order of addresses. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 43 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.5.1.10.7.1 Reading a Single Register Read a single register from the device by specifying nnn nnnn as zero in the RREG command word. As with all SPI commands on the ADS131M08, the response occurs on the output in the frame following the command. Instead of a unique acknowledgment word, the response word is the contents of the register whose address is specified in the command word. Figure 8-23 shows an example of reading a single register. DRDY CS SCLK DIN DOUT Hi-Z RREG CRC Response Channel 0 Data Channel 1 Data CRC Channel 7 Data Hi-Z Command CRC Register Data Channel 0 Data Figure 8-23. Reading a Single Register 8.5.1.10.7.2 Reading Multiple Registers Multiple registers are read from the device when nnn nnnn is specified as a number greater than zero in the RREG command word. Like all SPI commands on the ADS131M08, the response occurs on the output in the frame following the command. Instead of a single acknowledgment word, the response spans multiple words in order to shift out all requested registers. Continue toggling SCLK to accommodate outputting the entire data stream. ADC conversion data are not output in the frame following an RREG command to read multiple registers. Figure 8-24 shows an example of reading multiple registers. CS SCLK DIN DOUT Hi-Z RREG CRC Response Channel 0 Data Channel 1 Data Channel 7 Data CRC Hi-Z Command CRC RREG ack 1st UHJLVWHU¶V data 2nd UHJLVWHU¶V data N-1th UHJLVWHU¶V data Nth UHJLVWHU¶V data CRC Hi-Z Figure 8-24. Reading Multiple Registers 44 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.5.1.10.8 WREG (011a aaaa annn nnnn) The WREG command allows writing an arbitrary number of contiguous device registers. The binary format of the command word is 011a aaaa annn nnnn, where a aaaa a is the binary address of the register to begin writing and nnn nnnn is the unsigned binary number of consecutive registers to write minus one. Send the data to be written immediately following the command word. Write the intended contents of each register into individual words, MSB aligned. If the input CRC is enabled, write this CRC after the register data. The registers are written to the device as they are shifted into DIN. Therefore, a CRC error does not prevent an erroneous value from being written to a register. An input CRC error during a WREG command sets the CRC_ERR bit in the STATUS register. The device ignores writes to read-only registers or to out-of-bounds addresses. Gaps in the register map address space are still included in the parameter nnn nnnn, but are not writeable so no change is made to them. The response to the WREG command that occurs in the following frame appears as 010a aaaa ammm mmmm where mmm mmmm is the number of registers actually written minus one. This number can be checked by the host against nnn nnnn to ensure the expected number of registers are written. Figure 8-25 shows a typical WREG sequence. In this example, the number of registers to write is larger than the number of ADC channels and, therefore, the frame is extended beyond the ADC channels and output CRC word. Ensure all of the ADC data and output CRC are shifted out during each transaction where new data are available. Therefore, the frame must be extended beyond the number of words required to send the register data in some cases. DRDY CS SCLK DIN DOUT Hi-Z WREG 1st UHJLVWHU¶V data 2nd UHJLVWHU¶V data 8th UHJLVWHU¶V data 9th UHJLVWHU¶V data Response Channel 0 Data Channel 1 Data Channel 7 Data CRC 10th UHJLVWHU¶V data N-1th UHJLVWHU¶V data 'RQ¶W &DUH Nth UHJLVWHU¶V data CRC Hi-Z Command CRC Response Channel 0 Data Figure 8-25. Writing Registers 8.5.1.11 Short SPI Frames The SPI frame can be shortened to only send commands and receive responses if the ADCs are disabled and no ADC data are being output by the device. Read out all of the expected output data words from each sample period if the ADCs are enabled. Reading all of the data output with each frame ensures predictable DRDY pin behavior. If reading out all the data on each output data period is not feasible, see the Collecting Data for the First Time or After a Pause in Data Collection section on how to begin reading data again after a pause from when the ADCs were last enabled. A short frame is not possible when using the RESET command. A full frame must be provided for a device reset to take place when providing the RESET command. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 45 ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 www.ti.com 8.5.2 Synchronization Synchronization can be performed by the host to ensure the ADC conversions are synchronized to an external event. For example, synchronization can realign the data capture to the expected timing of the host if a glitch on the clock causes the host and device to become out of synchronization. Provide a negative pulse on the SYNC/RESET pin with a duration less than tw(RSL) but greater than a CLKIN period to trigger synchronization. The device internally compares the leading negative edge of the pulse to its internal clock that tracks the data rate. The internal data rate clock has timing equivalent to the DRDY pin if configured to assert with a phase calibration setting of 0b. If the negative edge on SYNC/RESET aligns with the internal data rate clock, the device is determined to be synchronized and therefore no action is taken. If there is misalignment, the digital filters on the device are reset to be synchronized with the SYNC/RESET pulse. Conversions are immediately restarted when the SYNC/RESET pin is toggled in global-chop mode. The phase calibration settings on all channels are retained during synchronization. Thus, channels with non-zero phase calibration settings generate conversion results less than a data rate period after the synchronization event occurs. However, the results can be corrupted and are not settled until the respective channels have at least three conversion cycles for the sinc3 filter to settle. 46 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6 Registers Table 8-12 lists the ADS131M08 registers. All register offset addresses not listed in Table 8-12 should be considered as reserved locations and the register contents should not be modified. Table 8-12. Register Map ADDRESS REGISTER RESET VALUE BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DEVICE SETTINGS AND INDICATORS (Read-Only Registers) 00h ID 28xxh 01h STATUS 0500h RESERVED CHANCNT[3:0] RESERVED LOCK F_RESYNC REG_MAP CRC_ERR CRC_TYPE RESET DRDY7 DRDY6 DRDY5 DRDY4 DRDY3 DRDY2 REGCRC_EN RX_CRC_EN CRC_TYPE RESET WLENGTH[1:0] DRDY1 DRDY0 GLOBAL SETTINGS ACROSS CHANNELS 02h MODE 03h CLOCK FF0Eh 04h GAIN1 0000h 05h 06h GAIN2 CFG RESERVED 0510h 0000h 0600h 07h THRSHLD_MSB 0000h 08h THRSHLD_LSB 0000h RESERVED CH7_EN CH6_EN TIMEOUT CH5_EN CH4_EN RESERVED DRDY_SEL[1:0] CH3_EN CH2_EN WLENGTH[1:0] DRDY_HiZ DRDY_FMT CH1_EN CH0_EN OSR[2:0] PWR[1:0] RESERVED PGAGAIN3[2:0] RESERVED RESERVED PGAGAIN1[2:0] RESERVED PGAGAIN0[2:0] RESERVED PGAGAIN7[2:0] RESERVED PGAGAIN6[2:0] PGAGAIN5[2:0] RESERVED PGAGAIN4[2:0] RESERVED RESERVED CD_ALLCH PGAGAIN2[2:0] GC_DLY[3:0] CD_NUM[2:0] GC_EN CD_LEN[2:0] CD_EN CD_TH_MSB[15:8] CD_TH_MSB[7:0] RESERVED DCBLOCK[3:0] CHANNEL-SPECIFIC SETTINGS 09h CH0_CFG 0000h 0Ah CH0_OCAL_MSB 0000h 0Bh CH0_OCAL_LSB 0000h 0Ch CH0_GCAL_MSB 8000h 0Dh CH0_GCAL_LSB 0000h 0Eh CH1_CFG 0000h 0Fh CH1_OCAL_MSB 0000h 10h CH1_OCAL_LSB 0000h 11h CH1_GCAL_MSB 8000h 12h CH1_GCAL_LSB 0000h 13h CH2_CFG 0000h 14h CH2_OCAL_MSB 0000h 15h CH2_OCAL_LSB 0000h 16h CH2_GCAL_MSB 8000h 17h CH2_GCAL_LSB 0000h PHASE0[9:2] PHASE0[1:0] RESERVED DCBLK0_DIS0 MUX0[1:0] DCBLK1_DIS0 MUX1[1:0] DCBLK2_DIS0 MUX2[1:0] OCAL0_MSB[15:8] OCAL0_MSB[7:0] OCAL0_LSB[7:0] RESERVED GCAL0_MSB[15:8] GCAL0_MSB[7:0] GCAL0_LSB[7:0] RESERVED PHASE1[9:2] PHASE1[1:0] RESERVED OCAL1_MSB[15:8] OCAL1_MSB[7:0] OCAL1_LSB[7:0] RESERVED GCAL1_MSB[15:8] GCAL1_MSB[7:0] GCAL1_LSB[7:0] RESERVED PHASE2[9:2] PHASE2[1:0] RESERVED OCAL2_MSB[15:8] OCAL2_MSB[7:0] OCAL2_LSB[7:0] RESERVED GCAL2_MSB[15:8] GCAL2_MSB[7:0] GCAL2_LSB[7:0] RESERVED Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 47 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Table 8-12. Register Map (continued) ADDRESS 18h CH3_CFG RESET VALUE 0000h 19h CH3_OCAL_MSB 0000h 1Ah CH3_OCAL_LSB 0000h 1Bh CH3_GCAL_MSB 8000h 1Ch CH3_GCAL_LSB 0000h 1Dh CH4_CFG 0000h 1Eh CH4_OCAL_MSB 0000h 1Fh CH4_OCAL_LSB 0000h 20h CH4_GCAL_MSB 8000h 21h CH4_GCAL_LSB 0000h 22h CH5_CFG 0000h 23h CH5_OCAL_MSB 0000h 24h CH5_OCAL_LSB 0000h 25h CH5_GCAL_MSB 8000h 26h CH5_GCAL_LSB 0000h 27h CH6_CFG 0000h 28h CH6_OCAL_MSB 0000h 29h CH6_OCAL_LSB 0000h 2Ah CH6_GCAL_MSB 8000h 2Bh CH6_GCAL_LSB 0000h 2Ch 48 REGISTER CH7_CFG 0000h 2Dh CH7_OCAL_MSB 0000h 2Eh CH7_OCAL_LSB 0000h 2Fh CH7_GCAL_MSB 8000h 30h CH7_GCAL_LSB 0000h 3Eh REGMAP_CRC 0000h 3Fh RESERVED 0000h BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PHASE3[9:2] PHASE3[1:0] RESERVED DCBLK3_DIS0 MUX3[1:0] DCBLK4_DIS0 MUX4[1:0] DCBLK5_DIS0 MUX5[1:0] DCBLK6_DIS0 MUX6[1:0] DCBLK7_DIS0 MUX7[1:0] OCAL3_MSB[15:8] OCAL3_MSB[7:0] OCAL3_LSB[7:0] RESERVED GCAL3_MSB[15:8] GCAL3_MSB[7:0] GCAL3_LSB[7:0] RESERVED PHASE4[9:2] PHASE4[1:0] RESERVED OCAL4_MSB[15:8] OCAL4_MSB[7:0] OCAL4_LSB[7:0] RESERVED GCAL4_MSB[15:8] GCAL4_MSB[7:0] GCAL4_LSB[7:0] RESERVED PHASE5[9:2] PHASE5[1:0] RESERVED OCAL5_MSB[15:8] OCAL5_MSB[7:0] OCAL5_LSB[7:0] RESERVED GCAL5_MSB[15:8] GCAL5_MSB[7:0] GCAL5_LSB[7:0] RESERVED PHASE6[9:2] PHASE6[1:0] RESERVED OCAL6_MSB[15:8] OCAL6_MSB[7:0] OCAL6_LSB[7:0] RESERVED GCAL6_MSB[15:8] GCAL6_MSB[7:0] GCAL6_LSB[7:0] RESERVED PHASE7[9:2] PHASE7[1:0] RESERVED OCAL7_MSB[15:8] OCAL7_MSB[7:0] OCAL7_LSB[7:0] RESERVED GCAL7_MSB[15:8] GCAL7_MSB[7:0] GCAL7_LSB[7:0] RESERVED REG_CRC[7:0] RESERVED RESERVED Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Complex bit access types are encoded to fit into small table cells. Table 8-13 shows the codes that are used for access types in this section. Table 8-13. Access Type Codes Access Type Code Description R Read W Write Read Type R Write Type W Reset or Default Value -n Value after reset or the default value Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 49 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.1 ID Register (Address = 00h) [reset = 28xxh] The ID register is shown in Figure 8-26 and described in Table 8-14. Return to the Summary Table. Figure 8-26. ID Register 15 14 7 13 12 11 10 RESERVED CHANCNT[3:0] R-0010b R-1000b 6 5 4 3 2 9 8 1 0 RESERVED R-xxxxxxxxb Table 8-14. ID Register Field Descriptions Bit Field Type Reset Description RESERVED R 0010b Reserved always reads 0010b. 11:8 CHANCNT[3:0] R 1000b Channel count always reads 1000b. 7:0 RESERVED R xxxxxxxxb Reserved Values are subject to change without notice 15:12 50 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.2 STATUS Register (Address = 01h) [reset = 0500h] The STATUS register is shown in Figure 8-27 and described in Table 8-15. Return to the Summary Table. Figure 8-27. STATUS Register 15 14 13 12 11 10 9 8 LOCK F_RESYNC REG_MAP CRC_ERR CRC_TYPE RESET WLENGTH[1:0] R-0b R-0b R-0b R-0b R-0b R-1b R-01b 7 6 5 4 3 2 1 0 DRDY7 DRDY6 DRDY5 DRDY4 DRDY3 DRDY2 DRDY1 DRDY0 R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b Table 8-15. STATUS Register Field Descriptions Bit Field Type Reset Description 15 LOCK R 0b SPI interface lock indicator 0b = Unlocked (default) 1b = Locked 14 F_RESYNC R 0b ADC resynchronization indicator. Bit is set each time the ADC resynchronizes. 0b = No resynchronization (default) 1b = Resynchronization occurred 13 REG_MAP R 0b Register map CRC fault indicator 0b = No change in the register map CRC (default) 1b = Register map CRC changed 12 CRC_ERR R 0b SPI input CRC error indicator 0b = No CRC error (default) 1b = Input CRC error occured 11 CRC_TYPE R 0b CRC type 0b = 16 bit CCITT (default) 1b = 16 bit ANSI 10 RESET R 1b Reset status 0b = Not reset 1b = Reset occured (default) 9:8 WLENGTH[1:0] R 01b Data word length 00b = 16 bit 01b = 24 bits (default) 10b = 32 bits - zero padding 11b = 32 bits - sign extension for 24 bit ADC data 7 DRDY7 R 0b Channel 7 ADC data available indicator 0b = No new data available 1b = New data are available 6 DRDY6 R 0b Channel 6 ADC data available indicator 0b = No new data available 1b = New data are available Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 51 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Table 8-15. STATUS Register Field Descriptions (continued) Bit 5 Field Type Reset Description DRDY5 R 0b Channel 5 ADC data available indicator 0b = No new data available 1b = New data are available 4 DRDY4 R 0b Channel 4 ADC data available indicator 0b = No new data available 1b = New data are available 3 DRDY3 R 0b Channel 3 ADC data available indicator 0b = No new data available 1b = New data are available 2 DRDY2 R 0b Channel 2 ADC data available indicator 0b = No new data available 1b = New data are available 1 DRDY1 R 0b Channel 1 ADC data available indicator 0b = No new data available 1b = New data are available 0 DRDY0 R 0b Channel 0 ADC data available indicator 0b = No new data available 1b = New data are available 52 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.3 MODE Register (Address = 02h) [reset = 0510h] The MODE register is shown in Figure 8-28 and described in Table 8-16. Return to the Summary Table. Figure 8-28. MODE Register 15 14 13 12 11 RESERVED REG_CRC_EN RX_CRC_EN CRC_TYPE RESET WLENGTH[1:0] R/W-00b R/W-0b R/W-0b R/W-0b R/W-1b R/W-01b 4 3 2 7 6 5 10 9 8 1 0 RESERVED TIMEOUT DRDY_SEL[1:0] DRDY_HiZ DRDY_FMT R/W-000b R/W-1b R/W-00b R/W-0b R/W-0b Table 8-16. MODE Register Field Descriptions Bit 15:14 13 Field Type Reset Description RESERVED R/W 00b Reserved always reads 00b REG_CRC_EN R/W 0b Register Map CRC enable 0b = Disabled (default) 1b = Enabled 12 RX_CRC_EN R/W 0b SPI input CRC enable 0b = Disabled (default) 1b = Enabled 11 CRC_TYPE R/W 0b SPI and register map CRC type 0b = 16-bit CCITT (default) 1b = 16-bit ANSI 10 RESET R/W 1b Reset write 0b to clear this bit in the STATUS register 0b = No reset 1b = Reset happened (default by definition) 9:8 WLENGTH[1:0] R/W 01b Data word length selection 00b = 16 bits 01b = 24 bits (default) 10b = 32 bits: LSB zero padding 11b = 32 bits: MSB sign extension 7:5 4 RESERVED R/W 000b Reserved always write 000b TIMEOUT R/W 1b SPI Timeout enable 0b = Disabled 1b = Enabled (default) 3:2 DRDY_SEL[1:0] R/W 00b DRDY pin signal source selection 00b = Most lagging enabled channel (default) 01b = Logic OR of all the enabled channels 10b = Most leading enabled channel 11b = Most leading enabled channel Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 53 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Table 8-16. MODE Register Field Descriptions (continued) Bit 1 Field Type Reset Description DRDY_HiZ R/W 0b DRDY pin state when conversion data is not available 0b = Logic high (default) 1b = High impedance 0 DRDY_FMT R/W 0b DRDY signal format when conversion data is available 0b = Logic low (default) 1b = Low pulse with a fixed duration 54 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.4 CLOCK Register (Address = 03h) [reset = FF0Eh] The CLOCK register is shown in Figure 8-29 and described in Table 8-17. Return to the Summary Table. Figure 8-29. CLOCK Register 15 14 13 12 11 10 9 8 CH7_EN CH6_EN CH5_EN CH4_EN CH3_EN CH2_EN CH1_EN CH0_EN R/W-1b R/W-1b R/W-1b R/W-1b R/W-1b R/W-1b R/W-1b R/W-1b 4 3 2 1 7 6 5 XTAL_DIS EXTREF_EN RESERVED OSR[2:0] PWR 0 R/W-0b R/W-0b R/W-0b R/W-011b R/W-10b Table 8-17. CLOCK Register Field Descriptions Bit Field Type Reset Description 15 CH7_EN R/W 1b Channel 7 ADC enable 0b = Disabled 1b = Enabled (default) 14 CH6_EN R/W 1b Channel 6 ADC enable 0b = Disabled 1b = Enabled (default) 13 CH5_EN R/W 1b Channel 5 ADC enable 0b = Disabled 1b = Enabled (default) 12 CH4_EN R/W 1b Channel 4 ADC enable 0b = Disabled 1b = Enabled (default) 11 CH3_EN R/W 1b Channel 3 ADC enable 0b = Disabled 1b = Enabled (default) 10 CH2_EN R/W 1b Channel 2 ADC enable 0b = Disabled 1b = Enabled (default) 9 CH1_EN R/W 1b Channel 1 ADC enable 0b = Disabled 1b = Enabled (default) 8 CH0_EN R/W 1b Channel 0 ADC enable 0b = Disabled 1b = Enabled (default) 7 XTAL_DIS R/W 0b Crystal oscillator disable 0b = Enabled (default) 1b = Disabled 6 EXTREF_EN R/W 0b External reference enable 0b = Disabled (default) 1b = Enabled Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 55 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Table 8-17. CLOCK Register Field Descriptions (continued) Bit 5 4:2 Field Type Reset Description RESERVED R/W 0b Reserved always write 0b OSR[2:0] R/W 011b Modulator oversampling ratio selection 000b = 128 001b = 256 010b = 512 011b = 1024 (default) 100b = 2048 101b = 4096 110b = 8192 111b = 16256 1:0 PWR R/W 10b Power mode selection 00b = Very-low-power 01b = Low-power 10b = High-resolution (default) 11b = High-resolution 56 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.5 GAIN1 Register (Address = 4h) [reset = 0000h] The GAIN1 register is shown in Figure 8-30 and described in Table 8-18. Return to the Summary Table. Figure 8-30. GAIN1 Register 15 14 13 12 11 10 9 RESERVED PGAGAIN3[2:0] RESERVED PGAGAIN2[2:0] R/W-0b R/W-000b R/W-0b R/W-000b 7 6 5 4 3 2 1 RESERVED PGAGAIN1[2:0] RESERVED PGAGAIN0[2:0] R/W-0b R/W-000b R/W-0b R/W-000b 8 0 Table 8-18. GAIN1 Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R/W 0b Reserved always write 0b PGAGAIN3[2:0] R/W 000b PGA gain selection for channel 3 14:12 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 11 10:8 RESERVED R/W 0b Reserved always write 0b PGAGAIN2[2:0] R/W 000b PGA gain selection for channel 2 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 7 6:4 RESERVED R/W 0b Reserved always write 0b PGAGAIN1[2:0] R/W 000b PGA gain selection for channel 1 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 57 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Table 8-18. GAIN1 Register Field Descriptions (continued) Bit 3 2:0 Field Type Reset Description RESERVED R/W 0b Reserved always write 0b PGAGAIN0[2:0] R/W 000b PGA gain selection for channel 0 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 58 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.6 GAIN2 Register (Address = 5h) [reset = 0000h] The GAIN2 register is shown in Figure 8-31 and described in Table 8-19. Return to the Summary Table. Figure 8-31. GAIN2 Register 15 14 13 12 11 10 9 RESERVED PGAGAIN7[2:0] RESERVED PGAGAIN6[2:0] R-0b R/W-000b R-0b R/W-000b 7 6 5 4 3 2 1 RESERVED PGAGAIN5[2:0] RESERVED PGAGAIN4[2:0] R/W-0b R/W-000b R/W-0b R/W-000b 8 0 Table 8-19. GAIN2 Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R/W 0b Reserved always write 0b PGAGAIN7[2:0] R/W 000b PGA gain selection for channel 7 14:12 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 11 10:8 RESERVED R/W 0b Reserved always write 0b PGAGAIN6[2:0] R/W 000b PGA gain selection for channel 6 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 7 6:4 RESERVED R/W 0b Reserved always write 0b PGAGAIN5[2:0] R/W 000b PGA gain selection for channel 5 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b =128 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 59 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Table 8-19. GAIN2 Register Field Descriptions (continued) Bit 3 2:0 Field Type Reset Description RESERVED R/W 0b Reserved always write 0b PGAGAIN4[2:0] R/W 000b PGA gain selection for channel 4 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 60 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.7 CFG Register (Address = 06h) [reset = 0600h] The CFG register is shown in Figure 8-32 and described in Table 8-20. Return to the Summary Table. Figure 8-32. CFG Register 15 14 13 12 11 10 9 8 RESERVED GC_DLY[3:0] GC_EN R/W-000b R/W-0011b R/W-0b 7 6 5 4 3 2 1 0 CD_ALLCH CD_NUM[2:0] CD_LEN[2:0] CD_EN R/W-0b R/W-000b R/W-000b R/W-0b Table 8-20. CFG Register Field Descriptions Field Type Reset Description 15:13 Bit RESERVED R/W 000b Reserved always write 000b 12:9 GC_DLY[3:0] R/W 0011b Global-chop delay selection Delay in modulator clock periods before measurement begins 0000b = 2 0001b = 4 0010b = 8 0011b = 16 (default) 0100b = 32 0101b = 64 0110b = 128 0111b = 256 1000b = 512 1001b = 1024 1010b = 2048 1011b = 4096 1100b = 8192 1101b = 16384 1110b = 32768 1111b = 65536 8 GC_EN R/W 0b Global-chop enable 0b = Disabled (default) 1b = Enabled 7 CD_ALLCH R/W 0b Current-detect channels selection Channels required to trigger current-detect 0b = Any channel (default) 1b = All channels Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 61 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 Table 8-20. CFG Register Field Descriptions (continued) Bit Field Type Reset Description 6:4 CD_NUM[2:0] R/W 000b Number of current-detect exceeded thresholds selection Number of current-detect exceeded thresholds to trigger a detection 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 3:1 CD_LEN[2:0] R/W 000b Current-detect measurement length selection Current-detect measurement length in conversion periods 000b = 128 (default) 001b = 256 010b = 512 011b = 768 100b = 1280 101b = 1792 110b = 2560 111b = 3584 0 CD_EN R/W 0b Current-detect mode enable 0b = Disabled (default) 1b = Enabled 62 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.8 THRSHLD_MSB Register (Address = 07h) [reset = 0000h] The THRSHLD_MSB register is shown in Figure 8-33 and described in Table 8-21. Return to the Summary Table. Figure 8-33. THRSHLD_MSB Register 15 14 13 12 11 10 9 8 2 1 0 CD_TH_MSB[23:16] R/W-0000000000000000b 7 6 5 4 3 CD_TH_MSB[15:8] R/W-0000000000000000b Table 8-21. THRSHLD_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description CD_TH_MSB[23:8] R/W 00000000 00000000b Current-detect mode threshold register bits [23:8]. Value provided in two's complement format. 8.6.9 THRSHLD_LSB Register (Address = 08h) [reset = 0000h] The THRSHLD_LSB register is shown in Figure 8-34 and described in Table 8-22. Return to the Summary Table. Figure 8-34. THRSHLD_LSB Register 15 14 13 12 11 10 9 8 2 1 0 CD_TH_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED DCBLOCK[3:0] R-0000b R/W-0000b Table 8-22. THRSHLD_LSB Register Field Descriptions Bit Field Type Reset Description 15:8 CD_TH_LSB[7:0] R/W 00000000b Current-detect mode threshold register bits [7:0] Value provided in two's complement format 7:4 RESERVED R 0000b Reserved always reads 0000b 3:0 DCBLOCK[3:0] R/W 0000b DC Block filter setting See Table 8-4 for details Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 63 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.10 CH0_CFG Register (Address = 09h) [reset = 0000h] The CH0_CFG register is shown in Figure 8-35 and described in Table 8-23. Return to the Summary Table. Figure 8-35. CH0_CFG Register 15 14 13 12 11 10 9 2 1 8 PHASE0[9:2] R/W-0000000000b 7 6 5 4 3 0 PHASE0[1:0] RESERVED DCBLK0_DIS MUX0[1:0] R/W-0000000000b R-000b R/W-0b R/W-00b Table 8-23. CH0_CFG Register Field Descriptions Field Type Reset 15:6 Bit PHASE0[9:0] R/W 0000000000 Channel 0 phase delay b Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details. 5:3 RESERVED R 000b Reserved always reads 000b DCBLK0_DIS R/W 0b Channel 0 DC Block filter disable 2 Description 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel 1:0 MUX0[1:0] R/W 00b Channel 0 input selection 00b = AIN0P and AIN0N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal 64 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.11 CH0_OCAL_MSB Register (Address = 0Ah) [reset = 0000h] The CH0_OCAL_MSB register is shown in Figure 8-36 and described in Table 8-24. Return to the Summary Table. Figure 8-36. CH0_OCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL0_MSB[15:8] R/W-0000000000000000b 7 6 5 4 3 OCAL0_MSB[7:0] R/W-0000000000000000b Table 8-24. CH0_OCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description OCAL0_MSB[15:0] R/W 00000000 00000000b Channel 0 offset calibration register bits [23:8]. Value provided in two's complement format. 8.6.12 CH0_OCAL_LSB Register (Address = 0Bh) [reset = 0000h] The CH0_OCAL_LSB register is shown in Figure 8-37 and described in Table 8-25. Return to the Summary Table. Figure 8-37. CH0_OCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL0_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-25. CH0_OCAL_LSB Register Field Descriptions Bit Field Type Reset Description 15:8 OCAL0_LSB[7:0] R/W 00000000b Channel 0 offset calibration register bits [7:0]. Value provided in two's complement format. 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 65 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.13 CH0_GCAL_MSB Register (Address = 0Ch) [reset = 8000h] The CH0_GCAL_MSB register is shown in Figure 8-38 and described in Table 8-26. Return to the Summary Table. Figure 8-38. CH0_GCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL0_MSB[15:8] R/W-1000000000000000b 7 6 5 4 3 GCAL0_MSB[7:0] R/W-1000000000000000b Table 8-26. CH0_GCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset GCAL0_MSB R/W 1000000000 Channel 0 gain calibration register bits [23:8] 000000b Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 Description 8.6.14 CH0_GCAL_LSB Register (Address = 0Dh) [reset = 0000h] The CH0_GCAL_LSB register is shown in Figure 8-39 and described in Table 8-27. Return to the Summary Table. Figure 8-39. CH0_GCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL0_LSB R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-27. CH0_GCAL_LSB Register Field Descriptions Bit 66 Field Type Reset Description 15:8 GCAL0_LSB[7:0] R/W 00000000b Channel 0 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.15 CH1_CFG Register (Address = 0Eh) [reset = 0000h] The CH1_CFG register is shown in Figure 8-40 and described in Table 8-28. Return to the Summary Table. Figure 8-40. CH1_CFG Register 15 14 13 12 11 10 9 2 1 8 PHASE1[9:2] R/W-0000000000b 7 6 5 4 3 0 PHASE1[1:0] RESERVED DCBLK1_DIS MUX1 R/W-0000000000b R-000b R/W-0b R/W-00b Table 8-28. CH1_CFG Register Field Descriptions Field Type Reset 15:6 Bit PHASE1[9:0] R/W 0000000000 Channel 1 phase delay b Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details. 5:3 RESERVED R 000b Reserved always reads 000b DCBLK1_DIS R/W 0b Channel 1 DC Block filter disable 2 Description 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel 1:0 MUX1 R/W 00b Channel 1 input selection 00b = AIN1P and AIN1N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 67 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.16 CH1_OCAL_MSB Register (Address = 0Fh) [reset = 0000h] The CH1_OCAL_MSB register is shown in Figure 8-41 and described in Table 8-29. Return to the Summary Table. Figure 8-41. CH1_OCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL1_MSB[15:8] R/W-0000000000000000b 7 6 5 4 3 OCAL1_MSB[7:0] R/W-0000000000000000b Table 8-29. CH1_OCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description OCAL1_MSB[15:0] R/W 00000000 00000000b Channel 1 offset calibration register bits [23:8] Value provided in two's complement format 8.6.17 CH1_OCAL_LSB Register (Address = 10h) [reset = 0000h] The CH1_OCAL_LSB register is shown in Figure 8-42 and described in Table 8-30. Return to the Summary Table. Figure 8-42. CH1_OCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL1_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-30. CH1_OCAL_LSB Register Field Descriptions Bit 68 Field Type Reset Description 15:8 OCAL1_LSB[7:0] R/W 00000000b Channel 1 offset calibration register bits [7:0] Value provided in two's complement format 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.18 CH1_GCAL_MSB Register (Address = 11h) [reset = 8000h] The CH1_GCAL_MSB register is shown in Figure 8-43 and described in Table 8-31. Return to the Summary Table. Figure 8-43. CH1_GCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL1_MSB[15:8] R/W-1000000000000000b 7 6 5 4 3 GCAL1_MSB[7:0] R/W-1000000000000000b Table 8-31. CH1_GCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset GCAL1_MSB[15:0] R/W 1000000000 Channel 1 gain calibration register bits [23:8] 000000b Unsigned number for the gain range from 0.0 to 2.0·(224 – 1)/224 Description 8.6.19 CH1_GCAL_LSB Register (Address = 12h) [reset = 0000h] The CH1_GCAL_LSB register is shown in Figure 8-44 and described in Table 8-32. Return to the Summary Table. Figure 8-44. CH1_GCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL1_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-32. CH1_GCAL_LSB Register Field Descriptions Bit Field Type Reset Description 15:8 GCAL1_LSB[7:0] R/W 00000000b Channel 1 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 69 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.20 CH2_CFG Register (Address = 13h) [reset = 0000h] The CH2_CFG register is shown in Figure 8-45 and described in Table 8-33. Return to the Summary Table. Figure 8-45. CH2_CFG Register 15 14 13 12 11 10 9 2 1 8 PHASE2[9:2] R/W-0000000000b 7 6 5 4 3 0 PHASE2[1:0] RESERVED DCBLK2_DIS MUX2 R/W-0000000000b R-000b R/W-0b R/W-00b Table 8-33. CH2_CFG Register Field Descriptions Field Type Reset 15:6 Bit PHASE2[9:0] R/W 0000000000 Channel 2 phase delay b Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details. 5:3 RESERVED R 000b Reserved always reads 000b DCBLK2_DIS R/W 0b Channel 2 DC Block filter disable 2 Description 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel 1:0 MUX2 R/W 00b Channel 2 input selection 00b = AIN2P and AIN2N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal 70 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.21 CH2_OCAL_MSB Register (Address = 14h) [reset = 0000h] The CH2_OCAL_MSB register is shown in Figure 8-46 and described in Table 8-34. Return to the Summary Table. Figure 8-46. CH2_OCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL2_MSB[15:8] R/W-0000000000000000b 7 6 5 4 3 OCAL2_MSB[7:0] R/W-0000000000000000b Table 8-34. CH2_OCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description OCAL2_MSB[15:0] R/W 00000000 00000000b Channel 2 offset calibration register bits [23:8] Value provided in two's complement format 8.6.22 CH2_OCAL_LSB Register (Address = 15h) [reset = 0000h] The CH2_OCAL_LSB register is shown in Figure 8-47 and described in Table 8-35. Return to the Summary Table. Figure 8-47. CH2_OCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL2_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-35. CH2_OCAL_LSB Register Field Descriptions Bit Field Type Reset Description 15:8 OCAL2_LSB[7:0] R/W 00000000b Channel 2 offset calibration register bits [7:0] Value provided in two's complement format 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 71 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.23 CH2_GCAL_MSB Register (Address = 16h) [reset = 8000h] The CH2_GCAL_MSB register is shown in Figure 8-48 and described in Table 8-36. Return to the Summary Table. Figure 8-48. CH2_GCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL2_MSB[15:8] R/W-1000000000000000b 7 6 5 4 3 GCAL2_MSB[7:0] R/W-1000000000000000b Table 8-36. CH2_GCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset GCAL2_MSB[15:0] R/W 1000000000 Channel 2 gain calibration register bits [23:8] 000000b Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 Description 8.6.24 CH2_GCAL_LSB Register (Address = 17h) [reset = 0000h] The CH2_GCAL_LSB register is shown in Figure 8-49 and described in Table 8-37. Return to the Summary Table. Figure 8-49. CH2_GCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL2_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-37. CH2_GCAL_LSB Register Field Descriptions Bit 72 Field Type Reset Description 15:8 GCAL2_LSB[7:0] R/W 00000000b Channel 2 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.25 CH3_CFG Register (Address = 18h) [reset = 0000h] The CH3_CFG register is shown in Figure 8-50 and described in Table 8-38. Return to the Summary Table. Figure 8-50. CH3_CFG Register 15 14 13 12 11 10 9 2 1 8 PHASE3[9:2] R/W-0000000000b 7 6 5 4 3 0 PHASE3[1:0] RESERVED DCBLK3_DIS MUX3 R/W-0000000000b R-000b R/W-0b R/W-00b Table 8-38. CH3_CFG Register Field Descriptions Field Type Reset 15:6 Bit PHASE3[9:0] R/W 0000000000 Channel 3 phase delay b Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details. 5:3 RESERVED R 000b Reserved always reads 00000000b DCBLK3_DIS R/W 0b Channel 3 DC Block filter disable 2 Description 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel 1:0 MUX3 R/W 00b Channel 3 input selection 00b = AIN3P and AIN3N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 73 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.26 CH3_OCAL_MSB Register (Address = 19h) [reset = 0000h] The CH3_OCAL_MSB register is shown in Figure 8-51 and described in Table 8-39. Return to the Summary Table. Figure 8-51. CH3_OCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL3_MSB[15:8] R/W-0000000000000000b 7 6 5 4 3 OCAL3_MSB[7:0] R/W-0000000000000000b Table 8-39. CH3_OCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description OCAL3_MSB[15:0] R/W 00000000 00000000b Channel 3 offset calibration register bits [23:8] Value provided in two's complement format 8.6.27 CH3_OCAL_LSB Register (Address = 1Ah) [reset = 0000h] The CH3_OCAL_LSB register is shown in Figure 8-52 and described in Table 8-40. Return to the Summary Table. Figure 8-52. CH3_OCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL3_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-40. CH3_OCAL_LSB Register Field Descriptions Bit 74 Field Type Reset Description 15:8 OCAL3_LSB[7:0] R/W 00000000b Channel 3 offset calibration register bits [7:0] Value provided in two's complement format 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.28 CH3_GCAL_MSB Register (Address = 1Bh) [reset = 8000h] The CH3_GCAL_MSB register is shown in Figure 8-53 and described in Table 8-41. Return to the Summary Table. Figure 8-53. CH3_GCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL3_MSB[15:8] R/W-1000000000000000b 7 6 5 4 3 GCAL3_MSB[7:0] R/W-1000000000000000b Table 8-41. CH3_GCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset GCAL3_MSB[15:0] R/W 1000000000 Channel 3 gain calibration register bits [23:8] 000000b Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 Description 8.6.29 CH3_GCAL_LSB Register (Address = 1Ch) [reset = 0000h] The CH3_GCAL_LSB register is shown in Figure 8-54 and described in Table 8-42. Return to the Summary Table. Figure 8-54. CH3_GCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL3_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-42. CH3_GCAL_LSB Register Field Descriptions Bit Field Type Reset Description 15:8 GCAL3_LSB[7:0] R/W 00000000b Channel 3 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 75 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.30 CH4_CFG Register (Address = 1Dh) [reset = 0000h] The CH4_CFG register is shown in Figure 8-55 and described in Table 8-43. Return to the Summary Table. Figure 8-55. CH4_CFG Register 15 14 13 12 11 10 9 2 1 8 PHASE4[9:2] R/W-0000000000b 7 6 5 4 3 0 PHASE4[1:0] RESERVED DCBLK4_DIS MUX4 R/W-0000000000b R-000b R/W-0b R/W-00b Table 8-43. CH4_CFG Register Field Descriptions Field Type Reset 15:6 Bit PHASE4[9:0] R/W 0000000000 Channel 4 phase delay b Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details. 5:3 RESERVED R 000b Reserved always reads 000b DCBLK4_DIS R/W 0b Channel 4 DC Block filter disable 2 Description 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel 1:0 MUX4 R/W 00b Channel 4 input selection 00b = AIN4P and AIN4N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal 76 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.31 CH4_OCAL_MSB Register (Address = 1Eh) [reset = 0000h] The CH4_OCAL_MSB register is shown in Figure 8-56 and described in Table 8-44. Return to the Summary Table. Figure 8-56. CH4_OCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL4_MSB[15:8] R/W-0000000000000000b 7 6 5 4 3 OCAL4_MSB[7:0] R/W-0000000000000000b Table 8-44. CH4_OCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description OCAL4_MSB[15:0] R/W 00000000 00000000b Channel 4 offset calibration register bits [23:8] Value provided in two's complement format 8.6.32 CH4_OCAL_LSB Register (Address = 1Fh) [reset = 0000h] The CH4_OCAL_LSB register is shown in Figure 8-57 and described in Table 8-45. Return to the Summary Table. Figure 8-57. CH4_OCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL4_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-45. CH4_OCAL_LSB Register Field Descriptions Bit Field Type Reset Description 15:8 OCAL4_LSB[7:0] R/W 00000000b Channel 4 offset calibration register bits [7:0] Value provided in two's complement format 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 77 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.33 CH4_GCAL_MSB Register (Address = 20h) [reset = 8000h] The CH4_GCAL_MSB register is shown in Figure 8-58 and described in Table 8-46. Return to the Summary Table. Figure 8-58. CH4_GCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL4_MSB[15:8] R/W-1000000000000000b 7 6 5 4 3 GCAL4_MSB[7:0] R/W-1000000000000000b Table 8-46. CH4_GCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset GCAL4_MSB[15:0] R/W 1000000000 Channel 4 gain calibration register bits [23:8] 000000b Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 Description 8.6.34 CH4_GCAL_LSB Register (Address = 21h) [reset = 0000h] The CH4_GCAL_LSB register is shown in Figure 8-59 and described in Table 8-47. Return to the Summary Table. Figure 8-59. CH4_GCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL4_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-47. CH4_GCAL_LSB Register Field Descriptions Bit 78 Field Type Reset Description 15:8 GCAL4_LSB[7:0] R/W 00000000b Channel 4 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.35 CH5_CFG Register (Address = 22h) [reset = 0000h] The CH5_CFG register is shown in Figure 8-60 and described in Table 8-48. Return to the Summary Table. Figure 8-60. CH5_CFG Register 15 14 13 12 11 10 9 2 1 8 PHASE5[9:2] R/W-0000000000b 7 6 5 4 3 0 PHASE5[1:0] RESERVED DCBLK5_DIS MUX5 R/W-0000000000b R-000b R/W-0b R/W-00b Table 8-48. CH5_CFG Register Field Descriptions Field Type Reset 15:6 Bit PHASE5[9:0] R/W 0000000000 Channel 5 phase delay b Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details. 5:3 RESERVED R 000b Reserved always reads 000b DCBLK5_DIS R/W 0b Channel 5 DC Block filter disable 2 Description 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel 1:0 MUX5 R/W 00b Channel 5 put selection 00b = AIN5P and AIN5N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 79 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.36 CH5_OCAL_MSB Register (Address = 23h) [reset = 0000h] CH5_OCAL_MSB is shown in Figure 8-61 and described in Table 8-49. Return to the Summary Table. Figure 8-61. CH5_OCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL5_MSB[15:8] R/W-0000000000000000b 7 6 5 4 3 OCAL5_MSB[7:0] R/W-0000000000000000b Table 8-49. CH5_OCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description OCAL5_MSB[15:0] R/W 00000000 00000000b Channel 5 offset calibration register bits [23:8] Value provided in two's complement format 8.6.37 CH5_OCAL_LSB Register (Address = 24h) [reset = 0000h] The CH5_OCAL_LSB register is shown in Figure 8-62 and described in Table 8-50. Return to the Summary Table. Figure 8-62. CH5_OCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL5_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-50. CH5_OCAL_LSB Register Field Descriptions Bit 80 Field Type Reset Description 15:8 OCAL5_LSB[7:0] R/W 00000000b Channel 5 offset calibration register bits [7:0] Value provided in two's complement format 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.38 CH5_GCAL_MSB Register (Address = 25h) [reset = 8000h] The CH5_GCAL_MSB register is shown in Figure 8-63 and described in Table 8-51. Return to the Summary Table. Figure 8-63. CH5_GCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL5_MSB[15:8] R/W-1000000000000000b 7 6 5 4 3 GCAL5_MSB[7:0] R/W-1000000000000000b Table 8-51. CH5_GCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset GCAL5_MSB[15:0] R/W 1000000000 Channel 5 gain calibration register bits [23:8] 000000b Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 Description 8.6.39 CH5_GCAL_LSB Register (Address = 26h) [reset = 0000h] The CH5_GCAL_LSB register is shown in Figure 8-64 and described in Table 8-52. Return to the Summary Table. Figure 8-64. CH5_GCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL5_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-52. CH5_GCAL_LSB Register Field Descriptions Bit Field Type Reset Description 15:8 GCAL5_LSB[7:0] R/W 00000000b Channel 5 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 81 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.40 CH6_CFG Register (Address = 27h) [reset = 0000h] The CH6_CFG register is shown in Figure 8-65 and described in Table 8-53. Return to the Summary Table. Figure 8-65. CH6_CFG Register 15 14 13 12 11 10 9 2 1 8 PHASE6[9:2] R/W-0000000000b 7 6 5 4 3 0 PHASE6[1:0] RESERVED DCBLK6_DIS MUX6 R/W-0000000000b R-000b R/W-0b R/W-00b Table 8-53. CH6_CFG Register Field Descriptions Field Type Reset 15:6 Bit PHASE6[9:0] R/W 0000000000 Channel 6 phase delay b Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details. 5:3 RESERVED R 000b Reserved always reads 000b DCBLK6_DIS R/W 0b Channel 6 DC Block filter disable 2 Description 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel 1:0 MUX6 R/W 00b Channel 6 input selection 00b = AIN6P and AIN6N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal 82 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.41 CH6_OCAL_MSB Register (Address = 28h) [reset = 0000h] The CH6_OCAL_MSB register is shown in Figure 8-66 and described in Table 8-54. Return to the Summary Table. Figure 8-66. CH6_OCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL6_MSB[15:8] R/W-0000000000000000b 7 6 5 4 3 OCAL6_MSB[7:0] R/W-0000000000000000b Table 8-54. CH6_OCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description OCAL6_MSB[15:0] R/W 00000000 00000000b Channel 6 offset calibration register bits [23:8] Value provided in two's complement format 8.6.42 CH6_OCAL_LSB Register (Address = 29h) [reset = 0000h] The CH6_OCAL_LSB register is shown in Figure 8-67 and described in Table 8-55. Return to the Summary Table. Figure 8-67. CH6_OCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL6_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-55. CH6_OCAL_LSB Register Field Descriptions Bit Field Type Reset Description 15:8 OCAL6_LSB[7:0] R/W 00000000b Channel 6 offset calibration register bits [7:0] Value provided in two's complement format 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 83 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.43 CH6_GCAL_MSB Register (Address = 2Ah) [reset = 8000h] The CH6_GCAL_MSB register is shown in Figure 8-68 and described in Table 8-56. Return to the Summary Table. Figure 8-68. CH6_GCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL6_MSB[15:8] R/W-1000000000000000b 7 6 5 4 3 GCAL6_MSB[7:0] R/W-1000000000000000b Table 8-56. CH6_GCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset GCAL6_MSB[15:0] R/W 1000000000 Channel 6 gain calibration register bits [23:8] 000000b Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 Description 8.6.44 CH6_GCAL_LSB Register (Address = 2Bh) [reset = 0000h] The CH6_GCAL_LSB register is shown in Figure 8-69 and described in Table 8-57. Return to the Summary Table. Figure 8-69. CH6_GCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL6_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-57. CH6_GCAL_LSB Register Field Descriptions Bit 84 Field Type Reset Description 15:8 GCAL6_LSB[7:0] R/W 00000000b Channel 6 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.45 CH7_CFG Register (Address = 2Ch) [reset = 0000h] The CH7_CFG register is shown in Figure 8-70 and described in Table 8-58. Return to the Summary Table. Figure 8-70. CH7_CFG Register 15 14 13 12 11 10 9 2 1 8 PHASE7[9:2] R/W-0000000000b 7 6 5 4 3 0 PHASE7[1:0] RESERVED DCBLK7_DIS MUX7 R/W-0000000000b R-000b R/W-0b R/W-00b Table 8-58. CH7_CFG Register Field Descriptions Field Type Reset 15:6 Bit PHASE7[9:0] R/W 0000000000 Channel 7 phase delay b Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details. 5:3 RESERVED R 000b Reserved always reads 000b DCBLK7_DIS R/W 0b Channel 7 DC Block filter disable 2 Description 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel 1:0 MUX7 R/W 00b Channel 7 input selection 00b = AIN7P and AIN7N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 85 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.46 CH7_OCAL_MSB Register (Address = 2Dh) [reset = 0000h] The CH7_OCAL_MSB register is shown in Figure 8-71 and described in Table 8-59. Return to the Summary Table. Figure 8-71. CH7_OCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL7_MSB[15:8] R/W-0000000000000000b 7 6 5 4 3 OCAL7_MSB[7:0] R/W-0000000000000000b Table 8-59. CH7_OCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description OCAL7_MSB[15:0] R/W 00000000 00000000b Channel 7 offset calibration register bits [23:8] Value provided in two's complement format 8.6.47 CH7_OCAL_LSB Register (Address = 2Eh) [reset = 0000h] The CH7_OCAL_LSB register is shown in Figure 8-72 and described in Table 8-60. Return to the Summary Table. Figure 8-72. CH7_OCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 OCAL7_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-60. CH7_OCAL_LSB Register Field Descriptions Bit 86 Field Type Reset Description 15:8 OCAL7_LSB[7:0] R/W 00000000b Channel 7 offset calibration register bits [7:0] Value provided in two's complement format 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.48 CH7_GCAL_MSB Register (Address = 2Fh) [reset = 8000h] The CH7_GCAL_MSB register is shown in Figure 8-73 and described in Table 8-61. Return to the Summary Table. Figure 8-73. CH7_GCAL_MSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL7_MSB[15:8] R/W-1000000000000000b 7 6 5 4 3 GCAL7_MSB[7:0] R/W-1000000000000000b Table 8-61. CH7_GCAL_MSB Register Field Descriptions Bit 15:0 Field Type Reset Description GCAL7_MSB[15:0] R/W 10000000 00000000b Channel 7 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 8.6.49 CH7_GCAL_LSB Register (Address = 30h) [reset = 0000h] The CH7_GCAL_LSB register is shown in Figure 8-74 and described in Table 8-62. Return to the Summary Table. Figure 8-74. CH7_GCAL_LSB Register 15 14 13 12 11 10 9 8 2 1 0 GCAL7_LSB[7:0] R/W-00000000b 7 6 5 4 3 RESERVED R-00000000b Table 8-62. CH7_GCAL_LSB Register Field Descriptions Bit Field Type Reset Description 15:8 GCAL7_LSB[7:0] R/W 00000000b Channel 7 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(224 – 1) / 224 7:0 RESERVED R 00000000b Reserved always reads 00000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 87 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 8.6.50 REGMAP_CRC Register (Address = 3Eh) [reset = 0000h] The REGMAP_CRC register is shown in Figure 8-75 and described in Table 8-63. Return to the Summary Table. Figure 8-75. REGMAP_CRC Register 15 14 13 12 11 10 9 8 2 1 0 10 9 8 2 1 0 REG_CRC[15:8] R-0000000000000000b 7 6 5 4 3 REG_CRC[7:0] R-0000000000000000b Table 8-63. REGMAP_CRC Register Field Descriptions Bit 15:0 Field Type Reset Description REG_CRC[15:0] R 00000000 00000000b Register map CRC value 8.6.51 RESERVED Register (Address = 3Fh) [reset = 0000h] The RESERVED register is shown in Figure 8-76 and described in Table 8-64. Return to the Summary Table. Figure 8-76. RESERVED Register 15 14 13 12 11 RESERVED R/W-0000000000000000b 7 6 5 4 3 RESERVED R/W-0000000000000000b Table 8-64. RESERVED Register Field Descriptions Bit 15:0 88 Field Type Reset Description RESERVED R/W 00000000 00000000b Reserved Always write 0000000000000000b Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Unused Inputs and Outputs Leave any unused analog inputs floating or connect them to AGND. Do not float unused digital inputs because excessive power-supply leakage current can result. Tie all unused digital inputs to the appropriate levels, DVDD or DGND. Leave the DRDY pin unconnected or connect it to DVDD using a weak pullup resistor if unused. 9.1.2 Antialiasing An analog low-pass filter is required in front of each of the channel inputs to prevent out-of-band noise and interferers from coupling into the band of interest. Because the ADS131M08 is a delta-sigma ADC, the integrated digital filter provides substantial attenuation for frequencies outside of the band of interest up to the frequencies adjacent to fMOD. Therefore, a single-order RC filter provides sufficient antialiasing protection in the vast majority of applications. Choosing the values of the resistor and capacitor depends on the desired cutoff frequency, limiting source impedance for the ADC inputs, and providing enough instantaneous charge to the ADC input sampling circuit through the filter capacitor. Figure 9-1 shows the recommended filter component values. These recommendations are sufficient for CLKIN frequencies between 2 MHz and 8.2 MHz. 1k 10 nF To ADC Inputs 1k Figure 9-1. Recommended Antialiasing Circuitry Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 89 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 9.1.3 Minimum Interface Connections Figure 9-2 depicts how the ADS131M08 can be configured for the minimum number of interface pins. This configuration is useful when using data isolation to minimize the number of isolation channels required or when the microcontroller (MCU) pins are limited. The CLKIN pin requires an LVCMOS clock that can be either generated by the MCU or created using a local LVCMOS output device. Tie the SYNC/RESET pin to DVDD in hardware if unused. The DRDY pin can be left floating if unused. Connect either SYNC/RESET or DRDY to the MCU to ensure the MCU stays synchronized to ADC conversions. If the MCU provides CLKIN, the CLKIN periods can be counted to determine the sample period rather than forcing synchronization using the SYNC/RESET pin or monitoring the DRDY pin. Synchronization cannot be regained if a bit error occurs on the clock and samples can be missed if the SYNC/ RESET or DRDY pins are not used. CS can be tied low in hardware if the ADS131M08 is the only device on the SPI bus. Ensure the data input and output CRC are enabled and are used to guard against faulty register reads and writes if CS is tied low permanently. See the Clocking and Power Modes section for more information regarding synchronization and how to implement the clocking scheme for optimized device performance. Local Oscillator DVDD OR CLKIN CLKOUT SYNC/RESET GPIO OR DRDY Device GPIO CS CS MCU OR SCLK SCLK DIN MOSI DOUT MISO DGND Figure 9-2. Minimum Connections Required to Operate the ADS131M08 90 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 9.1.4 Power Metrology Applications Each channel of the ADS131M08 is identical, giving designers the flexibility to sense voltage or current with any channel. Simultaneous sampling allows the application to calculate instantaneous power for any simultaneous voltage and current measurement. This section provides a diagram depicting the common energy metrology configuration that can be used with the ADS131M08. A Rogowski coil can alternatively be used to sense current in the following example wherever a CT is used. The integration to determine the current flowing through the Rogowski coil is done digitally if that modification is made. RC antialiasing filters are not shown in the following diagrams for simplicity, but are recommended for all channels. Figure 9-3 illustrates a three-phase configuration where live and neutral currents are monitored using CTs, the phase voltages are measured using a voltage divider, and the final channel is used for an auxiliary measurement. This auxiliary measurement can be temperature if connected to an external thermistor or other voltage output temperature sensor. Otherwise, this measurement can sense any other signal that requires monitoring on the board. Load VDD AVDD AIN0N AIN0P AIN1P AIN1N AIN2N AIN2P AIN3P AIN3N AIN4N ADS131M08 AIN4P AIN5P AIN5N AIN6N AIN6P AIN7P Aux AIN7N AGND A N B C Figure 9-3. Three-Phase Current and Voltage Measurement Front-End With a Neutral Current Monitor Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 91 ADS131M08 www.ti.com SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 9.1.5 Multiple Device Configuration Multiple ADS131M08 devices can be arranged to capture all signals simultaneously. The same clock must be provided to all devices and the SYNC/RESET pins must be strobed simultaneously at least one time to align the sample periods internally between devices. The phase settings of each device can be changed uniquely, but the host must take care to record which channel in the group of devices represents the zero phase. The devices can also share the SPI bus where only the CS pins for each device are unique. Each device can be addressed sequentially by asserting CS for the device that the host wishes to communicate with. The DOUT pin remains high impedance when the CS pin is high, allowing the DOUT lines to be shared between devices as long as no two devices sharing the bus simultaneously have their CS pins low. Figure 9-4 shows multiple devices configured for simultaneous data acquisition while sharing the SPI bus. Monitoring the DRDY output of only one of the devices is sufficient because all devices convert simultaneously. Device 1 SYNC/RESET GPIO CLKIN CLKOUT DRDY IRQ SCLK SCLK DIN MOSI DOUT MISO CS MCU CS1 CS2 ... CSn Device 2 SYNC/RESET CLKIN DRDY SCLK DIN DOUT CS Device n SYNC/RESET CLKIN DRDY SCLK DIN DOUT CS Figure 9-4. Multiple Device Configuration 92 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS131M08 www.ti.com ADS131M08 SBAS950B – OCTOBER 2019 – REVISED FEBRUARY 2021 9.1.6 Code Example This section contains example pseudocode for a simple program that configures and streams data from the ADS131M08. The pseudocode is written to resemble C code. The code uses several descriptive precompilerdefined constants that are indicated in upper case. The definitions are not included for brevity. The program works in three sections: MCU initialization, ADC configuration, and data streaming. This code is not optimized for using the fast startup feature of the ADS131M08. The MCU is initialized by enabling the necessary peripherals for this example. These peripherals include an SPI port, a GPIO configured as an input for the ADS131M08 DRDY output, a clock output to connect to the ADS131M08 CLKIN input, and a direct memory access (DMA) module that streams data from the SPI port into memory without significant processor intervention. The SPI port is configured to a 24-bit word size because the ADC default SPI word size is 24 bits. The CS pin is configured to remain low as long as the SPI port is busy so that it does not de-assert in the middle of a frame. The ADC is configured through register writes. A function referred to as adcRegisterWrite writes an ADC register using the SPI peripheral. No CRC data integrity is used in this example for simplicity, but is recommended. The ADC outputs are initially disabled so short frames can be written during initialization consistent with the guidance provided in the Short SPI Frames section. The ADC is configured to output DRDY as pulses, the gain is changed to 32 for channels 1 and 3, and the DC block filter is used with a corner frequency of 622 mHz. Finally, the ADC word size is changed to 32 bits with an MSB sign extension to accommodate the MCU memory length and to allow for 32-bit DMA transfers. All other settings are left as defaults. Data streaming is performed by using an interrupt that is configured to trigger on a negative edge received on the GPIO connected to the DRDY pin. The interrupt service routine, referred to as DRDYinterrupt, sends six 32bit dummy words to assert CS and to toggle SCLK for the length of the entire ADC output frame. The ADC output frame consists of one 32-bit status word, four 32-bit ADC conversion data words, and an optional 32-bit CRC word. The frame is long enough for output CRC even though the CRC word is disabled in this example. The DMA module is configured to trigger upon receiving data on the SPI input. The DMA automatically sends the ADC data to a predetermined memory location as soon as the data are shifted into the MCU through the SPI input. numFrameWords = 10; // Number of words in a full ADS131M08 SPI frame unsigned long spiDummyWord[numFrameWords] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}; // Dummy word frame to write ADC during ADC data reads bool firstRead = true; // Flag to tell us if we are reading ADC data for the// first time signed long adcData; // Location where DMA will store ADC data in memory, // length defined elsewhere/* Interrupt the MCU each time DRDY asserts when collecting data */ DRDYinterupt(){ if(firstRead){ // Clear the ADC's 2-deep FIFO on the first read for(i=0; i