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ADS131A02, ADS131A04
SBAS590E – MARCH 2016 – REVISED JUNE 2020
ADS131A0x 2- or 4-Channel, 24-Bit, 128-kSPS, Simultaneous-Sampling, Delta-Sigma ADC
1 Features
3 Description
•
•
•
The ADS131A02 and ADS131A04 devices are twoand four-channel, simultaneous-sampling, 24-bit,
delta-sigma (ΔΣ), analog-to-digital converters (ADCs).
The wide dynamic range, with scalable data rates up
to 128 kSPS, and internal fault monitors make the
ADS131A02 or ADS131A04 a good choice when
designing for energy monitoring, grid protection, and
control applications. The ADC inputs can be
independently and directly interfaced to a resistordivider network, a current transformer, or a Rogowski
coil to measure voltage or current. Flexible powersupply options, including an internal negative charge
pump, are available to maximize the effective
resolution for high dynamic range applications.
1
•
•
•
•
•
•
•
•
•
2 or 4 simultaneous-sampling differential inputs
Data rates up to 128 kSPS
High performance:
– Single-channel accuracy: better than 0.1% at
10,000:1 dynamic range
– Effective resolution: 20.6 bits at 8 kSPS
– THD: –100 dB at 50 Hz and 60 Hz
Integrated negative charge pump allows absolute
input voltages below ground
Flexible analog power-supply operation:
– Using negative charge pump: 3.0 V to 3.45 V
– Unipolar supply: 3.3 V to 5.5 V
– Bipolar supply: ±2.5 V
Digital supply: 1.65 V to 3.6 V
Low-drift internal voltage reference: 6 ppm/°C
ADC self checks
Cyclic redundancy check (CRC) and hamming
code error correction on communications
Multiple SPI data interface modes:
– Asynchronous interrupt
– Synchronous master and slave
Package: 32-pin TQFP
Operating temperature range:
–40°C to +125°C
2 Applications
•
•
•
•
•
Asynchronous and synchronous master and slave
interface options are available, providing ADC
configuration flexibility when chaining multiple devices
in a single system. Several interface checks, ADC
startup checks, and data integrity checks can be
enabled on the interface to report errors in the ADC
and during data transfer.
The complete analog front-end (AFE) solutions are
packaged in a 32-pin TQFP package and are
specified over the industrial temperature range of
–40°C to +125°C.
Device Information(1)
PART NUMBER
ADS131A0x
PACKAGE
TQFP (32)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Electricity meters: commercial and residential
Circuit breakers
Battery test equipment
Battery management systems
Data acquisition systems
Simplified Block Diagram
AVDD
REFP
REFN
REFEXT
Reference
Mux
IOVDD
Voltage
Reference
Out-of-Range
Detect
M[2:0]
RESET
AIN1N
'6 ADC
AIN1P
Control and
Serial Interface
CS
SCLK
DIN
AIN2N
DOUT
'6 ADC
AIN2P
DRDY
Watchdog
Timer
DONE
ADS131A04 Only
AIN3N
'6 ADC
Data Integrity
AIN3P
AIN4N
'6 ADC
Negative
Charge
Pump
AIN4P
AVSS
VNCP
CLK/XTAL
XTAL1/CLKIN
XTAL2
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS131A02, ADS131A04
SBAS590E – MARCH 2016 – REVISED JUNE 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
6
6
8
7.1
7.2
7.3
7.4
7.5
7.6
Absolute Maximum Ratings ...................................... 8
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 9
Thermal Information .................................................. 9
Electrical Characteristics......................................... 10
Timing Requirements: Asynchronous Interrupt
Interface Mode ......................................................... 13
7.7 Switching Characteristics: Asynchronous Interrupt
Interface Mode ......................................................... 13
7.8 Timing Requirements: Synchronous Master Interface
Mode ........................................................................ 14
7.9 Switching Characteristics: Synchronous Master
Interface Mode ......................................................... 14
7.10 Timing Requirements: Synchronous Slave Interface
Mode ........................................................................ 15
7.11 Switching Characteristics: Synchronous Slave
Interface Mode ......................................................... 15
7.12 Typical Characteristics .......................................... 18
8
Parameter Measurement Information ................ 23
9
Detailed Description ............................................ 26
8.1 Noise Measurements .............................................. 23
9.1 Overview ................................................................. 26
9.2
9.3
9.4
9.5
9.6
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps ........................................................
26
27
37
38
59
10 Application and Implementation........................ 71
10.1
10.2
10.3
10.4
Application Information..........................................
Typical Application ................................................
What To Do and What Not To Do.........................
Initialization Set Up ..............................................
71
77
79
81
11 Power Supply Recommendations ..................... 83
11.1
11.2
11.3
11.4
Negative Charge Pump.........................................
Internal Digital LDO...............................................
Power-Supply Sequencing....................................
Power-Supply Decoupling.....................................
83
83
83
84
12 Layout................................................................... 85
12.1 Layout Guidelines ................................................. 85
12.2 Layout Example .................................................... 86
13 Device and Documentation Support ................. 87
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
87
87
87
87
87
87
87
14 Mechanical, Packaging, and Orderable
Information ........................................................... 87
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2018) to Revision E
Page
•
Changed Applications section ................................................................................................................................................ 1
•
Changed pin diagrams to orient pin names............................................................................................................................ 6
•
Changed NC and XTAL2 pin descriptions to match Unused Connections section ............................................................... 7
•
Deleted common-mode input voltage from Recommended Operating Conditions table ....................................................... 9
•
Added reference to Data Rate Settings table in Data Rate section ..................................................................................... 28
•
Changed Sinc3 Filter Settling figure and description in Digital Decimation Filter section to show ADC conversion
start and data availability ...................................................................................................................................................... 35
•
Changed Watchdog Timer section for clarity ....................................................................................................................... 36
•
Changed description of Low-Power and High-Resolution Mode and Power-Up sections for clarity.................................... 37
•
Changed RESET section for clarity ...................................................................................................................................... 37
•
Changed Device Word Length and Fixed versus Dynamic-Frame Mode sections for clarity .............................................. 38
•
Added description of 16- and 24-bit data word formats to Data Words section................................................................... 40
•
Added Communication Methods for Data Integrity Using Delta-Sigma Data Converters application report link to
Hamming Code section ........................................................................................................................................................ 42
•
Changed Cyclic Redundancy Check section........................................................................................................................ 43
•
Changed CRC with CRC_MODE = 1, CRC with CRC_MODE = 0, and CRC Using the WREGS Command figures to
clarify CRC modes................................................................................................................................................................ 44
2
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SBAS590E – MARCH 2016 – REVISED JUNE 2020
Revision History (continued)
•
Changed Asynchronous Interrupt Mode section .................................................................................................................. 46
•
Changed Synchronous Master Mode section....................................................................................................................... 48
•
Changed Synchronous Slave Mode section......................................................................................................................... 50
•
Added address location to description of RREG and 0000 0000 to device word in Command Definitions table ................ 52
•
Changed STANDBY: Enter Standby Mode section for clarity .............................................................................................. 54
•
Changed ADCx registers to ADC_ENA register in WAKEUP: Exit STANDBY Mode section ............................................. 55
•
Changed RREGS to RREG in RREG Command Status Response (Single Register Read) figure caption ........................ 56
•
Changed first command status response from 001a aaaa nnnn nnnn to 011a aaaa nnnn nnnn in RREGS: Read
Multiple Registers section..................................................................................................................................................... 56
•
Changed F_DRDY description in STAT_1: Status 1 Register section................................................................................. 61
•
Added All Devices Configured in Synchronous Slave Mode to include discussion of synchronization to a master clock... 76
•
Changed Bipolar Analog Power Supply to Unipolar Analog Power Supply with Negative Charge Pump Enabled
figures to correct power supply connections ........................................................................................................................ 84
Changes from Revision C (November 2016) to Revision D
Page
•
Changed document title from 2- or 4-Channel, 24-Bit, Simultaneously-Sampling, Delta-Sigma ADC to 2- or 4Channel, 24-Bit, 128-kSPS, Simultaneous-Sampling, Delta-Sigma ADC .............................................................................. 1
•
Changed VAVDD to AVDD, VAVSS to AVSS, VGND to GND, and VIOVDD to IOVDD throughout document ................................ 1
•
Changed Features section .................................................................................................................................................... 1
•
Changed Description section.................................................................................................................................................. 1
•
Deleted footnote 2 ................................................................................................................................................................. 7
•
Changed AVDD, AVSS, VNCP, and XTAL2 pin descriptions and footnote 1 for clarity ....................................................... 7
•
Changed CAP to GND Power supply voltage parameter specifications from GND – 0.3 V to 0.3 V for the minimum
specification and from GND + 2.0 V to 2.0 V for the maximum specification ........................................................................ 8
•
Changed Analog input voltage parameter descriptions from REFEXT to AVDD to REFEXT and from REFN input to
AVSS to REFN ....................................................................................................................................................................... 8
•
Changed Digital input voltage parameter description to include the names of the digital input pins ..................................... 8
•
Deleted CMRR footnote from Recommended Operating Conditions table ............................................................................ 9
•
Added symbol to Reference input voltage parameter ............................................................................................................ 9
•
Changed Offset drift parameter typical specification from 1.2 µV/°C to 2.5 µV/°C and maximum specification from 3
µV/°C to 4 µV/°C................................................................................................................................................................... 10
•
Changed Gain drift parameter typical specification from 0.25 ppm/°C to 0.5 ppm/°C ........................................................ 10
•
Deleted separate AVDD PSRR specification for the ADS131A02 ...................................................................................... 10
•
Changed Reference buffer offset parameter typical specification from 170 µV to 250 µV .................................................. 10
•
Changed Reference buffer offset drift parameter typical specification from 1.1 µV/°C to 4 µV/°C and maximum
specification from 4.3 µV/°C to 7 µV/°C ............................................................................................................................... 10
•
Changed Temperature drift parameter typical specification from 4 ppm/°C to 6 ppm/°C .................................................... 11
•
Deleted VNCP parameter minimum specification and changed typical specification from –1.95 V to –2 V........................ 11
•
Changed Electrical Characteristics table so all Power-Supply subsections are condensed to one Power-Supply
subsection............................................................................................................................................................................. 11
•
Changed free-air to ambient in condition statements of Timing Requirements tables......................................................... 13
•
Changed location of several interface timing parameters to the Timing Requirements and Switching Characteristics
tables from the Detailed Description section ....................................................................................................................... 13
•
Changed unit from ns to tCLKIN in tc(SC) and tw(SCHL) rows of Timing Requirements: Synchronous Master Interface
Mode table ............................................................................................................................................................................ 14
•
Added DRDY Synchronization Timing for Synchronous Slave Mode (CLKSRC = 0) to RESET Pin and Command
Timing figures ....................................................................................................................................................................... 17
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Product Folder Links: ADS131A02 ADS131A04
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3
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SBAS590E – MARCH 2016 – REVISED JUNE 2020
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•
Changed Clock section for clarification and changed setting of XTAL2 pin ........................................................................ 27
•
Changed Clock Mode Configurations figure to include load capacitors for clarity ............................................................... 28
•
Changed Analog Input section for clarity.............................................................................................................................. 29
•
Changed Equivalent Analog Input Circuitry figure................................................................................................................ 29
•
Changed Input Overrange and Underrange Detection section for clarity ............................................................................ 31
•
Changed location of Reference section .............................................................................................................................. 31
•
Changed External Reference Driver figure........................................................................................................................... 32
•
Changed Internal Reference figure ..................................................................................................................................... 32
•
Changed Digital Decimation Filter section for clarity............................................................................................................ 33
•
Deleted figure and table from Reset (RESET) section......................................................................................................... 37
•
Changed Fixed versus Dynamic-Frame Mode section for clarity......................................................................................... 38
•
Changed Data Ready (DRDY) section for clarity ................................................................................................................. 47
•
Changed pulldown to pullup in bulleted list of ADC Frame Complete (DONE) section ...................................................... 51
•
Changed description of UNLOCK from POR or RESET section.......................................................................................... 56
•
Changed description of RREG: Read a Single Register section ......................................................................................... 56
•
Changed number of registers written plus one (n+1) to number of registers written minus one in WREGS: Write
Multiple Registers section..................................................................................................................................................... 58
•
Changed User Register Description section for clarity......................................................................................................... 60
•
Changed Unused Inputs and Outputs section for clarity...................................................................................................... 71
•
Changed title of Multiple Device Configuration section and changed description for clarity ............................................... 72
•
Changed first paragraph of First Device Configured in Asynchronous Interrupt Mode to condense data from last
three paragraphs into one ................................................................................................................................................... 72
•
Changed description of First Device Configured in Synchronous Master Mode section to condense all paragraphs
into one ................................................................................................................................................................................. 74
•
Changed description of All Devices Configured in Synchronous Slave Mode section to condense all paragraphs into
one ....................................................................................................................................................................................... 76
•
Changed ADS131A0x Configuration Sequence figure......................................................................................................... 82
•
Changed GND to AVSS in VNCP pin description of Negative Charge Pump section ......................................................... 83
•
Changed title of Internal Digital LDO section ....................................................................................................................... 83
•
Changed description of Power-Supply Sequencing section................................................................................................. 83
•
Changed Bipolar Analog Power Supply to Unipolar Analog Power Supply with Negative Charge Pump Enabled figures . 84
•
Changed first sentence of Layout Example section ............................................................................................................. 86
•
Changed ADS131A0x Layout Example figure to improve layout ......................................................................................... 86
Changes from Revision B (September 2016) to Revision C
Page
•
Changed document title from Analog Front-Ends for Power Monitoring, Control, and Protection to SimultaneouslySampling, Delta-Sigma ADC .................................................................................................................................................. 1
•
Changed ENOB to Effective Resolution in second sub-bullet of Noise Performance Features bullet................................... 1
•
Changed effective number of bits to effective resolution in Description section ................................................................... 1
•
Changed format of Absolute Maximum Ratings table; specification values did not change.................................................. 8
•
Changed title of Multiple Device Effective Resolution Histogram figure .............................................................................. 18
•
Changed Noise Measurements section ............................................................................................................................... 23
Changes from Revision A (March 2016) to Revision B
Page
•
Released ADS131A02 to production...................................................................................................................................... 1
•
Changed AC Performance, PSRR, THD, and SFDR parameters in Electrical Characteristics table: added rows for
ADS131A02 and added ADS131A04 to rows specific to that device ................................................................................. 10
4
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SBAS590E – MARCH 2016 – REVISED JUNE 2020
•
Changed title of Figure 31 and Figure 32: added ADS131A04 ........................................................................................... 21
•
Added Figure 33 and Figure 34 ........................................................................................................................................... 22
•
Changed Noise Measurements section: changed Equation 1, Equation 2, Table 1, and Table 3 ...................................... 23
•
Added footnote to Figure 43 ................................................................................................................................................ 32
•
Changed R2 and R3 values in footnote of Figure 44 .......................................................................................................... 32
•
Changed Cyclic Redundancy Check (CRC) section ............................................................................................................ 41
•
Changed description of M2 pin functionality in Hamming Code Error Correction section ................................................... 41
•
Changed description of M0 pin functionality in SPI Interface section .................................................................................. 46
•
Changed first command status response value in RREGS: Read Multiple Registers section............................................. 56
•
Changed Table 15: changed register bits of row 00h, default setting and register bits of row 01h, and changed bits
2-0 of 11h, 12h, 13h, and 14h rows .................................................................................................................................... 59
•
Changed ID_MSB: ID Control Register MSB and ID_LSB: ID Control Register LSB registers ........................................... 60
•
Changed bits 2-0 of all ADCx: ADC Channel Digital Gain Configuration Registers ............................................................ 70
Changes from Original (March 2016) to Revision A
•
Page
Released ADS131A04 to production ..................................................................................................................................... 1
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SBAS590E – MARCH 2016 – REVISED JUNE 2020
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5 Device Comparison Table
PRODUCT
NO. OF ADC CHANNELS
MAXIMUM SAMPLE RATE (kSPS)
ADS131A02
2
128
ADS131A04
4
128
6 Pin Configuration and Functions
ADS131A02: PBS Package
32-Pin TQFP
Top View
M2
M1
M0
IOVDD
CAP
GND
XTAL2
XTAL1 / CLKIN
M2
M1
M0
IOVDD
CAP
GND
XTAL2
XTAL1 / CLKIN
ADS131A04: PBS Package
32-Pin TQFP
Top View
32
31
30
29
28
27
26
25
32
31
30
29
28
27
26
25
AIN1N
1
24
NC
AIN1N
1
24
NC
AIN1P
2
23
CS
AIN1P
2
23
CS
AIN2N
3
22
SCLK
AIN2N
3
22
SCLK
AIN2P
4
21
DOUT
AIN2P
4
21
DOUT
ADS131A02
ADS131A04
NC
7
18
DONE
AIN4N
7
18
DONE
NC
8
17
RESET
AIN4P
8
17
RESET
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
RESV
DRDY
IOVDD
19
REFEXT
6
REFN
AIN3P
REFP
DRDY
VNCP
19
AVSS
6
AVDD
NC
RESV
DIN
IOVDD
20
REFEXT
5
REFN
AIN3N
REFP
DIN
VNCP
20
AVSS
5
AVDD
NC
Pin Functions
PIN
NAME
NO.
DESCRIPTION (1)
I/O
ADS131A02
ADS131A04
AIN1N
1
1
Analog input
Negative analog input 1
AIN1P
2
2
Analog input
Positive analog input 1
AIN2N
3
3
Analog input
Negative analog input 2
AIN2P
4
4
Analog input
Positive analog input 2
AIN3N
—
5
Analog input
Negative analog input 3
AIN3P
—
6
Analog input
Positive analog input 3
AIN4N
—
7
Analog input
Negative analog input 4
AIN4P
—
8
Analog input
Positive analog input 4
AVDD
9
9
Supply
Positive analog power supply. Connect a 1-µF capacitor to AVSS.
AVSS
10
10
Supply
Negative analog power supply
CAP
28
28
Analog output
CS
23
23
Digital input
(1)
6
Digital low-dropout (LDO) regulator output. Connect a 1-µF
capacitor to GND.
Chip select; active low
See the Unused Inputs and Outputs section for unused pin connections.
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Pin Functions (continued)
PIN
NAME
NO.
DESCRIPTION (1)
I/O
ADS131A02
ADS131A04
DIN
20
20
Digital input
DONE
18
18
Digital output
Communication done signal; active low
DOUT
21
21
Digital output
Serial data output. Connect a 100-kΩ pullup resistor to IOVDD.
Serial data input
DRDY
19
19
Digital
input/output
GND
27
27
Supply
Digital ground
15
15
29
29
Supply
Digital I/O supply voltage. Connect a 1-µF capacitor to GND.
IOVDD
Data ready; active low; host interrupt and synchronization for multidevices
M0 (2)
30
30
Digital input
Serial peripheral interface (SPI) configuration mode.
IOVDD: Asynchronous interrupt mode
GND: Synchronous master mode
No connection: Synchronous slave mode; use for multi-device
mode
M1 (2)
31
31
Digital input
SPI word transfer size.
IOVDD: 32 bit
GND: 24 bit
No connection: 16 bit
M2 (2)
32
32
Digital input
Hamming code enable.
IOVDD: Hamming code word validation on
GND: Hamming code word validation off
No connection: reserved; do not use
NC
5-8
—
—
Leave floating or connect directly to AVSS.
NC
24
24
Digital output
Leave floating or tie to GND through a 10-kΩ pulldown resistor.
REFEXT
14
14
Analog input
Buffered external reference voltage input.
Connect a 1-µF capacitor to AVSS when using the internal
reference.
REFN
13
13
Analog input
Negative reference voltage. Connect to AVSS.
REFP
12
12
Analog output
Positive reference voltage output. Connect a 1-µF capacitor to
REFN.
RESET
17
17
Digital input
System reset; active low
RESV
16
16
Digital input
Reserved pin; connect to IOVDD
SCLK
22
22
Digital
input/output
Serial data clock
VNCP
11
11
Analog output
XTAL1/CLKIN
25
25
Digital input
XTAL2
26
26
Digital output
(2)
Negative charge pump voltage output.
Connect a 270-nF capacitor to AVSS when enabling the negative
charge pump. Connect directly to AVSS if the negative charge
pump is unused.
Master clock input, crystal oscillator buffer input
Crystal oscillator connection. Leave this pin floating if the crystal
oscillator is unused.
Mode signal states are latched following a power-on-reset (POR). Tie these pins high or low with a resistance less than 1-kΩ resistor.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
Power supply voltage
Analog input voltage
MIN
MAX
AVDD to AVSS (charge pump enabled)
–0.3
3.6
AVDD to AVSS (charge pump disabled)
–0.3
6.0
IOVDD to GND
–0.3
3.9
AVSS to GND
–3.0
0.3
VNCP to AVSS
–2.5
0.3
VNCP to AVDD
–6.0
0.3
CAP to GND
–0.3
2.0
Analog input voltage (charge pump enabled)
AVSS – 1.65
AVDD + 0.3
Analog input voltage (charge pump disabled)
AVSS – 0.3
AVDD + 0.3
REFEXT
AVSS – 0.3
AVDD + 0.3
REFN
AVSS – 0.05
AVSS + 0.05
GND – 0.3
IOVDD + 0.3
V
–10
10
mA
Digital input voltage
CS, DIN, DRDY, RESET, SCLK, XTAL1/CLKIN,
M0, M1, M2, RESV
Input current
Continuous, any pin except supply pins
Temperature
(1)
Junction, TJ
Storage, Tstg
UNIT
V
V
150
–60
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
8
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD to AVSS
3.0
3.3
3.45
AVDD to GND
3.0
3.3
3.45
AVSS to GND
–0.05
0
0.05
IOVDD to GND
1.65
3.3
3.6
AVDD to AVSS
3.0
5.0
5.5
AVDD to GND
1.5
2.5
5.5
AVSS to GND
–2.75
–2.5
0.05
IOVDD to GND
1.65
3.3
3.6
V
POWER SUPPLY
Negative Charge Pump Enabled (VNCPEN (1) = 1)
Analog supply voltage
Digital supply voltage (2)
V
V
Negative Charge Pump Disabled (VNCPEN = 0)
Analog supply voltage
Digital supply voltage (2)
V
ANALOG INPUTS
VIN
Differential input voltage
VAINxP, VAINxN
VIN = VAINxP – VAINxN
Absolute input voltage
–VREF / Gain
VREF / Gain
V
VNCPEN = 0
AVSS
AVDD
V
VNCPEN = 1
AVSS – 1.5
AVDD
V
AVDD – 0.5
V
EXTERNAL REFERENCE
VREF
Reference input voltage
VREFN
Reference negative input
REFEXT – REFN
VREFEXT
External reference positive input
2.0
2.5
AVSS
V
VREFN + 2.0
VREFN + 2.5
AVDD – 0.5
IOVDD > 2.7 V
0.4
16.384
25
IOVDD ≤ 2.7 V
0.4
8.192
15.6
16.384
16.5
V
EXTERNAL CLOCK SOURCE
fCLKIN
External clock input frequency
XTAL clock frequency
fSCLK
(3)
SCLK input to derive fMOD
CLKSRC bit = 1, fSCLK = fICLK,
IOVDD > 2.7 V
0.2
16.384
25
CLKSRC bit = 1, fSCLK = fICLK,
IOVDD ≤ 2.7 V
0.2
8.192
15.6
MHz
MHz
MHz
DIGITAL INPUTS
Digital input voltage
GND
IOVDD
V
–40
125
°C
TEMPERATURE
TA
(1)
(2)
(3)
Operating ambient temperature
VNCPEN is bit 7 of the A_SYS_CFG register.
Tie IOVDD to the CAP pin if IOVDD ≤ 2.0 V.
Set IOVDD > 3.0 V to use a crystal across the XTAL1/CLKIN and XTAL2 pins.
7.4 Thermal Information
ADS131A0x
THERMAL METRIC (1)
PBS (TQFP)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
77.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
19.0
°C/W
RθJB
Junction-to-board thermal resistance
30.2
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
30.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C; all
specifications are at IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF =
2.442 V, fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, and gain = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Cs
Input capacitance
Zin
Differential input impedance
fMOD = 4.096 MHz
3.5
pF
130
kΩ
24
Bits
ADC PERFORMANCE
Resolution
Gain
Data rate
1, 2, 4, 8, 16
fMOD = 4.096 MHz
1
128
kSPS
DC PERFORMANCE
105
Dynamic range
AVDD – AVSS = 5 V, VREF = 4 V, VNCPEN bit = 0
Integral nonlinearity
dB
115
See Noise Measurements
section
All other settings
INL
111
Best fit
8
Offset error
500
Offset drift
2.5
Gain error
Excluding voltage reference and reference buffer error
±0.03
Gain drift
Excluding voltage reference and reference buffer error
0.5
fCM = 50 Hz or 60 Hz
100
20
ppm
4
µV/°C
µV
% of FS
2
ppm/°C
AC PERFORMANCE
CMRR
PSRR
Common-mode rejection ratio
Power-supply rejection ratio
Crosstalk
SNR
THD
SINAD
SFDR
Signal-to-noise ratio
AVDD supply, fPS = 50 Hz and 60 Hz
80
IOVDD supply, fPS = 50 Hz and 60 Hz
105
fIN = 50 Hz and 60 Hz
111
fIN = 50 Hz or 60 Hz, VREF = 4.0 V, VIN = –20 dBFS,
normalized
115
fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS,
ADS131A04
–103.5
fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS
101
fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS,
ADS131A02
102.5
fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS,
ADS131A04
105
Reference buffer offset
TA = 25°C
250
Reference buffer offset drift
–40°C ≤ TA ≤ +125°C
Spurious-free dynamic range
dB
dB
–101.5
Signal-to-noise + distortion
dB
–125
fIN = 50 Hz or 60 Hz, VREF = 2.442 V, VIN = –20 dBFS,
normalized
fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS,
ADS131A02
Total harmonic distortion
dB
dB
dB
dB
EXTERNAL REFERENCE
4
REFEXT input impedance
10
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50
µV
7
µV/°C
MΩ
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SBAS590E – MARCH 2016 – REVISED JUNE 2020
Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C; all
specifications are at IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF =
2.442 V, fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, and gain = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE VOLTAGE (REFP – REFN)
VREF
Reference output voltage
VREF_4V bit = 0
2.442
VREF_4V bit = 1, AVDD – AVSS > 4.5 V
Accuracy
Temperature drift
±0.1%
Including reference buffer drift, –40°C ≤ TA ≤ +125°C
6
REFEXT = 1-µF to AVSS, settled to 1%
Start-up time
V
4.0
20
ppm/°C
0.2
REFEXT = 1-µF to AVSS, settled to 0.1%
1.2
REFEXT = 1-µF to AVSS, settled to 0.01%
250
REFP source capability
ms
100
µA
EXTERNAL CLOCK SOURCE
fICLK
Internal ICLK frequency (SCLK output
in master mode)
CLKSRC bit = 0
High-resolution mode
fMOD
ADC modulator frequency
Low-power mode
0.2
8.192
12.5
VNCPEN bit = 0
0.1
4.096
4.25
VNCPEN bit = 1
0.512
4.096
4.25
VNCPEN bit = 0
0.1
1.024
1.05
VNCPEN bit = 1
0.512
1.024
1.05
MHz
MHz
DIGITAL INPUT/OUTPUT
VIH
High-level input voltage
VIL
Low-level input voltage
0.8 IOVDD
VOH
High-level output voltage
IOH = 1 mA
VOL
Low-level output voltage
IOL = –1 mA
IIN
Input current
0 V < VDigital Input < IOVDD
GND
IOVDD
V
0.2 IOVDD
V
0.8 IOVDD
V
–10
0.2 IOVDD
V
10
μA
–1.65
V
POWER-SUPPLY
VNCP
Negative charge pump output voltage
–2
ADS131A02, high-resolution
mode
AVDD current
ADS131A04, high-resolution
mode
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
Negative charge pump
disabled
3
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
4
Negative charge pump
disabled
4
ADS131A02, low-power mode
IOVDD current
ADS131A04, high-resolution
mode
3.75
mA
4.7
0.9
ADS131A04, low-power mode
ADS131A02, high-resolution
mode
3.2
1.1
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
0.6
Negative charge pump
disabled
0.6
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
0.8
Negative charge pump
disabled
0.8
ADS131A02, low-power mode
0.5
ADS131A04, low-power mode
0.5
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0.8
mA
1.0
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Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C; all
specifications are at IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF =
2.442 V, fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, and gain = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADS131A02, high-resolution
mode
ADS131A04, high-resolution
mode
Power dissipation
ADS131A02, low-power
mode
ADS131A04, low-power
mode
MIN
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
Negative charge pump
disabled
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MAX
UNIT
12.5
17
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
15.8
Negative charge pump
disabled
22.7
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
4.6
Negative charge pump
disabled
6.5
AVDD = 3.3 V, AVSS = 0 V,
negative charge pump
enabled
5.3
Negative charge pump
disabled
7.2
Standby mode, fCLKIN = 16.384 MHz
12
TYP
21
26.8
mW
2.6
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7.6 Timing Requirements: Asynchronous Interrupt Interface Mode
over operating ambient temperature range (unless otherwise noted)
1.65 V ≤ IOVDD ≤ 2.7 V
MIN
2.7 V < IOVDD ≤ 3.6 V
MAX
MIN
MAX
UNIT
Single device
64
40
Multiple device chaining
88
56
Single device
32
20
Multiple device chaining
44
28
16
16
ns
5
4
ns
Single device
64
40
Multiple device chaining
88
64
Single device
32
20
Multiple device chaining
44
32
tc(CLKIN)
External clock period
ns
tw(CP)
Pulse duration,
CLKIN high or low
td(CSSC)
Delay time, CS falling edge to first SCLK rising edge
td(SCS)
Delay time, SCLK falling edge to CS falling edge
tc(SC)
SCLK period
tw(SCHL)
Pulse duration,
SCLK high or low
td(SCCS)
Delay time, final SCLK falling edge to CS rising edge
5
5
ns
tsu(DI)
Setup time, DIN valid before SCLK falling edge
5
5
ns
th(DI)
Hold time, DIN valid after SCLK falling edge
8
8
ns
tw(CSH)
Pulse duration, CS high
20
15
ns
tw(RSL)
Pulse duration, RESET low
800
800
ns
ns
ns
ns
7.7 Switching Characteristics: Asynchronous Interrupt Interface Mode
over operating ambient temperature range (unless otherwise noted)
1.65 V ≤ IOVDD ≤ 2.7 V
MIN
MAX
2.7 V < IOVDD ≤ 3.6 V
MIN
MAX
UNIT
tp(SCDOD)
Propagation delay time,
first SCLK rising edge to DOUT driven
28
15
ns
tp(SCDO)
Propagation delay time,
SCLK rising edge to valid new DOUT
26
15
ns
HIZDLY = 00
th(LSB)
tp(DN)
6
30
HIZDLY = 01
8
HIZDLY = 10
10
HIZDLY = 11
DNDLY = 00
DNDLY = 01
Propagation delay time, SCLK
falling edge to DONE falling edge DNDLY = 10
DNDLY = 11
12
Hold time, last SCLK falling edge
to DOUT 3-state
6
20
37
8
27
43
10
43
12
47
12
47
6
33
6
21
8
39
8
27
10
44
10
32
48
12
36
ns
ns
tp(CSDN)
Propagation delay time,
CS rising edge to DONE rising edge
32
32
ns
tp(CSDR)
Propagation delay time,
CS rising edge to DRDY rising edge
2.0
2.0
tICLK
td(RSSC)
Delay time,
RESET rising edge to READY response
4.5
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7.8 Timing Requirements: Synchronous Master Interface Mode
over operating ambient temperature range (unless otherwise noted)
1.65 V ≤ IOVDD ≤ 2.7 V
MIN
MAX
2.7 V < IOVDD ≤ 3.6 V
MIN
Single device
64
40
Multiple device chaining
88
56
Single device
32
20
Multiple device chaining
44
28
MAX
UNIT
tc(CLKIN)
External clock period
ns
tw(CP)
Pulse duration,
CLKIN high or low
tc(SC)
SCLK period
2
2
tCLKIN
tw(SCHL)
Pulse duration, SCLK high or low
1
1
tCLKIN
tsu(DI)
Setup time, DIN valid before SCLK falling edge
5
5
ns
th(DI)
Hold time, DIN valid after SCLK falling edge
8
8
ns
tw(RSL)
Pulse duration, RESET low
800
800
ns
ns
7.9 Switching Characteristics: Synchronous Master Interface Mode
over operating ambient temperature range (unless otherwise noted)
1.65 V ≤ IOVDD ≤ 2.7 V
MIN
MAX
2.7 V < IOVDD ≤ 3.6 V
MIN
MAX
UNIT
tp(SCDOD)
Propagation delay time,
first SCLK rising edge to DOUT driven
28
15
ns
tp(SCDO)
Propagation delay time,
SCLK rising edge to valid new DOUT
26
15
ns
tp(SDR)
Propagation delay time,
SCLK falling edge to DRDY falling edge
31
20
ns
HIZDLY = 00
6
30
6
20
HIZDLY = 01
8
37
8
27
HIZDLY = 10
10
43
10
43
HIZDLY = 11
12
47
12
47
DNDLY = 00
6
33
6
21
tp(DN)
DNDLY = 01
Propagation delay time, SCLK
falling edge to DONE falling edge DNDLY = 10
8
39
8
27
10
44
10
32
DNDLY = 11
12
48
12
36
tp(CSDN)
Propagation delay time,
CS rising edge to DONE rising edge
32
32
ns
tp(DRS)
Delay time,
last SCLK rising edge to DRDY rising edge
17
15
ns
td(RSSC)
Delay time,
RESET rising edge to READY response
th(LSB)
14
Hold time, last SCLK falling edge
to DOUT 3-state
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4.5
4.5
ns
ns
ms
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SBAS590E – MARCH 2016 – REVISED JUNE 2020
7.10 Timing Requirements: Synchronous Slave Interface Mode
over operating ambient temperature range (unless otherwise noted)
1.65 V ≤ IOVDD ≤ 2.7 V
MIN
2.7 V < IOVDD ≤ 3.6 V
MAX
MIN
Single device
64
40
Multiple device chaining
88
56
Single device
32
20
Multiple device chaining
44
28
tc(CLKIN)
External clock period (1)
tw(CP)
Pulse duration,
CLKIN high or low (1)
td(SCS)
Delay time, SCLK falling edge to CS falling edge
td(CSSC)
Delay time, CS falling edge to first SCLK rising edge
tc(SC)
SCLK period
tw(SCHL)
Pulse duration,
SCLK high or low
tsu(DI)
th(DI)
MAX
UNIT
ns
ns
6
4
ns
16
16
ns
Single device
64
40
Multiple device chaining
88
64
Single device
32
20
Multiple device chaining
44
32
Setup time, DIN valid before SCLK falling edge
5
5
ns
Hold time, DIN valid after SCLK falling edge
8
6
ns
td(SCCS)
Delay time, last SCLK falling edge to CS rising edge
5
5
ns
tsu(sync)
Setup time, DRDY falling edge to master clock falling
edge
10
10
ns
th(sync)
Hold time, DRDY low after master clock falling edge
10
10
ns
tDATA
Data rate period
tw(RSL)
Pulse duration RESET low
(1)
ns
ns
Set by the CLK1 register and the CLK2 register
800
800
ns
Only valid if CLKSRC = 0
7.11 Switching Characteristics: Synchronous Slave Interface Mode
over operating ambient temperature range (unless otherwise noted)
1.65 V ≤ IOVDD ≤ 2.7 V
MIN
MAX
2.7 V < IOVDD ≤ 3.6 V
MIN
MAX
UNIT
tp(SCDOD)
Propagation delay time,
first SCLK rising edge to DOUT driven
28
15
ns
tp(SCDO)
Propagation delay time,
SCLK rising edge to valid new DOUT
26
15
ns
HIZDLY = 00
th(LSB)
tp(DN)
Hold time, last SCLK falling edge
to DOUT 3-state
6
30
6
20
HIZDLY = 01
8
HIZDLY = 10
10
37
8
27
43
10
43
HIZDLY = 11
12
47
12
47
DNDLY = 00
6
33
6
21
DNDLY = 01
Propagation delay time, SCLK
falling edge to DONE falling edge DNDLY = 10
8
39
8
27
10
44
10
32
DNDLY = 11
12
48
12
36
tp(CSDN)
Propagation delay time,
CS rising edge to DONE rising edge
td(RSSC)
Delay time,
RESET rising edge to READY response
32
4.5
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ns
ns
32
4.5
ns
ms
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tw(CP)
tc(CLKIN)
CLKIN
§
DRDY
tp(CSDR)
§
CS
td(CSSC)
td(SCS)
td(SCCS)
tc(SC)
tw(SCHL)
tw(CSH)
§
SCLK
tsu(DI)
th(DI)
§ §
DIN
tp(SCDOD)
DOUT
tp(SCDO)
§ §
MSB
MSB - 1
th(LSB)
LSB + 1
LSB
NOTE: SPI settings are CPOL = 0 and CPHA = 1. CS transitions must take place when SCLK is low.
Figure 1. Asynchronous Interrupt Mode SPI Timing Diagram
tw(CP)
tc(CLKIN)
CLKIN
§
§
DRDY
tp(SDR)
tc(SC)
tw(SCHL)
tp(DRS)
§
§
SCLK
tsu(DI)
th(DI)
tp(SCDO)
tp(SCDOD)
MSB - 1
th(LSB)
LSB + 1
LSB
§
§ §
MSB
DOUT
§ §
§ §
DIN
NOTE: SPI settings are CPOL = 0 and CPHA = 1.
Figure 2. Synchronous Master Mode SPI Timing Diagram
tw(CP)
tc(CLKIN)
CLKIN
§
§
CS
td(CSSC)
td(SCS)
tc(SC)
tw(SCHL)
tp(SCCS)
§
§
SCLK
tsu(DI)
th(DI)
tp(SCDO)
tp(SCDOD)
th(LSB)
LSB + 1
LSB
§
MSB - 1
§ §
MSB
DOUT
§ §
§ §
DIN
NOTE: SPI settings are CPOL = 0 and CPHA = 1. CS can be tied directly to DRDY.
Figure 3. Synchronous Slave Mode SPI Timing Diagram
16
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Optional Pulse
Optional Pulse
tDATA
DRDY
tDATA
tsu(sync)
th(sync)
CLKIN
Figure 4. DRDY Synchronization Timing for Synchronous Slave Mode (CLKSRC = 0)
Optional Pulse
Optional Pulse
tDATA
DRDY
tDATA
tsu(sync)
th(sync)
SCLK
Figure 5. DRDY Synchronization Timing for Synchronous Slave Mode (CLKSRC = 1)
DONE
tp(CSDN)
CS
tp(DN)
SCLK
LSB + 1
DIN, DOUT
LSB
Figure 6. DONE Signal Timing
§
tw(RSL)
§
RESET
or
RESET
§ §
DIN
td(RSSC)
§ §
§
DOUT
Ready
Figure 7. RESET Pin and Command Timing
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7.12 Typical Characteristics
at TA = 25°C, IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF = 2.442 V,
fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, HR mode, and gain = 1 (unless otherwise noted)
25
16000
14000
15
Number of Occurrences
Input-Referred Noise (PV)
20
10
5
0
-5
-10
12000
10000
8000
6000
4000
-15
2000
-20
0
-25
0
1
2
3
4
Time (s)
5
6
7
-10
8
D008
Number of Occurrences
Number of Occurrences
25000
20000
15000
10000
5000
0
-5
0
5
10
15
18
18.1
18.2
18.3
18.4
Effective Number of Bits
D001
Shorted inputs, 8 kSPS, 262144 points, offset removed
D001
Shorted inputs, 8 kSPS, 560 devices, multiple lots
Figure 10. Single Device Noise Histogram
Figure 11. Multiple Device Effective Resolution Histogram
0
0
-20
-20
-40
-40
-60
-60
Amplitude (dB)
Amplitude (dB)
D001
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
20
Input Referred Voltage (PV)
-80
-100
-120
-80
-100
-120
-140
-140
-160
-160
-180
-180
0
500
1000
1500 2000 2500
Frequency (Hz)
3000
3500
4000
Figure 12. THD FFT Plot at 8 kSPS and –0.5 dBFS
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0
500
1000
D011
fIN = 60 Hz, 32768 points
18
10
Figure 9. Single Device Noise Histogram
30000
-10
5
Shorted inputs, 1 kSPS, 65536 points, offset removed
Figure 8. Input-Referred Noise vs Time
-15
0
Input Referred Voltage (PV)
Shorted inputs, 65536 points
-20
-5
1500 2000 2500
Frequency (Hz)
3000
3500
4000
D012
fIN = 60 Hz, 32768 points
Figure 13. THD FFT Plot at 8 kSPS and –20 dBFS
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Typical Characteristics (continued)
0
0
-20
-20
-40
-40
-60
-60
Amplitude (dB)
Amplitude (dB
at TA = 25°C, IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF = 2.442 V,
fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, HR mode, and gain = 1 (unless otherwise noted)
-80
-100
-120
-80
-100
-120
-140
-140
-160
-160
-180
-180
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Frequency (Hz)
D001
0
1000
fIN = 60 Hz, 8 kSPS
2000
3000 4000 5000
Frequency (Hz)
6000
7000
8000
D029
fIN = 60 Hz, 32768 points
Figure 14. Low-Frequency FFT Plot
Figure 15. THD FFT Plot at 16 kSPS and –0.5 dBFS
-90
0
-95
-20
-40
-105
-60
-110
THD (dB)
Amplitude (dB)
-100
-80
-100
-115
-120
-125
-130
-120
-135
-140
-140
-160
-145
-180
-150
0
1000
2000
3000 4000 5000
Frequency (Hz)
6000
7000
0
8000
500
1000
D028
1500 2000 2500
Input Frequency (Hz)
3000
3500
4000
D001
fIN = 60 Hz, 32768 points
Figure 17. THD vs Input Frequency
Figure 16. THD FFT Plot at 16 kSPS and –20 dBFS
4
5.4
Ta = -40
Ta = 25
Ta = 125
2
5.2
1
0
Noise (PVrms)
Integral Nonlinearity (ppm)
3
-1
-2
-3
5
4.8
-4
Ch 1
Ch 2
Ch 3
Ch 4
4.6
-5
-6
-7
-2.5
-2
-1.5
-1
-0.5
0
0.5
Input Voltage (V)
1
1.5
2
2.5
4.4
-50
-25
D001
Figure 18. INL vs Temperature
0
25
50
Temperature (qC)
75
100
125
D018
Figure 19. Noise RMS vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF = 2.442 V,
fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, HR mode, and gain = 1 (unless otherwise noted)
900
0.05
Offset Error (PV)
800
Gain Error (% of FS)
Ch 1
Ch 2
Ch 3
Ch 4
700
600
500
400
-50
-25
0
25
50
Temperature (qC)
75
100
0.025
0
-0.025
-0.05
-50
125
Ch 1
Ch 2
Ch 3
Ch 4
-25
0
D020
Figure 20. Offset Error vs Temperature
25
50
Temperature (qC)
75
100
125
D021
Figure 21. Gain Error vs Temperature
112
2.448
111.5
Normalized SNR (dB)
Reference Votlage (V)
111
2.446
2.444
2.442
110.5
110
109.5
109
108.5
108
107.5
2.44
-50
-25
0
25
50
Temperature (qC)
75
100
107
-120
125
Ta = -40qC
Ta = 25qC
Ta = 125qC
-100
D013
-80
-60
-40
Input Voltage (dBFS)
-20
0
D001
30 units, multiple lots
Figure 22. Internal VREF vs Temperature
Figure 23. Normalized SNR vs Amplitude
140
-100
Ta = -40qC
Ta = 25qC
Ta = 125qC
130
-110
CMRR (dB)
Normalized THD (dB)
-105
-115
-120
120
110
-125
100
Ta = -40 qC
Ta = 25 qC
Ta = 125 qC
-130
-135
-35
90
-30
-25
-20
-15
-10
Input Voltage (dBFS)
-5
Figure 24. Normalized THD vs Amplitude
20
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0
0
2000
D001
4000
Frequency (Hz)
6000
8000
D009
Figure 25. CMRR vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF = 2.442 V,
fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, HR mode, and gain = 1 (unless otherwise noted)
120
40
Channel 1
Channel 2
Channel 3
Channel 4
35
Number of Occurrences
AC PSRR (dB)
100
80
60
40
20
100
1000
10000 100000 1000000
Frequency (Hz)
25
20
15
10
5
AVDD
IOVDD
0
10 20
30
0
-135
1E+7
-130
Differential Input Impedance (k:)
Differential Input Impedance (k:)
1000000
2000000
3000000
fMOD (Hz)
4000000
141.3
141.2
141.1
141
140.9
140.8
140.7
140.6
140.5
140.4
140.3
140.2
140.1
140
-40
D001
0
20
40
60
Temperature (qC)
80
100
120
D001
Figure 29. Differential Input Impedance vs
Temperature at 4.096-MHz fMOD
564.5
4500
564
4000
563.5
3500
563
AVDD Current (PA)
Differential Input Impedance (k:)
-20
D001
Figure 28. Differential Input Impedance vs
Modulator Clock
562.5
562
561.5
561
560.5
3000
2500
2000
1500
1000
560
ADS131A04 LPM
ADS131A04 HRM
500
559.5
559
-40
-120
Figure 27. Crosstalk Histogram
Figure 26. PSRR vs Frequency
7000
6500
6000
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
0
0
-125
Crosstalk (dB)
D019
0
-20
0
20
40
60
Temperature (qC)
80
100
120
0
0.5
1
D001
1.5
2
2.5
3
fMOD (MHz)
3.5
4
4.5
5
D001
LPM = low-power mode, HRM = high-resolution mode
Figure 30. Differential Input Impedance vs
Temperature at 1.024-MHz fMOD
Figure 31. ADS131A04 AVDD Current vs fMOD
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Typical Characteristics (continued)
at TA = 25°C, IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF = 2.442 V,
fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, HR mode, and gain = 1 (unless otherwise noted)
900
3600
800
3300
3000
AVDD Current (PA)
IOVDD Current (PA)
700
600
500
400
300
200
2400
2100
1800
1500
1200
900
ADS131A04 LPM
ADS131A04 HRM
100
2700
ADS131A02 HRM
ADS131A02 LPM
600
300
0
0
0.5
1
1.5
2
2.5
fMOD (MHz)
3
3.5
4
0
4.5
0.5
1
1.5
D001
2
2.5
3
fMOD (MHz)
3.5
4
4.5
LPM = low-power mode, HRM = high-resolution mode
Figure 32. ADS131A04 IOVDD Current vs fMOD
Figure 33. ADS131A02 AVDD Current vs fMOD
IOVDD Current (PA)
LPM = low-power mode, HRM = high-resolution mode
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
5
D001
ADS131A02 HRM
ADS131A02 LPM
0
0.5
1
1.5
2
2.5
3
fMOD (MHz)
3.5
4
4.5
5
D001
LPM = low-power mode, HRM = high-resolution mode
Figure 34. ADS131A02 IOVDD Current vs fMOD
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8 Parameter Measurement Information
8.1 Noise Measurements
Adjust the data rate and gain to optimize the ADS131A02 and ADS131A04 noise performance. When averaging
is increased by reducing the data rate, noise drops correspondingly. Table 1 and Table 2 summarize the
ADS131A0x noise performance with a 2.442-V reference and a 3.3-V analog power supply. Table 3 and Table 4
summarize the ADS131A02 and ADS131A04 noise performance with a 4.0-V reference and a 5-V analog power
supply (or using ±2.5-V bipolar analog power supplies). The data are representative of typical noise performance
at TA = 25°C when fMOD = 4.096 MHz. The data shown are typical results with the analog inputs shorted together
and taking an average of multiple readings across all channels. A minimum 1 second of consecutive readings are
used to calculate the RMS noise for each reading. The data are also representative of the ADS131A0x noise
performance when using a low-noise external reference, such as the REF5025 or REF5040. The effective
resolution data and dynamic range data in Table 1, Table 2, Table 3, and Table 4 are calculated using
Equation 1 and Equation 2. The μVrms noise numbers in the tables are input-referred.
§ 2 u VREF ·
Effective Resolution = log2 ¨
¸
© Gain u VRMS ¹
(1)
§
·
VREF
Dynamic Range = 20 u log ¨
¸¸
¨ 2 u Gain u V
RMS ¹
©
(2)
Table 1. Dynamic Range, Effective Resolution, and Noise in μVrms at 3.3-V Analog Supply, and 2.442-V
Reference for Gain = 1, 2, and 4
GAIN
x1
x2
x4
μVrms
DYNAMIC
RANGE (dB)
EFFECTIVE
RESOLUTION
(Bits)
μVrms
DYNAMIC
RANGE (dB)
EFFECTIVE
RESOLUTION
(Bits)
μVrms
OSR
SETTING
fDATA AT
4.096-MHz
fMOD (kHz)
DYNAMIC
RANGE (dB)
EFFECTIVE
RESOLUTION
(Bits)
4096
1.000
119.49
21.35
1.82
113.49
20.35
1.82
108.08
19.46
1.70
2048
2.000
116.47
20.85
2.58
110.97
19.94
2.44
105.22
18.98
2.36
1024
4.000
113.85
20.41
3.49
107.91
19.43
3.47
101.77
18.41
3.52
800
5.120
112.93
20.26
3.88
106.72
19.23
3.98
101.05
18.29
3.82
768
5.333
112.90
20.25
3.90
106.69
19.22
3.99
100.76
18.24
3.95
512
8.000
110.73
19.89
5.01
104.83
18.91
4.95
98.75
17.91
4.97
400
10.240
109.74
19.73
5.61
103.69
18.72
5.64
97.76
17.74
5.58
384
10.667
109.53
19.70
5.75
103.65
18.72
5.66
97.58
17.71
5.69
256
16.000
107.74
19.40
7.07
101.67
18.39
7.11
95.72
17.40
7.06
200
20.480
106.48
19.19
8.17
100.55
18.20
8.09
94.54
17.21
8.08
192
21.333
106.28
19.16
8.36
100.17
18.14
8.45
94.11
17.13
8.49
128
32.000
104.05
18.78
10.81
97.98
17.78
10.88
92.00
16.78
10.82
96
42.667
101.90
18.43
13.85
95.95
17.44
13.74
89.90
16.43
13.79
64
64.000
97.63
17.72
22.64
91.61
16.72
22.64
85.52
15.71
22.83
48
85.333
92.58
16.88
40.50
86.62
15.89
40.22
80.59
14.89
40.26
32
128.000
85.12
15.62
96.82
78.96
14.62
97.12
73.02
13.61
97.51
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Table 2. Dynamic Range, Effective Resolution, and Noise in μVrms at 3.3-V Analog Supply, and 2.442-V
Reference for Gain = 8 and 16
GAIN
x8
x16
OSR SETTING
fDATA AT 4.096-MHz
fMOD (kHz)
DYNAMIC RANGE
(dB)
EFFECTIVE
RESOLUTION (Bits)
μVrms
DYNAMIC RANGE
(dB)
EFFECTIVE
RESOLUTION (Bits)
4096
1.000
101.72
18.40
μVrms
1.77
95.45
17.36
2048
2.000
98.88
1.82
17.93
2.45
93.07
16.96
1024
4.000
2.39
95.97
17.44
3.43
89.82
16.42
800
3.48
5.120
95.03
17.29
3.82
88.66
16.23
3.98
768
5.333
94.63
17.22
4.00
88.41
16.19
4.09
512
8.000
92.75
16.91
4.96
87.00
15.95
4.81
400
10.240
91.84
16.76
5.51
85.62
15.72
5.64
384
10.667
91.52
16.70
5.72
85.50
15.70
5.72
256
16.000
89.57
16.38
7.16
83.58
15.38
7.14
200
20.480
88.44
16.19
8.16
82.45
15.20
8.12
192
21.333
88.26
16.16
8.32
82.12
15.14
8.44
128
32.000
86.02
15.79
10.77
79.80
14.76
11.02
96
42.667
83.91
15.44
13.74
77.72
14.41
14.00
64
64.000
79.52
14.71
22.78
73.45
13.70
22.92
48
85.333
74.60
13.89
40.14
68.47
12.87
40.66
32
128.000
66.93
12.62
97.05
60.97
11.61
97.61
Table 3. Dynamic Range, Effective Resolution, and Noise in μVrms at ±2.5-V Analog Supply, and 4.0-V
Reference for Gain = 1, 2, and 4
GAIN
24
x1
x2
x4
μVrms
DYNAMIC
RANGE (dB)
EFFECTIVE
RESOLUTION
(Bits)
μVrms
DYNAMIC
RANGE (dB)
EFFECTIVE
RESOLUTION
(Bits)
μVrms
OSR
SETTING
fDATA AT
4.096-MHz
fMOD (kHz)
DYNAMIC
RANGE (dB)
EFFECTIVE
RESOLUTION
(Bits)
4096
1.000
124.55
22.19
1.66
118.69
21.22
1.64
112.32
20.16
1.71
2048
2.000
121.47
21.68
2.38
114.98
20.60
2.51
109.58
19.70
2.34
1024
4.000
118.44
21.18
3.37
112.48
20.18
3.36
106.31
19.16
3.41
800
5.120
117.58
21.03
3.72
111.46
20.02
3.77
105.29
18.99
3.84
768
5.333
116.75
20.89
4.10
110.88
19.92
4.03
105.06
18.95
3.94
512
8.000
115.16
20.63
4.93
109.23
19.65
4.88
103.10
18.63
4.94
400
10.240
114.15
20.46
5.53
108.33
19.50
5.41
102.28
18.49
5.43
384
10.667
113.88
20.42
5.71
107.83
19.41
5.73
101.70
18.39
5.80
256
16.000
112.09
20.12
7.02
105.76
19.07
7.27
99.83
18.08
7.19
200
20.480
110.71
19.89
8.22
104.65
18.88
8.27
98.37
17.84
8.51
192
21.333
110.13
19.79
8.79
104.10
18.79
8.80
97.99
17.78
8.90
128
32.000
106.93
19.26
12.72
100.76
18.24
12.94
94.59
17.21
13.15
96
42.667
104.17
18.80
17.47
98.18
17.81
17.41
92.00
16.78
17.74
64
64.000
98.84
17.92
32.27
92.74
16.91
32.58
86.50
15.87
33.40
48
85.333
93.30
17.00
61.06
87.45
16.03
59.91
81.31
15.01
60.74
32
128.000
85.10
15.64
156.92
78.87
14.60
160.84
73.35
13.67
153.69
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Table 4. Dynamic Range, Effective Resolution, and Noise in μVrms at ±2.5-V Analog Supply, and 4.0-V
Reference for Gain = 8 and 16
GAIN
x8
OSR SETTING
fDATA AT 4.096-MHz
fMOD (kHz)
DYNAMIC RANGE
(dB)
EFFECTIVE
RESOLUTION (Bits)
4096
1.000
106.35
19.17
2048
2.000
103.40
1024
4.000
800
x16
μVrms
DYNAMIC RANGE
(dB)
EFFECTIVE
RESOLUTION (Bits)
μVrms
1.70
100.66
18.22
1.63
18.68
2.38
97.37
17.68
2.39
100.46
18.19
3.35
94.59
17.21
3.29
5.120
99.53
18.04
3.72
93.28
17.00
3.83
768
5.333
99.19
17.98
3.87
93.09
16.97
3.91
512
8.000
97.31
17.67
4.81
91.08
16.63
4.93
400
10.240
96.23
17.49
5.45
90.16
16.48
5.48
384
10.667
95.84
17.42
5.70
89.85
16.43
5.68
256
16.000
93.87
17.09
7.15
87.73
16.07
7.25
200
20.480
92.70
16.90
8.18
86.43
15.86
8.41
192
21.333
92.10
16.80
8.77
85.68
15.73
9.17
128
32.000
88.58
16.22
13.14
82.42
15.19
13.36
96
42.667
86.27
15.83
17.15
80.00
14.79
17.64
64
64.000
80.60
14.89
32.92
74.48
13.87
33.31
48
85.333
75.29
14.01
60.68
69.10
12.98
61.90
32
128.000
67.06
12.64
156.51
61.17
11.64
156.32
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9 Detailed Description
9.1 Overview
The ADS131A02 and ADS131A04 are low-power, two- and four-channel, simultaneous-sampling, 24-bit, deltasigma (ΔΣ), analog-to-digital converters (ADCs) with an integrated low-drift internal reference voltage. Data rate
flexibility, wide dynamic range, and interface options make these devices good choices when designing for
smart-grid and other industrial power monitor, control, and protection applications. The ADC interface data
integrity features provide for a very low rate of transmission errors. Throughout this document, the ADS131A02
and ADS131A04 are referred to as the ADS131A0x.
The ADS131A0x has very flexible power-supply options. A 5-V single-supply (or ±2.5-V bipolar-supply) operation
is available to support up to a 4.5-V external reference to maximize the dynamic range of the converter.
Alternatively, a negative charge pump can be enabled to accept absolute input signals down to –1.5 V below
ground when powered from a single 3.3-V supply. Five gain options are available to help maximize the ADC
code range and 16 selectable oversampling ratio (OSR) options are selectable to optimize the converter for a
specific data rate. The low-drift internal reference can be programmed to either 2.442 V or 4 V. Input signal outof-range detection can be accomplished by using the integrated comparators, with programmable trigger-point
settings. A detailed diagram of the ADS131A0x is shown in the Functional Block Diagram section.
The device offers multiple serial peripheral interface (SPI) communication options to provide flexibility for
interfacing to microprocessors or field-programmable gate arrays (FPGAs). Synchronous real-time and
asynchronous interrupt communication modes are available using the SPI-compatible interface. Multiple devices
can share a common SPI port and are synchronized by using the DRDY signal. Device communication is
specified through configuration of the M0 interface mode pin and chaining of the DONE signal. Optional cyclic
redundancy check (CRC) and Hamming code correction on the interface enhance communication integrity.
9.2 Functional Block Diagram
AVDD
REFP
REFN
REFEXT
Reference
Mux
IOVDD
Voltage
Reference
Out-of-Range
Detect
M[2:0]
RESET
AIN1N
'6 ADC
AIN1P
Control and
Serial Interface
CS
SCLK
DIN
AIN2N
DOUT
'6 ADC
AIN2P
DRDY
Watchdog
Timer
DONE
ADS131A04 Only
AIN3N
'6 ADC
Data Integrity
AIN3P
AIN4N
'6 ADC
Negative
Charge
Pump
AIN4P
AVSS
26
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CLK/XTAL
XTAL1/CLKIN
XTAL2
GND
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9.3 Feature Description
This section contains details of the ADS131A0x internal feature elements. The ADC clocking is discussed first,
followed by the analog blocks and the digital filter.
9.3.1 Clock
Multiple clocks are created from one external master clock source in the ADS131A0x to create device
configuration flexibility. The ADC operates from the internal system clock, ICLK, which is provided in one of three
ways.
• An external master clock, CLKIN, can be applied directly to the XTAL1/CLKIN pin to be divided down to
generate ICLK using the CLK_DIV[2:0] bits in the CLK1 register. In this case, leave the XTAL2 pin floating.
• A crystal oscillator can be applied between XTAL1/CLKIN and XTAL2, generating a master clock to be
divided down using the CLK_DIV[2:0] bits in the CLK1 register to generate ICLK.
• A free-running SCLK can be internally routed to be set as ICLK. This mode is only available in synchronous
slave interface mode. Tie the CLKIN/XTAL1 pin to GND. Leave the XTAL2 pin unconnected.
The system ICLK is passed through a second 3-bit clock divider (ICLK_DIV[2:0] in the CLK2 register) to create
the modulator clock, MODCLK. MODCLK is used for timing of the delta-sigma (ΔΣ) modulator sampling and
digital filter.
The interface operation mode determines the options for sourcing ICLK. When in asynchronous interrupt or
synchronous master mode, generate ICLK by applying a direct external master clock signal to the XTAL1/CLKIN
pin or by using a crystal oscillator across the XTAL1/CLKIN and XTAL2 pins. If directly applying a master clock to
the XTAL1/CLKIN pin, leave XTAL2 floating. In synchronous slave mode, a free-running SCLK line can be
connected directly into the ICLK_DIV block in place of the divided XTAL or CLKIN source. Use the CLKSRC bit
in the CLK1 register to select between the XTAL1/CLKIN or SCLK input as the master clock source for the ADC.
The CLKSRC bit must be set prior to powering up the ADC channels. Using SCLK as ICLK is useful in galvanic
isolated applications to limit the digital I/O lines crossing the isolation barrier. Figure 35 shows the clock dividers
and clocking names.
AINxP
Sinc3 LPF
ADC
CS
AINxN
DONE
DIN
XTAL1/CLKIN
X
XTAL2
fCLKIN
fICLK
CLK_DIV
[2:0]
DOUT
CLKSRC
M
ICLK_DIV
[2:0]
fMOD
OSR
[3:0]
fDATA
SPI
+
Ctrl
DRDY
sync
M0
SCLK
Figure 35. ADC Clock Generation
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Feature Description (continued)
9.3.1.1 XTAL1/CLKIN and XTAL2
XTAL1/CLKIN is the external clock input to the ADC and can be supplied from a clock source or by using a
crystal (along with the XTAL2 pin). Figure 36 shows the configuration for the two clock input options.
XTAL2
XTAL1/CLKIN
XTAL2
XTAL1/CLKIN
16.384-MHz
Clock
50 Ÿ
a) External Clock Mode
b) Crystal Oscillator Mode
Figure 36. Clock Mode Configurations
Input the clock directly to the XTAL1/CLKIN pin and leave the XTAL2 pin floating when using a direct clock
source.
Connect the crystal and load capacitors as shown in Figure 36b to the XTAL1/CLKIN and XTAL2 pins. Place the
crystal and crystal load capacitors close to the ADC pins using short, direct traces. Connect the load capacitors
to the digital ground. Do not connect any other external circuit to the crystal oscillator. Table 5 lists recommended
crystals for use with the ADS131A0x. The crystal oscillator start-up time is typically 5 ms, but can be longer
depending on the crystal characteristics.
Table 5. Recommended Crystals
MANUFACTURER
FREQUENCY
OPERATING TEMPERATURE
RANGE
PART NUMBER
Abracon
16.384 MHz
–40°C to +125°C
ABLS-16.384MHZ-L4Q-T
Abracon
16.384 MHz
–40°C to +85°C
ABM3C-16.384MHZ-D4Y-T
ECS
16.384 MHz
–40°C to +85°C
ECS-163-18-5PXEN-TR
9.3.1.2 ICLK
ICLK is the internal system clock to the ADC. ICLK is derived from CLKIN set through the CLK_DIV[2:0] bits in
the CLK1 register or is set as SCLK when operating in synchronous slave mode. ICLK is used as the SCLK
output when operating in synchronous master mode in addition to being used for the internal ADC clock timing.
Use the CLKSRC bit to set the source for ICLK.
9.3.1.3 MODCLK
MODCLKis the modulator clock used for the ADC sampling. MODCLK is derived from ICLK set through the
ICLK_DIV[2:0] bits in the CLK2 register. Verify that the fMOD minimum and maximum limits are met in the
Electrical Characteristics table by adjusting the CLK_DIV[2:0] and ICLK_DIV[2:0] clock dividers.
9.3.1.4 Data Rate
The data rate is the rate at which conversion results are generated by the ADC. In a delta-sigma ADC, the
oversampling ratio (OSR) is the ratio between the modulator frequency and the output data rate. The OSR[3:0]
bits in the CLK2 register set the OSR on the ADS131A0x. The output data rate is the frequency of MODCLK
(fMOD) divided by the OSR. The ADC data rate is shown in Table 30 based on the OSR setting and the fMOD
frequency.
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9.3.2 Analog Input
The ADS131A0x analog inputs are directly connected to the switched-capacitor sampling network of the ΔΣ
modulator without a multiplexer or integrated buffer. The device inputs are measured differentially (VIN = VAINxP –
VAINxN) and can span from –VREF / Gain to VREF / Gain. Figure 38 shows a conceptual diagram of the modulator
circuit charging and discharging the sampling capacitor through switches, although the actual implementation is
slightly different. The timing for switches S1 and S2, as shown in Figure 37, are 180 degrees out-of-phase of one
another.
tMOD = 1 / fMOD
S1
On
Off
S2
On
Off
Figure 37. S1 and S2 Switch Timing
Electrostatic discharge (ESD) circuitry protects the inputs. Figure 38 shows a simplified representation of the
ESD circuit. Protection for input voltages exceeding AVDD can be modeled as a simple diode.
The negative charge pump voltage, VNCP, controls the voltage at which the low-side protection devices begin
conducting. Tie VNCP to AVSS if the charge pump is not used to ensure the clamping voltage is properly set.
The charge pump cannot provide a large amount of current. The mechanism shown in Figure 38 ensures current
provided by the charge pump is limited in the case of an overvoltage event.
AVDD
VNCP
AINxP
S1
S2
Cs
2
AINxN
S1
VNCP
AVDD
Figure 38. Equivalent Analog Input Circuitry
To prevent the ESD diodes from being enabled, the absolute voltage on any input must stay within the range
provided by Equation 3 when the internal charge pump is disabled and within the range in Equation 4 when the
internal charge pump is enabled:
AVSS – 0.3 V < VAINxP or VAINxN < AVDD + 0.3 V
AVSS – 1.65 V < VAINxP or VAINxN < AVDD + 0.3 V
(3)
(4)
If the voltages on the input pins have any potential to violate these conditions, external clamp diodes or series
resistors may be required to limit the input currents to safe values (see the Absolute Maximum Ratings table).
The charging of the input capacitors draws a transient current from the sensor driving the ADS131A0x inputs.
The average value of this current can be used to calculate an effective impedance of ZIN, where ZIN = VIN /
IAVERAGE. This effective input impedance is a function of the modulator sampling frequency and Equation 5 can
be used to calculate an estimate value. When using fMOD = 4.096 MHz, the input impedance is approximately
130 kΩ.
2
Zin
fMOD u Cs
where
•
•
fMOD = modulator clock and
CS = 3.5 pF
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There are two general methods of driving the ADS131A0x analog inputs, as shown in Figure 39: pseudodifferential or fully-differential.
VREF / Gain
to
VREF / Gain
VREF / Gain
Peak-to-Peak
Device
Device
Common
Voltage
Common
Voltage
a) Psuedo-Differential Input
VREF / Gain
Peak-to-Peak
b) Differential Input
Figure 39. Pseudo-Differential and Fully-Differential Inputs
To apply a pseudo-differential signal to the fully-differential inputs, apply a dc voltage to AINxN, preferably to the
analog mid-supply [(AVDD + AVSS) / 2] or [(AVDD + VNCP) / 2] when the negative charge pump is enabled.
The AINxP pins can swing between –VREF / Gain to VREF / Gain (as shown in Figure 40) around the common
voltage. The common-mode voltage, VCM, changes with VAINxP.
Configure the signals at AINxP and AINxN to be 180° out-of-phase centered around a common-mode voltage to
use a fully-differential input method. Both the AINxP and AINxN inputs swing from VCM +½ VREF / Gain to VCM –½
VREF / Gain, as shown in Figure 41. The differential voltage at the maximum and minimum points is equal to VREF
/ Gain to –VREF / Gain, respectively. The VCM voltage remains fixed when AINxP and AINxN swing. Use the
ADS131A0x in a differential configuration to maximize the dynamic range of the data converter. For optimal
performance, the VCM is recommended to be set at the midpoint of the analog supplies.
Tie any unused analog input channels directly to AVSS.
AINxP
AINxN
AINxP
VCM
VCM
AINxN
Figure 40. Pseudo-Differential Input Mode
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Figure 41. Fully-Differential Input Mode
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9.3.3 Input Overrange and Underrange Detection
Each ADS131A0x channel has two integrated comparators to detect overrange and underrange conditions on
the input signals. Use the COMP_TH[2:0] bits in the A_SYS_CFG register to set a high and low threshold level
using a 3-bit digital-to-analog converter (DAC). This threshold voltage is compared to the voltage on the input
pins. The voltage monitor triggers an alarm by setting the F_ADCIN bit of the STAT_1 register when the
individual voltage on AINxP or AINxN exceeds the threshold set by the COMP_TH[2:0] bits. When the F_ADCIN
bit of the STAT_1 register is set, indicating an out-of-range event, read the STAT_P register or STAT_N register
to determine exactly which input pin exceeded the set threshold. Figure 42 shows an input overrange and
underrange detection block diagram.
COMP_TH[2:0]
±
+
Latch
±
COMP_TH[2:0]
+
S
Q
R
Q
Conversion
Start Reset
DOUT Data Frame
AINxP
Status
Digital
Filter
ADC
ADC
Channel 1 Channel 2 Channel 3 Channel 4
Data
Data
Data
Data
CRC
AINxN
COMP_TH[2:0]
±
+
Latch
±
COMP_TH[2:0]
+
S
Q
R
Q
Conversion
Start Reset
Figure 42. ADC Out-of-Range Detection Monitor
9.3.4 Reference
The ADS131A0x offers an integrated low-drift, 2.442-V or 4.0-V reference option. For applications that require a
different reference voltage, the device offers a reference input option for use with an external reference voltage.
The reference source is selected by the INT_REFEN bit in the A_SYS_CFG register. By default, the external
reference is selected (INT_REFEN = 0). The internal voltage reference requires 0.2 ms to settle to 1% and 250
ms to fully settle to 0.01% when switching from an external reference source to the internal reference (using the
recommended bypass capacitor values). The external reference input is internally buffered to increase input
impedance. Therefore, additional reference buffers are usually not required when using an external reference.
Connect the reference voltage to the REFEXT pin when using an external reference.
External band-limiting capacitors determine the amount of reference noise contribution. For high-end systems,
choose capacitor values such that the bandwidth is limited to less than 10 Hz so that the reference noise does
not dominate the system noise. In systems with strict ADC power-on requirements, using a large capacitor on the
reference increases the time for the voltage to meet the desired value, thus increasing system power-on time.
Figure 43 illustrates a typical external reference drive circuitry with recommended filtering options.
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1 µF
5V
AVDD
VOUT
100 Ÿ
AVSS
REF50xx
10 µF
GND
AVSS
REFEXT
AVSS
+
REFP
R2
1 µF
R3
REFN
AVSS
To ADC
NOTE: R2 = 62.3 kΩ, R3 = 97.5 kΩ.
Figure 43. External Reference Driver
Set the INTREF_EN bit to 1 in the A_SYS_CFG register to use the internal reference. When the internal
reference is selected, use the VREF_4V bit to select between a 2.442-V or 4.0-V reference. By default, the
device is set to use the 2.442-V reference. The VREF_4V bit has no function when set to use the external
reference. When enabling the negative charge pump with a 3.0-V to 3.45-V analog supply, the internal reference
must be set to 2.442 V. Figure 44 shows a simplified block diagram of the internal ADS131A0x reference. The
reference voltage is generated with respect to AVSS requiring a direct connection between REFN and AVSS.
1 µF
AVSS
REFEXT
R1
+
Bandgap
REFP
INT_REFEN = 1
VREF_4V = 0
R2
VREF_4V = 1
1 µF
R3
REFN
AVSS
To ADC
NOTE: R1 = 20 kΩ, R2 = 62.3 kΩ, R3 = 97.5 kΩ.
Figure 44. Internal Reference
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9.3.5
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ΔΣ Modulator
The ADS131A0x is a multichannel, simultaneous sampling ΔΣ ADC where each channel has an individual
modulator and digital filter. The modulator samples the input signal at the rate of fMOD derived as a function of the
ADC operating clock, fICLK. As in the case of any ΔΣ modulator, the ADS131A0x noise is shaped until fMOD / 2.
The modulator converts the analog input voltage into a pulse-code modulated (PCM) data stream. The on-chip
digital decimation filters take this bitstream and provide attenuation to the now shaped, higher frequency noise.
This ΔΣ sample and conversion process drastically reduces the complexity of the analog antialiasing filters
typically required with Nyquist ADCs.
9.3.6 Digital Decimation Filter
The digital filter receives the modulator output and decimates the data stream to create the final conversion
result. The digital filter on each channel consists of a third-order sinc filter. The oversampling ratio (OSR)
determines the number of samples taken to create the output data word, and is set by the modulator rate divided
by the data rate (fMOD / fDATA). The OSR of the sinc filters is adjusted by the OSR[3:0] bits in the CLK2 register.
The OSR setting is a global setting that affects all channels and, therefore, all channels operate at the same data
rate in the device. By adjusting the OSR, tradeoffs can be made between noise and data rate to optimize the
signal chain: filter more for lower noise (thus creating lower data rates), filter less for higher data rates.
The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the
filter from the modulator at the rate of fMOD. Equation 6 shows the scaled sinc3 filter Z-domain transfer function.
As shown in Table 6, the integer N is the set OSR and the integer K is a scaling factor for OSR values that are
not an integer power of 2.
1 Z
H z
3
N
Ku
Nu 1 Z
1
(6)
Equation 7 shows the sinc filter frequency domain transfer function. As shown in Table 6, the integer N is the set
OSR and the integer K is a scaling factor for OSR values that are not an integer power of 2.
H f
ª NSf º
sin «
»
fMOD ¼
¬
Ku
ª Sf º
N u sin «
»
¬ fMOD ¼
3
where:
N = oversampling ratio
(7)
Table 6. K Scaling Factor
OSR (N)
K SCALING VALUE
800, 400, 200
0.9983778
4096, 2048, 1024, 512, 256, 128, 64, 32
1.0
768, 384, 192, 96, 48
1.00195313
The sinc3 filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these
frequencies, the filter has infinite attenuation. Figure 45 and Figure 46 illustrate the digital filter frequency
response out to a normalized input frequency (fIN / fDATA) of 5 and 0.5, respectively. Figure 47, Figure 48, and
Figure 49 illustrate the frequency response for OSR = 32, OSR = 512, and OSR = 4096 up to fMOD, respectively.
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0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-2
-4
-6
Amplitude (dB)
Amplitude (dB)
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-8
-10
-12
-14
-16
-18
-20
0
0.5
1
1.5
2
2.5
3
3.5
4
Normalized Frequency (fIN/fDATA)
4.5
0
5
0.1
D001
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.5
D002
Figure 46. Sinc3 Filter Roll-Off
0
-20
-40
Amplitude (dB)
Amplitude (dB)
Figure 45. Sinc3 Filter Frequency Response
0.2
0.3
0.4
Normalized Frequency (fIN/fDATA)
-60
-80
-100
-120
-140
-160
-180
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32
Normalized Frequency (fIN/fDATA)
D003
Figure 47. Sinc3 Filter Frequency Response (OSR 32)
0
60
120
180
240
300
360
420
Normalized Frequency (fIN/fDATA)
480
D004
Figure 48. Sinc3 Filter Frequency Response (OSR 512)
0
-25
-50
Amplitude (dB)
-75
-100
-125
-150
-175
-200
-225
-250
0
400
800 1200 1600 2000 2400 2800 3200 3600 4000
Normalized Frequency (fIN/fDATA)
D005
Figure 49. Sinc3 Filter Frequency Response (OSR 4096)
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The K scaling factor for OSR values that are not an integer power of two adds a non-integer gain factor to the
sinc3 frequency response across all frequencies. The host must account for the K scaling factor to obtain the
ADC gain error given in the Electrical Characteristics table. Figure 50 overlays the digital filter frequency
response for the three K scaling options in Table 6. Graph scaling is set to a narrow limit to show the small gain
variation between OSR values.
0.05
OSR 512
OSR 768
OSR 800
0
-0.05
Amplitude (dB)
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
-0.45
-0.5
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
Normalized Frequency (fIN/fDATA)
3
0.1
D006
Figure 50. Non-Binary OSR Sinc Filter Frequency Response
The ADS131A0x immediately begins ADC conversions when powered up and brought out of standby mode
using the WAKEUP command. The DRDY falling edge indicates when each ADC conversion completes. The
sinc3 digital filter requires three conversion cycles to settle (tSETTLE), assuming the analog input has settled to its
final value. The output data are not gated when the digital filter settles, meaning that the first two ADC
conversion results show unsettled data from the filter path before settled data are available for the third ADC
conversion. The first two unsettled ADC conversions, though unsettled, can be used for diagnostic purposes to
ensure the ADC is coming out of standby as expected.
In addition to the sinc3 filter settling, the ADC requires an extra data period to report the conversion data. After
the ADC accumulates the digital filter data, an additional data period is required for the ADC data to reach the
DOUT buffer. Because of the digital filter settling and the DOUT buffer, the device requires four data periods to
retrieve data from DOUT. Figure 51 shows the data ready behavior and time needed for the digital filter settling
and data retrieval coming out of standby.
ADC starts conversions
ADC
Status
DIN
ADCs enabled
ADCs wakeup
ADC_EN
WAKEUP
Sinc3 filter settles in three conversion cycles
Data period 1
Data period 2
Data period 3
Data period 4
tSETTLE
DRDY
0
One data period delay for
conversion to reach DOUT buffer
1
Data available
for data period 1
2
3
Data available
for data period 2
Settled data
available for
data period 3
Figure 51. Sinc3 Filter Settling
The digital filter uses a multiple stage linear-phase digital filter. Linear-phase filters exhibit constant delay time
across all input frequencies (also known as constant group delay). This behavior results in zero-phase error
when measuring multi-tone signals. For more information about group delay in delta-sigma ADCs, see the
Accounting for delay from multiple sources in delta-sigma ADCs white paper.
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9.3.7 Watchdog Timer
The ADS131A0x offers an integrated watchdog timer to protect the device from entering an unresponsive state.
Enable the watchdog timer by setting the WDT_EN bit in the D_SYS_CFG register. The timer resets with each
data frame when the CS signal transitions from high to low. If a timer reset does not take place, the watchdog
timer expires after 500 ms and checks the status of the DONE pin.
If DONE is high when the watchdog timer expires, the device assumes that an unresponsive state has occurred
and issues a watchdog timer reset. Following the reset, the device enters the power-up state (see the Power-Up
section) and sets the F_WDT bit in the STAT_1 register, indicating that a watchdog timer reset has taken place.
After this watchdog reset, the device requires re-initialization, as if powering up the device for the first time.
If DONE is low when the watchdog timer expires, the device itself has completed the communication frame and
assumes that there is an issue in the system itself outside the device. In this case, the device sets the F_WDT bit
in the STAT_1 register without resetting the device to preserve the configuration.
The watchdog timer feature is useful for devices connected in a daisy-chain communication. With a synchronous
master and synchronous slaves in chain, the watchdog timer can determine if a device has become
unresponsive so that the device can be reset and then re-initialized. By default, the watchdog timer is not
enabled.
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9.4 Device Functional Modes
9.4.1 Low-Power and High-Resolution Mode
The ADS131A0x offers two modes of operation: high-resolution and low-power mode. High-resolution mode
requires a faster modulator clock, up to fMOD = 4.25 MHz, to maximize performance at higher data rates. Lowpower mode scales the analog and digital currents and restricts the maximum fMOD to 1.05 MHz. Select the
operating mode using the HRM bit in the A_SYS_CFG register.
9.4.2 Power-Up
After all supplies are established and the RESET pin goes high, an internal power-on-reset (POR) is performed.
As part of the POR process, all registers are initialized to the default states, the states of the M0, M1, and M2
pins are latched, the interface is placed in a locked state, and the device enters standby mode. POR can take up
to 4.5 ms to complete.
When the host first communicates with the ADS131A0x, the SPI interface requires one SCLK pulse to wake up.
To start communications, NULL commands can be sent to the device to check the device response. The device
is ready to accept commands when the power-on cycle is completed and the SPI responds with a READY status
word. The STAT_S register indicates if the ADC powered up properly or if a fault occurred during device
initialization. Send an UNLOCK command to enable the interface and begin communicating with the device. See
Table 14 for more information on the READY status word and the UNLOCK from POR or RESET or RESET:
Reset to POR Values sections for more information on bringing the device out of POR.
9.4.3 Standby and Wake-Up Mode
After being unlocked from POR or after reset, the device enters a low-power standby mode with all ADC
channels powered down. After the registers are properly configured, enable all the ADC channels together by
writing to the ADC_ENA register and issue a WAKEUP command to start conversions. To enter standby mode
again, send the STANDBY command and disable all ADC channels by writing to the ADC_ENA register. The
ADS131A0x requires using the WAKEUP and STANDBY commands together with writing to the ADC_ENA
register to disable or enable ADC channels to start and stop conversions.
9.4.4 Conversion Mode
The device runs in continuous conversion mode. When a conversion completes, the device places the result in
the output buffer and immediately begins another conversion. Data are available at the next data-ready indicator,
although data may not be fully settled through the digital filter (see the Digital Decimation Filter section for more
information on settled data).
9.4.5 Reset (RESET)
There are two methods to reset the ADS131A0x: pull the RESET pin low for at least tw(RSL) or send the RESET
command. The RESET pin must be tied high if the RESET command is used. The RESET command takes effect
at the completion of the command (see the RESET: Reset to POR Values section for more information). As part
of the reset process, all registers are initialized to the default states, the status of the M0, M1, and M2 pins are
latched, the interface is placed in a locked state, and the device enters standby mode. Reset can take up to 4.5
ms to complete. The device outputs a READY status word indicating that the reset is completed and the device
is ready to accept commands. Send an UNLOCK command to enable the interface and begin communicating
with the device. See Table 13 for more information on the READY status word, the UNLOCK from POR
command, and the RESET command. Figure 7 illustrates the critical timing relationship of taking the ADS131A0x
into reset and bringing the device out of reset.
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9.5 Programming
9.5.1 Interface Protocol
The ADS131A0x is designed with an interface protocol that expands the capability of outputting more ADC
system monitors without disrupting data flow. This protocol communicates through standard serial peripheral
interface (SPI) methods, using allocated device words within a single data transmission frame to pass
information. A single data frame starts when the interface is enabled, typically done by pulling the CS line low.
The duration of a data frame is made up of several device words with programmable bit lengths. A visual
representation showing how a data frame is made up of multiple device words is shown in Figure 52.
Data Frame
DOUT
Device Word 1 Device Word 2 Device Word 3
DIN, DOUT
§
Device Word 1 Device Word 2 Device Word 3
§
DIN
§
SCLK
Device word is length set by M1: 16, 24, or 32 bits.
a) Frame
b) Single Device Word
Figure 52. Data Frame and Device Word
9.5.1.1 Device Word Length
The interface is full duplex, allowing the device to be read from and written to within the same data frame. The
length of the individual device words is programmable through the state of the M1 pin. This pin must be set to
one of three states at power-up. The pin state is latched at power-up and changing the pin state after power-up
has no effect. Table 7 lists the modes associated with the M1 pin state. The M1 pin must be tied high to IOVDD
through a < 1-kΩ resistor, low to GND through a < 1-kΩ resistor, or left floating.
Table 7. M1 Pin Setting
M1 STATE
DEVICE WORD LENGTH (Bits)
IOVDD
32
GND
24
Float
16
9.5.1.2 Fixed versus Dynamic-Frame Mode
The device has two data frame size options to set the number of device words per frame: fixed and dynamicframe mode, controlled by the FIXED bit in the D_SYS_CFG register. By default, the ADS131A0x powers up in
dynamic-frame mode.
In fixed-frame mode, there are always six device words for each data frame for the ADS131A04. The first device
word is reserved for the status word, the next four device words are reserved for the conversion data for each of
the four channels, and the last word is reserved for the cyclic redundancy check (CRC) data word. For the
ADS131A02, there are two fewer words because there are two fewer channels reporting data words.
In dynamic-frame mode, the number of device words per data frame is dependent on if the ADCs are enabled
and if CRC data integrity is enabled. The device words in a data frame of the command or status word, the data
words for enabled ADC channels, and the CRC word if enabled.
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Figure 53 shows the fixed-frame and dynamic-frame modes for the ADS131A04 in standby mode with CRC data
integrity enabled and disabled. Figure 54 shows the fixed-frame and dynamic-frame modes for the ADS131A04
with ADC channels and CRC data integrity enabled and disabled.
Data Frame
Data Frame
DIN
DOUT
Command
00
00
00
00
00
DIN
Status
00
00
00
00
00
DOUT
a) Fixed-Frame Size (CRC Disabled)
Command
Status
b) Dynamic Frame Size (CRC Disabled)
Data Frame
Data Frame
DIN
DOUT
Command
00
00
00
00
CRC
DIN
Status
00
00
00
00
CRC
DOUT
c) Fixed-Frame Size (CRC Enabled)
Command
CRC
Status
CRC
d) Dynamic Frame Size (CRC Enabled)
Figure 53. Fixed versus Dynamic-Frame Modes in Standby Mode
Data Frame
DIN
DOUT
Data Frame
Command
00
00
00
00
00
DIN
Status
Channel 1
Data
Channel 2
Data
Channel 3
Data
Channel 4
Data
00
DOUT
Command
00
00
00
00
Status
Channel 1
Data
Channel 2
Data
Channel 3
Data
Channel 4
Data
a) Fixed-Frame Size (CRC Disabled)
b) Dynamic Frame Size (CRC Disabled)
Data Frame
DIN
DOUT
Data Frame
Command
00
00
00
00
CRC
DIN
Status
Channel 1
Data
Channel 2
Data
Channel 3
Data
Channel 4
Data
CRC
DOUT
Command
00
00
00
00
CRC
Status
Channel 1
Data
Channel 2
Data
Channel 3
Data
Channel 4
Data
CRC
c) Fixed-Frame Size (CRC Enabled)
d) Dynamic Frame Size (CRC Enabled)
Figure 54. Fixed versus Dynamic-Frame Modes With ADCs Enabled
Enabling the ADCs in the ADC_ENA register changes the SPI frame size when using dynamic-frame mode. This
change may result in an F_FRAME error if the next command frame is not adjusted. The number of words in a
frame is dependent on how many ADCs are enabled and if the CRC is enabled.
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9.5.1.3 Command Word
The command word is the first device word on every DIN data frame. This frame is reserved for sending user
commands to write or read from registers (see the SPI Command Definitions section). The commands are standalone, 16-bit words that appear in the 16 most significant bits (MSBs) of the first device word of the DIN data
frame. Write zeroes to the remaining unused least significant bits (LSBs) when operating in either 24-bit or 32-bit
word size modes.
9.5.1.4 Status Word
The status word is the first device word in every DOUT data frame. The status word either provides a status
update of the ADC internal system monitors or functions as a status response to an input command; see the SPI
Command Definitions section. The contents of the status word are always 16 bits in length with the remaining
LSBs set to zeroes depending on the device word length; see Table 7.
9.5.1.5 Data Words
ADC conversion data words follow the status word in the communication data frame. The device outputs
individual channel data in separate device words. The ADS131A0x converter is 24-bit resolution regardless of
the device word length set by pin M1 shown in Table 7. However, the ADC conversion data are truncated to 16
bits when using a 16-bit device word length setting, or when using the 24-bit device word length setting with the
Hamming code enabled set by the M2 pin.
9.5.1.5.1 ADC Data Word 16-Bit Format
The ADC conversion data word is set to a 16-bit format with either of two conditions. First, if the M1 pin input is
left floating, the device word format is set to a 16-bit word length. This sets the ADC output data length to 16-bits.
Second, if the M1 pin input is set to GND and the M2 pin is set to IOVDD, the device word format is set to a 24bit word length. In this second condition, the first 16 bits are used for the ADC data, while the last eight bits are
used for the Hamming code. The 16 bits of data per channel are sent in binary two's complement format, MSB
first. The size of one code (LSB) is calculated using Equation 8:
1 LSB = (2 × VREF / Gain) / 216 = FS / 215
(8)
A positive full-scale input [VIN ≥ (FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFh and a
negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 8000h. The output clips at these
codes for signals that exceed full-scale.
Table 8 summarizes the ideal output codes for different input signals.
Table 8. 16-Bit Ideal Output Code versus Input Signal
INPUT SIGNAL, VIN
VAINxP - VAINxN
IDEAL OUTPUT CODE (1)
≥ FS (215 – 1) / 215
7FFFh
15
FS / 2
(1)
40
0001h
0
0000h
–FS / 215
FFFFh
≤ –FS
8000h
Excludes the effects of noise, INL, offset, and gain errors.
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9.5.1.5.2 ADC Data Word 24-Bit Format
For all other configurations, the ADC conversion data is set to a 24-bit data format. If the M1 pin is set to GND,
the device word is a 24-bit word length. However, if the M1 pin is set to IOVDD, the device data word is 32 bits.
With the 32-bit device word length, the last eight bits are used for the Hamming code when enabled, and are 0s
when the Hamming code is disabled. In these settings, the ADS131A0x outputs 24 bits of data per channel in
binary two's complement format, MSB first. The size of one code (LSB) is calculated using Equation 9:
1 LSB = (2 × VREF / Gain) / 224 = FS / 223
(9)
A positive full-scale input [VIN ≥ (FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFFFh and
a negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 800000h. The output clips at
these codes for signals that exceed full-scale.
Table 9 summarizes the ideal output codes for different input signals.
Table 9. 24-Bit Ideal Output Code versus Input Signal
INPUT SIGNAL, VIN
VAINxP - VAINxN
23
≥ FS (2
IDEAL OUTPUT CODE (1)
23
– 1) / 2
7FFFFFh
FS / 223
(1)
000001h
0
000000h
–FS / 223
FFFFFFh
≤ –FS
800000h
Excludes the effects of noise, INL, offset, and gain errors.
9.5.1.6 Hamming Code Error Correction
Hamming code is an optional data integrity feature used to correct for single-bit errors and detect multiple-bit
errors in each device word. Enable Hamming code with M2 pin settings (see Table 10 for details). Tie the M2 pin
to IOVDD through a < 1-kΩ resistor to enable Hamming code, or tie the M2 pin to GND through a < 1-kΩ resistor
to disable Hamming code.
Hamming code is only supported in 24-bit and 32-bit device word sizes. The ADS131A0x outputs 24 bits of
conversion data and an 8-bit Hamming code per channel when operating in 32-bit word size. The ADS131A0x
outputs 16 bits of conversion data and an 8-bit Hamming code per channel when operating in 24-bit word size.
Table 10 lists the configuration options of the M1 and M2 hardware pins and the associated device word size.
The status and command words are always 16 bits in length, reserving the eight least significant bits for
Hamming code.
Table 10. M2 Pin Setting Options
M2 STATE
IOVDD
GND
Float
M1 STATE
DEVICE WORD SIZE
CONVERSION DATA
HAMMING DATA
IOVDD
32 bits
24 bits
On: 8 bits
GND
24 bits
16 bits
On: 8 bits
Float
Not available
Not available
Not available
IOVDD
32 bits
24 bit + 8 zeroes
Off
GND
24 bits
24 bit
Off
Float
16 bits
16 bit
Off
N/A
Not available
Not available
Not available
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When enabled, the Hamming code byte is an additional 8-bits appended to the end of each device word on both
the device input on DIN and the output on DOUT, as shown in Figure 55. This additional eight bits are a
combination of five Hamming code (Hamming) bits, two checksum (ChS) bits, and one zero bit, as shown in
Figure 56.
32-Bit Command, Status
Device Word
16 Command, Status Bits
24-Bit Command, Status
Device Word
32-Bit ADC Data
Device Word
00h
8 HC Bits
16 Command, Status Bits
8 HC Bits
24 Data Bits
24-Bit ADC Data
Device Word
8 HC Bits
16 Data Bits
32-Bit CRC
Device Word
16 CRC Bits
8 HC Bits
00h
24-Bit CRC
Device Word
8 HC Bits
16 CRC Bits
8 HC Bits
Figure 55. Hamming Code on Each Device Word
2 ChS
Bits
5 Hamming Bits
Bits
0
Figure 56. Hamming Code Bit Allocation
CRC can be used with the Hamming code error correction enabled. When the Hamming code error correction is
enabled with CRC, the 8-bit Hamming data per device word is not protected by the CRC and is ignored in the
calculation. For example, if the 32-bit word size is used with Hamming code enabled, the CRC check only uses
the most significant 24 bits of each device word and ignores the last eight bits used for the Hamming code. The
CRC considers each device word as being 24 bits.
Table 11 shows the Hamming bit coverage for 24-bit data. The encoded data bit 00 corresponds to the LSB of
the data and bit 23 is the MSB of the data. The Hamming code bits are interleaved within the data bits. H0 is the
least significant bit of the Hamming code and H4 is the most significant bit.
Table 11. ADS131A0x Hamming Codes
HAMMING OR
DATA
Encoded data
bits
H0
D
D
D
D
D
D
D
D
D
D
D
D
D
H
D
D
D
D
D
D
D
H
D
D
D
H
D
H
H
00
01
02
03
04
05
06
07
08
09
10
11
12
04
13
14
15
16
17
18
19
03
20
21
22
02
23
01
00
x
x
H1
Parity bit
coverage
x
x
x
x
H2
x
x
H3
x
x
x
x
x
x
H4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
For more information about Hamming code implementation, see the Communication Methods for Data Integrity
Using Delta-Sigma Data Converters application report.
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9.5.1.7 Cyclic Redundancy Check (CRC)
Cyclic redundancy check (CRC) is a method for detecting errors in data communication between the device and
the master. The CRC uses a polynomial division with binary data and the remainder word becomes a check to
verify that the communication is correct. The ADS131A0x implements a standard CRC16-CCITT algorithm using
a polynomial of 11021h and an initial remainder of FFFFh.
The CRC word is the last device word in the DIN and DOUT data frame. The CRC device word is optional and is
enabled by the CRC_EN control bit in the D_SYS_CFG register. When enabled, a 16-bit CRC data check word
is present in the 16 most significant bits of the last device word in the data frame on both DIN and DOUT. Use
the CRC to provide detection of single and multiple bit errors during data transmission.
The CRC on all DIN commands is verified by the device prior to command execution except for the WREGS
command; see the WREGS: Write Multiple Registers section. The WREGS command does not check the CRC
prior to writing registers but does indicate if an error occurred. If the CRC on DIN is incorrect, F_CHECK in the
STAT_1 register is set to 1 and the input command does not execute (for all commands except WREGS). Fill the
unused device words on DIN with zeroes, placing the CRC word in the last device word.
The number of input CRC errors is counted and stored in the error count register. The register counts errors up
to 255 before rolling over to 0. The counter is cleared by reading the error count register.
9.5.1.7.1 Computing the CRC
The CRC byte is the 16-bit remainder of the bitwise exclusive-OR (XOR) operation of the data bytes by a CRC
polynomial. The CRC is based on the CRC-CCITT polynomial X16 + X12 + X5 + 1.
The binary coefficients of the polynomial are: 1 0001 0000 0010 0001. Calculate the CRC by dividing the data
bytes (with the XOR operation, thus excluding the CRC) with the polynomial and compare the calculated CRC
values to the provided CRC value. If the values do not match, then a data transmission error has occurred. In the
event of a data transmission error, read or write the data again.
The following shows a general procedure to compute the CRC value. Assume the shift register is 16 bits wide:
1. Set the polynomial value to 1021h
2. Set the shift register to FFFFh
3. For each byte in the data stream:
– Shift the next data byte left by eight bits and XOR the result with the shift register, placing the result into
the shift register
– Do the following eight times:
1. If the most significant bit of the shift register is set, shift the register left by one bit and XOR the result
with the polynomial, placing the result into the shift register
2. If the most significant bit of the shift register is not set, shift the register left by one bit
4. The result in the shift register is the CRC check value
NOTE
The CRC algorithm used here employs an assumed set X16 bit. This bit is divided out by
left-shifting the X16 bit 16 times out of the register prior to XORing with the polynomial
register. This process makes the CRC calculable with a 16-bit word size.
The Communication Methods for Data Integrity Using Delta-Sigma Data Converters application report provides
more information about CRC implementation, including example code.
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9.5.1.7.2 CRC With CRC_MODE = 1
The CRC is calculated using specific device words in the data frame determined by the CRC_MODE bit in the
D_SYS_CFG register. When the CRC_MODE = 1, the CRC is calculated using all of the bits sent to the device
preceding the CRC word. For DIN this includes any command word, device words, and any zero words sent to
the devices. For DOUT, all device words sent are used for the CRC. This includes the response word, device
words, and ADC data words. However, when Hamming codes are enabled, the Hamming byte of each word is
not used in the CRC calculation.
Figure 57 shows the device words used for calculating the CRC when the CRC_MODE is set to 1.
Data Frame
DIN words used to generate CRC
DIN
Command
Zero
Zero
Zero
Zero
CRC
Status
Channel 1
Data
Channel 2
Data
Channel 3
Data
Channel 4
Data
CRC
DOUT
CRC_MODE = 1
DOUT words used to generate CRC
Figure 57. CRC with CRC_MODE = 1
In addition to the CRC_MODE bit, the FIXED bit in the D_SYS_CFG register determines the number of words in
the communication frame. When the FIXED bit is 1, the ADS131A04 has six device words per frame and the
ADS131A02 has four device words per frame. When the FIXED bit is 0, each disabled ADC reduces the number
of device words in the communication frame by 1.
9.5.1.7.3 CRC with CRC_MODE = 0
When CRC_MODE = 0, the CRC is computed from only device words. For DIN, this includes commands and any
additional device words. However, any zero-valued words (not part of the command or device words) sent to
DIN, are not used for CRC calculation. For DOUT, all device words sent are used for the CRC. When Hamming
codes are enabled, the Hamming byte of each word is not used in the CRC calculation.
Figure 58 shows the device words used for calculating the CRC when the CRC_MODE is set to 0.
Data Frame
Device words used to generate CRC
Zero bit words not used to generate CRC
DIN
Command
Zero
Zero
Zero
Zero
CRC
Status
Channel 1
Data
Channel 2
Data
Channel 3
Data
Channel 4
Data
CRC
DOUT
CRC_MODE = 0
DOUT words used to generate CRC
Figure 58. CRC with CRC_MODE = 0
Similar to the CRC_MODE = 1 case, the FIXED bit determines the number of words in the communication frame.
When the FIXED bit is 1, the ADS131A04 has six device words per frame and the ADS131A02 has four device
words per frame. When the FIXED bit is 0, the number of device words depends on the number of ADCs
enabled.
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9.5.1.7.4 CRC Using the WREGS Command
As mentioned previously, the WREGS command does not check the CRC prior to writing registers but does
indicate if an error occurred. The CRC on all other DIN commands is verified by the device prior to command
execution.
The WREGS command causes the data frame to extend until the last register is written (see the WREGS: Write
Multiple Registers section for more details), thus requiring the CRC to be placed on DIN after the data frame
extension. The ADS131A0x places the CRC word on DOUT at the end of all ADC data. When sending the
WREGS command, the device words following the CRC on DOUT are padded with zeroes and are not included
in the CRC calculation. The device words that are not checked are highlighted in red.
Figure 59 shows the device words used for calculating the CRC when using the WREGS command.
Data Frame
DIN words used to generate CRC
DIN
DOUT
Command
Registers
1, 2
Registers
3, 4
Registers
5, 6
Registers
7, 8
Registers
9, 10
CRC
Status
Channel 1
Data
Channel 2
Data
Channel 3
Data
Channel 4
Data
CRC
Zero
Zero padding
DOUT words used to generate CRC
Figure 59. CRC Using the WREGS Command
The WREGS command does not check the CRC prior to writing registers. If CRC verification is desired before
executing a register write operation, the user should avoid using the WREGS command, and use individual
WREG commands instead.
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9.5.2 SPI Interface
The device SPI-compatible serial interface is used to read conversion data, read and write the device
configuration registers, and control device operation. Only CPOL = 0 and CPHA = 1 are supported. The interface
consists of five control lines (CS, SCLK, DIN, DOUT, and DRDY) but can be used with only four signals as well.
Three interface configurations are selectable in the ADS131A0x by M0 pin settings, as shown in Table 12:
asynchronous interrupt mode, synchronous master mode, and synchronous slave mode.
The M0 pin settings (listed in Table 12) are latched on power-up to set the interface. The same communication
lines are used for all three interface modes: SCLK, DIN, DOUT, and DRDY, with CS as an option in 5-wire mode.
An optional sixth signal (DONE) is available for use when chaining multiple devices, as discussed in the ADC
Frame Complete (DONE) section. Tie the M0 pin high to IOVDD through a < 1-kΩ resistor, low to GND through a
< 1-kΩ resistor, or leave the M0 pin floating.
Table 12. M0 Pin Settings
M0 STATE
INTERFACE MODE
IOVDD
Asynchronous interrupt mode
GND
Synchronous master mode
Float
Synchronous slave mode
9.5.2.1 Asynchronous Interrupt Mode
Asynchronous interrupt mode is the preferred mode for the operation of a single device. After the ADCs are
enabled and converting, the DRDY pin can be used as an interrupt for the master to read the conversion data.
The DRDY indication is output by the ADC at the data rate programmed into the device set by the modulator
clock (fMOD) and the OSR. Because the DRDY pin can be used as an interrupt, the device and the master do not
require a synchronous master clock.
The SPI uses five interface signals: CS, SCLK, DIN, DOUT, and DRDY in asynchronous interrupt mode. Use the
four interface lines, CS, SCLK, DIN, and DOUT to read conversion data, read and write registers, and send
commands to the ADS131A0x. Use the DRDY output as a status signal to indicate when new conversion data
are ready. Figure 60 shows typical device connections for the ADS131A0x to a host microprocessor or digital
signal processor (DSP) in asynchronous interrupt mode.
IOVDD
IOVDD
Device
CS
M0
Master
CLK
SCLK
CLKIN
CS
MPU, DSP
SCLK
DIN
MOSI
DOUT
MISO
DRDY
IRQ
DONE
Master
Slave
Figure 60. Asynchronous Interrupt Mode Device Connections
9.5.2.1.1 Chip Select (CS)
Chip select (CS) is an active-low input that selects the device for SPI communication and controls the beginning
and end of a data frame in asynchronous interrupt mode. CS must remain low for the entire duration of the serial
communication to complete a command or data readback. When CS is taken high, the serial interface (including
the data frame) is reset, SCLK and DIN are ignored, and DOUT enters a high-impedance state. DRDY transitions
low when data conversion is complete, regardless of whether CS is high or low. As with other SPI devices,
multiple ADS131A0x devices in asynchronous interrupt mode can be controlled at the same time but each device
requires its own CS line.
9.5.2.1.2 Serial Clock (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input and is used to clock data into and out of the device on
DIN and DOUT, respectively. SCLKs can be sent continuously or in byte increments to the ADC. Even though
the input has hysteresis, keeping the SCLK signal as clean as possible is recommended to prevent glitches from
accidentally shifting data. When the serial interface is idle, hold SCLK low.
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9.5.2.1.3 Data Input (DIN)
Use the data input (DIN) pin and SCLK to communicate with the ADS131A0x (user commands and register
data). The device latches data on DIN on the SCLK falling edge. The command or register write takes effect
following completion of the data frame.
9.5.2.1.4 Data Output (DOUT)
Use the data output (DOUT) pin with SCLK to read conversion and register data from the ADS131A0x. Data on
DOUT are shifted out on the SCLK rising edge. DOUT goes to a high-impedance state when CS is high or after
the least significant bit is shifted from the output shift register (see the th(LSB) specification in the Switching
Characteristics: Asynchronous Interrupt Interface Mode table).
9.5.2.1.5 Data Ready (DRDY)
DRDY indicates when a new conversion result is ready for retrieval. When DRDY transitions from high to low,
new conversion data are ready. The DRDY signal remains low for the duration of the data frame and returns high
either when CS returns high (signaling the completion of the frame), or prior to new data being available. The
high-to-low DRDY transition occurs at the set data rate regardless of the CS state. If data are not completely
shifted out when new data are ready, the DRDY signal toggles high for a duration of 0.5 × tMOD and back low.
The device sets the F_DRDY bit in the STAT_1 register indicating that the DOUT output shift register is not
updated with the new conversion result. Figure 61 shows an example of new data being ready before previous
data are shifted out, causing the new conversion result to be lost. The DRDY pin is always actively driven, even
when CS is high.
fDATA
DRDY
New data are lost,
F_DRDY = 1.
CS
Status
DOUT
Channel 1
Data
Channel 2
Data
Channel 3
Data
Figure 61. Asynchronous Interrupt Mode Conversion Update During a Read Operation
9.5.2.1.6 Asynchronous Interrupt Mode Data Retrieval
Figure 62 shows the relationship between DRDY, CS, SCLK, DIN, and DOUT during data retrieval. The high-tolow DRDY transition indicates that new data are available. Transition CS from high to low to begin a data frame.
At the end of the data frame, CS returns high and brings DRDY high.
DRDY
§
CS
§
SCLK
§
DIN
§ §
DOUT
§ §
Figure 62. DRDY Behavior with Data Retrieval in Asynchronous Interrupt Mode
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9.5.2.2 Synchronous Master Mode
Synchronous master mode can be used with the ADS131A0x device as the master, using the microcontroller as
the slave to read the data after each conversion. Devices in synchronous master mode and in asynchronous
interrupt mode may be used to synchronize the conversions for slave devices set in synchronous slave mode.
The SPI uses four interface signals: SCLK, DIN, DOUT, and DRDY in synchronous master mode. Connect the
CS signal to the DONE signal when using a single device in synchronous master mode. The SCLK, DRDY, and
DOUT signals are outputs from the device. Provide DIN from the microprocessor (MPU) or DSP using the SCLK
edge timing of the ADS131A0x. Figure 63 shows typical device connections for the ADS131A0x in synchronous
master mode to a host microprocessor or DSP.
IOVDD
Device
MPU, DSP
CS
M0
Master
CLK
CLKIN
CS
SCLK
SCLK
DIN
MOSI
DOUT
MISO
DRDY
IRQ
DONE
Slave
Master
Figure 63. Synchronous Master Mode Device Connections
9.5.2.2.1 Serial Clock (SCLK)
SCLK is the serial peripheral interface (SPI) serial clock. Use SCLK to shift in commands and shift out data from
the device, similar to the description provided in the Asynchronous Interrupt Mode section. The SCLK output
equals the ICLK derived from the input clock, CLKIN, using the clock divider control in the CLK1 register. SCLKs
continuously output at the ICLK rate with the beginning of a data frame set by a DRDY falling edge.
9.5.2.2.2 Data Input (DIN)
Use the data input (DIN) pin and SCLK to communicate with the ADS131A0x (user commands and register
data). The device latches data on DIN on the SCLK falling edge. The command or register write takes effect
following completion of the data frame.
9.5.2.2.3 Data Output (DOUT)
Use the data output pin (DOUT) with SCLK to read conversion and register data from the ADS131A0x. Data on
DOUT are shifted out on the SCLK rising edge. DOUT goes to a high impedance state when CS is high or after
the least significant bit is shifted from the output shift register (see the th(LSB) specification in the Switching
Characteristics: Synchronous Master Interface Mode table).
9.5.2.2.4 Data Ready (DRDY)
The DRDY signal is an output that functions as a new data ready indicator and as the control for the start and
stop of a data frame. A high-to-low transition of DRDY from the ADC indicates that the output shift register is
updated with new data and begins a new data frame. Subsequent SCLKs shift out the first device word on
DOUT.
9.5.2.2.5 Chip Select (CS)
For single device operation in synchronous master mode, tie the CS line to the DONE output signal.
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9.5.2.2.6 Synchronous Master Mode Data Retrieval
Figure 64 shows the relationship between DRDY, DOUT, DIN, and SCLK during data retrieval in synchronous
master mode. The high-to-low DRDY transition from the ADS131A0x starts a data frame and indicates that new
data are available. DIN and DOUT transition on the SCLK rising edge. After the LSB is shifted out DRDY returns
high, completing the data frame. The ICLK speed must be fast enough to shift out the required bits before new
data are available because ICLK determines the SCLK output rate, as described in the Serial Clock (SCLK)
section. Tie the CS signal to the DONE signal in single device synchronous master mode.
§
DRDY
SCLK
§
DIN
§ §
DOUT
§ §
Figure 64. Data Retrieval in Synchronous Master Mode
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9.5.2.3 Synchronous Slave Mode
Synchronous slave mode can be used when there is a synchronous master clock and a master available
control the slave device. This mode of operation can be best used to control one or more slave devices and
collect data from all devices similar to a daisy-chain configuration. The master can be a device used
asynchronous interrupt mode, a device used in synchronous master mode, or a microcontroller. Regardless
the selected interface type, the master must have a synchronous clock and must be able to send clocks
exactly the proper timing to maintain synchronization.
to
to
in
of
at
The SPI uses five interface signals: CS, SCLK, DIN, DOUT, and DRDY in synchronous slave mode. The CS,
SCLK, DIN, and DRDY signals are inputs to the device and the DOUT signal is an output. DRDY can be tied
directly to CS (for a total of four interface lines) or can be used independently as a fourth input signal for
synchronization to an external event; see the Data Ready (DRDY) section for more information on using the
DRDY line for synchronization. Figure 65 shows typical device connections for the ADS131A0x in synchronous
slave mode to a host microprocessor or DSP.
IOVDD
Device
CS
CS
Float
Master
CLK
M0
SCLK
CLKIN
MPU, DSP
SCLK
DIN
MOSI
DOUT
MISO
DRDY
nIRQ
DONE
Master
Slave
Figure 65. Synchronous Slave Mode Device Connections
9.5.2.3.1 Chip Select (CS)
Chip select (CS) is an active-low input that selects the device for SPI communication and controls the beginning
and end of a data frame in synchronous slave mode. CS must remain low for the entire duration of the serial
communication to complete a command or data readback. When CS is taken high, the serial interface (including
the data frame) is reset, SCLK and DIN are ignored, and DOUT enters a high-impedance state. Tie CS directly to
the DRDY input signal to minimize communication lines as long as the synchronization timing in Figure 5 is met.
Otherwise, the CS line can be used independent of DRDY.
9.5.2.3.2 Serial Clock (SCLK)
SCLK is the SPI serial clock. Use SCLK to shift in commands on DIN and shift out data from the device on
DOUT, similar to the description in the Asynchronous Interrupt Mode section.
If the SCLK source is free-running, the SCLK input signal can be set as the ADC ICLK, removing the need of a
separate CLKIN. The CLKSRC bit in the CLK1 register controls the source for the ADC ICLK. The modulator
clock is derived from the ICLK using the ICLK_DIV[2:0] bits in the CLK2 register; see Figure 35 for a diagram of
how SCLK is routed into the device when serving as the ICLK. Setting SCLK as the internal ICLK requires that
clocks are sent continuously without any delay or stop periods. Care must be taken to prevent glitches on SCLK
at all times.
9.5.2.3.3 Data Input (DIN)
Use the data input pin (DIN) along with SCLK to communicate with the ADS131A0x (user commands and
register data). The device latches data on DIN on the SCLK falling edge. The command or register write takes
effect following the completion of the data frame.
9.5.2.3.4 Data Output (DOUT)
Use the data output pin (DOUT) with SCLK to read conversion and register data from the ADS131A0x. Data on
DOUT are shifted out on the SCLK rising edge. DOUT goes to a high impedance state when CS is high or after
the least significant bit is shifted from the output shift register (see the th(LSB) specification in the Switching
Characteristics: Synchronous Slave Interface Mode table).
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9.5.2.3.5 Data Ready (DRDY)
In synchronous slave mode, DRDY is an input signal that must be pulsed at the device set data rate. The DRDY
input signal is compared to an internally-generated data update signal to verify that these two signals are
synchronized. A high-to-low DRDY transition is expected at the programmed data rate or at multiples thereof. In
the event of an unexpected DRDY input pulse, the F_RESYNC bit flags in the STAT_1 register and the ADC
digital filter resets. Use the DRDY input signal as a synchronization method to align new data ready with an
external event or with a second ADS131A0x device. See the Timing Requirements: Synchronous Slave Interface
Mode table for the timing requirements of the DRDY input in synchronous slave mode.
9.5.2.3.6 Synchronous Slave Mode Data Retrieval
Figure 66 shows the relationship between DRDY, CS, SCLK, DIN, and DOUT during data retrieval in
synchronous slave mode. In synchronous slave mode, the high-to-low DRDY transition sent from the processor
must be synchronized with the data rate programmed, or multiples thereof, to avoid a digital filter reset. The data
frame begins with a high-to-low CS transition with or after DRDY transitions low. The DIN and DOUT signals
transition on the SCLK rising edge. DRDY can return high at any point but must maintain a high-to-low transition
at the set data rate to avoid a resynchronization event. To minimize interface lines, the CS signal can be tied
directly to the DRDY signal; the timing specifications in the Timing Requirements: Synchronous Slave Interface
Mode table are still maintained.
tDATA
DRDY
CS
SCLK
DIN
DOUT
Figure 66. Data Retrieval in Synchronous Slave Mode
9.5.2.4 ADC Frame Complete (DONE)
The DONE output signal is an optional interface line that enables chaining multiple devices together to increase
channel count. Connect the DONE signal to the CS of the next chained data converter in the system to control
the start and stop of the subsequent converter interface. The DONE signal transitions from high to low following
the LSB being shifted out. The delay time from the SCLK falling edge shifting out the LSB to the high-to-low
DONE transition is configured using the DNDLY[1:0] bits in the D_SYS_CFG register. See Figure 6 for details of
the signals and timings of the DONE signal.
For single device operation, configure DONE in the following ways:
• In asynchronous slave mode, either float the DONE output signal or pull the DONE output signal to IOVDD
through a 100-kΩ pullup resistor.
• In synchronous master mode, tie the DONE output signal to the CS input line.
• In synchronous slave mode, either float the DONE output signal or pull the DONE output signal to IOVDD
through a 100-kΩ pullup resistor.
See the Multiple Device Configuration section for more information on using the DONE signal for multiple device
chaining.
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9.5.3 SPI Command Definitions
The ADS131A0x device operation is controlled and configured through ten commands. Table 13 summarizes the
available commands. The commands are stand-alone, 16-bit words and reside in the first device word of the data
frame. Write zeroes to the remaining LSBs when operating in either 24-bit or 32-bit word sizes because each
command is 16-bits in length. The commands are decoded following the completion of a data frame and take
effect immediately. Each recognized command is acknowledged with a status output in the first device word of
the next data frame.
Table 13. Command Definitions
COMMAND
DESCRIPTION
DEVICE WORD
ADDITIONAL
DEVICE WORD
COMMAND
STATUS
RESPONSE
SYSTEM COMMANDS
NULL
Null command
0000h
STATUS
RESET
Software reset
0011h
READY
STANDBY
Enter low-power standby mode
0022h
ACK = 0022h
WAKEUP
Wake-up from standby mode
0033h
ACK = 0033h
LOCK
Places the interface in a locked state and
ignores all commands except NULL, RREGS,
and UNLOCK
0555h
ACK = 0555h
UNLOCK
Brings the device out of an unconfigured POR
state or a locked state
0655h
ACK = 0655h
REGISTER WRITE AND READ COMMANDS
RREG
Read a single register at address a aaaa
(001a aaaa 0000
0000)b
REG
RREGS
Read (nnnn nnnn + 1) registers starting at
address a aaaa
(001a aaaa nnnn
nnnn)b
RREGS
WREG
Write a single register at address a aaaa with
data dddd dddd
(010a aaaa dddd
dddd)b
REG (updated
register)
WREGS
Write (nnnn nnnn + 1) registers beginning at
address a aaaa. Additional device words are
required to send data (dddd dddd) to register
address (a) and data (eeee eeee) to register
address (a+1). Each device word contains data
for two registers.
The data frame size is extended by (n / 2) device
words to allow for command completion.
(011a aaaa nnnn
nnnn)b
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(dddd dddd eeee
eeee)b
ACK =
(010a_aaaa_nnnn_n
nnn)b
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A command status response is 16 bits in length, located in the MSBs of the first device word in the DOUT data
frame. The response indicates that the command in the previous data frame is executed. When operating in 24bit or 32-bit word size modes, the remaining LSBs of the command status response device word read back as
zero unless Hamming code is used. An example showing the acknowledgment to a user input command is
shown in Figure 67.
Data Frame
DIN
DOUT
User Command
Status Response
User Command
Channel Data
Status Response
Channel Data
Figure 67. User Command Status Response
Some user commands require multiple data words over multiple device frames. This section describes the
commands and details which commands require multiple data words.
The command status responses to the user commands are listed in Table 14. Every data frame begins with one
of the listed command status responses on DOUT.
Table 14. Command Status Responses
DESCRIPTION
DEVICE WORD
ADDITIONAL
DEVICE WORD
READY
Fixed-status word stating that the device is in a power-up ready
state or standby mode and is ready for use. The least significant
byte of the device word indicates the address 0 hardware device ID
code (dd). In the READY state, the device transmits only one word,
allowing a 1-word command to be received. An UNLOCK command
must be issued before the device responds to other commands.
(FFdd)h
—
ACK
Acknowledgment response. The device has received and executed
the command and repeats the received command (cccc) as the
command status response. (A NULL input does not result in an ACK
response).
(cccc)h
—
STATUS/REG
Status byte update. Register address a aaaa contains data dddd
dddd. This command status response is the response to a
recognized RREGS or WREG command.
An automatic status update of register address (02h) is sent when
the NULL command is sent.
(001a aaaa dddd
dddd)b
—
RREGS
Response for read (nnnn nnnn + 1) registers starting at address a
aaaa. Data for two registers are output per device word. If the
resulting address extends beyond the usable register space, zeroes
are returned for remaining non-existent registers. During an RREGS
response, any new input commands are ignored until the RREGS
status response completes.
(011a aaaa nnnn
nnnn)b
(dddd dddd eeee
eeee)b
RESPONSE
SYSTEM RESPONSE
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9.5.3.1 NULL: Null Command
The NULL command has no effect on ADC registers or data. Rather than producing an ACK response on DOUT,
the command issues a register readback of the STAT_1 register to monitor for general fault updates. An example
of the response to a NULL command is shown in Figure 68.
Data Frame
DIN
NULL (0000h)
DOUT
Status Response
User Command
Channel Data
REG(STAT_1)
Channel Data
Figure 68. NULL Command Status Response
9.5.3.2 RESET: Reset to POR Values
The RESET command places the ADC into a power-on reset (POR) state, resetting all user registers to the
default states. The reset begins following the completion of the frame at the rising edge of CS. When reset
completes, the ADC enters a reset locked state and outputs the READY status response on DOUT as the
command status response. An example of the response to a RESET command is shown in Figure 69.
Data Frame
DIN
RESET (0011h)
DOUT
Status Response
NULL
Channel Data
READY (FFxx)
Reset Delay
Locked State
Figure 69. RESET Command Status Response
9.5.3.3 STANDBY: Enter Standby Mode
The STANDBY command places the ADC in a low-power standby mode, halting conversions. The digital
interface remains powered, allowing all registers to retain the previous states. When in standby mode, writing
and reading from registers is possible and any programmable bits that activate circuitry take effect in the device
after the WAKEUP command is issued. The command status response following a STANDBY command is
0022h. In standby mode, the command status response is dependent on the user command that is sent. All ADC
channels must be disabled by writing to the ADC_ENA register prior to entering standby mode to reduce current
consumption. An example for the response to the STANDBY command and behavior when in standby mode is
shown in Figure 70.
Data Frame
DIN
STANDBY
(0022h)
DOUT
Status
Response
Channel Data
User Command
NULL
WAKEUP
(0033h)
ACK (0022h)
Status
Response
RREG
(STAT_1)
Standby
Standby
Standby
Figure 70. STANDBY Command Status Response
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9.5.3.4 WAKEUP: Exit Standby Mode
The WAKEUP command brings the ADC out of standby mode. The ADC channels must be enabled by writing to
the ADC_ENA register before bringing the device out of standby mode. Allow enough time for all circuits in
standby mode to power-up (see the Electrical Characteristics table for details). The command status response
following a WAKEUP command is 0033h. An example showing the response to exiting standby mode using the
WAKEUP command is shown in Figure 71.
Data Frame
DIN
DOUT
NULL
WAKEUP (0033h)
RREG (STAT_1)
RREG (STAT_1)
ACK (0033h)
Standby
Standby
Normal
Data
Figure 71. WAKEUP Command Status Response
9.5.3.5 LOCK: Lock ADC Registers
The LOCK command places the converter interface in a locked state where the interface becomes unresponsive
to most input commands. The UNLOCK, NULL, RREG, and RREGS commands are the only commands that are
recognized when reading back data. Following the LOCK command, the first DOUT status response reads 0555h
followed by the command status response of a NULL command (by reading the STAT_1 register). An example
showing the response to sending a LOCK command and entering a register locked state is shown in Figure 72.
Data Frame
DIN
DOUT
LOCK (0555h)
NULL
Status Response
Data
ACK (0555h)
NULL
Data
Locked
ACK (STAT_1)
Data
Locked
Figure 72. LOCK Command Status Response
9.5.3.6 UNLOCK: Unlock ADC Registers
The UNLOCK command brings the converter out of the locked state, allowing all registers to be accessed in the
next data frame. The command status response associated with the UNLOCK command is 0655h. An example
of bringing the interface out of the locked state using the UNLOCK command is shown in Figure 73.
Data Frame
DIN
NULL
DOUT
ACK (STAT_1)
UNLOCK (0655h)
Data
Locked
ACK (STAT_1)
User Command
Data
Locked
ACK (0655h)
Data
Unlocked
Figure 73. UNLOCK Command Status Response
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9.5.3.6.1 UNLOCK from POR or RESET
When powering up the device or coming out of a power-on reset (POR) state, the ADC does not accept any
commands. During this time, the host can poll the ADC until the command status response reads back FFDDh
(DD denotes the channel count defined by the NU_CH[3:0] bits in the ID_MSB register), indicating that the ADC
power-on reset cycle is complete and that the ADC is ready to accept commands. Use the UNLOCK command
to enable the SPI interface and begin communication with the device. The command status response associated
with the UNLOCK command is 0655h. Figure 74 shows an example of unlocking the device after POR using the
UNLOCK command.
POR_EVENT
Data Frame
POR_EVENT
DIN
NULL
UNLOCK (0655h)
User Command
READY (FFxx)
READY (FFxx)
ACK (0655h)
POR_EVENT
DOUT
Locked
Locked
Data
Unlocked
Figure 74. UNLOCK from a POR Command Status Response
9.5.3.7 RREG: Read a Single Register
The RREG command reads register data from the ADC. RREG is a 16-bit command containing the command,
the register address, and the number of registers to be to read. The command details are shown below:
First byte: 001a aaaa, where a aaaa is the register address
Second byte: 00h
The ADC executes the command upon completion of the data frame and the register data transmission begins
on the first device word of the following data frame. The response contains an 8-bit acknowledgment byte with
the register address and an 8-bit data byte with the register content. Figure 75 shows an example command
response to a single register read.
Data Frame
DIN
DOUT
RREG REG(a)
Status Word
RREG REG(b)
Data
REG(a)
NULL
Data
REG(b)
Data
Figure 75. RREG Command Status Response (Single Register Read)
9.5.3.8 RREGS: Read Multiple Registers
For a multiple register read back, the command status response exceeds the 16-bit reserved device word space,
causing an overflow to additional command status words. The first command status response is an
acknowledgment of multiple registers to be read back and the additional command status responses shift out
register data. The command status response details are shown below:
First command status response: 011a aaaa nnnn nnnn, where a aaaa is the starting register address and
nnnn nnnn is the number of registers to read minus one (n-1).
Additional command status responses: dddd dddd eeee eeee , where dddd dddd is the register data from the
first register read back and eeee eeee is the register data from the second read back register.
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The number of additional command status responses across multiple frames is dependent on the number of
registers to be read back. During a RREGS command status response, any new input commands are ignored
until the command completes by shifting out all necessary command status responses. If the resulting address
extends beyond the usable register space, zeroes are returned for any remaining non-existent registers. An
example of the command response to reading four registers using a RREGS command is shown in Figure 76.
Data Frame
RREGS (2003h)
DIN
Status Word
DOUT
NULL
Data
Ack (RREGS)
NULL
Data
REG (00h+01h)
NULL
REG (02h+03h)
Data
Data
Figure 76. RREGS Command Status Response (Multiple Register Read)
9.5.3.9 WREG: Write Single Register
The WREG command writes data to a single register. The single register write command is a two-byte command
containing the address and the data to write to the address. The command details are shown below:
First byte: 010a aaaa, where a aaaa is the register address.
Second byte: dddd dddd, where dddd dddd is the data to write to the address.
The resulting command status response is a register read back from the updated register. An example of a
single register write and response is shown in Figure 77.
Data Frame
DIN
DOUT
WREG REG(a)
Status Response
WREG REG(b)
Data
REG(a)
NULL
Data
REG(b)
Data
Figure 77. WREG Command Status Response (Single Register Write)
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9.5.3.10 WREGS: Write Multiple Registers
The WREGS command writes data to multiple registers. The command steps through each register
incrementally, thus allowing the user to incrementally write to each register. This process extends the data frame
by (n) device words to complete the command. If the resulting address extends beyond the usable register
space, any following data for non-existent registers are ignored. The 16 bits contained in the first device word
contain the command, the starting register address, and the number of registers to write, followed by additional
device words for the register data. The command details are shown below:
First user command device word: 011a aaaa nnnn nnnn, where a aaaa is the starting register address and
nnnn nnnn is the number of registers to write minus one (n-1).
Additional user command device words: dddd dddd eeee eeee, where dddd dddd is the data to write to the
first register and eeee eeee is the register data for the second register.
The user command device word uses the 16 MSBs regardless of word length (that is, only the 16 MSBs are
used in 16-bit, 24-bit, or 32-bit word lengths). When additional command device words are required, only a
maximum of two 8-bit registers can be written per command and any additional LSBs beyond 16 bits are ignored.
The command status response for the WREGS command is 010a aaaa nnnn nnnn, where a aaaa is the starting
register address and nnnn nnnn is the number of registers written minus one. An example of a multiple register
write and the command status response is shown in Figure 78.
Data Frame
DIN
WREGS
Command
REG (a+b)
REG (c+d)
DOUT
Status Response
Channel 1 Data
Channel 2 Data
Data
REG (m+n)
NULL
00h
WREGS
Response
Data
Figure 78. WREGS Command Status Response (Multiple Register Write)
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9.6 Register Maps
Table 15. Register Map
ADDRESS
(Hex)
REGISTER NAME
DEFAULT
SETTING
REGISTER BITS
7
6
5
4
3
2
1
0
F_CHECK
Read Only ID Registers
00h
ID_MSB
xxh
NU_CH[7:0]
01h
ID_LSB
xxh
REV_ID[7:0]
02h
STAT_1
00h
0
F_OPC
F_SPI
F_ADCIN
F_WDT
F_RESYNC
F_DRDY
03h
STAT_P
00h
0
0
0
0
F_IN4P
F_IN3P
F_IN2P
F_IN1P
04h
STAT_N
00h
0
0
0
0
F_IN4N
F_IN3N
F_IN2N
F_IN1N
05h
STAT_S
00h
0
0
0
0
0
F_STARTUP
F_CS
F_FRAME
06h
ERROR_CNT
00h
07h
STAT_M2
xxh
0
0
08h
Reserved
00h
0
0
0
0
0
0
0
0
09h
Reserved
00h
0
0
0
0
0
0
0
0
00h
0
0
0
0
0
0
0
0
1
VREF_4V
INT_REFEN
Status Registers
ER[7:0]
M2PIN[1:0]
M1PIN[1:0]
M0PIN[1:0]
User Configuration Registers
0Ah
(1)
Reserved
0Bh
A_SYS_CFG
60h
VNCPEN
HRM
0Ch
D_SYS_CFG
3Ch
WDT_EN
CRC_MODE
0Dh
CLK1
08h
CLKSRC
0
0Eh
CLK2
86h
0Fh
ADC_ENA
00h
0
0
0
0
10h
Reserved
00h
0
0
0
0
0
11h
ADC1
00h
0
0
0
0
0
GAIN1_[2:0]
12h
ADC2
00h
0
0
0
0
0
GAIN2_[2:0]
13h
ADC3 (1)
00h
0
0
0
0
0
GAIN3_[2:0]
14h
ADC4 (1)
00h
0
0
0
0
0
GAIN4_[2:0]
DNDLY[1:0]
0
ICLK_DIV[2:0]
COMP_TH[2:0]
HIZDLY[1:0]
0
FIXED
CLK_DIV[2:0]
0
CRC_EN
0
OSR[3:0]
ENA[3:0]
0
0
0
This register is for the ADS131A04 only. This register is reserved for the ADS131A02.
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9.6.1 User Register Description
9.6.1.1 ID_MSB: ID Control Register MSB (address = 00h) [reset = xxh]
This register is programmed during device manufacture to indicate device characteristics.
Figure 79. ID_MSB Register
7
6
5
4
3
2
1
0
1
0
NU_CH[7:0]
R-xxh
LEGEND: R = Read only; -n = value after reset
Table 16. ID_MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
NU_CH[7:0]
R
xxh
Channel count identification bits.
These bits indicate the device channel count.
02h : 2-channel device
04h : 4-channel device
9.6.1.2 ID_LSB: ID Control Register LSB (address = 01h) [reset = xxh]
This register is reserved for future use.
Figure 80. ID_LSB Register
7
6
5
4
3
2
REV_ID[7:0]
R-xxh
LEGEND: R = Read only; -n = value after reset
Table 17. ID_LSB Register Field Descriptions
60
Bit
Field
Type
Reset
Description
7:0
REV_ID[7:0]
R
xxh
Reserved.
These bits indicate the revision of the device and are subject to change
without notice.
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9.6.1.3 STAT_1: Status 1 Register (address = 02h) [reset = 00h]
This register contains general fault updates. This register is automatically transferred on the command status
response when the NULL command is sent.
Figure 81. STAT_1 Register
7
0
R-0h
6
F_OPC
R-0h
5
F_SPI
R-0h
4
F_ADCIN
R-0h
3
F_WDT
R-0h
2
F_RESYNC
R-0h
1
F_DRDY
R-0h
0
F_CHECK
R-0h
LEGEND: R = Read only; -n = value after reset
Table 18. STAT_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
R
0h
Reserved.
Always read 0.
6
F_OPC
R
0h
Command fault.
This bit indicates that a received command is not recognized as valid and
the command is ignored. This bit auto-clears on a STAT_1 data transfer,
unless the condition remains.
When in a locked state, this bit is set if any command other than LOCK,
UNLOCK, NULL, or RREGS is written to the device.
0 : No fault has occurred
1 : Possible invalid command is ignored
5
F_SPI
R
0h
SPI fault.
This bit indicates that one of the status bits in the STAT_S register is set.
Read the STAT_S register to clear the bit.
0 : No fault has occurred
1 : A bit in the STAT_S register is set high
4
F_ADCIN
R
0h
ADC input fault.
This bit indicates that one of the ADC input fault detection bits in the
STAT_P or STAT_N register is set. Read the STAT_P and STAT_N
registers to clear the bit.
0 : No fault has occurred
1 : A bit in the STAT_P or STAT_N register is set high
3
F_WDT
R
0h
Watchdog timer timeout.
This bit indicates if the watchdog timer times out before a new data frame
transfer occurs.
0 : No fault has occurred
1 : Timer has run out (resets following register read back)
2
F_RESYNC
R
0h
Resynchronization fault.
This bit is set whenever the signal path is momentarily reset resulting from
a DRDY synchronization event. This fault is only possible in synchronous
slave mode.
0 : Devices are in sync
1 : Signal path is momentarily reset to maintain synchronization
1
F_DRDY
R
0h
Data ready fault.
This bit is set if data shifted out from the previous result are not complete
by the time new ADC data are ready. This bit auto-clears on a STAT_1
transfer, unless the condition remains.
0 : Data read back complete before new data update
1 : New data update during DOUT data transmission
0
F_CHECK
R
0h
DIN check fault.
This bit is set if either of the following conditions are detected:
•
Uncorrectable Hamming error correction state is determined for any
DIN word transfer when Hamming code is enabled.
•
CRC check word on DIN fails. The input command that triggered this
error is ignored.
This bit auto-clears on a STAT_S transfer, unless the condition remains.
0 : No error in DIN transmission
1 : DIN transmission error
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9.6.1.4 STAT_P: Positive Input Fault Detect Status Register (address = 03h) [reset = 00h]
This register stores the status of whether the positive input on each channel exceeds the threshold set by the
COMP_TH[2:0] bits; see the Input Overrange and Underrange Detection section for details.
Figure 82. STAT_P Register
7
0
R-0h
6
0
R-0h
5
0
R-0h
4
0
R-0h
3
F_IN4P
R-0h
2
F_IN3P
R-0h
1
F_IN2P
R-0h
0
F_IN1P
R-0h
LEGEND: R = Read only; -n = value after reset
Table 19. STAT_P Register Field Descriptions
(1)
Bit
Field
Type
Reset
Description
7:4
Reserved
R
0h
Reserved.
Always read 0h.
3
F_IN4P (1)
R
0h
AIN4P threshold detect.
0 : The channel 4 positive input pin does not exceed the set threshold
1 : The channel 4 positive input pin exceeds the set threshold
2
F_IN3P (1)
R
0h
AIN3P threshold detect.
0 : The channel 3 positive input pin does not exceed the set threshold
1 : The channel 3 positive input pin exceeds the set threshold
1
F_IN2P
R
0h
AIN2P threshold detect.
0 : The channel 2 positive input pin does not exceed the set threshold
1 : The channel 2 positive input pin exceeds the set threshold
0
F_IN1P
R
0h
AIN1P threshold detect.
0 : The channel 1 positive input pin does not exceed the set threshold
1 : The channel 1 positive input pin exceeds the set threshold
This bit is not available in the ADS131A02 and always read 0.
9.6.1.5 STAT_N: Negative Input Fault Detect Status Register (address = 04h) [reset = 00h]
This register stores the status of whether the negative input on each channel exceeds the threshold set by the
COMP_TH[2:0] bits; see the Input Overrange and Underrange Detection section for details.
Figure 83. STAT_N Register
7
0
R-0h
6
0
R-0h
5
0
R-0h
4
0
R-0h
3
F_IN4N
R-0h
2
F_IN3N
R-0h
1
F_IN2N
R-0h
0
F_IN1N
R-0h
LEGEND: R = Read only; -n = value after reset
Table 20. STAT_N Register Field Descriptions
(1)
62
Bit
Field
Type
Reset
Description
7:4
Reserved
R
0h
Reserved.
Always read 0h.
3
F_IN4N (1)
R
0h
AIN4N threshold detect.
0 : The channel 4 negative input pin does not exceed the set threshold
1 : The channel 4 negative input pin exceeds the set threshold
2
F_IN3N (1)
R
0h
AIN3N threshold detect.
0 : The channel 3 negative input pin does not exceed the set threshold
1 : The channel 3 negative input pin exceeds the set threshold
1
F_IN2N
R
0h
AIN2N threshold detect.
0 : The channel 2 negative input pin does not exceed the set threshold
1 : The channel 2 negative input pin exceeds the set threshold
0
F_IN1N
R
0h
AIN1N threshold detect.
0 : The channel 1 negative input pin does not exceed the set threshold
1 : The channel 1 negative input pin exceeds the set threshold
This bit is not available in the ADS131A02 and always read 0.
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9.6.1.6 STAT_S: SPI Status Register (address = 05h) [reset = 00h]
This register indicates the detection of SPI fault conditions.
Figure 84. STAT_S Register
7
0
R-0h
6
0
R-0h
5
0
R-0h
4
0
R-0h
3
0
R-0h
2
F_STARTUP
R-0h
1
F_CS
R-0h
0
F_FRAME
R-0h
LEGEND: R = Read only; -n = value after reset
Table 21. STAT_S Register Field Descriptions
Bit
Field
Type
Reset
Description
7:3
Reserved
R
00h
Reserved.
Always read 00h.
2
F_STARTUP
R
0h
ADC startup fault.
This bit indicates if an error is detected during power-up. This bit clears
only when power is recycled.
0 : No fault has occurred
1 : A fault has occurred
1
F_CS
R
0h
Chip-select fault.
This bit is set if CS transitions when the SCLK pin is high. This bit autoclears on a STAT_S transfer, unless the condition remains.
0 : CS is asserted or deasserted when SCLK is low
1 : CS is asserted or deasserted when SCLK is high
0
F_FRAME
R
0h
Frame fault.
This bit is set if the device detects that not enough SCLK cycles are sent in
a data frame for the existing mode of operation. This bit auto-clears on a
STAT_S transfer, unless the condition remains.
0 : Enough SCLKs are sent per frame
1 : Not enough SCLKs are sent per frame
9.6.1.7 ERROR_CNT: Error Count Register (address = 06h) [reset = 00h]
This register counts the Hamming and CRC errors. This register is cleared when read.
Figure 85. ERROR_CNT Register
7
ER7
R-0h
6
ER6
R-0h
5
ER5
R-0h
4
ER4
R-0h
3
ER3
R-0h
2
ER2
R-0h
1
ER1
R-0h
0
ER0
R-0h
LEGEND: R = Read only; -n = value after reset
Table 22. ERROR_CNT Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
ER[7:0]
R
00h
Error tracking count.
These bits count the number of Hamming and CRC errors on the input.
The counter saturates if the number of errors exceeds 255, FFh. This
register is cleared when read.
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9.6.1.8 STAT_M2: Hardware Mode Pin Status Register (address = 07h) [reset = xxh]
This register indicates detection of the captured states of the hardware mode pins.
Figure 86. STAT_M2 Register
7
0
R-0h
6
0
R-0h
5
4
3
M2PIN[1:0]
R-xh (1)
2
1
M1PIN[1:0]
R-xh (1)
0
M0PIN[1:0]
R-xh (1)
LEGEND: R = Read only; -n = value after reset
(1)
Reset values are dependent on the state of the hardware pin.
Table 23. STAT_M2 Register Field Descriptions
(1)
Bit
Field
Type
Reset
Description
7:6
Reserved
R
0h
Reserved.
Always read 0h.
5:4
M2PIN[1:0]
R
xh (1)
M2 captured state.
These bits indicate the captured state of the M2 hardware control pin.
00 : GND (Hamming code word validation off)
01 : IOVDD (Hamming code word validation on)
10 : No connection
11 : Reserved
3:2
M1PIN[1:0]
R
xh (1)
M1 captured state.
These bits indicate the captured state of the M1 hardware control pin.
00 : GND (24-bit device word)
01 : IOVDD (32-bit device word)
10 : No connection (16-bit device word)
11 : Reserved
1:0
M0PIN[1:0]
R
xh (1)
M0 captured state.
These bits indicate the captured state of the M0 hardware control pin.
00 : GND (synchronous master mode)
01 : IOVDD (asynchronous slave mode )
10 : No connection (synchronous slave mode )
11 : Reserved
Reset values are dependent on the state of the hardware pin.
9.6.1.9 Reserved Registers (address = 08h to 0Ah) [reset = 00h]
This register is reserved for future use.
Figure 87. Reserved Registers
7
0
R-0h
6
0
R-0h
5
0
R-0h
4
0
R-0h
3
0
R-0h
2
0
R-0h
1
0
R-0h
0
0
R-0h
LEGEND: R = Read only; -n = value after reset
Table 24. Reserved Registers Field Descriptions
64
Bit
Field
Type
Reset
Description
7:0
Reserved
R
00h
Reserved.
Always read 00h.
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9.6.1.10 A_SYS_CFG: Analog System Configuration Register (address = 0Bh) [reset = 60h]
This register configures the analog features in the ADS131A0x.
Figure 88. A_SYS_CFG Register
7
VNCPEN
R/W-0h
6
HRM
R/W-1h
5
1
R/W-1h
4
VREF_4V
R/W-0h
3
INT_REFEN
R/W-0h
2
1
COMP_TH[2:0]
R/W-0h
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 25. A_SYS_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
VNCPEN
R/W
0h
Negative charge pump enable.
This bit enables the negative charge pump when using a 3.0-V to 3.45-V
unipolar power supply.
0 : Negative charge pump powered down (default)
1 : Negative charge pump enabled
6
HRM
R/W
1h
High-resolution mode.
This bit selects between high-resolution and low-power mode.
0 : Low-power mode
1 : High-resolution mode (default)
5
Reserved
R/W
1h
Reserved.
Always write 1h.
4
VREF_4V
R/W
0h
REFP reference voltage level.
This bit determines the REFP reference voltage level when using the
internal reference.
0 : REFP is set to 2.442 V (default)
1 : REFP is set to 4.0 V
3
INT_REFEN
R/W
0h
Internal reference enable.
This bit connects the internal reference voltage to the reference buffer to
use the internal reference
0 : External reference voltage selected (default)
1 : Internal reference voltage enabled and selected
COMP_TH[2:0]
R/W
0h
Fault detect comparator threshold.
These bits determine the fault detect comparator threshold level settings;
see the
2:0
Input Overrange and Underrange Detection section for details.
Table 26 lists the bit settings for the high- and low-side thresholds. Values
are approximate and are referenced to the device analog supply range.
When VNCPEN = 0, AVDD and AVSS are used for the high and low
threshold.
When VNCPEN = 1, AVDD is used for the high threshold value. A –1.5-V
supply, generated from the negative charge pump, is used for the low
threshold value.
Table 26. COMP_TH[2:0] Bit Settings
COMP_TH[2:0]
COMPARATOR HIGH-SIDE THRESHOLD
(%)
COMPARATOR LOW-SIDE THRESHOLD
(%)
000 (default)
95
5
001
92.5
7.5
010
90
10
011
87.5
12.5
100
85
15
101
80
20
110
75
25
111
70
30
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9.6.1.11 D_SYS_CFG: Digital System Configuration Register (address = 0Ch) [reset = 3Ch]
This register configures the digital features in the ADS131A0x.
Figure 89. D_SYS_CFG Register
7
WDT_EN
R/W-0h
6
CRC_MODE
R/W-0h
5
4
3
DNDLY[1:0]
R/W-3h
2
HIZDLY[1:0]
R/W-3h
1
FIXED
R/W-0h
0
CRC_EN
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 27. D_SYS_CFG Register Field Descriptions
Bit
66
Field
Type
Reset
Description
7
WDT_EN
R/W
0h
Watchdog timer enable.
This bit enables the watchdog timeout counter when set.
Issue a hardware or software reset when disabling the watchdog timer for
internal device synchronization; see the Watchdog Timer section.
0 : Watchdog disabled (default)
1 : Watchdog enabled
6
CRC_MODE
R/W
0h
CRC mode select.
This bit determines which bits in the frame the CRC is valid for; see the
Cyclic Redundancy Check (CRC) section.
0 : CRC is valid on only the device words being sent and received (default)
1 : CRC is valid on all bits received and transmitted
5:4
DNDLY[1:0]
R/W
3h
DONE delay.
These bits configure the time before the device asserts DONE after the
LSB is shifted out.
00 : ≥ 6-ns delay
01 : ≥ 8-ns delay
10 : ≥ 10-ns delay
11 : ≥ 12-ns delay (default)
3:2
HIZDLY[1:0]
R/W
3h
Hi-Z delay.
These bits configure the time that the device asserts Hi-Z on DOUT after
the LSB of the data frame is shifted out.
00 : ≥ 6-ns delay
01 : ≥ 8-ns delay
10 : ≥ 10-ns delay
11 : ≥ 12-ns delay (default)
1
FIXED
R/W
0h
Fixed word size enable.
This bit sets the data frame size.
0 : Device words per data frame depends on whether the CRC and ADCs
are enabled (default)
1 : Fixed six device words per frame for the ADS131A04 or fixed four
device words per data frame for the ADS131A02
0
CRC_EN
R/W
0h
Cyclic redundancy check enable.
This bit enables the CRC data word for both the DIN and DOUT data frame
transfers. When enabled, DIN commands must pass the CRC checks to be
recognized by the device.
0 : CRC disabled (default)
1 : CRC enabled
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9.6.1.12 CLK1: Clock Configuration 1 Register (address = 0Dh) [reset = 08h]
This register configures the ADC clocking and sets the internal clock dividers.
Figure 90. CLK1 Register
7
CLKSRC
R/W-0h
6
0
R/W-0h
5
0
R/W-0h
4
0
R/W-0h
3
2
CLK_DIV[2:0]
R/W-4h
1
0
0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 28. CLK1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CLKSRC
R/W
0h
ADC clock source.
This bit selects the source for ICLK; see the Clock section for more
information on ADC clocking.
0 : XTAL1/CLKIN pin or XTAL1/CLKIN and XTAL2 pins (default)
1 : SCLK pin
6:4
Reserved
R/W
0h
Reserved.
Always write 0h.
3:1
CLK_DIV[2:0]
R/W
4h
CLKIN divider ratio.
These bits set the CLKIN divider ratio to generate the internal fICLK
frequency. ICLK is used as the fSCLK output when the ADC is operating in
synchronous master mode.
000 : Reserved
001 : fICLK = fCLKIN / 2
010 : fICLK = fCLKIN / 4
011 : fICLK = fCLKIN / 6
100 : fICLK = fCLKIN / 8 (default)
101 : fICLK = fCLKIN / 10
110 : fICLK = fCLKIN / 12
111 : fICLK = fCLKIN / 14
Reserved
R/W
0h
Reserved.
Always write 0.
0
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9.6.1.13 CLK2: Clock Configuration 2 Register (address = 0Eh) [reset = 86h]
This register configures the ADC modulator clock and oversampling ratio for the converter.
Figure 91. CLK2 Register
7
6
ICLK_DIV[2:0]
R/W-4h
5
4
0
R/W-0h
3
2
1
0
OSR[3:0]
R/W-6h
LEGEND: R/W = Read/Write; -n = value after reset
Table 29. CLK2 Register Field Descriptions
68
Bit
Field
Type
Reset
Description
7:5
ICLK_DIV[2:0]
R/W
4h
ICLK divider ratio.
These bits set the divider ratio to generate the ADC modulator clock, fMOD,
from the fICLK signal.
000 : Reserved
001 : fMOD = fICLK / 2
010 : fMOD = fICLK / 4
011 : fMOD = fICLK / 6
100 : fMOD = fICLK / 8 (default)
101 : fMOD = fICLK / 10
110 : fMOD = fICLK / 12
111 : fMOD = fICLK / 14
4
Reserved
R/W
0h
Reserved.
Always write 0h.
3:0
OSR[3:0]
R/W
6h
Oversampling ratio.
These bits set the OSR to create the ADC output data rate, fDATA; see
Table 30 for more details.
0000 : fDATA = fMOD / 4096
0001 : fDATA = fMOD / 2048
0010 : fDATA = fMOD / 1024
0011 : fDATA = fMOD / 800
0100 : fDATA = fMOD / 768
0101 : fDATA = fMOD / 512
0110 : fDATA = fMOD / 400 (default)
0111 : fDATA = fMOD / 384
1000 : fDATA = fMOD / 256
1001 : fDATA = fMOD / 200
1010 : fDATA = fMOD / 192
1011 : fDATA = fMOD / 128
1100 : fDATA = fMOD / 96
1101 : fDATA = fMOD / 64
1110 : fDATA = fMOD / 48
1111 : fDATA = fMOD / 32
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Table 30. Data Rate Settings
OSR[3:0]
OSR
fDATA AT 2.048-MHz fMOD
(kHz)
fDATA AT 4.096-MHz fMOD
(kHz)
fDATA AT 4-MHz fMOD
(kHz)
0000
4096
0.500
1.000
0.977
0001
2048
1.000
2.000
1.953
0010
1024
2.000
4.000
3.906
0011
800
2.560
5.120
5.000
0100
768
2.667
5.333
5.208
0101
512
4.000
8.000
7.813
0110
400
5.120
10.240
10.000
0111
384
5.333
10.667
10.417
1000
256
8.000
16.000
15.625
1001
200
10.240
20.480
20.000
1010
192
10.667
21.333
20.833
1011
128
16.000
32.000
31.250
1100
96
21.333
42.667
41.667
1101
64
32.000
64.000
62.500
1110
48
42.667
85.333
83.333
1111
32
64.000
128.000
125.000
9.6.1.14 ADC_ENA: ADC Channel Enable Register (address = 0Fh) [reset = 00h]
This register controls the enabling of ADC channels.
Figure 92. ADC_ENA Register
7
0
R/W-0h
6
0
R/W-0h
5
0
R/W-0h
4
0
R/W-0h
3
2
1
0
ENA[3:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 31. ADC_ENA Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
Reserved
R/W
0h
Reserved.
Always write 0h.
3:0
ENA[3:0]
R/W
0h
Enable ADC channels.
These bits power-up or power-down the ADC channels. This setting is
global for all channels.
0000 : All ADC channels powered down (default)
1111 : All ADC channels powered up
All other settings: Do not use
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9.6.1.15 Reserved Register (address = 10h) [reset = 00h]
This register is reserved for future use.
Figure 93. Reserved Register
7
0
R/W-0h
6
0
R/W-0h
5
0
R/W-0h
4
0
R/W-0h
3
0
R/W-0h
2
0
R/W-0h
1
0
R/W-0h
0
0
R/W-0h
LEGEND: R = Read only; -n = value after reset
Table 32. Reserved Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R/W
00h
Reserved.
Always write 00h.
9.6.2 ADCx: ADC Channel Digital Gain Configuration Registers (address = 11h to 14h) [reset = 00h]
These registers control the digital gain setting for the individual ADC channel (x denotes the ADC channel).
For the ADS131A02, these registers are reserved.
Figure 94. ADCx Register
7
0
R/W-0h
6
0
R/W-0h
5
0
R/W-0h
4
0
R/W-0h
3
0
R/W-0h
2
1
GAINx_[2:0]
R/W-0h
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 33. ADCx Registers Field Descriptions
70
Bit
Field
Type
Reset
Description
7:3
Reserved
R/W
00h
Reserved.
Always write 00h.
2:0
GAINx_[2:0]
R/W
0h
Gain control (digital scaling).
These bits determine the digital gain of the ADC output.
000 : Gain = 1 (default)
001 : Gain = 2
010 : Gain = 4
011 : Gain = 8
100 : Gain = 16
101, 110, 111 : Reserved
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Unused Inputs and Outputs
To minimize leakage currents on the analog inputs, leave any unused analog inputs floating or connected to
AVSS. For the ADS131A02, the NC pins (pins 5-8) can be left floating or tied directly to AVSS.
Pin 24 is a digital output unconnected (NC) pin. Leave pin 24 floating or tied to GND through a 10-kΩ pulldown
resistor.
Do not float unused digital inputs because excessive power-supply leakage current can result. Tie all unused
digital inputs to the appropriate levels, IOVDD or DGND, even when in power-down mode.
If the DONE or DRDY outputs are not used, leave these pins (pins 18 and 19, respectively) unconnected or tie
these pins to IOVDD using a weak pullup resistor. Current consumed by the pullup resistor flows into the device
and therefore increases power consumption.
10.1.2 Power Monitoring Specific Applications
Each channel of the ADS131A0x is identical, giving designers the flexibility to sense voltage or current with any
channel. Simultaneous sampling allows the application to calculate instantaneous power for any simultaneous
voltage and current measurement. Figure 95 shows an example system that measures voltage and current
simultaneously.
Phase B
Phase A
2.5 V
R1
AVDD
RFILT
AIN1P
CFILT
R2
R2
R1
RFILT
AIN1N
CFILT
Device
RFILT
CT
AIN2P
R3
CFILT
AIN2N
AVSS
-2.5 V
Figure 95. Example Power-Monitoring System
In Figure 95, channel 1 is dedicated to measuring the voltage between phase A and phase B and channel 2 is
dedicated to measuring the current on phase A.
The resistors R1 and R2 form a voltage divider that steps the line voltage down to within the measurement range
of the ADC. R1 can be formed by multiple resistors in series to dissipate power across several components. This
configuration is also valid if the voltage is measured with respect to neutral instead of between phases.
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Application Information (continued)
Channel 2 is dedicated to measuring current that flows on phase A. Resistor R3 serves as a burden resistor that
shunts the current flowing across the secondary coil of the current transformer (CT). Current can also be
measured using a Rogowski coil and an analog integrator or by performing integration digitally after a
conversion.
The RC filters formed by RFILT and CFILT serve as antialiasing filters for the converter. If an application requires a
steeper filter roll-off, a second-order RC filter can be used.
10.1.3 Multiple Device Configuration
The ADS131A0x allows the designer to add channels to the system by placing an additional device on the SPI
bus. The first device in the chain of devices can be configured using any of the interface modes. All subsequent
devices must be configured in synchronous slave mode. In all cases, however, the chain of ADS131A0x devices
appear to the host as a single device with extra channels with the exception that each device sends individual
status and data integrity words. In this manner, no additional pins on the host are required for more devices on
the chain. There are no special provisions that must be made in the interface except for extending the frame to
the appropriate length.
10.1.3.1 First Device Configured in Asynchronous Interrupt Mode
Figure 96 illustrates a multiple device configuration where the first device is configured in asynchronous interrupt
mode as indicated by the state of the M0 pin. The second ADS131A0x device and any additional devices are
configured in synchronous slave mode. The DONE pin of each device connects to the CS of the subsequent
device. In each case, after a device shifts out all of its data, the device deasserts DONE, selecting the
subsequent device for communication. The DOUT of a device whose contents are already shifted out assumes a
high-impedance state, allowing the DOUT pins of all devices to be tied together. To send commands to specific
devices, send the respective command of the device when that device is selected for communication. The DRDY
output of the first device serves as the DRDY input to all other devices to synchronize conversions. Figure 97
illustrates an example interface timing diagram for this configuration.
IOVDD
MCU/DSP/FPGA
IOVDD
CS
ADS131A0x
Device 1
M0
Asynchronous
Interrupt Mode
CLKIN
CLK
CS
SCLK
SCLK
DIN
MOSI
DOUT
MISO
DRDY
IRQ
DONE
CS
ADS131A0x
Device 2
Synchronous
Slave Mode
Float
SCLK
M0
DIN
DOUT
CLKIN
DRDY
DONE
To Next Device
Figure 96. Multiple Device Configuration Using Asynchronous Interrupt Mode
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Application Information (continued)
DRDY
CS(1)
SCLK
DIN
MSB(1)
DOUT
LSB(1) MSB(2)
LSB(N)
DONE(1), CS(2)
NOTE:
(1)
denotes device 1, (2) denotes device 2, and
(N)
denotes device N.
Figure 97. Multiple Device Configuration Timing Diagram when Using Asynchronous Interrupt Mode
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Application Information (continued)
10.1.3.2 First Device Configured in Synchronous Master Mode
Figure 98 shows a multiple device configuration where the first device is configured in synchronous master mode
as indicated by the state of the M0 pin. The second ADS131A0x device and any additional devices are
configured in synchronous slave mode. The DONE pin of each device connects to the CS pin of the subsequent
device. In each case, after a device shifts out all of its data, the device deasserts DONE, selecting the
subsequent device for communication. Tie the DONE pin of the last device to the CS pin of the first device to
allow for an immediate second read back of conversion data in the case a data integrity test failed. The DOUT of
a device whose contents are already shifted out assumes a high-impedance state, allowing the DOUT pins of all
devices to be tied together. To send commands to specific devices, send the respective command of the device
when that device is selected for communication. The DRDY output of the first device serves as the DRDY input
to all other devices to synchronize conversions. DRDY also serves as the chip-select or frame sync signal for the
host. SCLK is free running with the same frequency as ICLK in this configuration. Figure 99 illustrates an
example interface timing diagram for this configuration.
IOVDD
CS
ADS131A0x
Device 1
M0
Synchronous
Master Mode
CLKIN
CLK
MCU/DSP/FPGA
SCLK
SCLK
DIN
MISO
DOUT
MOSI
DRDY
CS, FSYNC
DONE
CS
ADS131A0x
Device 2
Float
M0
SCLK
DIN
Synchronous
Slave Mode
DOUT
CLKIN
DRDY
DONE
Devices 3
through N-1
CS
ADS131A0x
Device N
Float
M0
SCLK
DIN
Synchronous
Slave Mode
DOUT
CLKIN
DRDY
DONE
Figure 98. Multiple Device Configuration Using Synchronous Master Mode
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Application Information (continued)
DRDY
SCLK
DIN
MSB(1)
DOUT
LSB(1) MSB(2)
LSB(N)
DONE(1), CS(2)
NOTE:
(1)
denotes device 1, (2) denotes device 2, and
(N)
denotes device N.
Figure 99. Multiple Device Configuration Timing Diagram When Using Synchronous Master Mode
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Application Information (continued)
10.1.3.3 All Devices Configured in Synchronous Slave Mode
Figure 100 illustrates a multiple device configuration where all devices are configured in synchronous slave
mode. Figure 100 illustrates a master clock at the CLKIN pin, but a free-running SCLK can also be used as the
conversion clock in this mode. SCLK must be free-running if the modulator clock is derived from the serial clock
(CLKSRC = 1). See the Synchronous Slave Mode section for more information about clocking the device using
SCLK. The DONE pin of each device connects to the CS pin of the subsequent device for communication. The
DOUT pin of a device whose contents are already shifted out assumes a high-impedance state, allowing the
DOUT pins of all devices to be tied together. To send commands to specific devices, send the respective
command to the device when that device is selected for communication. In this configuration, conversions must
be synchronized by the master. Synchronization is accomplished by tying the chip select or frame sync output of
the host to the DRDY input of each device. The master must have a synchronous clock and must be able to
send clocks at exactly the proper timing to maintain synchronization. See the Synchronous Slave Mode section
for more information about conversion synchronization using slave mode. Figure 101 illustrates an example
interface timing diagram for this configuration.
IOVDD
MCU/DSP/FPGA
CS
ADS131A0x
Device 1
Synchronous
Slave Mode
Float
SCLK
DIN
MOSI
DOUT
MISO
M0
CLKIN
CLK
CS, FSYNC
SCLK
DRDY
DONE
CS
ADS131A0x
Device 2
Float
SCLK
M0
DIN
Synchronous
Slave Mode
DOUT
CLKIN
DRDY
DONE
To Next Device
Figure 100. Multiple Device Configuration Using Synchronous Slave Mode
DRDY, CS(1)
SCLK
DIN
MSB(1)
DOUT
LSB(1) MSB(2)
LSB(N)
DONE(1), CS(2)
NOTE:
(1)
denotes device 1, (2) denotes device 2, and
(N)
denotes device N.
Figure 101. Multiple Device Configuration Timing Diagram When Using Synchronous Slave Mode
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10.2 Typical Application
Figure 102 shows an ADS131A0x device used as part of a power-metering application. The ADS131A0x device
is ideal because this device allows for simultaneous sampling of voltage and current. The upper channel is used
to measure voltage, accomplished by stepping down the line voltage with a voltage divider. The lower channel
measures current directly from the line by measuring voltage across the burden resistors R4.
2.5 V
Line
R1
R1
R3
R1
AVDD
INxP
R2
C1
R3
Neutral
INxN
ADS131A04
R3
2000:1
Line Current IN
INxP
R4
C1
R4
R3
INxN
Line Current OUT
AVSS
-2.5 V
Figure 102. Typical Power Metering Connections
10.2.1 Design Requirements
Table 34. Power Metering Design Requirements
DESIGN PARAMETER
VALUE
Voltage input
230 VRMS at 50 Hz
Current input range
0.05 ARMS to 100 ARMS
Active power measurement error
< 0.2%
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10.2.2 Detailed Design Procedure
In this configuration, line voltage is measured as a single-ended input. The 230-VRMS signal must be stepped
down such that the signal peaks fall within the measurement range of the ADS131A04 when using the internal
2.442-V reference. A voltage divider using the series combination of multiple R1 resistors and the R2 resistor
steps the input to within an acceptable range. Using multiple R1 resistors along with proper spacing disperses
energy among several components and provides a line of defense against short-circuits caused when one
resistor fails. The output of this voltage divider can be calculated using Equation 10:
VIN
§
·
R2
VLINE ¨
¸
© 3 u R1 R2 ¹
(10)
If R1 and R2 are chosen as 330 kΩ and 3.9 kΩ, respectively, the voltage at the input of the ADS131A0x is 0.9025
VRMS, corresponding to a 1.276 Vpeak that is within the measurement range of the ADC.
Line current is measured by stepping the input current down through a current transformer (CT) then shunting
the current on the secondary side through burden resistors. Then, the voltage is measured across the resistors
and current is back calculated in the processor. The voltage across the burden resistors R4 is measured
differentially by grounding the node between the two resistors. Equation 11 relates the voltage at the input to the
ADS131A0x to the line current.
§ 2 u ILINE u R 4 ·
VIN ¨
¸
N
©
¹
(11)
If a CT with a 2000:1 turns ratio is used and R4 is chosen to be 8.2 Ω, then 100 ARMS of line current corresponds
to 0.82 VRMS (1.16 Vpeak) at the input to the ADS131A0x. The design minimum line current of 50 mARMS
corresponds to 0.41 mVRMS (0.58 mVpeak).
The combination of R3 and C1 on each line serves as an antialiasing filter. Having C1 populated differentially
between the inputs helps improve common-mode rejection because the tolerance of the capacitor is shared
between the inputs. The half-power frequency of this filter can be calculated according to Equation 12:
§
·
1
f 3dB ¨
¸
© 4 u S u R3 u C1 ¹
(12)
A filter with R3 populated as 100 Ω and C1 as 2.7 nF gives a cutoff frequency of approximately 295 kHz. This
filter provides nearly 17 dB of attenuation at the modulator frequency when the ADS131A04 modulator frequency
is set to 2.048 MHz. R3 must be kept relatively low because large series resistance degrades THD.
To get an accurate picture of instantaneous power, the phase delay of the current transformer must be taken into
account. Many kinds of digital filters can be implemented in the application processor to delay the current
measurement to better align with the input voltage.
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10.2.3 Application Curve
Figure 103 shows the active power measurement accuracy for the ADS131A0x across varying currents. Data
was taken for a 0.5 lead, 0.5 lag, and unity power factors. For this test, the external 16.384-MHz crystal
frequency was divided to give a modulator frequency of 2.048 MHz. Finally, an OSR of 256 was chosen to give
the ADS131A04 an output data rate of 8 kSPS.
0.5
Power Factor
Unity
0.5 Lead
0.5 Lag
0.4
0.3
Error (%)
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
10
20
30
40
50
60
70
Current Magnitude (A)
80
90
100
D007
Figure 103. Active Power Measurement Error
10.3 What To Do and What Not To Do
•
•
•
•
•
•
•
•
•
•
•
•
•
Do partition the analog, digital, and power-supply circuitry into separate sections on the printed circuit board
(PCB).
Do use a single ground plane for analog and digital grounds.
Do place the analog components close to the ADC pins using short, direct connections.
Do keep the SCLK pin free of glitches and noise.
Do verify that the analog input voltages are within the specified voltage range under all input conditions.
Do tie unused analog input pins to GND.
Do provide current limiting to the analog inputs in case overvoltage faults occur.
Do use a low-dropout (LDO) regulator to reduce ripple voltage generated by switch-mode power supplies.
This reduction is especially true for AVDD where the supply noise can affect performance.
Do keep the input series resistance low to maximize THD performance.
Do not cross analog and digital signals.
Do not allow the analog power supply voltages (AVDD – AVSS) to exceed 3.6 V under any conditions,
including during power-up and power-down when the negative charge pump is enabled.
Do not allow the analog power supply voltages (AVDD – AVSS) to exceed 6 V under any conditions,
including during power-up and power-down when the negative charge pump is disabled.
Do not allow the digital supply voltage to exceed 3.9 V under any conditions, including during power-up and
power-down.
Figure 104 and Figure 105 illustrate correct and incorrect ADC circuit connections.
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What To Do and What Not To Do (continued)
3.3 V
5V
3.3 V
2.5 V
CORRECT
CORRECT
AVDD
Device
AVDD
IOVDD
Device
24-Bit
û ADC
24-Bit
û ADC
AVSS
IOVDD
AVSS
GND
GND
-2.5 V
Low-impedance supply connections.
Low-impedance supply connections.
3.3 V
5V
3.3 V
5V
INCORRECT
AVDD
Device
INCORRECT
IOVDD
AVDD
Device
24-Bit
û ADC
AVSS
GND
24-Bit
û ADC
AVSS
Inductive supply or ground connections.
GND
AGND, DGND isolation.
5V
INCORRECT
5V
CORRECT
AVDD
Device
AVDD
Device
24-Bit
û ADC
AVSS
VNCPEN = 1
24-Bit
û ADC
AVSS
Charge pump enabled with unipolar analog supply,
AVDD > 3.6 V.
IOVDD
VNCPEN = 0
Charge pump disabled with unipolar analog supply,
AVDD > 3.6 V.
CORRECT
3.3 V
Device
AVDD
24-Bit
û ADC
AVSS
VNCPEN = 1
Charge pump enabled with unipolar analog supply,
AVDD < 3.6 V.
Figure 104. Correct and Incorrect Circuit Connections
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What To Do and What Not To Do (continued)
INCORRECT
CORRECT
2.5 V
AVDD
2.5 V
Device
AVDD
Device
24-Bit
û ADC
AVSS
24-Bit
û ADC
VNCPEN = 1
AVSS
-2.5 V
-2.5 V
Charge pump is enabled with a bipolar analog supply.
Charge pump is disabled with a bipolar analog supply.
INCORRECT
CORRECT
3.3 V
AVDD
3.3 V
Device
AVDD
AINxP
Device
AIN1P
24-Bit
û ADC
AINxN
24-Bit
û ADC
AIN1N
+
+
-1 V
±
VNCPEN = 0
AVSS
VNCPEN = 0
Input swings below ground, charge pump is disabled.
-1 V
±
AVSS
VNCPEN = 1
Input swings below ground, charge pump is enabled.
Figure 105. Correct and Incorrect Circuit Connections, Continued
10.4 Initialization Set Up
Figure 106 illustrates a general procedure to configure the ADS131A0x to collect data.
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Initialization Set Up (continued)
Power Off
// Pull up, pull down or float the M0 pin
Set M0 mode pin
Power up
Analog + Digital Supply
SET
RESET = 1
N
Wait
Receive READY Word?
// Analog and Digital supply can come up together
// RESET can come up with Power Supply
// Monitor serial output for 0xFF02 (ADS131A02) or 0xFF04
(ADS131A04)
Y
Unlock Device
Configure Device
Write Registers
Receive Command Status
Response
// Send UNLOCK command 0x0655
// Receive Command Status Response 0x0655
// Configure Int/Ext reference, CLK dividers, OSR, comparator
threshold, negative charge pump, and power mode setting
// Use the WREG or WREGS commands
// Verify registers are written successfully
// Device Data Frame or Data Rate may change if coresponding
register is changed
Y
Write another register?
N
Enable ADCs
// Write 0Fh to the ADC_ENA register to enable ADCs
Wakeup Device
// Send WAKEUP command 0x0033
// Start conversions
Lock Registers
// Send LOCK command 0x0555
Capture Data
// Use DRDY indicator to indicate new data is available
Figure 106. ADS131A0x Configuration Sequence
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11 Power Supply Recommendations
The device requires two power supplies: analog (AVDD, AVSS) and digital (IOVDD, GND). The analog power
supply can be bipolar (for example, AVDD = 2.5 V, AVSS = –2.5 V), unipolar (for example, AVDD = 5 V, AVSS =
0 V), or unipolar using the negative charge pump (for example, AVDD = 3.3 V, AVSS = VNCP), and is
independent of the digital power supply. The digital supply range sets the digital I/O levels.
11.1 Negative Charge Pump
An optional negative charge pump is available to power AVSS with an operating voltage of –1.95 V. Enabling the
negative charge pump allows for input signals below analog ground when using a unipolar analog supply (for
example, AVDD = 3.3 V, AVSS = 0 V). The VNCPEN bit in the A_SYS_CFG register must be set high by the
user to enable the negative charge pump. The VNCP pin outputs the nominal –1.95-V negative charge pump
output and requires a capacitor to AVSS in the range of 220 pF to 470 pF. The charge pump operates at a
switching frequency of 2fMOD. The minimum ADC absolute input voltage range is –1.5 V with the negative charge
pump enabled. The maximum analog supply limit (AVDD – AVSS) is restricted to 3.6 V maximum. Exceeding this
limit can permanently damage the device.
The negative charge pump is internally activated when the VNCPEN bit is set to 1 and the device is in wake-up
mode with all ADC channels enabled (ADC_ENA = 0Fh).
Connect VNCP directly to AVSS when not using the negative charge pump.
11.2 Internal Digital LDO
The ADS131A0x digital core voltage operates from 1.8 V, created from an internal LDO from IOVDD. The CAP
pin outputs the LDO voltage created from the IOVDD supply and requires an external bypass capacitor. When
operating from VIOVDD > 2 V, place a 1-µF capacitor on the CAP pin to GND. If VIOVDD ≤ 2 V, tie the CAP pin
directly to the IOVDD pin and decouple both pins using a 1-µF capacitor to GND.
11.3 Power-Supply Sequencing
The power supplies can be sequenced in any order but the analog or digital inputs must never exceed the
respective analog or digital power-supply voltage limits.
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11.4 Power-Supply Decoupling
Good power-supply decoupling is important to achieve optimum performance. AVDD, AVSS (when using a
bipolar supply), and IOVDD must be decoupled with at least a 1-µF capacitor, as shown in Figure 107,
Figure 108, and Figure 109. A 270-nF capacitor is required on the VNCP pin when using the negative charge
pump. Place the bypass capacitors as close to the power-supply pins of the device as possible with lowimpedance connections. Using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics are recommended for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins can offer superior noise immunity. The use of multiple vias in parallel lowers the
overall inductance and is beneficial for connections to ground planes. The analog and digital ground are
recommended to be connected together as close to the device as possible.
2.5 V
5V
3.3 V
1 PF
3.3 V
1 PF
1 PF
1 PF
±2.5 V
AVDD
RESV
AVDD
IOVDD
RESV
IOVDD
CAP
CAP
1 PF
1 PF
REFEXT
REFEXT
ADS131A0x
ADS131A0x
1 PF
1 PF
REFP
REFP
±2.5 V
1 PF
AVSS
VNCP
1 PF
REFN
GND
AVSS
VNCP
REFN
GND
±2.5 V
±2.5 V
Figure 108. Unipolar Analog Power Supply
Figure 107. Bipolar Analog Power Supply
3.3V
3.3 V
1 PF
1 PF
AVDD
RESV
IOVDD
CAP
1 PF
REFEXT
ADS131A0x
1 PF
REFP
1 PF
AVSS
VNCP
REFN
GND
270 nF
Figure 109. Unipolar Analog Power Supply with Negative Charge Pump Enabled
84
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Product Folder Links: ADS131A02 ADS131A04
ADS131A02, ADS131A04
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SBAS590E – MARCH 2016 – REVISED JUNE 2020
12 Layout
12.1 Layout Guidelines
Use a low-impedance connection for ground so that return currents flow undisturbed back to the respective
sources. For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal
traces on this layer. Keep connections to the ground plane as short and direct as possible. When using vias to
connect to the ground layer, use multiple vias in parallel to reduce impedance to ground. Figure 110 shows the
proper component placement for the system.
A mixed-signal layout sometimes incorporates separate analog and digital ground planes that are tied together at
one location; however, separating the ground planes is not necessary when analog, digital, and power-supply
components are properly placed. Proper placement of components partitions the analog, digital, and powersupply circuitry into different PCB regions to prevent digital return currents from coupling into sensitive analog
circuitry. If ground plane separation is necessary, then make the connection at the ADC. Connecting individual
ground planes at multiple locations creates ground loops, and is not recommended. A single ground plane for the
analog and digital grounds avoids ground loops.
Bypass the supply pins with a low-ESR ceramic capacitor. The placement of the bypass capacitors must be as
close as possible to the supply pins using short, direct traces. For optimum performance, the ground-side
connections of the bypass capacitors must also be made with low-impedance connections. The supply current
flows through the bypass capacitor pin first and then to the supply pin to make the bypassing most effective (also
known as a Kelvin connection). If multiple ADCs are on the same PCB, use wide power-supply traces or
dedicated power-supply planes to minimize the potential of crosstalk between ADCs.
If external filtering is used for the analog inputs, use C0G-type ceramic capacitors when possible. C0G
capacitors have stable properties and low-noise characteristics. Ideally, route differential signals as pairs to
minimize the loop area between the traces. Route digital circuit traces (such as clock signals) away from all
analog pins. Note that the internal reference output return shares the same pin as the AVSS power supply. To
minimize coupling between the power-supply trace and reference return trace, route the two traces separately;
ideally, as a star connection at the AVSS pin.
Treat the AVSS pin as a sensitive analog signal and connect directly to the supply ground with proper shielding.
Leakage currents between the PCB traces can exceed the input bias current of the ADS131A0x if shielding is not
implemented. Keep digital signals as far as possible from the analog input signals on the PCB.
The SCLK input of the serial interface must be free from noise and glitches when this device is configured in a
slave mode. This configuration is especially true when SCLK is used as the master clock for this device. Even
with relatively slow SCLK frequencies, short digital signal rise and fall times can cause excessive ringing and
noise. For best performance, keep the digital signal traces short, using termination resistors as needed, and
make sure all digital signals are routed directly above the ground plane with minimal use of vias.
Ground Fill or
Ground Plane
Supply
Generation
Interface
Transceiver
Microcontroller
Device
Optional: Split
Ground Cut
Signal
Conditioning
(RC Filters
and
Amplifiers)
Ground Fill or
Ground Plane
Optional: Split
Ground Cut
Ground Fill or
Ground Plane
Connector
or Antenna
Ground Fill or
Ground Plane
Figure 110. System Component Placement
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Product Folder Links: ADS131A02 ADS131A04
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12.2 Layout Example
Figure 111 is an example layout of the ADS131A04. This example shows the device supplied with a bipolar
supply, though the layout can be replicated for a unipolar case. In general, analog signals and planes are
partitioned to the left and digital signals and planes to the right.
+3.3 V
Via to corresponding
voltage plane or pour
Via to ground plane
or pour
25: XTAL1
26: XTAL2
27: GND
29: IOVDD
28: CAP
31: M1
30: M0
32: M2
+3.3 V
1: AIN1N
24: NC
2: AIN1P
23: CS
3: AIN2N
22: SCLK
4: AIN2P
21:DOUT
Device
5: AIN3N
20:DIN
6: AIN3P
19: DRDY
16: RESV
14: REFEXT
15: IOVDD
13: REFN
12: REFP
11: VNCP
17: RESET
10: AVSS
18: DONE
8: AIN4P
9: AVDD
7: AIN4N
Long digital input lines
terminated with resistors to
prevent reflection
+3.3 V
Inputs filtered with
differential capacitors
+2.5 V
-2.5 V
-2.5 V
-2.5 V
Reference, CAP, and power
supply decoupling capacitors
close to pins
Figure 111. ADS131A0x Layout Example
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Product Folder Links: ADS131A02 ADS131A04
ADS131A02, ADS131A04
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SBAS590E – MARCH 2016 – REVISED JUNE 2020
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, THS4531A Ultra Low-Power, Rail-to-Rail Output, Fully Differential Amplifier data sheet
• Texas Instruments, REF60xx High-Precision Voltage Reference With Integrated ADC Drive Buffer data sheet
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 35. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ADS131A02
Click here
Click here
Click here
Click here
Click here
ADS131A04
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2016–2020, Texas Instruments Incorporated
Product Folder Links: ADS131A02 ADS131A04
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS131A02IPBS
ACTIVE
TQFP
PBS
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
131A02
ADS131A02IPBSR
ACTIVE
TQFP
PBS
32
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
131A02
ADS131A04IPBS
ACTIVE
TQFP
PBS
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
131A04
ADS131A04IPBSR
ACTIVE
TQFP
PBS
32
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
131A04
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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