ADS1602IPFBT

ADS1602 SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 16-Bit, 2.5MSPS Analog-to-Digital Converter FEATURES D High Speed: D Data Rate: 2.5MSPS Bandwidth: 1.23MHz Outstanding Performance: SNR: 91dB at fIN = 100kHz, −1dBFS THD: −101dB at fIN = 100kHz, −6dBFS SFDR: 103dB at fIN = 100kHz, −6dBFS Ease-of-Use: High-Speed 3-Wire Serial Interface Directly Connects to TMS320 DSPs On-Chip Digital Filter Simplifies Anti-Alias Requirements Simple Pin-Driven Control—No On-Chip Registers to Program Selectable On-Chip Voltage Reference Simultaneous Sampling with Multiple ADS1602s Low Power: 530mW at 2.5MSPS Power-Down Mode DESCRIPTION The ADS1602 is a high-speed, high-precision, delta-sigma analog-to-digital converter (ADC) manufactured on an advanced CMOS process. The ADS1602 oversampling topology reduces clock jitter sensitivity during the sampling of high-frequency, large amplitude signals by a factor of four over that achieved by Nyquist-rate ADCs. Consequently, signal-to-noise ratio (SNR) is particularly improved. Total harmonic distortion (THD) is −101dB, and the spurious-free dynamic range (SFDR) is 103dB. Optimized for power and performance, the ADS1602 dissipates only 530mW while providing a full-scale differential input range of ±3V. Having such a wide input range makes out-of-range signals unlikely. The OTR pin indicates if an analog input out-of-range condition does occur. The differential input signal is measured against the differential reference, which can be generated internally or supplied externally on the ADS1602. The ADS1602 uses an inherently stable advanced modulator with an on-chip decimation filter. The filter stop band extends to 38.6MHz, which greatly simplifies the anti-aliasing circuitry. The modulator samples the input signal up to 40MSPS, depending on fCLK, while the 16x decimation filter uses a series of four half-band FIR filter stages to provide 75dB of stop band attenuation and 0.001dB of passband ripple. Output data is provided over a simple 3-wire serial interface at rates up to 2.5MSPS, with a −3dB bandwidth of 1.23MHz. The output data or its complementary format directly connects to DSPs such as TI’s TMS320 family, FPGAs, or ASICs. A dedicated synchronization pin enables simultaneous sampling with multiple ADS1602s in multi-channel systems. Power dissipation is set by an external resistor that allows a reduction in dissipation when operating at slower speeds. All of the ADS1602 features are controlled by dedicated I/O pins, which simplify operation by eliminating the need for on-chip registers. The high performing, easy-to-use ADS1602 is especially suitable for demanding measurement applications in sonar, vibration analysis, and data acquisition. The ADS1602 is offered in a small, 7mm x 7mm TQFP-48 package and is specified from −40°C to +85°C. D D APPLICATIONS D Sonar D Vibration Analysis D Data Acquisition VREFP VREFN VMID RBIAS VCAP AVDD DVDD IOVDD CLK SYNC Reference and Bias Circuits FSO FSO AINP AINN Serial Interface SCLK SCLK DOUT DOUT OTR PD ∆Σ Modulator Linear Phase FIR Digital Filter ADS1602 AGND DGND REFEN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2004−2005, Texas Instruments Incorporated www.ti.com ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 PACKAGE/ORDERING INFORMATION For the most current package and ordering information see the Package Option Addendum located at the end of this datasheet or visit the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ADS1602 AVDD to AGND DVDD to DGND IOVDD to DGND AGND to DGND Input Current Input Current Analog I/O to AGND Digital I/O to DGND Maximum Junction Temperature Operating Temperature Range Storage Temperature Range −0.3 to +6 −0.3 to +3.6 −0.3 to +6 −0.3 to +0.3 100mA, Momentary 10mA, Continuous −0.3 to AVDD + 0.3 −0.3 to IOVDD + 0.3 +150 −40 to +105 −60 to +150 V V °C °C °C UNIT V V V V This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ADS1602 passes standard 200V machine model and 1.5K CDM testing. ADS1602 passes 1kV human body model testing (TI Standard is 2kV). ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Lead Temperature (soldering, 10s) +260 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. ADS1602 PARAMETER Analog Input Differential input voltage (VIN) (AINP − AINN) Common-mode input voltage (VCM) (AINP + AINN) / 2 Absolute input voltage (AINP or AINN with respect to AGND) Dynamic Specifications Data Rate fIN = 10kHz, −1dBFS fIN = 10kHz, −3dBFS fIN = 10kHz, −6dBFS fIN = 100kHz, −1dBFS Signal-to-noise ratio (SNR) fIN = 100kHz, −3dBFS fIN = 100kHz, −6dBFS fIN = 800kHz, −1dBFS fIN = 800kHz, −3dBFS fIN = 800kHz, −6dBFS fIN = 10kHz, −1dBFS fIN = 10kHz, −3dBFS fIN = 10kHz, −6dBFS fIN = 100kHz, −1dBFS Total harmonic distortion (THD) fIN = 100kHz, −3dBFS fIN = 100kHz, −6dBFS fIN = 800kHz, −1dBFS fIN = 800kHz, −3dBFS fIN = 800kHz, −6dBFS fIN = 10kHz, −1dBFS fIN = 10kHz, −3dBFS fIN = 10kHz, −6dBFS fIN = 100kHz, −1dBFS Signal-to-noise + distortion (SINAD) fIN = 100kHz, −3dBFS fIN = 100kHz, −6dBFS fIN = 800kHz, −1dBFS fIN = 800kHz, −3dBFS fIN = 800kHz, −6dBFS fIN = 10kHz, −1dBFS fIN = 10kHz, −3dBFS fIN = 10kHz, −6dBFS fIN = 100kHz, −1dBFS Spurious-free dynamic range (SFDR) fIN = 100kHz, −3dBFS fIN = 100kHz, −6dBFS fIN = 800kHz, −1dBFS fIN = 800kHz, −3dBFS fIN = 800kHz, −6dBFS Intermodulation distortion (IMD) Aperture delay f1 = 995kHz, −6dBFS f2 = 1005kHz, −6dBFS 90 93 90 93 85 82 85 82 87 84 87 84 2.50 f CLK 40MHz TEST CONDITIONS MIN TYP MAX UNIT 0dBFS ±VREF V V 4.6 V 1.45 −0.1 MSPS dB dB dB dB dB dB dB dB dB dB −92 −93 dB dB dB −90 −92 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB ns 92 90 87 91 89 86 91 89 86 −94 −106 −108 −90 −96 −101 −116 −114 −110 89 90 87 87 88 86 91 89 86 95 107 112 91 96 103 120 119 114 94 4 3 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. ADS1602 PARAMETER Digital Filter Characteristics Passband Passband ripple −0.1dB attenuation Passband transition −3.0dB attentuation f CLK 40MHz 1.23 f CLK 40MHz f CLK 40MHz f CLK 1.15 40MHz TEST CONDITIONS MIN TYP MAX UNIT 0 1.1 f CLK 40MHz MHz dB MHz ±0.001 MHz Stop band Stop band attenuation Group delay 1.4 38.6 MHz dB 75 10.4 40MHZ f CLK 40MHZ f CLK µs Settling time Static Specifications Resolution No missing codes Input-referred noise Integral nonlinearity Differential nonlinearity Offset error Offset error drift Gain error Gain error drift Common-mode rejection Power-supply rejection Internal Voltage Reference VREF = (VREFP − VREFN) VREFP VREFN VMID VREF drift Startup time External Voltage Reference VREF = (VREFP − VREFN) VREFP VREFN VMID Complete settling 20.4 µs 16 16 0.5 −1dBFS signal 0.75 0.25 −0.1 −0.1 0.25 Excluding reference drift At DC At DC REFEN = low 2.75 3.5 0.5 2.3 3 4.0 1.0 2.5 50 15 REFEN = high 2.0 3.5 0.5 2.3 3 4 1 2.5 3.25 4.25 1.5 2.6 3.25 4.3 1.3 2.7 10 75 65 0.85 Bits Bits LSB, rms LSB LSB %FSR ppmFSR/ °C % ppm/°C dB dB V V V V ppm/°C ms V V V V 4 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. ADS1602 PARAMETER Clock Input Frequency (fCLK) Duty Cycle Digital Input/Output VIH VIL VOH VOL Input leakage Power-Supply Requirements AVDD DVDD IOVDD AVDD current (IAVDD) DVDD current (IDVDD) IOVDD current (IIOVDD) Power dissipation Temperature Range Specified Operating Storage −40 −40 −60 +85 +105 +150 °C °C °C IOH = 50µA REFEN = low REFEN = high IOVDD = 3V IOVDD = 3V AVDD = 5V, DVDD = 3V, IOVDD = 3V, REFEN = high PD = low, CLK disabled 4.75 2.7 2.7 110 88 25 8 530 10 5.25 3.3 5.25 125 98 30 10 610 V V V mA mA mA mA mW mW IOH = 50µA IOL = 50µA DGND < VDIGIN < IOVDD 0.7 x IOVDD DGND IOVDD − 0.5 DGND + 0.5 ±10 IOVDD 0.3 x IOVDD V V V V µA fCLK = 40MHz 45 40 55 MHz % TEST CONDITIONS MIN TYP MAX UNIT 5 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 DEFINITIONS Absolute Input Voltage Absolute input voltage, given in volts, is the voltage of each analog input (AINN or AINP) with respect to AGND. Intermodulation Distortion (IMD) IMD, given in dB, is measured while applying two input signals of the same magnitude, but with slightly different frequencies. It is calculated as the difference between the rms amplitude of the input signal to the rms amplitude of the peak spurious signal. Aperture Delay Aperture delay is the delay between the rising edge of CLK and the sampling of the input signal. Common-Mode Input Voltage Common-mode input voltage (VCM) is the average voltage of the analog inputs: Offset Error Offset Error, given in % of FSR, is the output reading when the differential input is zero. (AINP ) AINN) 2 Differential Input Voltage Differential input voltage (VIN) is the voltage difference between the analog inputs (AINP−AINN). Offset Error Drift Offset error drift, given in ppm of FSR/_C, is the drift over temperature of the offset error. The offset error is specified as the larger of the drift from ambient (T = 25_C) to the minimum or maximum operating temperatures. Signal-to-Noise Ratio (SNR) SNR, given in dB, is the ratio of the rms value of the input signal to the sum of all the frequency components below fCLK/2 (the Nyquist frequency) excluding the first six harmonics of the input signal and the dc component. Differential Nonlinearity (DNL) DNL, given in least-significant bits of the output code (LSB), is the maximum deviation of the output code step sizes from the ideal value of 1LSB. Full-Scale Range (FSR) FSR is the difference between the maximum and minimum measurable input signals (FSR = 2VREF). Signal-to-Noise and Distortion (SINAD) SINAD, given in dB, is the ratio of the rms value of the input signal to the sum of all the frequency components below fCLK/2 (the Nyquist frequency) including the harmonics of the input signal but excluding the dc component. Gain Error Gain error, given in %, is the error of the full-scale input signal with respect to the ideal value. Spurious-Free Dynamic Range (SFDR) SFDR, given in dB, is the difference between the rms amplitude of the input signal to the rms amplitude of the peak spurious signal. Gain Error Drift Gain error drift, given in ppm/_C, is the drift over temperature of the gain error. The gain error is specified as the larger of the drift from ambient (T = 25_C) to the minimum or maximum operating temperatures. Total Harmonic Distortion (THD) THD, given in dB, is the ratio of the sum of the rms value of the first six harmonics of the input signal to the rms value of the input signal. Integral Nonlinearity (INL) INL, given in least-significant bits of the output code (LSB), is the maximum deviation of the output codes from a best fit line. 6 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 PIN ASSIGNMENTS VREFN VREFN VREFP VREFP IOVDD 37 DGND 38 AGND AGND 39 AVDD VCAP VMID CLK 40 48 47 46 45 44 43 42 41 AGND AVDD AGND AINN AINP 1 2 3 4 5 6 7 8 9 36 DGND 35 NC 34 DVDD 33 DGND 32 FSO TQFP PACKAGE (TOP VIEW) AGND AVDD RBIAS AGND ADS1602 31 FSO 30 DOUT 29 DOUT 28 SCLK 27 SCLK 26 NC 25 NC AVDD 10 AGND 11 AVDD 12 13 REFEN 14 NC 15 RPULLUP 16 NC 17 PD 18 DVDD 19 DGND 20 SYNC 21 OTR 22 DGND 23 DVDD 24 NC Terminal Functions TERMINAL NAME AGND AVDD AINN AINP RBIAS REFEN NC RPULLUP PD DVDD DGND SYNC OTR SCLK SCLK DOUT DOUT NO. 1, 3, 6, 9, 11, 39, 41 2, 7, 10, 12, 42 4 5 8 13 14, 16, 24−26, 35 15 17 18, 23, 34 19, 22, 33, 36, 38 20 21 28 27 30 29 32 31 37 40 43 44, 45 46 47, 48 FUNCTION Analog Analog Analog input Analog input Analog Digital input: active low Do not connect Digital Input Digital input: active low Digital Digital Digital input Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital Digital input Analog Analog Analog Analog Analog ground Analog supply Negative analog input Positive analog input DESCRIPTION Terminal for external analog bias setting resistor. Internal reference enable. Internal pull-down resistor of 170kΩ to DGND. These terminals must be left unconnected. Pull-up to DVDD with 10kΩ resistor (see Figure 53). Power down all circuitry. Internal pull-up resistor of 170kΩ to DGND. Digital supply Digital ground Synchronization control input Indicates analog input signal is out of range. Serial clock output Serial clock output, complementary signal. Data output Data output, complementary signal. Frame synchronization output Frame synchronization output, complementary signal. Digital I/O supply Clock input Terminal for external bypass capacitor connection to internal bias voltage. Negative reference voltage Midpoint voltage Positive reference voltage 7 FSO FSO IOVDD CLK VCAP VREFN VMID VREFP ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TIMING DIAGRAMS CLK t STL SYNC tSYPW FSO Figure 1. Initialization Timing TIMING REQUIREMENTS For TA = −40°C to +85°C, DVDD = 2.7V to 3.6V, IOVDD = 2.7V to 5.25V. SYMBOL tSYPW tSTL DESCRIPTION SYNC positive pulse width Settling time of ADS1602(1) MIN 2 51 816 TYP MAX 16 52 832 UNIT CLK periods Conversions CLK periods NOTE: (1) An FSO pulse occuring prior to TSTL ≥ 816 CLK period should be ignored. tC CLK t CPW tCPW tCF FSO tFPW tCS SCLK tDHD DOUT Bit 0 (LSB) tDPD Bit 15 (MSB) Bit 14 Bit 1 Bit 0 (LSB) Old Data New Data Figure 2. Data Retrieval Timing TIMING REQUIREMENTS For TA = −40°C to +85°C, DVDD = 2.7V to 3.6V, IOVDD = 2.7V to 5.25V. SYMBOL tC tCPW tCF tFPW tCS tDHD tDPD DESCRIPTION CLK period (1/fCLK) CLK positive or negative pulse width Rising edge of CLK to rising edge of FSO FSO positive pulse width Rising edge of CLK to rising edge of SCLK SCLK rising edge to old DOUT invalid (hold time) SCLK rising edge to new DOUT valid (propagation delay) 0 5 1 15 MIN 25 11.25 15 TYP MAX UNIT ns ns ns CLK period ns ns ns 8 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SPECTRAL RESPONSE 0 − 20 − 40 Amplitude (dB) − 60 − 80 − 100 − 120 − 140 − 160 0 200 400 600 800 Frequency (kHz) 1000 1200 fIN = 10kHz, − 1dBFS SNR = 92dB THD = − 94dB SFDR = 95dB 0 − 20 − 40 Amplitude (dB) − 60 − 80 − 100 − 120 − 140 − 160 0 200 SPECTRAL RESPONSE fIN = 10kHz, − 6dBFS SNR = 87dB THD = − 108dB SFDR = 112dB 400 600 800 1000 1200 Frequency (kHz) Figure 3 SPECTRAL RESPONSE 0 − 20 − 40 Amplitude (dB) − 60 − 80 − 100 − 120 − 140 − 160 0 200 400 600 800 1000 1200 Frequency (kHz) fIN = 10kHz, − 10dBFS SNR = 83dB THD = − 105dB SFDR = 110dB 0 − 20 − 40 Amplitude (dB) − 60 − 80 − 100 − 120 − 140 − 160 0 200 Figure 4 SPECTRAL RESPONSE fIN = 100kHz, − 1dBFS SNR = 90dB THD = − 90dB SFDR = 91dB 400 600 800 Frequency (kHz) 1000 1200 Figure 5 SPECTRAL RESPONSE 0 − 20 − 40 Amplitude (dB) − 60 − 80 − 100 − 120 − 140 − 160 0 200 400 600 800 Frequency (kHz) 1000 1200 f IN = 100kHz, − 6dBFS SNR = 86dB THD = − 101dB SFDR = 103dB 0 − 20 − 40 Amplitude (dB) − 60 − 80 − 100 − 120 − 140 − 160 0 200 Figure 6 SPECTRAL RESPONSE fIN = 100kHz, − 10dBFS SNR = 82dB THD = − 100dB SFDR = 102dB 400 600 800 1000 1200 Frequency (kHz) Figure 7 Figure 8 9 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SPECTRAL RESPONSE 0 − 20 − 40 Amplitude (dB) − 60 − 80 −100 −120 −140 −160 0 200 400 600 800 1000 1200 Frequency (kHz) fIN = 504kHz, − 1dBFS SNR = 91dB THD = − 119dB SFDR = 119dB 0 − 20 − 40 Amplitude (dB) − 60 − 80 − 100 − 120 − 140 − 160 0 200 SPECTRAL RESPONSE fIN = 504kHz, − 6dBFS SNR = 86dB THD = − 103dB SFDR = 103dB 800 400 600 Frequency (kHz) 1000 1200 Figure 9 SPECTRAL RESPONSE 0 − 20 − 40 Amplitude (dB) − 60 − 80 − 100 − 120 − 140 − 160 0 200 400 600 800 1000 1200 Frequency (kHz) fIN = 504kHz, − 10dBFS SNR = 82dB THD = − 96dB SFDR = 96dB 0 − 20 − 40 Amplitude (dB) − 60 − 80 − 100 − 120 − 140 − 160 0 200 Figure 10 SPECTRAL RESPONSE fIN = 799kHz, − 1dBFS SNR = 91dB THD = − 116dB SFDR = 120dB 800 400 600 Frequency (kHz) 1000 1200 Figure 11 SPECTRAL RESPONSE 0 − 20 − 40 Amplitude (dB) − 60 − 80 − 100 − 120 − 140 − 160 0 200 800 400 600 Frequency (kHz) 1000 1200 fIN = 799kHz, − 6dBFS SNR = 86dB THD = − 110dB SFDR = 114dB Amplitude (dB) 0 − 20 − 40 − 60 − 80 − 100 − 120 − 140 − 160 0 200 Figure 12 SPECTRAL RESPONSE f IN = 799kHz, − 10dBFS SNR = 82dB THD = − 107dB SFDR = 112dB 800 400 600 Frequency (kHz) 1000 1200 Figure 13 Figure 14 10 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE SIGNAL−TO−NOISE RATIO, TOTAL HARMONIC DISTORTION, SPURIOUS−FREE DYNAMIC RANGE (dB) 140 120 100 80 SNR 60 40 20 − 80 fIN = 10kHz − 70 − 60 − 50 − 40 − 30 − 20 − 10 0 SIGNAL−TO−NOISE RATIO, TOTAL HARMONIC DISTORTION, SPURIOUS−FREE DYNAMIC RANGE (dB) 120 110 100 90 80 70 60 50 40 30 20 − 80 SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE SFDR THD SNR SFDR THD fIN = 50kHz − 70 − 60 − 50 − 40 − 30 − 20 − 10 0 Input Signal Amplitude, VIN (dB) Input Signal Amplitude, VIN (dB) Figure 15 SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE SIGNAL−TO−NOISE RATIO, TOTAL HARMONIC DISTORTION, SPURIOUS−FREE DYNAMIC RANGE (dB) 140 120 100 SFDR 80 60 40 fIN = 100kHz 20 − 80 − 70 − 60 − 50 − 40 − 30 − 20 − 10 0 THD SNR SIGNAL−TO−NOISE RATIO, TOTAL HARMONIC DISTORTION, SPURIOUS−FREE DYNAMIC RANGE (dB) 140 120 100 Figure 16 SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE SFDR 80 60 SNR 40 THD fIN = 500kHz 20 − 80 − 70 − 60 − 50 − 40 − 30 − 20 − 10 0 Input Signal Amplitude, VIN (dB) Input Signal Amplitude, VIN (dB) Figure 17 SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE SIGNAL−TO−NOISE RATIO, TOTAL HARMONIC DISTORTION, SPURIOUS−FREE DYNAMIC RANGE (dB) 140 120 100 SNR (dB) SFDR 80 60 SNR 40 fIN = 800kHz 20 − 80 − 70 − 60 − 50 − 40 − 30 − 20 − 10 0 70 10k 75 THD 85 95 Figure 18 SIGNAL−TO−NOISE RATIO vs INPUT FREQUENCY VIN = − 1dB 90 VIN = − 6dB VIN = − 10dB 80 100k Input Frequency, fIN (Hz) 1M Input Signal Amplitude, VIN (dB) Figure 19 Figure 20 11 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY − 80 − 85 − 90 THD (dB) − 95 − 100 − 105 − 110 − 115 − 120 10k 100k Input Frequency, fIN (Hz) VIN = − 1dB 1M 70 10k VIN = − 6dB VIN = − 10dB SFDR (dB) 130 120 SPURIOUS−FREE DYNAMIC RANGE vs INPUT FREQUENCY VIN = − 10dB 110 100 90 80 VIN = − 6dB VIN = − 1dB 100k Input Frequency, fIN (Hz) 1M Figure 21 SIGNAL−TO−NOISE RATIO vs INPUT COMMON−MODE VOLTAGE 93 92 91 SNR (dB) THD (dB) 90 89 88 87 86 85 1.0 1.4 1.8 2.2 2.6 3.0 3.4 Input Common−Mode Voltage, VCM (V) fIN = 100kHz, VIN = − 6dB fIN = 10kHz, VIN = − 6dB − 110 1.0 f IN = 10kHz, VIN = − 1dB fIN = 100kHz, VIN = − 1dB − 70 Figure 22 TOTAL HARMONIC DISTORTION vs INPUT COMMON−MODE VOLTAGE fIN = 100kHz, VIN = − 1dB − 80 fIN = 10kHz, VIN = − 1dB − 90 − 100 fIN = 10kHz, VIN = − 6dB 1.4 1.8 2.2 fIN = 100kHz, VIN = − 6dB 2.6 3.0 3.4 Input Common−Mode Voltage, VCM (V) Figure 23 SPURIOUS−FREE DYNAMIC RANGE vs INPUT COMMON−MODE VOLTAGE 110 105 100 SFDR (dB) 95 90 85 fIN = 100kHz, VIN = − 1dB 80 1.0 1.4 1.8 2.2 2.6 3.0 3.4 Input Common−Mode Voltage, VCM (V) f IN = 10kHz VIN = − 1dB f IN = 10kHz, VIN = − 6dB fIN = 100kHz, VIN = − 6dB Offset (LSB) 3 2 1 0 −1 −2 −3 0 Figure 24 OFFSET DRIFT OVER TIME 100 200 300 400 500 600 700 800 900 1000 Time Interval (s) Figure 25 12 Figure 26 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SIGNAL−TO−NOISE RATIO vs CLOCK FREQUENCY 100 90 80 80 SNR (dB) 70 RBIAS = 210kΩ 60 50 RBIAS = 267kΩ 40 30 5 10 15 20 25 30 35 40 45 50 Clock Frequency, fCLK (MHz) RBIAS = 140kΩ RBIAS = 100kΩ RBIAS = 60kΩ THD (dB) 70 60 50 40 30 20 5 10 VIN = − 6dBFS, f IN = 10kHz 110 RBIAS = 30kΩ RBIAS = 37kΩ 100 90 TOTAL HARMONIC DISTORTION vs CLOCK FREQUENCY RBIAS = 37kΩ RBIAS = 267kΩ RBIAS = 210kΩ RBIAS = 140kΩ RBIAS = 60kΩ RBIAS = 30kΩ RBIAS = 100kΩ VIN = − 6dBFS, fIN = 10kHz 15 20 25 30 35 40 45 50 Clock Frequency, fCLK (MHz) Figure 27 SPURIOUS−FREE DYNAMIC RANGE vs CLOCK FREQUENCY 110 100 90 SFDR (dB) 80 70 60 50 40 30 20 5 10 15 20 25 30 35 40 45 50 Clock Frequency, fCLK (MHz) RBIAS = 267kΩ RBIAS = 210kΩ RBIAS = 140kΩ VIN = − 6dBFS, fIN = 10kHz RBIAS = 60kΩ RBIAS = 30kΩ RMS Noise (LSB) 1000 RBIAS = 37kΩ 100 Figure 28 NOISE vs DC INPUT VOLTAGE 10 RBIAS = 100kΩ 1 0.1 −3 −2 −1 0 1 2 3 Input DC Voltage (V) Figure 29 Figure 30 POWER−SUPPLY CURRENT vs TEMPERATURE 120 VIN = 0 100 Current (mA) 80 60 40 20 RBIAS = 37kΩ, fCLK = 40MHz 0 IDVDD + IIOVDD IAVDD (REFEN = low) IAVDD ( REFEN = high) NOISE HISTOGRAM 1540 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 Occurrences −4 −3 −2 −1 0 1 2 3 4 − 40 − 15 10 35 60 85 Output Code (LSB) Temperature (_ C) Figure 31 Figure 32 13 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SUPPLY−CURRENT vs CLOCK FREQUENCY 140 120 Supply Current (mA) 100 80 60 40 20 0 0 5 10 15 20 25 30 35 40 Clock Frequency, fCLK (MHz) I IOVDD + IDVDD IAVDD (REFEN = high) Analog Supply Current, I AVDD (mA) VIN = − 6dBFS, fIN = 10kHz, RBIAS = 37kΩ IAVDD (REFEN = low) 130 110 90 70 50 30 10 0 ANALOG SUPPLY CURRENT vs RBIAS VIN = − 6dBFS, fIN = 10kHz, f CLK = 40MHz IAVDD (REFEN = low) IAVDD (REFEN = high) 50 100 150 RBIAS (kΩ ) 200 250 300 Figure 33 SIGNAL−TO−NOISE RATIO vs TEMPERATURE 100 95 VIN = − 1dB 90 SNR (dB) VIN = − 6dB 85 80 75 fIN = 100kHz 70 − 40 − 15 10 35 60 85 Temperature (_ C) − 105 − 40 − 15 − 100 VIN = − 10dB VIN = − 10dB THD (dB) − 90 − 95 − 80 − 85 VIN = − 1dB VIN = − 6dB Figure 34 TOTAL HARMONIC DISTORTION vs TEMPERATURE 10 35 60 85 Temperature (_ C) Figure 35 SPURIOUS−FREE DYNAMIC RANGE vs TEMPERATURE 120 115 110 SFDR (dB) 105 100 95 90 85 80 − 40 − 15 10 35 60 VIN = − 6dB VIN = − 10dB Figure 36 VIN = − 1dB 85 Temperature (_ C) Figure 37 14 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 OVERVIEW The ADS1602 is a high-performance delta-sigma ADC. The modulator uses an inherently stable 2-1-1 multi-stage architecture incorporating proprietary circuitry that allows for very linear high-speed operation. The modulator samples the input signal at 40MSPS (when fCLK = 40MHz). A low-ripple linear phase digital filter decimates the modulator output by 16 to provide high resolution 16-bit output data. Conceptually, the modulator and digital filter measure the differential input signal, VIN = (AINP – AINN), against the scaled differential reference, VREF = (VREFP – VREFN), as shown in Figure 38. The voltage reference can either be generated internally or supplied externally. A 3-wire serial interface, designed for direct connection to DSPs, outputs the data. A separate power supply for the I/O allows flexibility for interfacing to different logic families. Out-of-range conditions are indicated with a dedicated digital output pin. Analog power dissipation is controlled using an external resistor. This control allows reduced dissipation when operating at slower speeds. When not in use, power consumption can be dramatically reduced by setting the PD pin low to enter Power-Down mode. digital output code of 7FFFh. Likewise, the most negative measurable differential input is –VREF, which produces the most negative digital output code of 8000h. The ADS1602 supports a very wide range of input signals. For VREF = 3V, the full-scale input voltages are ±3V. Having such a wide input range makes out-of-range signals unlikely. However, should an out-of-range signal occur, the digital output OTR will go high. The analog inputs must be driven with a differential signal to achieve optimum performance. For the input signal: V CM + AINP ) AINN 2 the recommended common-mode voltage is 1.5V. In addition to the differential and common-mode input voltages, the absolute input voltage is also important. This is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is: * 0.1V t (AINN or AINP) t 4.6V If either input is taken below –0.1V, ESD protection diodes on the inputs will turn on. Exceeding 4.6V on either input will result in degradation in the linearity performance. ESD protection diodes will also turn on if the inputs are taken above AVDD (+5V). The recommended absolute input voltage is: ANALOG INPUTS (AINP, AINN) The ADS1602 measures the differential signal, VIN = (AINP – AINN), against the differential reference, VREF = (VREFP – VREFN). The most positive measurable differential input is VREF, which produces the most positive * 0.1V t (AINN or AINP) t 4.2V Keeping the inputs within this range provides for optimum performance. VREFP VREFN IOVDD CLK Σ VREF AINP AINN VIN Σ∆ Modulator Digital Filter Serial Interface Σ FSO FSO SCLK SCLK DOUT DOUT Figure 38. Conceptual Block Diagram 15 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 INPUT CIRCUITRY The ADS1602 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged internally with this cycle repeating at the frequency of CLK. Figure 39 shows a conceptual diagram of these circuits. Switches S2 represent the net effect of the modulator circuitry in discharging the sampling capacitors; the actual implementation is different. The timing for switches S1 and S2 is shown in Figure 40. ADS1602 S1 AINP S2 10pF 8pF external capacitors, between the inputs and from each input to AGND, improve linearity and should be placed as close to the pins as possible. Place the drivers close to the inputs and use good capacitor bypass techniques on their supplies, such as a smaller high-quality ceramic capacitor in parallel with a larger capacitor. Keep the resistances used in the driver circuits low—thermal noise in the driver circuits degrades the overall noise performance. When the signal can be ac-coupled to the ADS1602 inputs, a simple RC filter can set the input common-mode voltage. The ADS1602 is a high-speed, high-performance ADC. Special care must be taken when selecting the test equipment and setup used with this device. Pay particular attention to the signal sources to ensure they do not limit performance when measuring the ADS1602. VMID S1 AINN S2 10pF 8pF VCM(1) − VIN 2 392Ω 392Ω 40pF 0.01µF 392Ω OPA28 22 (2) 49.9Ω AINP 100pF VMID AGND 392Ω 1µ F 392 Ω 1kΩ (2) VCM(1) (2) 100pF(3) ADS1602 Figure 39. Conceptual Diagram of Internal Circuitry Connected to the Analog Inputs VIN 2 392Ω 40pF 1kΩ 0.01µF 49.9Ω AINN 100pF 392Ω V CM(1) OPA28 22 (2) t SAMPLE = 1/f CLK On S1 Off On S2 Off 392Ω 1µ F A GND (1) Recommended VCM = 1.5V. (2) Optional ac−coupling circuit provides common−mode input voltage. (3) Increase to 390pF when fIN ≤ 100kHz for improved SNR and THD. Figure 41. Recommended Driver Circuit Using the OPA2822 Figure 40. Timing for the Switches in Figure 39 22pF 24.9Ω DRIVING THE INPUTS The external circuits driving the ADS1602 inputs must be able to handle the load presented by the switching capacitors within the ADS1602. The input switches S1 in Figure 39 are closed for approximately one-half of the sampling period, tsample, allowing only ≈ 11ns for the internal capacitors to be charged by the inputs when fCLK = 40MHz. Figure 41 and Figure 42 show the recommended circuits when using single-ended or differential op amps, respectively. The analog inputs must be driven differentially to achieve optimum performance. The − VIN +VIN 392Ω 392Ω VCM AINP 392Ω THS4503 100pF 100pF 24.9Ω AINN 100pF ADS1602 392Ω 22pF Figure 42. Recommended Driver Circuit Using the THS4503 Differential Amplifier 16 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 REFERENCE INPUTS (VREFN, VREFP, VMID) The ADS1602 can operate from an internal or external voltage reference. In either case, the reference voltage VREF is set by the differential voltage between VREFN and VREFP: VREF = (VREFP – VREFN). VREFP and VREFN each use two pins, which should be shorted together. VMID equals approximately 2.5V and is used by the modulator. VCAP connects to an internal node and must also be bypassed with an external capacitor. of providing both a dc and a transient current. Figure 44 shows a simplified diagram of the internal circuitry of the reference when the internal reference is disabled. As with the input circuitry, switches S1 and S2 open and close as shown by the timing in Figure 40. ADS1602 S1 VREFP VREFP S2 300Ω VREFN VREFN S1 50pF INTERNAL REFERENCE (REFEN = LOW) To use the internal reference, set the REFEN pin low. This activates the internal circuitry that generates the reference voltages. The internal reference voltages are applied to the pins. Good bypassing of the reference pins is critical to achieve optimum performance and is done by placing the bypass capacitors as close to the pins as possible. Figure 43 shows the recommended bypass capacitor values. Use high-quality ceramic capacitors for the smaller values. Avoid loading the internal reference with external circuitry. If the ADS1602 internal reference is to be used by other circuitry, buffer the reference voltages to prevent directly loading the reference pins. ADS1602 VREFP VREFP Figure 44. Conceptual Internal Circuitry for the Reference When REFEN = High Figure 45 shows the recommended circuitry for driving these reference inputs. Keep the resistances used in the buffer circuits low to prevent excessive thermal noise from degrading performance. Layout of these circuits is critical; be sure to follow good high-speed layout practices. Place the buffers, and especially the bypass capacitors, as close to the pins as possible. VCAP is unaffected by the setting on REFEN and must be bypassed when using the internal or an external reference. 392Ω 0.001µF ADS1602 10µ F 0.1µ F 0.1µF VMID 10µ F 0.1µF OPA2822 4V 392Ω 10µF 0.1µF 0.1µF VREFP VREFP VREFN VREFN 10µ F 0.1µF 0.001µF OPA2822 VMID 10µF 0.1µ F VCAP 0.1µF AGND 2.5V 392Ω 0.001µF Figure 43. Reference Bypassing When Using the Internal Reference EXTERNAL REFERENCE (REFEN = HIGH) To use an external reference, set the REFEN pin high. This deactivates the internal generators for VREFP, VREFN and VMID, and saves approximately 25mA of current on the analog supply (AVDD). The voltages applied to these pins must be within the values specified in the Electrical Characteristics table. Typically, VREFP = 4V, VMID = 2.5V and VREFN = 1V. The external circuitry must be capable OPA2822 VREFN VREFN 10µF 0.1µ F 1V VCAP 0.1µ F AGND Figure 45. Recommended Buffer Circuit When Using an External Reference 17 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 CLOCK INPUT (CLK) The ADS1602 requires an external clock signal to be applied to the CLK input pin. The sampling of the modulator is controlled by this clock signal. As with any high-speed data converter, a high quality clock is essential for optimum performance. Crystal clock oscillators are the recommended CLK source; other sources, such as frequency synthesizers, are usually inadequate. Make sure to avoid excess ringing on the CLK input; keeping the trace as short as possible will help. Measuring high-frequency, large amplitude signals requires tight control of clock jitter. The uncertainty during sampling of the input from clock jitter limits the maximum achievable SNR. This effect becomes more pronounced with higher frequency and larger magnitude inputs. Fortunately, the ADS1602 oversampling topology reduces clock jitter sensitivity over that of Nyquist rate converters such as pipeline and successive approximation converters by a factor of 16. In order to not limit the ADS1602 SNR performance, keep the jitter on the clock source below the values shown in Table 1. When measuring lower frequency and lower amplitude inputs, more CLK jitter can be tolerated. In determining the allowable clock source jitter, select the worst-case input (highest frequency, largest amplitude) that will be seen in the application. DATA FORMAT The 16-bit output data is in binary two’s complement format as shown in Table 2. When the input is positive out-of-range, exceeding the positive full-scale value of VREF, the output clips to all 7FFFh and the OTR output goes high. Likewise, when the input is negative out-of-range by going below the negative full-scale value of –VREF, the output clips to 8000h and the OTR output goes high. The OTR remains high while the input signal is out-of-range. Table 2. Output Code Versus Input Signal INPUT SIGNAL (INP – INN) ≥ +VREF (> 0dB) VREF (0dB) IDEAL OUTPUT CODE(1) 7FFFh 7FFFh 0001h 0000h FFFFh 8000h 8000h OTR 1 0 0 0 0 0 1 +V REF 2 15 *1 0 −V REF 2 15 −V REF *1 2 15 2 15 * 1 2 15 2 15 * 1 v −V REF Table 1. Maximum Allowable Clock Source Jitter for Different Input Signal Frequencies and Amplitude INPUT SIGNAL MAXIMUM FREQUENCY 1MHz 1MHz 500kHz 500kHz 100kHz 100kHz MAXIMUM AMPLITUDE −2dB −20dB −2dB −20dB −2dB −20dB MAXIMUM ALLOWABLE CLOCK SOURCE JITTER 3.8ps 28ps 7.6ps 57ps 38ps 285ps (1) Excludes effects of noise, INL, offset and gain errors. OUT-OF-RANGE INDICATION (OTR) If the output code exceeds the positive or negative full-scale, the out-of-range digital output OTR will go high on the falling edge of SCLK. When the output code returns within the full-scale range, OTR returns low on the falling edge of SCLK. DATA RETRIEVAL Data retrieval is controlled through a simple serial interface. The interface operates in a master fashion by outputting both a frame sync indicator (FSO) and a serial clock (SCLK). Complementary outputs are provided for the frame sync output (FSO), serial clock (SCLK) and data output (DOUT). When not needed, leave the complementary outputs unconnected. 18 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 INITIALIZING THE ADS1602 After the power supplies have stabilized, you must initialize the ADS1602 by issuing a SYNC pulse as shown in Figure 1. This operation needs only to be done once after power-up and does not need to be performed when exiting the Power-Down mode. STEP RESPONSE Figure 47 plots the normalized step response for an input applied at t = 0. The x-axis units of time are conversions cycles. It takes 51 cycles to fully settle; for fCLK = 40MHz, this corresponds to 20.4µs. SYNCHRONIZING MULTIPLE ADS1602s The SYNC input can be used to synchronize multiple ADS1602s to provide simultaneous sampling. All devices to be synchronized must use a common CLK input. With the CLK inputs running, pulse SYNC on the falling edge of CLK, as shown in Figure 46. Afterwards, the converters will be converting synchronously with the FSO outputs updating simultaneously. After synchronization, FSO is held low until the digital filter has fully settled. 1.2 1.0 0.8 Step Response 0.6 0.4 0.2 0 ADS16021 SYNC CLK SYNC CLK FSO DOUT FSO1 DOUT1 − 0.2 0 10 20 30 40 50 Time (Conversion Cycles) ADS16022 SYNC CLK FSO DOUT FSO2 DOUT2 Figure 47. Step Response CLK ... ... SYNC t STL FSO 1 FSO 2 Figure 46. Synchronizing Multiple Converters 19 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 FREQUENCY RESPONSE The linear phase FIR digital filter sets the overall frequency response. Figure 48 shows the frequency response from dc to 20MHz for fCLK = 40MHz. The frequency response of the ADS1602 filter scales directly with CLK frequency. For example, if the CLK frequency is decreased by half (to 20MHz), the values on the X-axis in Figure 48 would need to be scaled by half, with the span becoming dc to 10MHz. Figure 49 shows the passband ripple from dc to 1200kHz (fCLK = 40MHz). Figure 50 shows a closer view of the passband transition by plotting the response from 900kHz to 1300kHz (fCLK = 40MHz). 0.5 0 − 0.5 Magnitude (dB) − 1.0 − 1.5 − 2.0 − 2.5 − 3.0 − 3.5 800 900 1000 1100 1200 1300 Frequency (kHz) fCLK = 40MHz 20 fCLK = 40MHz 0 − 20 Magnitude (dB) − 40 − 60 − 80 − 100 − 120 − 140 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 50. Passband Transition ANTI−ALIAS REQUIREMENTS Higher frequency, out-of-band signals must be eliminated to prevent aliasing with ADCs. Fortunately, the ADS1602 on-chip digital filter greatly simples this filtering requirement. Figure 51 shows the ADS1602 response out to 120MHz (fCLK = 40MHz). Since the stop band extends out to 38.6MHz, the anti-alias filter in front of the ADS1602 only needs to be designed to remove higher frequency signals than this, which can usually be accomplished with a simple RC circuit on the input driver. Figure 48. Frequency Response 20 0.001 0.0008 0.0006 Magnitude (dB) Magnitude (dB) 0.0004 0.0002 0 − 0.0002 − 0.0004 − 0.0006 − 0.0008 − 0.001 0 200 400 600 Frequency (kHz) fCLK = 40MHz 800 1000 1200 fCLK = 40MHz 0 − 20 − 40 − 60 − 80 − 100 − 120 − 140 0 20 40 60 80 100 120 Frequency (MHz) Figure 51. Frequency Response Out to 120MHz Figure 49. Passband Ripple 20 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 ANALOG POWER DISSIPATION An external resistor connected between the RBIAS pin and the analog ground sets the analog current level, as shown in Figure 52. The current is inversely proportional to the resistor value. Table 3 shows the recommended values of RBIAS for different CLK frequencies. Notice that the analog current can be reduced when using a slower frequency CLK input because the modulator has more time to settle. Avoid adding any capacitance in parallel to RBIAS, since this will interfere with the internal circuitry used to set the biasing. Table 3. Recommended RBIAS Resistor Values for Different CLK Frequencies fCLK 16MHz 24MHz 32MHz 40MHz DATA RATE 1MHz 1.5MHz 2MHz 2.5MHz RBIAS 140kΩ 100kΩ 60kΩ 37kΩ TYPICAL POWER DISSIPATION WITH REFEN HIGH 200mW 270mW 390mW 530mW POWER DOWN (PD) When not in use, the ADS1602 can be powered down by taking the PD pin low. All circuitry will be shut down, including the voltage reference. To minimize the digital current during power down, stop the clock signal supplied to the CLK input. There is an internal pull-up resistor of 170kΩ on the PD pin, but it is recommended that this pin be connected to IOVDD if not used. Make sure to allow time for the reference to start up after exiting power-down mode. The internal reference typically requires 15ms. After the reference has stabilized, allow at least 100 conversions for the modulator and digital filter to settle before retrieving data. ADS1602 RBIAS RBIAS AGND Figure 52. External Resistor Used to Set Analog Power Dissipation 21 ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 POWER SUPPLIES Three supplies are used on the ADS1602: analog (AVDD), digital (DVDD) and digital I/O (IOVDD). Each supply must be suitably bypassed to achieve the best performance. It is recommended that a 1µF and 0.1µF ceramic capacitor be placed as close to each supply pin as possible. Connect each supply-pin bypass capacitor to the associated ground, as shown in Figure 53. Each main supply bus should also be bypassed with a bank of capacitors from 47µF to 0.1µF, as shown. The I/O and digital supplies (IOVDD and DVDD) can be connected together when using the same voltage. In this case, only one bank of 47µF to 0.1µF capacitors is needed on the main supply bus, though each supply pin must still be bypassed with a 1µF and 0.1µF ceramic capacitor. DVDD 47µF 4.7µ F 1 µF 0.1µ F IOVDD 47µF AVDD 47µF 4.7µ F 1 µF 0.1µ F 42 AVDD 1 CP AGND 41 AGND 55 AGND 38 DGND 37 IOVDD 34 DVDD 33 DGND DGND 36 4.7µ F 1 µF 0.1µ F CP CP CP If using separate analog and digital ground planes, connect together on the ADS1602 PCB. 2 3 AVDD 6 CP AGND DGND AGND 7 AVDD ADS1602 9 AGND NOTE: CP = 1µF   0.1µF CP 10 AVDD 11 AGND CP 12 AVDD RPULLUP DGND DGND 22 CP DVDD 15 18 CP 19 23 10kΩ Figure 53. Recommended Power-Supply Bypassing 22 DVDD ADS1602 www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 LAYOUT ISSUES AND COMPONENT SELECTION The ADS1602 is a very high-speed, high-resolution data converter. In order to achieve maximum performance, the user must give very careful consideration to both the layout of the printed circuit board (PCB) in addition to the routing of the traces. Capacitors that are critical to achieve the best performance from the device should be placed as close to the pins of the device as possible. These include capacitors related the analog inputs, the reference and the power supplies. For critical capacitors, it is recommended that Class II dielectrics such as Z5U be avoided. These dielectrics have a narrow operating temperature, a large tolerance on the capacitance and will lose up to 20% of the rated capacitance over 10,000 hours. Rather, select capacitors with a Class I dielectric. C0G (also known as NP0), for example, has a tight tolerance < ±30PPM/ °C and is very stable over time. Should Class II capacitors be chosen because of the size constraints, select an X7R or X5R dielectric to minimize the variations of the capacitor’s critical characteristics. The resistors used in the circuits driving the input and reference should be kept as low as possible to prevent excess thermal noise from degrading the system performance. The digital outputs from the device should always be buffered. This will have a number of benefits: it will reduce the loading of the internal digital buffers, which decreases noise generated within the device, and it will also reduce device power consumption. The McBSP provides a host of functions including: D D D Full-duplex communication Double-buffered data registers Independent framing and clocking for reception and transmission of data The sequence begins with a one-time synchronization of the serial port by the microprocessor. The ADS1602 recognizes the SYNC signal if it is high for a least 1 CLK period. Transfers are initiated by the ADS1602 after the SYNC signal is de-asserted by the microprocessor. The FSO signal from the ADS1602 indicates that data is available to be read, and is connected to the Frame Sync Receive (FSR) pin of the DSP. The Clock Receiver (CLKR) is derived directly from the ADS1602 serial clock output to ensure continued synchronization of data with the clock. ADS1602 FSO TMS320 FSR SCLK CLKR DOUT DR SYNC FSX APPLICATIONS INFORMATION Interfacing the ADS1602 to the TMS320 DSP family. Since the ADS1602 communicates with the host via a serial interface, the most suitable method to connect to any of the TMS320 DSPs is via the Multi-channel Buffered Serial Port (McBSP). A typical connection to the TMS320 DSP is shown in Figure 54. Figure 54. ADS1602—TMS320 Interface Connection An Evaluation Module (EVM) is available from Texas Instruments. The module consists of the ADS1602 and supporting circuits, allowing users to quickly assess the performance and characteristics of the ADS1602. The EVM easily connects to various microcontrollers and DSP systems. For more details, or to download a copy of the ADS1602EVM User’s Guide, visit the Texas Instruments web site at www.ti.com. 23 PACKAGE OPTION ADDENDUM www.ti.com 19-Apr-2005 PACKAGING INFORMATION Orderable Device ADS1602IPFBR ADS1602IPFBRG4 ADS1602IPFBT ADS1602IPFBTG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE Package Type TQFP TQFP TQFP TQFP Package Drawing PFB PFB PFB PFB Pins Package Eco Plan (2) Qty 48 48 48 48 1000 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,50 36 25 0,27 0,17 0,08 M 37 24 48 13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,05 MIN 1,05 0,95 Seating Plane 0,75 0,45 Gage Plane 0,25 0°– 7° 12 1,20 MAX 0,08 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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