ADS1672
AD
S1
672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
625kSPS, 24-Bit Analog-to-Digital Converter
Check for Samples: ADS1672
FEATURES
DESCRIPTION
•
The ADS1672 is a high-speed, high-precision
analog-to-digital converter (ADC). Using an advanced
delta-sigma (ΔΣ) architecture, it operates at speeds
up to 625kSPS with outstanding ac performance and
dc accuracy.
1
2
•
•
•
•
•
•
•
AC Performance:
107dB of Dynamic Range at 625kSPS
115.5dB of Dynamic Range at 78kSPS
–113dB THD
DC Accuracy:
3ppm INL
2mV/°C Offset Drift
2ppm/°C Gain Drift
Programmable Digital Filter with
User-Selectable Path:
– Low-Latency: Completely settles in 5.5ms
– Wide-Bandwidth: 305kHz BW with flat
passband
Flexible Read-Only Serial Interface:
– Standard CMOS
– Serialized LVDS
Easy Conversion Control with START Pin
Out-of-Range Detection
Supply: Analog +5V, Digital +3V
Power: 350mW
The ADS1672 ADC is comprised of a low-drift,
chopper-stabilized modulator with out-of-range
detection and a dual-path programmable digital filter.
The dual filter path allows the user to select between
two
post-processing
filters:
low-latency
or
wide-bandwidth. The low-latency filter settles quickly
in one cycle, for applications with large instantaneous
changes, such as a multiplexer. The wide-bandwidth
path provides an optimized frequency response for ac
measurements with a passband ripple of less than
0.001dB, stop band attenuation of 86dB, and a
bandwidth of 305kHz.
The ADS1672 is controlled through I/O pins—there
are no registers to program. A dedicated START pin
allows for direct control of conversions: toggle the
START pin to begin a conversion, and then retrieve
the output data. The flexible serial interface supports
data readback with either standard CMOS and LVDS
logic levels, allowing the ADS1672 to directly connect
to a wide range of microcontrollers, digital signal
processors (DSPs), or field-programmable grid arrays
(FPGAs).
APPLICATIONS
Automated Test Equipment
Vibration Analysis
Sonar
Test and Measurement
DVDD
AVDD
VREFP
The ADS1672 operates from an analog supply of 5V
and digital supply of 3V, and dissipates 350mW of
power. When not in use, the PDWN pin can be used
to power down all device circuitry. The device is fully
specified over the industrial temperature range and is
offered in a TQFP-64 package.
VREFN
•
•
•
•
Dual Filter
Path
AINP
DS
Modulator
AINN
Low-Latency Filter
CMOS and
LVDS
Compatible
Serial
Interface
Wide-Bandwidth Filter
Control
Data Ready
Data Output
Serial Shift Clock
Chip Select
Interface Configuration
Master Clock
Filter Path
Data Rate
Start Conversion
Power Down
Out-of-Range
DGND
AGND
ADS1672
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2010, Texas Instruments Incorporated
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
datasheet or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
ADS1672
UNIT
AVDD to AGND
–0.3 to +6
V
DVDD to DGND
–0.3 to +3.6
V
AGND to DGND
–0.3 to +0.3
V
Momentary
100
mA
Continuous
10
mA
Analog I/O to AGND
–0.3 to AVDD +0.3
V
Digital I/O to DGND
–0.3 to DVDD +0.3
V
+150
°C
Operating temperature range
–40 to +85
°C
Storage temperature range
–60 to +150
°C
Input
current
Maximum junction temperature
(1)
2
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
ELECTRICAL CHARACTERISTICS
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 20MHz, VREF = +3V, and RBIAS = 7.5kΩ,
unless otherwise noted.
ADS1672
PARAMETER
TEST CONDITIONS
MIN
TYP
ANALOG INPUTS
Full-scale input voltage
Common-mode input voltage
MAX
UNIT
.
VIN = (AINP – AINN)
±VREF
V
VCM = (AINP + AINN)/2
2.5
V
See Table 2
kSPS
AC PERFORMANCE
Data rate (fDATA)
Dynamic range
Signal-to-noise ratio (SNR)
Inputs shorted together,
wide-bandwidth path, fDATA = 625kSPS
105
107
Inputs shorted together,
wide-bandwidth path, fDATA =
78.125kSPS
113
115.5
fIN = 10kHz, –0.5dBFS,
wide-bandwidth path, fDATA = 625kSPS
102
fIN = 10kHz, –2dBFS,
wide-bandwidth path, fDATA = 625kSPS
103
fIN = 10kHz, –6dBFS,
wide-bandwidth path, fDATA = 625kSPS
99
fIN = 10kHz, –0.5dBFS
–105
fIN = 10kHz, –2dBFS
–109
fIN = 10kHz, –6dBFS
–113
fIN = 10kHz, –0.5dBFS,
signal harmonics excluded
–120
Total harmonic distortion (THD)
Spurious-free dynamic range (SFDR)
dB
dB
dB
dB
DC PRECISION
Resolution
24
Bits
24-bit
(monotonic)
Differential nonlinearity
Integral nonlinearity
Input range of ±0.5dBFS, TA = +25°C
Offset error
3
9.5
–2
ppm of FSR
2
Offset error drift
2
Gain error
TA = +25°C
1
Gain error drift
2
2
Noise
mV
mV/°C
%
ppm/°C
See Noise Performance table (Table 2)
Common-mode rejection
Power-supply rejection
At dc
92
dB
At dc, AVDD
92
dB
DIGITAL FILTER CHARACTERISTICS (WIDE-BANDWIDTH PATH)
Passband
0
Passband ripple
Passband transition
–0.1dB attenuation
0.432fDATA
–3.0dB attentuation
0.488fDATA
Stop band
0.424fDATA
Hz
±0.0001
dB
Hz
Hz
fCLK –
0.576fDATA
0.576fDATA
Hz
Stop band attenuation
86
dB
Group delay
28
tDRDY
Settling time
See Wide Bandwidth Filter section
DIGITAL FILTER CHARACTERISTICS (LOW-LATENCY PATH)
Bandwidth
–3dB attenuation
See Low-Latency Filter section
Settling time
Complete settling
1
tDRDY
VOLTAGE REFERENCE INPUTS
Reference input voltage (VREF)
VREF = (VREFP – VREFN)
VREFP
VREFN
2.75
3.0
3.25
V
2.75
3.0
3.25
V
Short to AGND
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
V
3
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 20MHz, VREF = +3V, and RBIAS = 7.5kΩ,
unless otherwise noted.
ADS1672
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLOCK (CLK)
VIH
0.7AVDD
AVDD
V
VIL
AGND
0.3AVDD
V
V
DIGITAL INPUTS
VIH
0.7DVDD
DVDD
VIL
DGND
0.3DVDD
V
±10
mA
Input leakage
DGND < VIN < DVDD
CMOS OUTPUTS
VOH
IOH = 2mA
VOL
IOL = 2mA
0.8DVDD
V
0.2DVDD
V
LVDS OUTPUTS
Steady-state differential output voltage
magnitude
340
mV
Change in steady-state differential
output voltage magnitude between
logic states
±50
mV
Steady-state common-mode voltage
output
1.2
V
Δ|VOC(SS)|
Change in steady-state common-mode
output voltage between logic states
±50
mV
VOC(pp)
Peak-to-peak change in common-mode
output voltage
50
VOY or VOZ = 0V
3
mA
VOD = 0V
3
mA
VO = 0V or +DVDD
±5
|VOD(SS)|
Δ|VOD(SS)|
VOC(SS)
Short-circuit output current (IOS)
High-impedance output current (IOZ)
Load
150
mV
mA
5
pF
V
POWER-SUPPLY REQUIREMENTS
AVDD
4.75
5.0
5.25
DVDD
2.7
3.0
3.3
V
51
55
mA
CMOS outputs, DVDD = 3V
28
32
mA
LVDS outputs, DVDD = 3V
33
37
mA
CMOS outputs,
AVDD = 5V, DVDD = 3V
350
370
mW
Power down
5
AVDD current
DVDD current
Power dissipation
4
Submit Documentation Feedback
mW
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
DEVICE INFORMATION
53
52
DVDD
54
DGND
55
DGND
56
DVDD
57
AGND
58
AVDD
59
AGND
60
CLK
61
AVDD
CAP1
62
AGND
VREFN
63
CAP2
64
VREFN
VREFP
VREFP
TQFP PACKAGE
(TOP VIEW)
51
50
49
AVDD
1
48 DVDD
AGND
2
47 DGND
AGND
3
46 DRDY
AINN
4
45 DRDY
AINP
5
44 DOUT
AGND
6
43 DOUT
AVDD
7
42 SCLK
RBIAS
8
41 SCLK
ADS1672
9
40 RSV3
AGND 10
39 OTRD
AGND
AVDD
38 CS
11
37 START
AVDD 12
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DVDD
DGND
DGND
DVDD
PDWN
SCLK _SEL
LVDS
DGND
LL_CONFIG
18
DVDD
17
RSV2
33 FPATH
RSV1
34 DVDD
DGND 16
DGND
35 DRATE[1]
DGND 15
DGND
DGND 14
DGND
36 DRATE[0]
DGND
VCM 13
Table 1. TERMINAL FUNCTIONS
PIN
NAME
NO.
FUNCTION
AVDD
1, 7, 11, 12, 53,
58
Analog
Analog supply
AGND
2, 3, 6, 9, 10,
54, 56, 57
Analog
Analog ground
AINN
4
Analog Input
Negative analog input
AINP
5
Analog Input
Positive analog input
RBIAS
8
Analog
Analog bias setting resistor
VCM
DESCRIPTION
13
Analog
Terminal for external bypass capacitor connection to internal common-mode voltage
DGND
14, 15, 16, 17,
18, 19, 20, 25,
26, 31, 47, 50,
51
Digital
Digital ground
RSV2
21
Reserved
Short to digital ground
RSV1
22
Reserved
Short to digital ground
DVDD
23, 24, 27, 34,
48, 49, 52
Digital
PDWN
28
Digital Input
Power-down control, active low
SCLK_SEL
29
Digital Input
Shift-clock source select.
If SCLK_SEL = '0', then SCLK is internally generated.
If SCLK_SEL = '1', then SCLK must be externally generated.
LVDS
30
Digital Input
Serial interface select.
If LVDS = '0', then interface is LVDS-compatible.
If LVDS = '1', then interface is CMOS-compatible.
Digital supply
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
5
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
Table 1. TERMINAL FUNCTIONS (continued)
PIN
NAME
NO.
FUNCTION
LL_CONFIG
32
Digital Input
Configure low-latency digital filter.
If LL_CONFIG = '0', then single-cycle settling is selected.
If LL_CONFIG = '1', then fast-response is selected.
FPATH
33
Digital Input
Digital filter path selection.
If FPATH = '0', then path is wide-bandwidth.
If FPATH = '1', then path is low-latency.
35, 36
Digital Input
Data rate selection
START
37
Digital Input
Start convert, reset, and synchronization control input
CS
38
Digital Input
Chip select; active low.
OTRD
39
Digital Output
RSV3
40
Reserved
SCLK
41
Digital Output
SCLK
42
DOUT
43
Digital Output
Negative LVDS serial data output
DOUT
44
Digital Output
Positive LVDS serial data output
DRDY
45
Digital Output
Negative data ready output
DRDY
46
Digital Output
Positive data ready output
CLK
55
Digital Input
CAP1
59
Analog
Terminal for 1mF external bypass capacitor
60, 61
Analog
Negative reference voltage. Short to analog ground.
62
Analog
Terminal for 1mF external bypass capacitor
63, 64
Analog
Positive reference voltage
DRATE[1:0]
VREFN
CAP2
VREFP
6
DESCRIPTION
Digital filter out-of-range indicator
This pin must be left floating. Do not connect or short to ground.
Negative shift clock output.
If SCLK_SEL = '0', then SCLK is the complementary shift clock output.
If SCLK_SEL = '1', then SCLK always output is 3-state.
Positive shift clock output.
Digital Input/Output If SCLK_SEL = '0', then SCLK is an output.
If SCLK_SEL = '1', then SCLK is an input.
Master clock input
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
TIMING CHARACTERISTICS
tCLK
CLK
tCLKDR
tDRPW
DRDY
tSCLK
tDRSCLK
SCLKinternal
tDOPD
tDOHD
MSB
DOUT
LSB
Figure 1. Data Retrieval Timing with Internal SCLK (SCLK_SEL = 0)
TIMING REQUIREMENTS: Internal SCLK
At TA = –40°C to +85°C, and DVDD = 2.7V to 3.3V.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
50
UNIT
tCLK
CLK period (1/fCLK)
tCLKDR
CLK to DRDY delay
36
ns
ns
tDRPW
DRDY pulse width
1
tCLK
tDRSCLK
Internally-generated SCLK rising edge to DRDY rising edge
4
ns
tSCLK
SCLK period (1/fSCLK)
1
tCLK
tDOPD
Rising edge of SCLK to new valid data output (propagation delay)
tDC
CLK duty cycle
tSPWH
SCLK pulse width high
3
45
55
20
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ns
%
ns
7
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
tCLK
CLK
tCLKDR
tSCLKDR
DRDY
tDRPW
CS
(1)
tCSSC
tSPW
tSPW
SCLKexternal
tSCLK
tDOPD
DOUT
Hi-Z
tCSRDO
MSB
LSB
tCSFDO
(1)
CS may be tied low.
Figure 2. Data Retrieval Timing with External SCLK (SCLK_SEL = 1)
TIMING REQUIREMENTS: External SCLK
At TA = –40°C to +85°C, and DVDD = 2.7V to 3.3V.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
50
UNIT
tCLK
CLK period (1/fCLK)
tCLKDR
CLK to DRDY delay
37
ns
ns
tDRPW
DRDY pulse width
1
tCLK
tCSSC
CS active low to first Shift Clock (setup time)
5
ns
tSCLK
SCLK period (1/fSCLK)
25
ns
tSPW
SCLK high or low pulse width
12
tDOPD
Rising edge of SCLK to new valid data output (propagation delay)
tSCLKDR
Setup time of DRDY rising after SCLK falling edge
tCRSDO
CS inactive to data output 3-state
ns
11
3
ns
tCLK
8
ns
tSTART_CLKR
CLK
tSETTLE
START
tSTART
tCLKDR
DRDY
Figure 3. START Timing
TIMING REQUIREMENTS: START
At TA = –40°C to +85°C, and DVDD = 2.7V to 3.3V.
SYMBOL
DESCRIPTION
tSTART_CLKR
Setup time, rising edge of START to rising edge of CLK
tSTART
Start pulse width
8
Submit Documentation Feedback
MIN
TYP
MAX
UNIT
0.5
tCLK
1
tCLK
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
TYPICAL CHARACTERISTICS
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 20MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless
otherwise noted.
OUTPUT SPECTRUM
(1k, –0.5dBFS SIGNAL)
OUTPUT SPECTRUM DETAIL VIEW
(1k, –0.5dBFS SIGNAL)
0
0
fIN = 1kHz, -0.5dBFS
THD = -109.1dBc
65,536 points
-40
-60
-80
-100
fIN = 1kHz, -0.5dBFS
THD = -109.1dBc
65,536 points
-20
Amplitude (dBFS)
Amplitude (dBFS)
-20
-40
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
50
100
150
200
250
0
300 325
1
2
3
5
6
8
7
Figure 4.
Figure 5.
OUTPUT SPECTRUM
(10k, –0.5dBFS SIGNAL)
OUTPUT SPECTRUM
(10k, –60dBFS SIGNAL)
9
10
0
0
fIN = 10kHz, -0.5dBFS
THD = -108.9dBc
65,536 points
-20
-40
-60
-80
-100
fIN = 10kHz, -60dBFS
SNR = 45.6dBc
THD = -71.6dBc
65,536 points
-20
Amplitude (dBFS)
Amplitude (dBFS)
4
Frequency (kHz)
Frequency (kHz)
-40
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
50
100
150
200
250
300 325
0
50
100
Frequency (kHz)
150
200
250
300 325
Frequency (kHz)
Figure 6.
Figure 7.
SNR and |THD|
vs INPUT FREQUENCY
SNR and |THD|
vs SAMPLING FREQUENCY
125
120
fIN = 10kHz
120
110
|THD|, AIN = -0.5dBFS
105
SNR, AIN = -0.5dBFS
100
SNR, |THD| (dBc)
SNR, |THD| (dBc)
115
115
SNR, AIN = -0.5dBFS
110
105
100
|THD|, AIN = -0.5dBFS
95
95
10
100
1000
0
Frequency (kHz)
5
10
15
20
25
Sampling Frequency (MHz)
Figure 8.
Figure 9.
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
9
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 20MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless
otherwise noted.
SNR and |THD|
vs INPUT AMPLITUDE
SNR and |THD|
vs INPUT COMMON-MODE
140
115
fIN = 10kHz
fIN = 10kHz
|THD|, AIN = -6dBFS
SNR, |THD| (dBc)
SNR, |THD| (dBc)
120
100
|THD|
80
SNR
60
110
|THD|, AIN = -0.5dBFS
105
SNR, AIN = -0.5dBFS
100
40
SNR, AIN = -6dBFS
20
95
-80
-70
-60
-50
-40
-30
-20
-10
1.6
0
2.0
2.2
2.4
2.6
Figure 10.
Figure 11.
SNR and |THD|
vs TEMPERATURE
NOISE HISTOGRAM
(OSR = 32)
2500
120
2.8
3.0
Wide Bandwidth, fDATA = 625kSPS
s = 27 Output Codes
65k Points
Input-Shorted
fIN = 10kHz
Number of Occurrences
115
SNR, |THD| (dBc)
1.8
Input Common-Mode (V)
Input Signal Amplitude (dBFS)
|THD|, AIN = -6dBFS
110
|THS|, AIN = -0.5dBFS
105
SNR, AIN = -0.5dBFS
100
2000
1500
1000
500
SNR, AIN = -6dBFS
-40
-15
10
35
Temperature (°C)
60
85
-126
-112
-98
-84
-70
-56
-42
-28
-14
0
14
28
42
56
70
84
98
112
126
0
95
24-Bit Output Code
Figure 12.
10
Figure 13.
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 20MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless
otherwise noted.
NOISE HISTOGRAM
(OSR = 256)
Wide Bandwidth
fDATA = 78.125kSPS
s = 10.8 Output Codes
65k Points
Number of Occurrences
4500
4000
3500
3000
2500
2000
1500
1000
116
Dynamic Range (dBFS)
5000
DYNAMIC RANGE vs
OVERSAMPLING RATIO
78.125kHz: OSR = 256
156.25kHz: OSR = 128
312.5kHz: OSR = 64
625kHz: OSR = 32
114
112
110
LL
108
WB
500
106
0
-48
-44
-40
-36
-32
-28
-24
-20
-16
-12
-8
-4
0
4
8
12
16
20
24
28
32
36
40
44
48
256
128
64
32
Oversampling Ration (OSR)
24-Bit Output Code
Figure 14.
Figure 15.
NOISE vs
INPUT VOLTAGE
INL vs
TEMPERATURE
5
14
10
8
FPATH = 1
DRATE = 11
FPATH = 1
DRATE = 00
6
4
FPATH = 0
DRATE = 00
2
Integral Nonlinearity (ppm)
RMS Noise (mV)
4
FPATH = 0
DRATE = 11
12
3
+85°C
2
-40°C
1
0
+25°C
-1
-2
-3
-4
-5
0
-95
-76
-57
-38 -19
0
19
38
57
76
95
-3
Analog Input Range (±100% of FSR)
Figure 16.
-2
-1
0
1
2
3
Analog Input Voltage (V)
Figure 17.
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
11
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 20MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless
otherwise noted.
|THD|
vs RBIAS
SNR
vs RBIAS
104
115
fCLK = 10MHz
100
110
SNR (dBc)
|THD| (dBc)
fCLK = 2.5MHz
102
fCLK = 2.5MHz
fCLK = 10MHz
98
96
105
94
fCLK = 20MHz
fCLK = 20MHz
92
fIN = 10kHz, AIN = -0.5dBFS
100
5
10
15
20
25
30
35
40
45
50
55
60
fIN = 10kHz, AIN = -0.6dBFS
90
0
65
10
20
30
40
RBIAS (kW)
RBIAS (kW)
Figure 18.
Figure 19.
50
60
70
POWER
vs RBIAS
500
fIN = 10kHz, AIN = -0.5dBFS
450
Power (mW)
400
350
300
fCLK = 20MHz
250
200
fCLK = 2.5MHz
fCLK = 10MHz
150
100
50
5
10
15
20
25
30
35
40
45
50
55
60
65
RBIAS (kW)
Figure 20.
12
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
OVERVIEW
The ADS1672 is a 24-bit, ΔΣ analog-to-digital
converter (ADC). It provides high-resolution
measurements of both ac and dc signals and features
an advanced multi-stage analog modulator with a
programmable and flexible digital decimation filter.
A dedicated START pin allows precise conversion
control; toggle the pin to begin the conversion
process. The ADS1672 is configured by setting the
appropriate I/O pins—there are no registers to
program. Data are retrieved over a serial interface
that can support either CMOS or LVDS voltage
levels. In addition, the serial interface can be
internally or externally clocked. This flexibility allows
direct connection to a wide range of digital hosts
including DSPs, FPGAs, and microcontrollers.
A detection circuit monitors the conversions to
indicate when the inputs are out-of-range for an
extended duration. A power-down pin (PDWN) shuts
off all circuitry when the ADS1672 is not in use.
x
x
DVDD
x
AVDD
VREFN
VREFP
CAP2
CAP1
RBIAS
Figure 21 shows a block diagram of the ADS1672.
The modulator is chopper-stabilized for low-drift
performance and measures the differential input
signal VIN = (AINP – AINN) against the differential
reference VREF = (VREFP – VREFN). The digital filter
receives the modulator signal and processes it
through the user-selected path. The low-latency path
provides single-cycle settling, and is ideal when using
a multiplexer or when measuring large transients. The
wide-bandwidth path provides outstanding frequency
response with very low passband ripple, a steep
transition band, and large stop band attenuation. This
path is well-suited for applications that require
high-resolution measurements of high-frequency ac
signal content.
ADS1672
VCM
S
CLK
Dual Filter
Path
VREF
AINP
AINN
S
PDWN
START
Biasing
Low-Latency Filter
VIN
DS
Modulator
Wide-Bandwidth Filter
CMOS- and
LVDSCompatible
Serial
Interface
and
Control
DRDY, DRDY
DOUT, DOUT
SCLK, SCLK
CS
LVDS
SCLK_SEL
DRATE[1:0]
FPATH
LL_CONFIG
DGND
AGND
OTRD
Figure 21. ADS1672 Block Diagram
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
13
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
NOISE PERFORMANCE
ANALOG INPUTS (AINP, AINN)
The ADS1672 offers outstanding noise performance
that can be optimized by adjusting the data rate. As
the averaging is increased (thus reducing the data
rate), the noise drops correspondingly. Table 2 shows
the noise as a function of data rate for both the
low-latency and the wide-bandwidth filter paths under
the conditions shown.
The ADS1672 measures the differential signal,
VIN = (AINP – AINN), against the differential
reference, VREF = (VREFP – VREFN). The most
positive measurable differential input is VREF, which
produces the most positive digital output code of
7FFFFFh. Likewise, the most negative measurable
differential input is –VREF, which produces the most
negative digital output code of 800000h.
Table 2 lists some of the more common methods of
specifying noise. The dynamic range is the ratio of
the root-mean-square (RMS) value of a full-scale sine
wave to the RMS noise with the inputs shorted
together. This value is expressed in decibels relative
to full-scale (dBFS). The input-referred noise is the
RMS value of the noise with the inputs shorted,
referred to the input of the ADS1672. The effective
number of bits (ENOB) is calculated from a dc
perspective using the formula in Equation 1, where
full-scale range equals 2VREF.
ln
Analog inputs must be driven with a differential signal
to achieve optimum performance. The recommended
common-mode voltage is 2.5V. The ADS1672
samples the analog inputs at very high speeds. It is
critical that a suitable driver be used. See the
Application Information section for recommended
circuit designs.
The ADS1672 uses a switched-capacitor circuitry to
measure the input voltage. Internal capacitors are
charged by the inputs and then discharged internally
with each clock (CLK) cycle. Figure 22 shows the
effective input impedance seen by the driving
amplifier.
Full-scale range
RMS noise
ENOB =
ln(2)
(1)
Noise-free bits specifies noise, again from a dc
perspective using Equation 1, with peak-to-peak
noise substituted for RMS noise.
AINP
ZEFF = 3.125kW ·
(
20MHz
fCLK
(
AINN
Figure 22. Effective Input Impedance
Table 2. Noise Performance (1)
FILTER PATH
DATA
RATE[1:0]
DATA RATE
DYNAMIC
RANGE
INPUT-REFERRED
NOISE
ENOB
NOISE-FREE
BITS
00
36kSPS
115dB
3.9mVRMS
20.6
17.8
01
68kSPS
113dB
5.0mVRMS
20.2
17.5
10
120kSPS
110dB
6.7mVRMS
19.8
17.1
11
180kSPS
108dB
8.9mVRMS
19.4
16.7
00
78.1kSPS
115.5dB
3.9mVRMS
20.6
17.8
01
156.3kSPS
113dB
5.0mVRMS
20.2
17.5
10
312.5kSPS
110dB
6.8mVRMS
19.8
17.0
11
625.0kSPS
107dB
10.1mVRMS
19.2
16.5
Low-Latency
(single-cycle settling
configuration)
Wide-Bandwidth
(1)
14
VREF = 3V, fCLK = 20MHz.
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
VOLTAGE REFERENCE INPUTS
(VREFN, VREFP)
CONVERSION START
The voltage reference for the ADS1672 is the
differential voltage between VREFP and VREFN:
VREF = (VREFP – VREFN)
(2)
A high-quality reference voltage with the appropriate
drive strength is essential for achieving the best
performance from the ADS1672. Noise and drift on
the reference degrade overall system performance.
See the Application Information section for reference
circuit examples.
It is recommended that a minimum 10mF and 0.1mF
ceramic bypass capacitors be used directly across
the reference inputs, VREFP and VREFN. These
capacitors should be placed as close as possible to
the device under test for optimal performance.
COMMON-MODE VOLTAGE (VCM)
The START pin provides an easy and precise
conversion control. To perform a single conversion,
pulse the START pin as shown in Figure 23. The
START signal is latched internally on the rising edge
of CLK. Multiple conversions are performed by
continuing to hold START high after the first
conversion completes; see the digital filter
descriptions for more details on multiple conversions,
because the timing depends on the filter path
selected.
A conversion can be interrupted by issuing another
START pulse before the ongoing conversion
completes. When an interruption occurs, the data for
the ongoing conversion are flushed and a new
conversion begins. DRDY indicates that data are
ready for retrieval after the filter has settled, as shown
in Figure 24.
The VCM pin outputs a voltage of AVDD/2 and can
be used to set the common-mode output of the
circuitry that drives the ADS1672. The pin must be
bypassed with a 1mF capacitor placed close to the
package pin, even if it is not connected elsewhere.
The VCM pin has very little drive capability and
should not be used to drive any loads.
tSTART_CLKR
CLK
tSETTLE
(1)
(1)
tSETTLE
START
tSTART
DRDY
Figure 23. START Pin Used for Single Conversions
Ongoing conversion flushed;
new conversion started
tSTART_CLKR
CLK
tSETTLE
(1)
START
tSTART
DRDY
(1) See Low-Latency Filter section and Wide Bandwidth Filter section for specific values of settling time tSETTLE.
Figure 24. Example of Restarting a Conversion with START
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
15
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
DIGITAL FILTER
LOW-LATENCY DIGITAL FILTER
In delta-sigma ADCs, the digital filter has a critical
influence on device performance. The digital filter
sets the frequency response, data rate, bandwidth,
and settling time. Choosing to optimize some of these
features in a filter means that compromises must be
made with other specifications. These tradeoffs
determine the applications for which the device is
best suited.
The low-latency (LL) filter provides a fast settling
response targeted for applications that need
high-precision measurements with minimal latency. A
good example of this type of application is using a
multiplexer to measure multiple inputs. The faster that
the ADC settles, the faster the measurement can
complete and the multiplexer can advance to the next
input.
The ADS1672 offers two digital filters on-chip, and
allows the user to direct the output data from the
modulator to either the Wide-Bandwidth or
Low-Latency filter. These filters allow the user to use
one converter design to address multiple applications.
The Low-Latency path filter has minimal latency or
settling time. This path is ideal for measurements with
large, quick changes on the inputs (for example,
when using a multiplexer). The low-latency
characteristic allows the user to cycle through the
multiplexer at high speeds. The frequency
characteristics are relaxed in order to provide the low
latency.
The ADS1672 LL filter supports two configurations to
help optimize performance for these types of
applications.
The other path provides a filter with excellent
frequency response characteristics. The passband
ripple is extremely small, the transition band is very
steep, and there is large stop band attenuation.
These characteristics are needed for high-resolution
measurements of ac signals. The tradeoff here is that
settling time increases; but for signal processing, this
increase is not generally a critical concern.
The FPATH digital input pin sets the filter path
selection, as shown in Table 3. Note that the START
pin must be strobed after a change to the filter path
selection or data rate. If a conversion is in process
during a filter path or data rate change, the output
data are not valid and should be discarded.
Table 3. ADS1672 Filter Path Selection
FPATH PIN
SELECTED FILTER PATH
1
Low-latency path
0
Wide-bandwidth path
The LL_CONFIG input pin selects the configuration,
as shown in Table 4. Be sure to strobe the START
pin after changing the configuration. If a conversion is
in process during a configuration change, the output
data for that conversion are not valid and should be
discarded.
Table 4. Low-Latency Pin Configurations
LL_CONFIG PIN
LOW-LATENCY
CONFIGURATION
0
Single-cycle settling
1
Fast response
The first configuration is single-cycle settling. As the
name implies, this configuration allows for the filter to
completely settle in one conversion cycle; there is no
need to discard data. Each data output is comprised
of information taken during only the previous
conversion. The DRATE[1:0] digital input pins select
the data rate for the Single-Cycle Settling
configuration, as shown in Table 5. Note that the
START pin must be strobed after a change to the
data rate. If a conversion is in process during a data
rate change, the output data for that conversion are
not valid and should be discarded.
blank
blank
Table 5. Low-Latency Data Rates with Single-Cycle Settling Configuration
(1)
16
SETTLING TIME, tSETTLE-LL
–3dB BANDWIDTH (1)
DRATE[1:0]
DATA RATE (1/tDRDY-SCS)
00
36.30kSPS
27.55ms
550 tCLK
34kHz
01
67.80kSPS
14.75ms
294 tCLK
68kHZ
10
119.76kSPS
8.35ms
166 tCLK
130kHZ
11
180.18kSPS
5.55ms
110 tCLK
215kHz
The input signal aliases when its frequency exceeds fDATA/2, in accordance with the Nyquist theorem.
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
The second configuration is fast response. The
DRATE[1:0] digital input pins select the data rate for
the Fast Response Configuration, as shown in
Table 6. When selected, this configuration provides a
higher output data rate. The faster output data rate
allows for more averaging by a post-processor within
a given time interval to reduce noise. It also provides
a faster indication of changes on the inputs when
monitoring quickly-changing signals (for example, in a
control loop application).
Figure 25 illustrates the response of both
configurations on approximately the same time scale
in order to highlight the differences. With the
single-cycle settling configuration, each conversion
fully settles; in other words, the conversion period
tDRDY-SCS = tSETTLE-LL. The benefit of this configuration
is its simplicity—the ADS1672 functions similar to a
SAR converter and there is no need to consider
discarding partially-settled data because each
conversion is fully settled.
Table 6. Low-Latency Data Rates with
Fast-Response Configuration
With the fast response configuration, the data rate for
conversions after initial settling is faster; that is, the
conversion time is less than the settling:
tDRDY-FR < tSETTLE-LL. One benefit of this configuration
is a faster response to changes on the inputs,
because data are supplied at a faster rate. Another
advantage is better support for post-processing. For
example, if multiple readings are averaged to reduce
noise, the higher data rate of the fast response
configuration allows this averaging to happen in less
time than it requires with the single-cycle settling
filter. A third benefit is the ability to measure higher
input frequencies without aliasing as a result of the
higher data rate.
DRATE
[1:0]
DATA RATE
(1/tDRDY-FR)
SETTLING TIME,
tSETTLE-LL
–3dB
BANDWIDTH
00
78.125kSPS
27.55ms
550 tCLK
01
156.25kSPS
14.75ms
294 tCLK
68kHZ
10
312.5kSPS
8.35ms
166 tCLK
130kHZ
11
625kSPS
5.55ms
110 tCLK
215kHz
34kHz
Settling Time
The settling time in absolute time (ms) is the same for
both configurations of the low-latency filter, as shown
in Table 5 and Table 6. The difference between the
configurations is seen with the timing of the
conversions after the filter has settled from a pulse on
the START pin.
tSTART_CLKR
CLK
tCLKDR
START
tSETTLE-LL
tDRDY-SCS = tSETTLE-LL
DRDYSCS
tDRDY-FR
DRDYFR
NOTE: DRDYSCS is the DRDY output with the low-latency single-cycle settling configuration. DRDYFR is the DRDY output with the
low-latency fast-response settling configuration.
Figure 25. Low-Latency Single-Cycle Settling and Fast-Response Configuration Conversion Timing
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
17
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
It is important to note, however, that the absolute
settling time of the low-latency path does not change
when using the fast response configuration. Changes
on the input signal during conversions after the initial
settling require multiple cycles to fully settle. To help
illustrate this requirement, consider a change on the
inputs as shown in Figure 29, where START is
assumed to have been taken high before the input
voltage was changed.
0
DRATE[1:0]=‘00’
-10
Magnitude (dB)
-20
DRATE[1:0]=‘11’
-30
-40
-50
-60
The readings after the input change settle as shown
in Figure 26. Conversion 3 provides a fully-settled
result at the new VIN signal.
-70
-80
0
120
0.2
0.3
0.4 0.5 0.6 0.7
Frequency (fIN/fDATA)
0.8
0.9
1.0
Figure 27. Frequency Response of Low-Latency
Filter in Fast-Response Configuration
100
80
60
0
40
-20
20
-40
Magnitude (dB)
Settling (%)
0.1
0
0
1
3
2
4
Conversions (1/fDRDY-FR)
-60
-80
-100
Figure 26. Step Response for Low-Latency Filter
with Fast-Response Configuration
-120
-140
0
Frequency Response
Figure 27 shows the frequency response for the
low-latency filter path normalized to the output data
rate, fDATA. The overall frequency response repeats at
the modulator sampling rate, which is the same as
the input clock frequency. Figure 28 shows the
response with the fastest data rate selected
(625kSPS when fCLK = 20MHz).
1
2
Frequency (fIN/fCLK)
3
Figure 28. Extended Frequency Response of
Low-Latency Path
Change on
Analog Inputs
VIN
Fully-Settled
Data Available
Data 0
Data 1
Data 2
Data 3
Data 4
DRDYLL-FR
NOTE: START pin held high previous to change on analog inputs.
Figure 29. Settling Example with the Low-Latency Filter in Fast-Response Configuration
18
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
Phase Response
20
0
-20
Magnitude (dB)
The low-latency filter uses a multiple stage linear
phase digital filter. Linear phase filters exhibit
constant delay time versus input frequency (also
know as constant group delay). This feature of linear
phase filters means that the time delay from any
instant of the input signal to the corresponding same
instant of the output data is constant and independent
of the input signal frequency. This behavior results in
essentially zero phase error when measuring
multi-tone signals.
-40
-60
-80
-100
-120
-140
WIDE-BANDWIDTH FILTER
0
The wide-bandwidth (WB) filter is well-suited for
measuring high-frequency ac signals. This digital filter
offers excellent passband and stop band
characteristics.
Table 7. Wide-Bandwidth Data Rates
DRATE
[1:0]
DATA RATE
(1/tDRDY-WB)
–3dB
BANDWIDTH
00
78.125kSPS
38kHz
704ms
14061 tCLK
01
156.25kSPS
76kHz
352ms
7033 tCLK
10
312.50kSPS
152kHz
176ms
3519 tCLK
11
625.0kSPS
305kHz
SETTLING TIME,
tSETTLE-WB
88ms
0.2
0.3
0.4 0.5 0.6 0.7
Frequency (fIN/fDATA)
0.8
0.9
1.0
Figure 30. Frequency Response of
Wide-Bandwidth Filter
blank
0.00005
-0.00005
Magnitude (dB)
The DRATE[1:0] digital input pins select from the four
data rates available with the WB filter, as shown in
Table 7. Note that the START pin must be strobed
after a change to the data rate. If a conversion is in
process during a data rate change, the output data
for that conversion are not valid and should be
discarded.
0.1
-0.00015
-0.00025
-0.00035
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency (fIN/fDATA)
1762 tCLK
Figure 31. Passband Response for
Wide-Bandwidth Filter
While using the wide-bandwidth filter path, the
LL_CONFIG pin must be set to logic HIGH. Setting
LL_CONFIG to a logic low forces the ADS1672 to
switch to the low-latency filter path, single cycle
settling mode overriding FPATH pin.
2
0
Figure 30 shows the frequency response for the
wide-bandwidth filter path normalized to the output
data rate, fDATA. Figure 31 shows the passband ripple,
and the transition from passband to stop band is
illustrated in Figure 32. These three plots are valid for
all of the data rates available on the ADS1672.
Simply substitute the selected data rate to express
the x-axis in absolute frequency.
Magnitude (dB)
Frequency Response
-2
-4
-6
-8
-10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Normalized Frequency (fIN/fDATA)
Figure 32. Transition Band Response for
Wide-Bandwidth Filter
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
19
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
Settling Time
The overall frequency response repeats at the
modulator sampling rate, which is the same as the
input clock frequency. Figure 33 shows the response
with the fastest data rate selected (625kSPS when
fCLK = 20MHz).
The Wide-Bandwidth filter fully settles before
indicating data are ready for retrieval after the START
pin is taken high, as shown in Figure 35. For this
filter, the settling time is larger than the conversion
time: tSETTLE-WB > tDRDY-WB. Instantaneous steps on
the input require multiple conversions to settle if
START is not pulsed. Figure 34 shows the settling
response with the x-axis normalized to conversions or
data-ready cycles. The output is fully settled after 55
data-ready cycles.
Magnitude (dB)
0
-50
120
-100
100
Fully settled
at 55
conversions
Settling (%)
80
-150
0
1
2
Frequency (fIN/fCLK)
3
60
40
20
Figure 33. Extended Frequency Response of
Wide-Bandwidth Path
0
-20
0
Phase Response
10
20
30
40
50
60
Conversions (1/tDRDY-WB)
The wide-bandwidth filter uses a multiple-stage,
linear-phase digital filter. Linear phase filters exhibit
constant delay time versus input frequency (also
know as constant group delay). This feature means
that the time delay from any instant of the input signal
to the corresponding same instant of the output data
is constant and independent of the input signal
frequency. This behavior results in essentially zero
phase error when measuring multi-tone signals.
Figure 34. Step Response for
Wide-Bandwidth Filter
tSTART_CLKR
CLK
tSETTLE
START
tDRDY
(1)
tDRDY
tDRDY
tDRDY
DRDY
(1) tDRDY = 1/fDATA. See Table 7 for the relationship between tSETTLE and tDRDY when using the Wide-Bandwidth filter.
Figure 35. START Pin Used for Multiple Conversions with Wide-Bandwidth Filter Path
20
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
OTRD FUNCTION
The ADS1672 provides an out-of-range (OTRD) pin
that can be used in feedback loops to set the
dynamic range of the input signal.
The OTRD function is triggered when the output code
of the digital filter exceeds the positive or negative
full-scale range. OTRD goes high on the rising edge
of DRDY. When the digital output code returns within
the full-scale range, OTRD returns low on the next
rising edge of DRDY. OTRD can also be used when
small out-of-range input glitches must be ignored.
SERIAL INTERFACE
The ADS1672 offers a flexible and easy-to-use,
read-only serial interface designed to connect to a
wide range of digital processors, including DSPs,
microcontrollers, and FPGAs. The ADS1672 serial
interface can be configured to support either standard
CMOS voltage swings or low-voltage differential
swings (LVDS). In addition, when using standard
CMOS voltage swings, SCLK can be internally or
externally generated.
The ADS1672 is entirely controlled by pins; there are
no registers to program. Connect the I/O pins to the
appropriate level to set the desired function.
Whenever changing the I/O pins that are used to
control the ADS1672, be sure to issue a START
pulse immediately after the change in order to latch
the new values.
USING LVDS OUTPUT SWINGS
When the LVDS pin is set to '0', the ADS1672
outputs are LVDS TIA/EIA-644A compliant. The data
out, shift clock, and data ready signals are output on
the differential pairs of pins DOUT/DOUT,
SCLK/SCLK, and DRDY/DRDY, respectively. The
voltage on the outputs is centered on 1.2V and
swings approximately 350mV differentially. For more
information on the LVDS interface, refer to the
document Low-Voltage Differential Signaling (LVDS)
Design Notes (literature number SLLA014) available
for download at www.ti.com.
When using LVDS, the CS function is not available
and SCLK must be internally generated. The states of
the CS and SCLK_SEL pins are ignored, but do not
leave these pins floating; they must be tied high or
low.
USING CMOS OUTPUT SWINGS
When the LVDS pin is set to '1', the ADS1672
outputs are CMOS-compliant and swing from rail to
rail. The data out and data ready signals are output
on the differential pairs of pins DOUT/DOUT and
DRDY/DRDY, respectively. Note that these are the
same pins used to output LVDS signals when the
LVDS pin is set to '0'. DOUT and DRDY are
complementary outputs provided for convenience.
When not in use, these pins should be left floating.
See the Serial Shift Clock section for a description of
the SCLK and SCLK pins.
DATA OUTPUT (DOUT, DOUT)
Data are output serially from the ADS1672, MSB first,
on the DOUT and DOUT pins. When LVDS signal
swings are used, these two pins act as a differential
pair to produce the LVDS-compatible differential
output signal. When CMOS signal swings are used,
the DOUT pin is the complement of DOUT. If DOUT
is not used, it should be left floating.
DATA READY (DRDY, DRDY)
Data ready for retrieval are indicated on the DRDY
and DRDY pins. When LVDS signal swings are used,
these two pins act as a differential pair to produce the
LVDS-compatible differential output signal. When
CMOS signal swings are used, the DRDY pin is the
complement of DRDY. If one of the data ready pins is
not used when CMOS swings are selected, it should
be left floating.
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
21
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
SERIAL SHIFT CLOCK (SCLK, SCLK,
SCLK_SEL)
The serial shift clock SCLK is used to shift out the
conversion data, MSB first, onto the Data Output
pins. Either an internally- or externally-generated shift
clock can be selected using the SCLK_SEL pin. If
SCLK_SEL is set to '0', a free-running shift clock is
generated internally from the master clock and
outputs on the SCLK and SCLK pins. The LVDS pin
determines if the output voltages are CMOS or LVDS.
If SCLK_SEL is set to '1' and LVDS is set to '1', the
SCLK pin is configured as an input to accept an
externally-generated shift clock. In this case, the
SCLK pin always outputs low. When SCLK_SEL is
set to '0', the SCLK and SCLK pins are configured as
outputs, and the shift clock is generated internally
using the master clock input (CLK).
When LVDS signal swings are used, the shift clock is
automatically generated internally regardless of the
state of SCLK_SEL. In this case, SCLK_SEL cannot
be left floating; it must be tied high or low.
Table 8 summarizes the ADS1672 supported serial
clock configurations.
exceeding full-scale. Table 9 summarizes the ideal
output codes for different input signals. When the
input is positive out-of-range, exceeding the positive
full-scale value of VREF, the output clips to all
7FFFFFh. Likewise, when the input is negative
out-of-range by going below the negative full-scale
value of –VREF, the output clips to 800000h.
Table 9. Ideal Output Code vs Input Signal
INPUT SIGNAL
VIN = (AINP – AINN)
IDEAL OUTPUT CODE(1)
≥ VREF
7FFFFFh
+VREF
2
23
000001h
-1
0
000000h
-VREF
2
23
FFFFFFh
-1
23
< -VREF
( 2 2 - 1)
23
8000000h
(1) Excludes effects of noise, INL, offset and gain errors.
CLOCK INPUT (CLK)
Table 8. Supported Serial Clock Configurations
DIGITAL OUTPUTS
SHIFT CLOCK (SCLK)
LVDS
Must be generated internally
CMOS
Internal (SCLK_SEL = '0')
External (SCLK_SEL = '1')
CHIP SELECT (CS)
The chip select input (CS) allows multiple devices to
share a serial bus. When CS is inactive (high), the
serial interface is reset and the data output pins
DOUT and DOUT enter a high-impedance state.
SCLK is internally generated; the SCLK and SCLK
output pins also enter a high-impedance state when
CS is inactive. The DRDY and DRDY outputs are
always active, regardless of the state of the CS
output. CS may be permanently tied low when the
outputs do not share a bus.
DATA FORMAT
The ADS1672 outputs 24 bits of data in two’s
complement format. A positive full-scale input
produces an output code of 7FFFFFh, and the
negative full-scale input produces an output code of
800000h. The output clips at these codes for signals
22
The ADS1672 requires that an external clock signal
be applied to the CLK input pin. The sampling of the
modulator is controlled by this clock signal. As with
any high-speed data converter, a high-quality clock is
essential for optimum performance. Crystal clock
oscillators are the recommended CLK source; other
sources, such as frequency synthesizers, are usually
inadequate. Make sure to avoid excess ringing on the
CLK input; keep the trace as short as possible.
Measuring high-frequency, large amplitude signals
requires tight control of clock jitter. The uncertainty
during sampling of the input from clock jitter limits the
maximum achievable SNR. This effect becomes more
pronounced with higher frequency and larger
magnitude inputs. Fortunately, the ADS1672
oversampling topology reduces clock jitter sensitivity
over that of Nyquist rate converters, such as pipeline
and successive approximation converters, by at least
a factor of √32.
For best performance, the duty cycle of CLK should
be very close to 50%. The rise and fall times of the
clock should be less than 2ns and the clock
amplitude should be equal to AVDD.
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
SYNCHRONIZING MULTIPLE ADS1672s
ANALOG POWER DISSIPATION
The START pin should be applied at power-up and
resets the ADS1672 filters. START begins the
conversion process, and the START pin enables
simultaneous sampling with multiple ADS1672s in
multichannel systems. All devices to be synchronized
must use a common CLK input.
An external resistor connected between the RBIAS
pin and the analog ground sets the analog current
level, as shown in Figure 37. The current is inversely
proportional to the resistor value. Figure 18 and
Figure 20 (in the Typical Characteristics) show power
and typical performance at values of RBIAS for
different CLK frequencies. Notice that the analog
current can be reduced when using a slower
frequency CLK input because the modulator has
more time to settle. Avoid adding any capacitance in
parallel to RBIAS, because this additional capacitance
interferes with the internal circuitry used to set the
biasing.
It is recommended that the START pin be aligned to
the falling edge of CLK to ensure proper
synchronization because the START signal is
internally latched by the ADS1672 on the rising edge
of CLK.
With the CLK inputs running, pulse START on the
falling edge of CLK, as shown in Figure 36.
Afterwards, the converters operate synchronously
with the DRDY outputs updating simultaneously. After
synchronization, DRDY is held high until the digital
filter has fully settled.
ADS1672
RBIAS
RBIAS
ADS16721
START
CLK
START1
DRDY
DRDY1
AGND
CLK
Figure 37. External Resistor Used to Set Analog
Power Dissipation (Depends on fCLK)
ADS16722
START2
DRDY
DRDY2
CLK
POWER DOWN (PDWN)
When not in use, the ADS1672 can be powered down
by taking the PDWN pin low. All circuitry shuts down,
including the voltage reference. To minimize the
digital current during power down, stop the clock
signal supplied to the CLK input. Make sure to allow
time for the reference to start up after exiting
power-down mode.
CLK
tSETTLE
START
DRDY1
After the reference has stabilized, allow for the
modulator and digital filter to settle before retrieving
data.
DRDY2
Figure 36. Synchronizing Multiple Converters
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
23
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
POWER SUPPLIES
blank
Two supplies are used on the ADS1672: analog
(AVDD) and digital (DVDD). Each supply must be
suitably bypassed to achieve the best performance. It
is recommended that a 1mF and 0.1mF ceramic
capacitor be placed as close to each supply pin as
possible. Connect each supply-pin bypass capacitor
to the associated ground. Each main supply bus
should also be bypassed with a bank of capacitors
from 47mF to 0.1mF. Figure 38 illustrates the
recommended method for ADS1672 power-supply
decoupling.
Power-supply pins 53 and 54 are used to drive
internal clock supply circuits and, as a result, are
generally very noisy. It is highly recommended that
traces from these pins not be shared or run close to
any of the adjacent AVDD or AGND pins of the
ADS1672. These pins should be well-decoupled,
using a 0.1mF ceramic capacitor placed close to the
pins, and immediately terminated into the power and
ground planes.
+5V
+3V
0.1mF
0.1mF
57
58
10mF
0.1mF
56
54
AVDD AGND AGND
53
52
51
50
49
AGND AVDD DVDD DGND DGND DVDD
1 AVDD
DVDD 48
2 AGND
DGND 47
0.1mF
10mF
3 AGND
+5V
0.1mF
10mF
6 AGND
ADS1672
7 AVDD
9 AGND
10 AGND
11 AVDD
12 AVDD
DGND DGND DGND DGND DVDD DVDD DGND DGND DVDD DGND
17
18
19
20
23
24
25
26
27
31
0.1mF
10mF
Figure 38. Power-Supply Decoupling
24
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
APPLICATIONS INFORMATION
To obtain the specified performance from the
ADS1672, the following layout and component
guidelines should be considered.
1. Power Supplies: The device requires two power
supplies for operation: DVDD and AVDD. For
both supplies, use a 10mF tantalum capacitor,
bypassed with a 0.1mF ceramic capacitor, placed
close to the device pins. Alternatively, a single
10mF ceramic capacitor can be used. The
supplies should be relatively free of noise and
should not be shared with devices that produce
voltage spikes (such as relays, LED display
drivers, etc.). If a switching power supply source
is used, the voltage ripple should be low (< 2mV).
The power supplies may be sequenced in any
order.
2. Ground Plane: A single ground plane connecting
both AGND and DGND pins can be used. If
separate digital and analog grounds are used,
connect the grounds together at the converter.
3. Digital Inputs: Source terminate the digital inputs
to the device with 50Ω series resistors. The
resistors should be placed close to the driving
end of the digital source (oscillator, logic gates,
DSP, etc.) These resistors help reduce ringing on
the digital lines, which may lead to degraded
ADC performance.
4. Analog/Digital Circuits: Place analog circuitry
(input buffer, reference) and associated tracks
together, keeping them away from digital circuitry
(DSP, microcontroller, logic). Avoid crossing
digital tracks across analog tracks to reduce
noise coupling and crosstalk.
5. Reference Inputs: Use a minimum 10mF
tantalum with a 0.1mF ceramic capacitor directly
across the reference inputs, VREFP and VREFN.
The reference input should be driven by a
low-impedance source. For best performance, the
reference should have less than 3mVRMS
broadband noise. For references with higher
noise, external reference filtering may be
necessary. The ADS1672 has 800Ω of resistance
across the VREFP and VREFN pins. The driving
amplifier must be able to provide this current as
well as another 1mA caused by switching at
20MHz. It is therefore recommended that the
driving amplifier be able to provide at least 5mA,
and enough decoupling capacitors be installed to
attenuate instantaneous current spikes seen at
20MHz.
6. Analog Inputs: The analog input pins must be
driven differentially to achieve specified
performance. A true differential driver or
transformer (ac applications) can be used for this
purpose. Route the analog inputs tracks (AINP,
AINN) as a pair from the buffer to the converter
using short, direct tracks and away from digital
tracks. A 750pF capacitor should be used directly
across the analog input pins, AINP and AINN. A
low-k dielectric (such as COG or film type) should
be used to maintain low THD. Capacitors from
each analog input to ground should be used.
They should be no larger than 1/10 the size of
the difference capacitor (typically 100pF) to
preserve the ac common-mode performance.
7. Component Placement: Place the power supply,
analog input, and reference input bypass
capacitors as close as possible to the device
pins. This placement is particularly important for
the
small-value
ceramic
capacitors.
Surface-mount components are recommended to
avoid the higher inductance of leaded
components.
Figure 39 to Figure 41 illustrate basic connections
and interfaces that can be used with the ADS1672.
The THS4520 and THS4503 are good input drivers
for the ADS1672. The THS4520 is a single-supply,
high-speed, low-power, fully differential amplifier. The
THS4503 is a high-speed, bipolar, fully differential
amplifier. The wider supply range of the THS4503
provides better THD and SFDR performance over the
entire input range of the converter, while sacrificing
noise. The THS4520 offers comparable performance
with lower power and higher noise performance.
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
25
ADS1672
SBAS402D – JUNE 2008 – REVISED JULY 2010
www.ti.com
1kW
10nF
+5V
0.1mF
100W
OPA211
100W
OUT
100mF
10mF
22mF
VIN
+5V
TRIM
22mF
REF5030
0.1mF
1mF
1mF
20MHz
Clock Source
64
63
62
61
60
59
55
VREFP VREFP CAP2 VREFN VREFN CAP1
CLK
10W
4 AINN
VINN
Differential
Inputs
10W
VINP
100pF
750pF
5 AINP
100pF
ADS1672
8 RBIAS
7.5kW
13 VCM
1mF
Figure 39. Basic Analog Signal Connection
RG
383W
RS
50W
RF
392W
RT
54.9W
VSIGNAL
5V
RG
392W
VIN+
+
-
VINN
+
VINP
THS4520
VIN-
RG
392W
RS
50W
CM
2.5V
Figure 40. Basic Differential Input Signal
Interface
5V
+
RG
383W
-
VINN
+
VINP
THS4520
-
CM
2.5V
RF
392W
26
CM
2.5V
CM
2.5V
RF
392W
RT
54.9W
CM
2.5V
CM
2.5V
RF
392W
Figure 41. Basic Single-Ended Input Signal
Interface
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
ADS1672
www.ti.com
SBAS402D – JUNE 2008 – REVISED JULY 2010
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (June, 2009) to Revision D
Page
•
Changed THD performance from –115dB to –113dB in Features list .................................................................................. 1
•
Revised Description text to reflect 86dB stop band attenuation ........................................................................................... 1
•
Updated total harmonic distortion parameter typical specification for fIN = 10kHz, –6dBFS to –113dB from –118dB ......... 3
•
Changed stop band attenuation typical specification from 115dB to 86dB .......................................................................... 3
•
Revised Figure 1 to show correct SCLK and DRDY timing sequence ................................................................................. 7
•
Revised description ot tDRSCLK timing .................................................................................................................................... 7
•
Deleted previously numbered Figures 6, 7, and 9 ................................................................................................................ 9
•
Revised Figure 8 ................................................................................................................................................................... 9
•
Updated Figure 9 .................................................................................................................................................................. 9
•
Changed Figure 10 to more closely represent actual device performance ........................................................................ 10
•
Revised Figure 12 ............................................................................................................................................................... 10
•
Added paragraph about switched-capacitor circuitry and Figure 22 to Analog Inputs (AINP, AINN) section .................... 14
•
Revised Reference Inputs discussion; added statements about requirements of driving amplifier ................................... 25
Changes from Revision B (November, 2008) to Revision C
Page
•
Added test condition to Integral nonlinearity parameter ....................................................................................................... 3
•
Deleted typical specification for Offset error parameter ....................................................................................................... 3
•
Revised last sentence of Common-Mode Voltage (VCM) section. ..................................................................................... 15
•
Updated Figure 36 .............................................................................................................................................................. 23
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672
27
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ADS1672IPAG
ACTIVE
TQFP
PAG
64
160
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
ADS1672I
Samples
ADS1672IPAGR
ACTIVE
TQFP
PAG
64
1500
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
ADS1672I
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
