ADS5221PFBR

ADS5221 ADS 522 1 SBAS262A – APRIL 2003 – REVISED DECEMBER 2003 12-Bit, 65MSPS Sampling, +3.3V ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● The ADS5221 is a pipeline, CMOS Analog-to-Digital Converter (ADC) that operates from a single +3.3V power supply. This converter provides excellent performance with a single-ended input and can be operated with a differential input for added spurious performance. This high-performance converter includes a 12-bit quantizer, high bandwidth track-and-hold, and a high accuracy internal reference; it also allows for the user to disable the internal reference and utilize external references, providing excellent gain and offset matching in multi-channel applications or in applications where full-scale range adjustment is required. ● ● ● ● HIGH SNR: 70dB HIGH SFDR: 88dBFS LOW POWER: 285mW INTERNAL/EXTERNAL REFERENCE OPTION SINGLE-ENDED OR FULLY DIFFERENTIAL ANALOG INPUT FLEXIBLE DUTY CYCLE ADJUST CIRCUITRY LOW DNL: 0.5LSB SINGLE +3.3V SUPPLY OPERATION TQFP-48 APPLICATIONS ● WIRELESS LOCAL LOOP ● COMMUNICATIONS ● MEDICAL IMAGING ● PORTABLE INSTRUMENTATION The ADS5221 employs digital error correction techniques to enable excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for medical imaging, communications, video, and test instrumentation. The ADS5221 offers power dissipation of 285mW and also provides two power-down modes. The ADS5221 is specified at a maximum sampling frequency of 65MHz and a differential input range of 1V to 2V. The ADS5221 is available in a TQFP-48. AVDD CLK VDRV ADS5221 Timing/Duty Cycle Adjust Circuitry IN VIN S/H IN 12-Bit Pipelined ADC Error Correction Logic 3-State Output D0 • • • D11 OVR Internal Reference STPD QPD REFT REFB RSEL VREF OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) AVDD, DVDD, VDRV .......................................................................... +3.8V Analog Input ........................................................... –0.3V to (AVDD + 0.3V) Logic Input ............................................................. –0.3V to (AVDD + 0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5221 " TQFP-48 " PFB " –40°C to +85°C " ADS5221PFB " ADS5221PFBT ADS5221PFBR Tape and Reel, 250 Tape and Reel, 2000 ADS5221 " QFN-48(2) " RGZ " –40°C to +85°C " ADS5221RGZ " ADS5221RGZ ADS5221RGZR Rails, 52 Tape and Reel, 1000 PRODUCT NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. (2) This package available beginning Q1 2004. ELECTRICAL CHARACTERISTICS: AVDD = 3.3V TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 65MSPS, 50% clock duty cycle, AVDD = 3.3V, VDRV = 2.5V, –1dBFS, internal reference voltage, and 2VPP differential input, unless otherwise noted. ADS5221 PARAMETER CONDITIONS MIN RESOLUTION SPECIFIED TEMPERATURE RANGE ANALOG INPUT Single-Ended Input Range Optional Single-Ended Input Range Differential Input Range Analog Input Bias Current Input Impedance Analog Input Bandwidth Ambient Air 2VPP 1VPP 2VPP DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 2.4MHz f = 9.7MHz No Missing Codes Integral Nonlinearity Error, f = 2.4MHz Spurious-Free Dynamic Range(1) f = 2.4MHz f = 9.7MHz f = 32.5MHz 2-Tone Intermodulation Distortion(3) f = 9.5MHz and 10.5MHz (–7dB each tone) Signal-to-Noise Ratio (SNR) f = 2.4MHz f = 9.7MHz f = 32.5MHz Signal-to-(Noise + Distortion) (SINAD) f = 2.4MHz f = 9.7MHz f = 32.5MHz Effective Number of Bits(4), f = 2.4MHz Output Noise Aperture Delay Time Aperture Jitter Over-Voltage Recovery Time Full-Scale Step Acquisition Time 2 MAX UNITS 12 Tested Bits –40 to +85 °C 0.5 1 1 2.5 2 2 V V V µA MΩ || pF MHz 65M Samples/s Clock Cycle ±0.75 LSB LSB ±1.75 LSBs 1 1.25 || 5 300 Static, No Clock –3dBFS Input CONVERSION CHARACTERISTICS Sample Rate Data Latency TYP 1M 5 ±0.3 ±0.5 Tested ±0.5 Referred to Full-Scale at 25°C 78 90 88 85 dBFS(2) dBFS dBFS 92 dBFS 70 70 69 dB dB dB 70 70 68 11.2 0.2 3.0 1.2 1.0 5 dB dB dB Bits LSBs rms ns ps rms Clock Cycle ns Referred to Full-Scale at 25°C 68 Referred to Full-Scale at 25°C Input Tied to Common-Mode 67 ADS5221 www.ti.com SBAS262A ELECTRICAL CHARACTERISTICS: AVDD = 3.3V (Cont.) TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 65MSPS, 50% clock duty cycle, AVDD = 3.3V, VDRV = 2.5V, –1dBFS, internal reference voltage, and 2VPP differential input, unless otherwise noted. ADS5221 PARAMETER DIGITAL INPUTS Logic Family Convert Command High Level Input Current(5) (VIN = 3VDD) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50µA to 1.5mA) High Output Voltage (IOH = 50µA to 0.5mA) 3-State Enable Time 3-State Disable Time Output Capacitance ACCURACY (Internal Reference, 2VPP, Unless Otherwise Noted) Zero Error (referred to midscale) Zero Error Drift (referred to midscale) Gain Error(6) Gain Error Drift(6) Power-Supply Rejection of Gain CONDITIONS MIN MAX CMOS-Compatible Rising Edge of Convert Clock 100 10 Start Conversion +1.7 +0.7 5 CMOS-Compatible Straight Offset Binary or BTC +0.1 VDRV = 2.5V +2.4 UNITS µA µA V V pF V V ns ns pF OE = H OE = L 20 2 5 40 10 fIN = 2.4MHz, at 25°C ±0.5 5 ±0.4 38 56 ±1.5 %FS ppm/°C %FS ppm/°C dB ±5 0.8 ±2.5 0.1 ±35 mV mV mV mV +3.3 +2.5 86 285 290 15 70 +3.6 +3.6 V V mA mW mW mW mW fIN = 9.7MHz, at 25°C ∆AVDD = ±5% INTERNAL VOLTAGE REFERENCE Output Voltage Error (1V) Load Regulation at 1.0mA Output Voltage Error (0.5V) Load Regulation at 0.5mA POWER-SUPPLY REQUIREMENTS Supply Voltage: AVDD, DVDD Driver Supply Voltage: VDRV Supply Current: +IS Power Dissipation: VDRV = 2.5V VDRV = 3.3V Standard Power-Down Quasi Power-Down Thermal Resistance, θJA TQFP-48 QFN-48 TYP Operating Operating (External Reference) +3.0 +2.3 63.7 26.1 295 °C/W °C/W NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) 2-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope. (4) Effective Number of Bits (ENOB) is defined by (SINAD – 1.76) /6.02. (5) A 50kΩ pull-down resistor is inserted internally on the OE pin. (6) Includes internal reference. ADS5221 SBAS262A www.ti.com 3 DVDD DVDD CLK DGND DGND AGND IN IN AGND AGND AGND AVDD PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 MSBI 1 36 AVDD OE 2 35 NC Mode Select 3 34 REFT STPD 4 33 NC QPD 5 32 REFB GDRV 6 GDRV 7 30 VREF VDRV 8 29 AGND VDRV 9 28 AGND D11 (MSB) 10 27 AGND 31 RSEL ADS5221 D4 D3 19 20 21 22 23 24 OVR 18 NC 17 NC 16 D0 (LSB) 15 D1 14 D2 13 D5 25 NC D6 D9 12 D7 26 NC D8 D10 11 PIN ASSIGNMENTS PIN I/O 1 4 DESCRIPTION MSBI Most Significant Bit Invert (HI = Binary Two’s Complement, LO = Straight Offset Binary) Tri-State (LO = Enabled, HI = Tri-State) Duty Cycle Adjust (HI = Enabled, LO = Normal Operation) Standard Power-Down (LO = Normal Operation, HI = Enabled) Quasi Power-Down (LO = Normal Operation, HI = Enabled) Output Driver Ground Output Driver Ground Output Driver Supply Output Driver Supply Data Bit 12 Data Bit 11 Data Bit 10 Data Bit 9 Data Bit 8 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 No Internal Connection No Internal Connection Over-Range Indicator 2 3 OE Mode Select 4 STPD 5 QPD 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GDRV GDRV VDRV VDRV D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) NC NC OVR O O O O O O O O O O O O PIN NAME I/O NAME DESCRIPTION 25 NC No Internal Connection 26 27 NC AGND No Internal Connection Analog Ground 28 29 AGND AGND Analog Ground Analog Ground 30 VREF Internal Reference Voltage (1/2V Reference) 31 RSEL 32 REFB Reference Mode Select (see Table I for settings) Bottom Reference Bypass 33 34 NC REFT No Internal Connection Top Reference Bypass 35 36 NC AVDD No Internal Connection Analog Supply 37 38 AVDD AGND Analog Supply Analog Ground 39 40 AGND AGND Analog Ground Analog Ground 41 42 I I 43 44 IN IN Analog Input Complementary Analog Input AGND DGND Analog Ground Digital Ground 45 46 I DGND CLK Digital Ground Convert Clock Input 47 48 I I DVDD DVDD Digital Supply Digital Supply ADS5221 www.ti.com SBAS262A TIMING DIAGRAM N+2 N+1 Analog In N+3 N tD N+4 N+5 tL tCONV N+6 N+7 tH Clock 5 Clock Cycles t2 Data Out N–5 N–4 N–3 N–2 N–1 Data Invalid SYMBOL tCONV tL tH tD t1 t2 N+1 N+2 t1 DESCRIPTION MIN Convert Clock Period Clock Pulse LOW Clock Pulse HIGH Aperture Delay Data Hold Time, CL = 0pF Propagation Delay Time, CL = 5pF max 15.4ns 6.7 6.7 ADS5221 SBAS262A N www.ti.com TYP MAX UNITS 100µs 7.7 7.7 3 6.0 6.5 ns ns ns ns ns 5 TYPICAL CHARACTERISTICS: AVDD = 3.3V TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 65MSPS, 50% clock duty cycle, AVDD = 3.3V, VDRV = 2.5V, –1dBFS, internal reference voltage, and 2VPP differential input, unless otherwise noted. SPECTRAL PERFORMANCE (Differential, 2VPP) SPECTRAL PERFORMANCE (Differential, 2VPP) 0 0 fIN = 2.4MHz (–1dBFS) SFDR = 90.2dBFS SNR = 70.2dBFS SINAD = 70.1dBFS –40 –60 –80 –100 –40 –60 –80 –100 –120 –120 0 6.5 13 26 32.5 0 6.5 SPECTRAL PERFORMANCE (Differential, 2VPP, External Reference) SPECTRAL PERFORMANCE (Differential, 1VPP) 0 fIN = 9.7MHz (–1dBFS) SFDR = 89.3dBFS SNR = 69.3dBFS SINAD = 69.2dBFS fIN = 2.4MHz (–1dBFS) SFDR = 89.3dBFS SNR = 66.9dBFS SINAD = 66.9dBFS –20 Amplitude (dB) –40 –60 –80 –100 –40 –60 –80 –100 –120 –120 0 6.5 13 26 32.5 0 6.5 Frequency (MHz) 13 26 32.5 Frequency (MHz) SPECTRAL PERFORMANCE (Single-Ended, 2VPP) TWO TONE INTERMODULATION DISTORTION 0 0 fIN = 2.4MHz (–1dBFS) SFDR = 84.0dBFS SNR = 69.6dBFS SINAD = 69.3dBFS –20 fIN = 9.5MHz (–7dBFS) fIN = 10.5MHz (–7dBFS) SFDR = 92.5dBFS –20 –40 Amplitude (dB) Amplitude (dB) 32.5 26 Frequency (MHz) –20 –60 –80 –40 –60 –80 –100 –100 –120 –120 0 6.5 13 26 32.5 0 6.5 13 26 32.5 Frequency (MHz) Frequency (MHz) 6 13 Frequency (MHz) 0 Amplitude (dB) fIN = 9.7MHz (–1dBFS) SFDR = 90.1dBFS SNR = 70.1dBFS SINAD = 69.9dBFS –20 Amplitude (dB) Amplitude (dB) –20 ADS5221 www.ti.com SBAS262A TYPICAL CHARACTERISTICS: AVDD = 3.3V (Cont.) TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 65MSPS, 50% clock duty cycle, AVDD = 3.3V, VDRV = 2.5V, –1dBFS, internal reference voltage, and 2VPP differential input, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR EXTERNAL REFERENCE TWO-TONE INTERMODULATION DISTORTION 0 1.0 fIN = 45MHz (–7dBFS) fIN = 46MHz (–7dBFS) SFDR = 86.7dBFS 0.6 0.4 –40 DLE (LSB) Amplitude (dB) –20 fIN = 9.7MHz 0.8 –60 –80 0.2 0 –0.2 –0.4 –0.6 –100 –0.8 –120 –1.0 0 6.5 13 32.5 26 0 1024 2048 Frequency (MHz) DIFFERENTIAL LINEARITY ERROR 1.0 fIN = 9.7MHz 0.8 0.6 0.6 0.4 0.4 0.2 0.2 ILE (LSB) DLE (LSB) INTEGRAL LINEARITY ERROR 1.0 fIN = 9.7MHz 0.8 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 1024 2048 3072 4096 0 1024 2048 Code 1.0 SWEPT POWER (SNR) 80 fIN = 9.7MHz 0.8 4096 3072 Code INTEGRAL LINEARITY ERROR EXTERNAL REFERENCE dBFS 70 0.6 fIN = 9.7MHz 60 SNR (dBc, dBFS) 0.4 ILE (LSB) 4096 3072 Code 0.2 0 –0.2 –0.4 50 dBc 40 30 20 –0.6 10 –0.8 0 –1.0 0 1024 2048 3072 4096 ADS5221 SBAS262A –70 –60 –50 –40 –30 –20 –10 0 Analog Input Level (dBFS) Code www.ti.com 7 TYPICAL CHARACTERISTICS: AVDD = 3.3V (Cont.) TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 65MSPS, 50% clock duty cycle, AVDD = 3.3V, VDRV = 2.5V, –1dBFS, internal reference voltage, and 2VPP differential input, unless otherwise noted. SWEPT POWER (SNR) (External Reference) SWEPT POWER (SFDR) 100 80 fIN = 9.7MHz dBFS 90 fIN = 9.7MHz dBFS 70 60 70 SNR (dBc, dBFS) SFDR (dBc, dBFS) 80 60 50 40 dBc 30 dBc 50 40 30 20 20 10 10 0 0 –80 –70 –60 –50 –40 –30 –20 –10 0 –70 –60 Analog Input Level (dBFS) –20 –10 0 DYNAMIC PERFORMANCE vs INPUT FREQUENCY 90 dBc 80 SFDR 85 70 SFDR, SNR (dBFS) SFDR (dBc, dBFS) –30 95 fIN = 9.7MHz 90 –40 Analog Input Level (dBFS) SWEPT POWER (SFDR) (External Reference) 100 –50 dBFS 60 50 40 30 80 75 65 60 20 55 10 50 0 SNR 70 45 –80 –70 –60 –50 –40 –30 –20 –10 0 1 10 Analog Input Level (dBFS) 100 Frequency (MHz) POWER DISSIPATION vs INPUT FREQUENCY 320 305 Power (mW) 290 275 260 245 230 215 200 1 10 100 Frequency (MHz) 8 ADS5221 www.ti.com SBAS262A ANALOG INPUT APPLICATION INFORMATION THEORY OF OPERATION The ADS5221 is a 12-bit, 65MSPS, CMOS ADC designed with a fully differential pipeline architecture. The pipeline consists of three sections: a 3-bit quantizer, eight middle stages with a 1.5-bit quantizer for each stage, and a 4-bit flash. The output of each pipeline stage is processed and formed into 12-bit data in the digital error correction logic section to ensure good differential linearity of the ADC. The converter includes a high bandwidth track-and-hold amplifier in the input stage as shown in Figure 1. It provides excellent performance for a single-ended input or differential input of IF (Intermediate Frequency) or an under-sampling signal. The rising edge of the input clock initiates the conversion process. Once the signal is captured by the input track-and-hold, the bits are sequentially encoded starting with the Most Significant Bit (MSB). This process results in a data latency of 5 clock cycles. The ADS5221 includes a high accuracy internal reference and also allows to the use of an external reference. The input full-scale range is up to +2V and is selectable based on the reference voltage setting. For normal operation, both analog inputs (IN, IN) require external common-mode voltage as signal swing center. The output data of ADS5221 is available as a 12-bit parallel word either coded in a Straight Offset Binary or Binary Two’s Complement format. The ADS5221 includes an option of a duty cycle stabilizer (DCS) that allows ADS5221 to operate with a nonsquare wave input clock, such as from a 30% to 70% duty cycle. When the DCS is selected the ADS5221 maintains an internal clock duty cycle at 50% with ±5% tolerance. The ADS5221 has low power dissipation in normal mode and has two power down modes for energy saving. The device operates from a single +3.3V power supply and has a separate digital output driver supply pin. Depending on the application and the desired level of performance , the analog input of the ADS5221 can be configured in various ways and driven with different circuits. The ADS5221 is particularly well-suited for communication systems that digitize large scale and wideband signals. In any case, the analog interface requirements should be carefully examined before selecting the appropriate circuit configuration. The circuit definition should include considerations on the input frequency band and amplitude, as well as the available power supplies. INPUT IMPEDANCE The input impedance of the ADS5221 is capacitive due to the input stray and sampling capacitors. These capacitors effectively result in a dynamic input impedance that is a function of the sampling and input frequency. Figure 2 depicts the differential input impedance of the ADS5221 as a function of the signal input frequency. At certain sampling rates, increasing the signal frequency will decrease the input impedance. This factor needs to be considered when the signal source is designed. For applications that use op amps to drive the ADC, it is recommended that a series resistor be added between the amplifier output and the converter inputs. This will isolate the capacitive input of the converter from the driving source and avoid gain peaking, or instability; furthermore, it will create a 1st-order, low-pass filter (LPF) in conjunction with the specified input capacitance of the ADS5221. The cutoff frequency of this LPF can be further adjusted by adding an external shunt capacitor from each signal input to ground. In any case, the use of the RC network is optional, but optimizing the values to adapt to the specific application is encouraged. DIFFERENTIAL INPUT IMPEDANCE 50 S5 40 S3 VBIAS CIN S2 CIN 30 Ohms S1 IN T&H 20 IN S4 S6 10 VBIAS 0 1 Tracking Phase: S1, S2, S3, S4 closed; S5, S6 open Hold Phase: 10 100 Input Frequency (MHz) S1, S2, S3, S4 open; S5, S6 closed FIGURE 2. Differential Input Impedance vs Input Frequency. FIGURE 1. Simplified Circuit of Input Track-and-Hold Amplifier of ADS5221. ADS5221 SBAS262A www.ti.com 9 INPUT COMMON-MODE VOLTAGE ANALOG INPUT DRIVEN BY TRANSFORMER The ADS5221 operates from a single +3.3V supply, and requires a external common-mode voltage. This allows a symmetrical signal swing while maintaining sufficient headroom to the supply rail. The common-mode voltage can be from an external DC voltage source, for example, an analog +3.3V supply with a simple resister divider, or from the input signal source with DC-coupling. When it is a single-ended input configuration, the common-mode voltage is typically +1.25V. When the input configuration is differential, the common-mode voltage is +1.5V. The ADS5221 can be driven by a transformer, which provides signal AC-coupling and allows a signal conversion from single-ended input to differential output, or from single-ended input to single-ended output. Using a transformer offers a number of advantages. As a passive component, it does not add to the total noise and has better harmonics in wide frequency bands, compared to an op amp driver. By using a step-up transformer, further signal amplification can be realized; as a result, the signal swing from the source can be reduced. For transformer selection, it is important to carefully examine the application requirements and determine the correct model, the desired impedance ratio, and frequency characteristics. Furthermore, the appropriate model must support the targeted distortion level and should not exhibit any core saturation at full-scale voltage levels. A variety of miniature RF transformers from different manufacturers, (such as, Mini-Circuits, Coilcraft, or Trak) can be selected. INPUT FULL SCALE RANGE The input full-scale range (FSR) of the ADS5221 is selectable from +1V to +2V and any value within this range, by setting the reference select pin RSEL and reference voltage pin VREF (see Table I). The input FSR (differential) is always twice VREF (the voltage at the VREF pin) for all reference modes. By choosing different signal input ranges, trade-offs can be made between noise and distortion performance. For maximizing SNR, the maximum signal input 2VPP range may be selected. This range may also be selected for low-level (–6dBFS to –40dBFS) but high-frequency multi-tone input. The signal distortion at the output of the device could be sensitive to the input signal with large full-scale. Reducing signal amplitude will improve the distortion performance. The large input signal amplitude of the converter will impose additional design constraints to the op amp due to its headroom requirements when the op amp is from single-supply and DC-coupling. Figure 3 shows a transformer-coupled input configuration of the ADS5221. The ADS5221 receives a differential AC signal from the output of the transformer and common-mode voltage of +1.5V from the center tap. A source termination resistor, RT , is required, which can be placed at the input or output of the transformer to satisfy the termination requirements of the source impedance, RS. The circuit also shows the use of an additional RC low-pass filter placed in series with each converter input to attenuate some of the wideband noise. The resistor values are typically in the range of 10Ω to 50Ω, and capacitors are in the range of 10pF to 100pF for individual application requirements. DIFFERENTIAL INPUTS The ADS5221 input structure is designed to accept both a single-end or differential analog signal. Distortion performance, however, can be improved by utilizing the differential input configuration. Differential operation of the ADS5221 requires that an input signal at the inputs (IN, IN) has the same amplitude and is 180 degrees out-of-phase. Differential signals offer a number of advantages: T4-6T 24.9Ω IN RS 24.9Ω IN RT 0.1µF • The signal amplitude is half that required for the singleended operation, and is therefore less demanding to achieve, while maintaining good linearity performance from the signal source. 1.7kΩ 3.3V ADS5221 22pF AVDD 1.5V 1.5kΩ • The reduced signal swing allows for more headroom of the interface circuitry, and therefore also allows a wider selection of the best suitable driver amplifier. • Minimization of even-order harmonics. • Improved noise immunity based on the common-mode input rejection of the converter. 10 FIGURE 3. Transformer-Coupled Differential Input Configuration of ADS5221. ADS5221 www.ti.com SBAS262A ANALOG INPUT DRIVEN BY OP AMPLIFIER The ADS5221 can be driven by an operational amplifier with DC or AC signal coupling, as shown in Figure 4 and Figure 5. In Figure 4, the THS4503, a differential amplifier, is used to convert a single-ended input to differential output with a gain of 2. The THS4503 provides an output common-mode voltage set by VOCM pin, and is DC-coupled to the input of ADS5221. A low-pass filter can be created by adding small capacitors (for example, 10pF) in parallel with the feedback resistors of the THS4503 as needed for some applications. Due to the THS4503 driving a capacitive load, small series resistors in the output ensure stable operation. Further details of this and other functions of the THS4503 may be found in its product datasheet, located on the Texas Instruments web site (www.ti.com). In general, differential amplifiers provide a higher performance driver solution as compared to a single-ended amplifier. +5V As shown in Figure 5, an AC-coupled, single-ended input configuration is realized with TI’s OPA695 for wideband applications. For narrowband applications, the OPA2822 can be used. In Figure 5, the OPA695 is configured at single supply +5V and noninverting operation. The AC gain of the amplifier is 2 and the DC offset of the amplifier is +2.5V, set by the voltage divider from the op amp power supply. The output of the amplifier can provide maximum full-scale voltage range for the ADS5221. The OPA695 is a very high bandwidth, current-feedback op amp that combines 4200V/ µs slew rate and low input voltage noise. It is optimized for high gain operation. Further details of the OPA695 can be found in the OPA695 data sheet. The common-mode voltage at the ADS5221 input is +1.25V, set by a voltage divider from +3.3V power supply. The +3.3V power supply must be decoupled, as shown in Figure 11. 10pF(1) 392Ω 187Ω 24.9Ω IN 50Ω VCM 60.4Ω THS4503 ADS5221 22pF 24.9Ω IN 0.1µF 392Ω 215Ω 10pF(1) AVDD –5V 1.7kΩ 1.5V 3.3V 1.5kΩ FIGURE 4. Using the THS4503 Differential Amplifier (Gain = 2) to Drive the ADS5221 in a DC-Coupled Configuration. +5V 0.1µF 6.8µF 1kΩ 1.6kΩ 806Ω 3.3V +5V 0.1µF 0.1µF 50Ω 57.6Ω 806Ω 30Ω IN OPA695 47pF 0.1µF 487Ω ADS5221 487Ω IN 0.1µF 47pF AVDD 1.6kΩ 3.3V 1.25V 1kΩ FIGURE 5. Single-Ended Input of ADS5221 Driven by OPA695 with Gain = 2. ADS5221 SBAS262A www.ti.com 11 CLOCK INPUT The clock input of the ADS5221 is designed to receive a single-ended pulse clock with CMOS/TTL level and DCcoupling. There is no external common-mode voltage requirement at the clock input pin (see Figure 6). The typical tolerance of the internal clock duty cycle is ±5% at its nominal value of 50% in order to maintain the high performance of the device. The ADS5221 contains an optional clock duty cycle adjust (DCA). When the DCA is enabled (Mode Select = high), a wide range of input clock duty cycle can be adjusted internally to 50% (±5% tolerance) by correcting the non-sampling edge of the clock. In this case, the noise and distortion performance will not be affected by the input clock duty cycle within this range. When the DCA is disabled (Mode Select = low), a clock duty cycle variation greater than ±5% will degrade the dynamic performance of the device. In this case, an input clock duty cycle less than 45% will automatically request a reduction in the sampling rate in order to maintain the track/hold period within the specified values for stable performance. The DCA disabled mode is suitable for nonuniform sampling ADC applications. CMOS/TTL CLK Clock Source 50Ω 50Ω ADS5221 FIGURE 6. General Input Clock Interface of ADS5221. In any case, a very low jitter clock is fundamental to preserving the excellent AC performance of the ADS5221. The device itself is specified for a low jitter, characterizing the outstanding capability of the internal clock and track-andhold circuitry. Generally, as input frequency increases, clock jitter becomes more critical to maintain a good signal-tonoise ratio. The following equation can be used to calculate the achievable SNR for a given input frequency and clock jitter (tJA in ps rms): Here, the tJA is the rms aperture jitter from all jitter sources, such as clock edge, input signal and the device. The fIN is input frequency. The crystal oscillator has very low jitter, but if using a clock conditioning circuit (gate, divider, logic lever converter, and so forth), an extra jitter and timing variation must be limited. In addition, the input clock is treated as an analog signal and its power supply should be separated from the power supply of the digital output driver to limit the digital noise. MINIMUM SAMPLING RATE The pipeline architecture of the ADS5221 uses a switchedcapacitor technique in its internal track-and-hold stages. The high sampling speed necessitates the use of very small capacitor values. In order to hold the droop errors low, the capacitors require a minimum refresh rate. To maintain accuracy of the acquired sample charge, the sampling clock on the ADS5221 must not drop below the specified minimum of 1MHz. REFERENCE ADS5221 provides both internal reference and external reference modes by setting pins RSEL and VREF (see Table 1). The input full-scale range (FSR) of ADS5221 is always twice the voltage VREF at the VREF pin. The REFT and REFB are internally buffered, and drive the ADC core for both the external reference and internal reference modes. The REFT and REFB are designed for external by pass only. The output resistance between the REFT and REFB pins is approximately 1Ω. When the internal reference mode is selected the voltage at VREF is generated by an internal 0.5V bandgap voltage through a VREF amplifier, and the VREF output can supply 2.5mA source current. When the external reference is selected, the internal VREF amplifier is powered down, the external reference voltage is added at the VREF pin, and the voltage is input to the internal REFT/REFB amplifier. The voltage at pins REFT, REFB and VREF, the full scale range (FSR) voltage at analog input for both external and internal reference modes, and the differential/single-ended input configurations are as follows: VREFT = VREF/2 +1.5V VREFB = 1.5V – VREF/2 SNR = 20 log [1/(2 • π • fIN • tJA)] VREF = VREFT – VREFB FSR (Differential) = 2 • VREF SELECTED MODE RSEL PIN CONNECT TO VREF PIN (V) INPUT FSR (V) (Differential) REFT (V) REFB (V) Internal Fixed Internal Fixed Internal Program External GND to 0.2V VREF Pin 0.2V to VREF AVDD (3.3V) 1.0 0.5 0.5 • (1+R2/R1) Ext. 0.5V to 1V 2 1 2 • VREF 2 • VREF 2 1.75 VREF/2 + 1.5 VREF/2 + 1.5 1 1.25 1.5 – VREF/2 1.5 – VREF/2 TABLE I. Reference Configuration. 12 ADS5221 www.ti.com SBAS262A The ADS5221 requires solid bypassing for all reference pins to keep the effects of clock feedthrough to a minimum and to achieve the specified levels of performance. Figure 7 to Figure 10 show the recommended decoupling scheme. All 0.1µF capacitors must be located as close to the pins as possible. In addition, pins REFT, VREF, and REFB must be decoupled with tantalum surface-mount capacitors (2.2µF, 4.7µF, 10µF or higher). RSEL R2 VREF 0.1µF 15µF 3.3V R1 ADS5221 402Ω 2Ω REFT INTERNAL REFERENCE 10µF There are two internal fixed reference modes and one internal programmable reference mode as shown in Table I and Figure 7 through Figure 9. Setting RSEL to ground (or < 0.2V) provides an internal reference voltage of +1.0V at VREF pin, +2V at REFT, and +1V at REFB pin. In this case, the input FSR is +2V peak-to-peak. Connecting RSEL to the VREF pin provides an internal reference voltage of +0.5V at VREF, +1.75V at REFT, and +1.25V at REFB. In this case, the input FSR is +1V peak-to-peak. Setting the resister divider as in Figure 9 provides an internal voltage between +0.5V and +1V at VREF, which is as follows: VREF = 0.5 • (1+R2/R1) In this case, the voltage at REFT and REFB and input FSR is calculated based on Table I. RSEL VREF 0.1µF ADS5221 2.2µF 1V Output 3.3V 402Ω 2Ω REFT 10µF 2.2µF 15µF 2.2µF 15µF 2Ω REFB 2.2µF 15µF 2.2µF 15µF 2Ω REFB 402Ω FIGURE 9. Internal Reference Mode for VREF = 0.5 • (1 + R2/R1). EXTERNAL REFERENCE For even more design flexibility, the ADS5221 can be operated with external references. Utilization of an external reference voltage may be considered for applications requiring higher accuracy, improved temperature stability, or flexible full-scale range. Particularly in multi-channel applications, the use of a common external reference offers the benefit of improving gain matching between converters. Setting RSEL to AVDD (+3.3V) provides an external reference mode for the ADS5221. In this case, the internal VREF amplifier is powered down, and the VREF pin requires an external reference voltage between +0.5V to +1V to provide an input FSR voltage of +1V to +2V. The REFT and REFB will appear with the voltage as shown in Table I and input FSR is always twice the voltage at the VREF pin. A voltage reference (REF1004 or TPS79225) and a single-supply amplifier (OPA2234 or OPA4227) can be used to generate a precision external reference. 402Ω AVDD FIGURE 7. Internal Reference Mode for VREF = 1V. RSEL RSEL VREF 0.1µF 15µF Input 0.5V to 1V VREF 0.5V Output 0.1µF 3.3V 3.3V 10µF ADS5221 ADS5221 402Ω 402Ω 2Ω 2Ω REFT REFT 10µF 2.2µF 10µF 15µF 2.2µF 15µF 2.2µF 15µF 2Ω 2Ω REFB REFB 2.2µF 15µF 402Ω 402Ω FIGURE 10. External Reference Configuration. FIGURE 8. Internal Reference Mode for VREF = 0.5V. ADS5221 SBAS262A www.ti.com 13 DIGITAL OUTPUTS DATA OUTPUT FORMAT The ADS5221 makes two data output formats available, either the Straight Offset Binary (SOB) code or the Binary Two’s Complement (BTC) code. The selection of the output coding is controlled through the MSBI pin. Applying a logic high will enable the BTC coding, whereas a logic low will enable the SOB code. The two code structures are identical with one exception: the MSB is inverted for the BTC format, as shown in Table II. If the input signal exceeds the FSR, the output code will remain at all 1s or all 0s. STRAIGHT OFFSET BINARY (SOB) BINARY TWO’S COMPLEMENT (BTC) +FS – 1LSB (+FS: VIP = 2V, VIN = 1V) 1111 1111 1111 0111 1111 1111 +1/2 FS (VIP = 1.75V, VIN = 1.25V) 1100 0000 0000 0100 0000 0000 Bipolar Zero (VIP = VIN = 1.5V) 1000 0000 0000 0000 0000 0000 –1/2 FS (VIN = 1.75V, VIP = 1.25V) 0100 0000 0000 1100 0000 0000 –FS (VIN = 2V, VIP = 1V) 0000 0000 0000 1000 0000 0000 DIFFERENTIAL INPUT the input voltage is (+FS – 1 LSB) or above this value, the ADS5221 outputs all 1s at 12 data bits; when the input voltage is –FS or below this value, the ADS5221 outputs all 0s at 12 data bits. When the input voltage is 0 (middle scale) or only the common-mode voltage at the input, the ADS5221 outputs 1 at MSB and 0s at the remaining 11 data bits. Another over-range control function of the ADS5221 is overrange indication, which is output by the OVR pin. The OVR pin is the function of the reference voltage and the output data bits, and has the same pipeline delay as the output data bits. OVR is at logic low if the input voltage is within the FSR, and is at logic high if the input voltage is over full-scale or under full-scale. OVR changes from logic low to high or logic high to low immediately following the change of the output data, when the input voltage changes from normal value to over FS or from over FS to normal value. When the input signal continues under full-scale or over full-scale, OVR stays high. TIMING OUTPUT ENABLE (OE ) The ADS5221 samples the analog signal at the rising edge of its input clock, and outputs the digital data at the rising edge of the input clock after a pipeline delay of 5 clocks. There is an aperture delay (typically 3ns) between the sampling edge and the actual sampling time. There is also a propagation delay between the rising edge of the clock and the time that data is valid on the data bus (see the timing diagram on page 5). The output data of the ADS5221 is latched data. The digital outputs of the ADS5221 can be set to output enable or output high impedance (tri-state) by the OE pin. For normal operation, this pin must be at a logic low, whereas a logic high disables the outputs or sets the output tri-state. POWER SUPPLIES AND POWER DISSIPATION TABLE II. Coding Table for Differential Input Configuration with FSR of 2V. ANALOG AND DIGITAL POWER SUPPLY OUTPUT LOADING It is recommended to keep the capacitive loading on the data output lines as low as possible, preferably below 5pF. Higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. These high current surges can feed back to the analog portion of the ADC and adversely affect device performance. If necessary, external buffers or latches (for example, the SN74LVTH16374) close to the converter output pins can be used to minimize capacitive loading. Buffers or latches also provide the added benefit of isolating the ADS5221 from any digital activities on the bus to limit the high-frequency noise. OVER-RANGE INDICATOR The ADS5221 has control functions for the input voltage over full-scale that includes output data code control and overrange indication. The output data code control of over fullscale is shown in Table II. In SOB format, for example, when 14 The ADS5221 includes power-supply pins of AVDD, DVDD and VDRV. The analog supply AVDD is +3.3V and digital supply DVDD is +3.3V. A digital output driver supply, VDRV, can be +2.5V up to +3.3V. AVDD, DVDD and VDRV are not tied together internally. Each of these supply pins must be bypassed separately with at least one 0.1µF ceramic chip capacitor. The analog supply (AVDD) and the digital supply (DVDD or VDRV) may be tied together externally with a ferrite bead or inductor between the supply pins. The digital output driver supply, VDRV, of +2.5V is used commonly. It is highly recommended to consider linear supplies instead of switching types. Even with good filtering, switching supplies can radiate noise that could interfere with any high-frequency input signal and cause unwanted modulation products. The supply voltage should stay within the tolerance given in the specification table. A basic application configuration with the power supply decoupling is shown in Figure 11. ADS5221 www.ti.com SBAS262A 30 31 24.9Ω 42 1.5V 36 AVDD AVDD 37 0.10µF 48 0.10µF DVDD 47 DVDD 4 5 Q PD 3 2 10µF + VREF NC RSEL NC OVR IN 2.2µF 2Ω +3.3 10µF 402Ω + 15µF 34 33 2Ω 2.2µF 32 38 39 40 43 44 45 27 28 29 46 NC D11 (MSB) D10 REFT D9 NC D8 REFB D7 ADS5221 D6 AGND D5 AGND D4 AGND D3 AGND D2 DGND D1 DGND D0 (LSB) AGND 26 25 24 23 22 LATCH 10 11 12 13 14 15 16 17 18 19 20 21 SN74LVTH16374 AGND AGND CLK GNDRV 15µF GNDRV + NC VDRV 35 NC IN VDRV 41 AVDD 10µF + 22pF 24.9Ω 1.5V 402Ω ST PD + Mode Select 2.2µF 0.10µF OE MSBI 1 DVDD – 7 6 49.9Ω 9 VPULSE 8 + 0.10µF 10µF + VDRV NC = No Connection. FIGURE 11. General Layout for the ADS5221. POWER DISSIPATION POWER DOWN (PD) In normal operating mode (STPD = low and QPD = low), the typical total power dissipation of the ADS5221 is 285mW. The majority of the power consumption is due to biasing; therefore, this part of the total power dissipation is independent of the applied clock frequency. The digital power dissipation from the output driver is less than 10% of the total power dissipation. This portion of the power consumption is proportional to the sampling rate, digital output load and number of the bits. The current on the VDRV supply is directly related to the capacitive loading of the data output pins; care must be taken to minimize such loading. The ADS5221 provides two power-down modes for different application requirements. One is standard power down (STPD); the second is quasi power down (QPD). Setting STPD to logic high (and QPD to logic low or high) will shut down the internal ADC core and power down the reference circuit. In this case the power dissipation is typically 15mW. With 10µF external decoupling capacitor at REFT and REFB, it takes about 800µs to fully restore normal operation after the normal mode is enabled. Setting QPD to logic high (and STPD to logic low) will shut down the internal ADC core and while the internal reference circuit power remains on. In this ADS5221 SBAS262A www.ti.com 15 case, power dissipation is typically 70mW. It takes about 2µs to fully restore normal operation after the normal mode is enabled. During power-down, data in the converter pipeline will be lost and new valid data will be subject to the specified pipeline delay. LAYOUT AND DECOUPLING Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for highfrequency designs. Achieving optimum performance with a fast sampling converter like the ADS5221 requires careful attention to the PC board layout in order to minimize the effect of board parasitics and optimize component placement. A multi-layer board usually ensures best results and allows convenient component placement. The ADS5221 must be treated as an analog component, and the AVDD pins connected to a clean analog supply. This ensures the most consistent results, because digital supplies often carry a high level of switching noise that could couple into the converter and degrade the performance. The driver supply pins (VDRV) must also be connected to a low-noise supply. Supplies of adjacent digital circuits can carry substantial current transients. The supply voltage must be thoroughly filtered before connecting to the VDRV supply of the converter. All ground connections on the ADS5221 are internally bonded to the metal flag (bottom of package) that forms a large ground plane. All ground pins must directly connect to an analog ground plane that covers the PC board area under the converter. Due to its high sampling frequency, the ADS5221 generates high frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. If not sufficiently bypassed, this adds noise to the conversion process. See Figure 11 for the recommended supply decoupling scheme for the ADS5221. All AVDD pins should be bypassed with a combination of 0.1µF ceramic chip capacitors (0805, low ESR) and a 10µF tantalum tank capacitor. A similar approach may be used on the digital 16 supply pins DVDD and driver supply pins, VDRV. In order to minimize the lead and trace inductance, the capacitors must be located as close to the supply pins as possible. They are best placed directly under the package where double-sided component mounting is allowed. In addition, larger bipolar decoupling capacitors (2.2µF to 10µF), effective at lower frequencies, must also be used on the main supply pins. They can be placed on the PC board in close proximity (< 0.5 inches) to the ADC. If the analog inputs to the ADS5221 are driven differentially, it is especially important to optimize towards a highly symmetrical layout. Small trace length differences can create phase shifts compromising a good distortion performance. For this reason, the use of two single op amps rather than one dual amplifier enables a more symmetrical layout and a better match of parasitic capacitances. The pin orientation of the ADS5221 package follows a flow-through design with the analog inputs located on one side of the package, whereas the digital outputs are located on the opposite side of the quad-flat package. This provides a good physical isolation between the analog and digital connections. While designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog portion. Try to match trace length for the differential clock signal (if used) to avoid mismatches in propagation delays. Single-ended clock lines must be short and should not cross any other signal traces. Short circuit traces on the digital outputs will minimize capacitive loading. Trace length must be kept short to the receiving gate (< 2 inches) with only one CMOS gate connected to one digital output. If possible, the digital data outputs must be buffered (with the TI SN74LTH16374, for example). Dynamic performance can also be improved with the insertion of series resistors at each data output line. This sets a defined time constant and reduces the slew rate that would otherwise flow as the fast edge rate. The resistor value may be chosen to give a time constant of 15% to 25% of the used data. ADS5221 www.ti.com SBAS262A PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2004 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS5221PFBR ACTIVE TQFP PFB 48 2500 None CU NIPDAU Level-2-220C-1 YEAR ADS5221PFBT ACTIVE TQFP PFB 48 250 None CU NIPDAU Level-2-220C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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