AD
S5
463
ADS5463-EP
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12-BIT, 500-MSPS ANALOG-TO-DIGITAL CONVERTER
Check for Samples :ADS5463-EP
FEATURES
1
•
•
23
•
•
•
•
•
•
•
•
•
•
•
500-MSPS Sample Rate
12-Bit Resolution, 10.5-Bits Effective Number
of Bits (ENOB)
2-GHz Input Bandwidth
SFDR = 75 dBc at 450 MHz and 500 MSPS
SNR = 64.6 dBFS at 450 MHz and 500 MSPS
2.2-Vpp Differential Input Voltage
LVDS-Compatible Outputs
Total Power Dissipation: 2.2 W
Offset Binary Output Format
Output Data Transitions on the Rising and
Falling Edges of a Half-Rate Output Clock
On-Chip Analog Buffer, Track and Hold, and
Reference Circuit
80-Pin TQFP PowerPAD™ Package
(14 mm × 14 mm)
Pin Similar to ADS5440/ADS5444
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
APPLICATIONS
•
•
•
•
•
•
(1)
Test and Measurement Instrumentation
Software-Defined Radio
Data Acquisition
Power Amplifier Linearization
Communication Instrumentation
Radar
Additional temperature ranges available - contact factory
DESCRIPTION/ORDERING INFORMATION
The ADS5463 is a 12-bit, 500-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and
3.3-V supply, while providing LVDS-compatible digital outputs. The ADS5463 input buffer isolates the internal
switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high
impedance input. An internal reference generator also is provided to simplify the system design.
Designed to optimize conversion of wide-bandwidth signals up to 500-MHz of input frequency at 500 MSPS, the
ADS5463 has outstanding low noise and linearity over a large input frequency range. Input signals above 500
MHz also can be converted due to the large input bandwidth of the device.
The ADS5463 is available in an 80-pin TQFP PowerPAD™ package. The ADS5463 is built on state-of-the-art
Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full extended
temperature range (–55°C to 125°C).
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ADS5463-EP
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VIN
VIN
A1
TH1
+
TH2
Σ
+
TH3
A2
ADC1
A3
ADC3
–
–
VREF
Σ
DAC1
ADC2
DAC2
Reference
5
5
5
Digital Error Correction
CLK
CLK
Timing
OVR
DRY
OVR
DRY
D[11:0]
B0061-03
Figure 1. Analog-to-Digital Converter Functional Block Diagram
Table 1. PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGE LEAD
ADS5463-EP
HTQFP-80 (3)
PowerPAD
(1)
(2)
(3)
2
PACKAGE
DESIGNATOR
PFP
(2)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
–55°C to 125°C
ADS5463MEP
ADS5463MPFPEP
Tray, 96
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Thermal pad size: 9.5 mm × 9.5 mm (minimum), 10 mm × 10 mm (maximum).
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
Supply voltage
AVDD5 to GND
6
AVDD3 to GND
5
DVDD3 to GND
5
AC signal
AIN, AIN to GND (2)
AIN to AIN
Voltage difference between
pin and ground
Voltage difference between
these pins
(2)
CLK, CLK to GND
CLK to CLK
(2)
Voltage difference between
pin and ground
Voltage difference between
these pins
0.4 to 4.4
DC signal, TJ = 125°C
1.0 to 3.8
AC signal
–5.2 to 5.2
DC signal, TJ = 105°C
–4 to 4
DC signal, TJ = 125°C
–2.8 to 2.8
0.1 to 4.7
DC signal, TJ = 125°C
1.1 to 3.7
AC signal
–3.3 to 3.3
DC signal, TJ = 105°C
–3.3 to 3.3
DC signal, TJ = 125°C
–2.6 to 2.6
Characterized case operating temperature range
Maximum junction temperature
Storage temperature range
ESD Human Body Model (HBM)
(1)
(2)
V
V
–0.3 to (AVDD5 + 0.3)
DC signal, TJ = 105°C
Data output to GND (2) LVDS digital outputs
V
–0.3 to (AVDD5 + 0.3)
DC signal, TJ = 105°C
AC signal
(2)
UNIT
V
V
–0.3 to (DVDD3 + 0.3)
V
–55 to 125
°C
150
°C
–65 to 150
°C
2
kV
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Valid when supplies are within recommended operating range.
THERMAL CHARACTERISTICS (1)
PARAMETER
(2)
RθJA
(3)
RθJP
(1)
(2)
(3)
TEST CONDITIONS
TYP
Soldered thermal pad, no airflow
23.7
Soldered thermal pad, 150 LFM airflow
17.8
Soldered thermal pad, 250 LFM airflow
16.4
Bottom of package (thermal pad)
2.99
UNIT
°C/W
°C/W
Using 36 thermal vias (6 × 6 array). See Application Information section.
RθJA is the thermal resistance from junction to ambient.
RθJP is the thermal resistance from junction to the thermal pad.
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Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may
result in a reduction of overall device life. See Figure 2 for additional information on thermal derating.
Electromigration failure mode applies to powered part. Kirkendall voiding failure mode is a function of
temperature only.
10000
Electromigration Fail Mode
1000
Years estimated life
Wirebond Voiding
Fail Mode
100
10
1
Note:
Silicon operating life design goal is 10 years @105°C junction temperature (does not include package interconnect
life).
0.1
100
110
120
130
140
150
160
170
180
Continuous Tj (°C)
Figure 2. ADS5463-EP Operating Life Derating Chart
4
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RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLIES
AVDD5
Analog supply voltage
4.75
5
5.25
V
AVDD3
Analog supply voltage
3
3.3
3.6
V
DVDD3
Output driver supply voltage
3
3.3
3.6
V
ANALOG INPUT
VCM
Differential input range
2.2
Vpp
Input common mode
2.4
V
10
pF
DIGITAL OUTPUT (DRY, DATA, OVR)
Maximum differential output load
CLOCK INPUT (CLK)
CLK input sample rate (sine wave)
20
Clock amplitude, differential sine wave
Clock duty cycle
TA
500
MSPS
3
Vpp
50%
Open free-air temperature
–55
125
°C
ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –55°C to TMAX = 125°C,
sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3 VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
12
Bits
Differential input range
2.2
Vpp
Input common mode
2.4
V
ANALOG INPUTS
VCM
Input resistance (dc)
Each input to ground
500
Ω
Input capacitance
Each input to ground
2.5
pF
Analog input bandwidth (–3 dB) Dependent on source impedance
CMRR
Common Mode Rejection Ratio
Common Mode Signal = 10MHz
2
GHz
80
dB
2.4
V
INTERNAL REFERENCE VOLTAGE
VREF
Reference voltage
DYNAMIC ACCURACY
No missing codes
Assured
DNL
Differential linearity error
fIN = 10 MHz
INL
Integral linearity error
fIN = 10 MHz
Offset error
–0.95
±0.25
0.95
LSB
–2.5 +0.8/–0.3
2.5
LSB
–11
11
Offset temperature coefficient
0.0005
Gain error
–5.2
Gain temperature coefficient
PSRR
5.2
%FS
Δ%/°C
–0.02
100kHz supply noise (see Figure 34)
mV
mV/°C
85
dB
POWER SUPPLY
IAVDD5
5-V analog supply current
IAVDD3
3.3-V analog supply current
300
365
mA
125
145
IDVDD3
3.3-V digital supply current
mA
82
92
mA
Total Power dissipation
2.18
2.575
W
Power-up time
200
VIN = full scale, fIN = 10 MHz,
fS = 500 MSPS
μs
DYNAMIC AC CHARACTERISTICS
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –55°C to TMAX = 125°C,
sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3 VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
fIN = 10 MHz
Signal-to-noise ratio
fIN = 300 MHz
Temp
63.5
65.3
63
65.3
65.1
25C
63.25
65
Temp
61.75
65
fIN = 450 MHz
64.6
fIN = 650 MHz
63.9
fIN = 900 MHz
62.6
fIN = 1.3 GHz
59.3
fIN = 10 MHz
85
fIN = 70 MHz
82
fIN = 100 MHz
25C
70
82
Temp
67
82
25C
64
77
Temp
62
77
fIN = 230 MHz
SFDR
Spurious free dynamic range
fIN = 300 MHz
fIN = 450 MHz
75
fIN = 650 MHz
65
fIN = 900 MHz
56
fIN = 1.3 GHz
45
fIN = 10 MHz
87
fIN = 100 MHz
fIN = 300 MHz
81
62.5
6
Third harmonic
77
80
fIN = 650 MHz
77
fIN = 900 MHz
66
fIN = 1.3 GHz
50
fIN = 10 MHz
85
fIN = 70 MHz
90
67.5
fIN = 230 MHz
HD3
80
fIN = 450 MHz
fIN = 100 MHz
fIN = 300 MHz
dBc
87
90
63
80
fIN = 450 MHz
75
fIN = 650 MHz
65
fIN = 900 MHz
56
fIN = 1.3 GHz
45
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dBc
82
67
fIN = 230 MHz
Second harmonic
dBFS
78
fIN = 70 MHz
HD2
UNIT
65.4
25C
fIN = 230 MHz
SNR
MAX
65.3
fIN = 70 MHz
fIN = 100 MHz
TYP
dBc
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –55°C to TMAX = 125°C,
sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3 VPP differential clock (unless otherwise noted)
PARAMETER
Worst harmonic/spur (other
than HD2 and HD3)
THD
Total Harmonic Distortion
TEST CONDITIONS
MIN
fIN = 10 MHz
86
fIN = 70 MHz
86
fIN = 100 MHz
86
fIN = 230 MHz
77
fIN = 300 MHz
81
fIN = 450 MHz
86
fIN = 650 MHz
85
fIN = 900 MHz
78
fIN = 1.3 GHz
67
fIN = 10 MHz
80
fIN = 70 MHz
79
fIN = 100 MHz
77
fIN = 230 MHz
75
fIN = 300 MHz
73
fIN = 450 MHz
73
fIN = 650 MHz
64
fIN = 900 MHz
55
fIN = 1.3 GHz
44
fIN = 10 MHz
65.2
fIN = 70 MHz
65.2
fIN = 100 MHz
62
fIN = 230 MHz
SINAD
Signal-to-noise and distortion
Two-Tone SFDR
ENOB
Effective number of bits
RMS idle-channel noise
TYP
fIN = 300 MHz
UNIT
dBc
dBc
65.1
64.7
58.75
64.5
fIN = 450 MHz
64.1
fIN = 650 MHz
61.5
fIN = 900 MHz
55.4
fIN = 1.3 GHz
45.1
fIN1 = 65 MHz, fIN2 = 70 MHz, Each tone at –7 dBFS
90
fIN1 = 65 MHz, fIN2 = 70 MHz, Each tone at –16 dBFS
89
fIN1 = 350 MHz, fIN2 = 355 MHz, Each tone at –7
dBFS
82
fIN1 = 350 MHz, fIN2 = 355 MHz, Each tone at –16
dBFS
89
fIN = 100 MHz
MAX
9.9
fIN = 300 MHz
dBc
dBc
10.5
Bits
10.4
Inputs tied to common-mode
0.7
LSB
LVDS DIGITAL OUTPUTS
VOD
Differential output voltage (±)
VOC
Common mode output voltage
TA = 25°C
247
1.125
400
454
1.375
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V
7
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Sample
N–1
N+4
N+2
ta
N
N+1
N+3
tCLKH
N+5
tCLKL
CLK
CLK
Latency = 4 Clock Cycles
tDRY
DRY
DRY
tDATA
D[11:0], OVR
N–1
N
N+1
D[11:0], OVR
T0158-01
Figure 3. Timing Diagram
8
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TIMING CHARACTERISTICS (1)
Typical values at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V,
DVDD3 = 3.3 V, and 3 VPP differential clock (unless otherwise noted)
PARAMETER
tA
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Aperture delay
200
ps
Aperture jitter, rms
160
fs
3.5
cycles
Latency
tCLK
Clock period
2
ns
tCLKH
Clock pulse duration, high
1
ns
tCLKL
Clock pulse duration, low
1
ns
(1)
tDRY
CLK to DRY delay
tDATA
CLK to DATA/OVR delay
tSKEW
DRY to DATA skew
tDATA – tDRY, 7 pF diff loading
tRISE
DRY/DATA/OVR rise time
tFALL
DRY/DATA/OVR fall time
(1)
(1)
Zero crossing, 7 pF diff loading
1100
ps
Zero crossing, 7 pF diff loading
1100
ps
0
ps
7 pF differential loading
500
ps
7 pF differential loading
500
ps
DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the data propagation
delay.
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D4
D5
D4
D5
GND
D6
DVDD3
D7
D6
D8
D7
D9
D8
D10
D9
D11 (MSB)
D10
DRY
D11 (MSB)
DRY
PFP PACKAGE
(TOP VIEW)
DVDD3
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
GND
2
59
D3
3
4
58
57
D2
D1
AVDD5
NC
D3
D2
NC
5
56
VREF
6
55
D1
GND
54
D0
AVDD5
7
8
53
D0
GND
9
52
GND
CLK
10
51
DVDD3
CLK
11
50
NC
ADS5463
GND
12
49
NC
AVDD5
13
48
NC
AVDD5
14
47
NC
GND
15
46
NC
AIN
16
45
NC
AIN
17
44
NC
GND
18
43
NC
AVDD5
19
42
OVR
GND
20
41
OVR
GND
AVDD3
GND
GND
AVDD3
AVDD3
GND
GND
RESERVED
GND
AVDD5
GND
RESERVED
GND
AVDD5
GND
AVDD5
GND
AVDD5
AVDD5
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P0027-02
10
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Table 2. TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
DESCRIPTION
AIN
16
Differential input signal (positive)
AIN
17
Differential input signal (negative)
AVDD5
3, 8, 13, 14, 19, 21,
23, 25, 27, 31
AVDD3
35, 37, 39
Analog power supply (3.3 V) (Suggestion for ≤250 MSPS: leave option to connect to 5 V for
ADS5440/4 compatibility)
DVDD3
1, 51, 66
Output driver power supply (3.3 V)
Analog power supply (5 V)
GND
2, 7, 9, 12, 15, 18,
20, 22, 24, 26, 28,
30, 32, 34, 36, 38,
40, 52, 65
CLK
10
Differential input clock (positive). Conversion is initiated on rising edge.
CLK
11
Differential input clock (negative)
Ground
D0, D0
54, 53
LVDS digital output pair, least-significant bit (LSB)
D1–D10,
D1–D10
55–64,
67–76
LVDS digital output pairs
D11, D11
78, 77
LVDS digital output pair, most-significant bit (MSB)
DRY, DRY
80, 79
Data ready LVDS output pair
4, 5, 43–50
No connect (4 and 5 should be left floating, 43–50 are possible future bit additions for this pinout
and therefore can be connected to a digital bus or left floating)
OVR, OVR
42, 41
Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale
range.
RESERVED
29, 33
Pin 29 is reserved for possible future Vcm output for this pinout; pin 33 is reserved for possible
future power-down control pin for this pinout.
NC
VREF
6
Reference voltage
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TYPICAL CHARACTERISTICS
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SPECTRAL PERFORMANCE
FFT FOR 30-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 100-MHz INPUT SIGNAL
0
0
SFDR = 82.4 dBc
SINAD = 65.3 dBFS
SNR = 65.4 dBFS
THD = 79 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−20
SFDR = 80.6 dBc
SINAD = 65.1 dBFS
SNR = 65.3 dBFS
THD = 77.1 dBc
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
50
Frequency − MHz
75 100 125 150 175 200 225 250
Frequency − MHz
G001
G002
Figure 4.
Figure 5.
SPECTRAL PERFORMANCE
FFT FOR 230-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 300-MHz INPUT SIGNAL
0
0
SFDR = 77.5 dBc
SINAD = 64.7 dBFS
SNR = 65.2 dBFS
THD = 73.7 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−20
SFDR = 77.1 dBc
SINAD = 64.5 dBFS
SNR = 65 dBFS
THD = 73.1 dBc
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
Frequency − MHz
50
75 100 125 150 175 200 225 250
Frequency − MHz
G003
Figure 6.
12
G004
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SPECTRAL PERFORMANCE
FFT FOR 450-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 650-MHz INPUT SIGNAL
0
0
SFDR = 74.3 dBc
SINAD = 64.3 dBFS
SNR = 64.8 dBFS
THD = 73 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−20
SFDR = 65.5 dBc
SINAD = 61.8 dBFS
SNR = 64 dBFS
THD = 64.9 dBc
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
50
Frequency − MHz
75 100 125 150 175 200 225 250
Frequency − MHz
G005
G006
Figure 8.
Figure 9.
SPECTRAL PERFORMANCE
FFT FOR 900-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 1,300-MHz INPUT SIGNAL
0
0
SFDR = 55.5 dBc
SINAD = 55.3 dBFS
SNR = 62.8 dBFS
THD = 55.1 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−20
SFDR = 45.6 dBc
SINAD = 45.1 dBFS
SNR = 59.3 dBFS
THD = 44.3 dBc
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
Frequency − MHz
50
75 100 125 150 175 200 225 250
Frequency − MHz
G007
Figure 10.
G008
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 65.1 MHz AND 70.1 MHz AT –7 dBFS)
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 65.1 MHz AND 70.1 MHz AT –16 dBFS)
0
0
fIN1 = 65.1 MHz, −7 dBFS
fIN2 = 70.1 MHz, −7 dBFS
IMD3 = 90.5 dBFS
SFDR = 90.3 dBFS
−20
−40
Amplitude − dB
Amplitude − dB
−20
fIN1 = 65.1 MHz, −16 dBFS
fIN2 = 70.1 MHz, −16 dBFS
IMD3 = 96.1 dBFS
SFDR = 88.8 dBFS
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
50
Frequency − MHz
75 100 125 150 175 200 225 250
Frequency − MHz
G009
G010
Figure 12.
Figure 13.
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 350 MHz AND 355 MHz AT –7 dBFS)
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 350 MHz AND 355 MHz AT –16 dBFS)
0
0
fIN1 = 350 MHz, −7 dBFS
fIN2 = 355 MHz, −7 dBFS
IMD3 = 81.6 dBFS
SFDR = 81.6 dBFS
−20
−40
Amplitude − dB
Amplitude − dB
−20
fIN1 = 350 MHz, −16 dBFS
fIN2 = 355 MHz, −16 dBFS
IMD3 = 101.1 dBFS
SFDR = 88.9 dBFS
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
Frequency − MHz
50
75 100 125 150 175 200 225 250
Frequency − MHz
G011
Figure 14.
14
G012
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
FULLSCALE GAIN RESPONSE
vs
INPUT FREQUENCY
DIFFERENTIAL NONLINEARITY
4
0.3
fS = 500 MSPS
fIN = 10 MHz
3
0.2
Differential Nonlinearity − LSB
Input Amplitude − dB
2
1
0
−1
−2
−3
−4
0.0
−0.1
−0.2
−5
fS = 500 MSPS
AIN= –1 dBFS
−6
0
−0.3
200 400 600 800 1000 1200 1400 1600 1800 2000
fIN − Input Frequency − MHz
50
550
1050 1550 2050 2550 3050 3550 4050
Code
G013
G014
Figure 16.
Figure 17.
INTEGRAL NONLINEARITY
NOISE HISTOGRAM WITH INPUTS SHORTED
1.0
60
fS = 500 MSPS
fIN = 10 MHz
0.8
55
fS = 500 MSPS
50
0.6
45
0.4
Percentage − %
INL − Integral Nonlinearity − LSB
0.1
0.2
0.0
−0.2
−0.4
40
35
30
25
20
15
−0.6
10
−0.8
5
−1.0
0
50
550
1050 1550 2050 2550 3050 3550 4050
2050
Code
G015
Figure 18.
2049
2048
2047
2046
Code Number
G016
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
AC PERFORMANCE
vs
INPUT AMPLITUDE (100-MHz INPUT SIGNAL)
AC PERFORMANCE
vs
INPUT AMPLITUDE (300-MHz INPUT SIGNAL)
120
100
120
SFDR (dBFS)
80
SNR (dBFS)
60
Performance − dB
Performance − dB
80
SFDR (dBFS)
100
40
SFDR (dBc)
20
0
SNR (dBFS)
60
40
SFDR (dBc)
20
0
SNR (dBc)
SNR (dBc)
−20
−20
−40
−60
−120
−40
fS = 500 MSPS
fIN = 100.3 MHz
−100
−80
−60
−40
−20
fS = 500 MSPS
fIN = 301.1 MHz
−60
−120
0
−100
Input Amplitude − dBFS
−80
−60
−40
−20
G017
G018
Figure 20.
Figure 21.
AC PERFORMANCE
vs
INPUT AMPLITUDE (350-MHz AND 355-MHz TWO-TONE INPUT
SIGNAL)
SFDR
vs
CLOCK DUTY CYCLE
85
SFDR − Spurious-Free Dynamic Range − dBc
100
80
Worst Spur (dBFS)
AC Performance − dB
SNR (dBFS)
60
Worst Spur (dBc)
40
20
SNR (dBc)
0
−20
−80
fS = 500 MSPS
fIN1 = 350 MHz
fIN2 = 355 MHz
fIN = 100 MHz
80
75
fIN = 300 MHz
70
65
60
55
fS = 500 MSPS
50
−70
−60
−50
−40
−30
−20
−10
20
0
30
40
50
60
70
80
Duty Cycle − %
Input Amplitude − dBFS
G021
G020
Figure 22.
16
0
Input Amplitude − dBFS
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SFDR
vs
CLOCK LEVEL
SNR
vs
CLOCK LEVEL
66.0
79
fIN = 100 MHz
SNR − Signal-to-Noise Ratio − dBFS
SFDR − Spurious-Free Dynamic Range − dBc
80
78
77
fIN = 300 MHz
76
75
74
73
72
65.0
fIN = 300 MHz
64.5
64.0
63.5
63.0
fS = 500 MSPS
fS = 500 MSPS
62.5
71
0
1
2
3
4
0
5
Clock Amplitude − VP−P
1
2
3
4
5
Clock Amplitude − VP−P
G022
Figure 24.
Figure 25.
SFDR
vs
CLOCK COMMON MODE
SNR
vs
CLOCK COMMON MODE
G023
66
85
fIN = 100 MHz
SNR − Signal-to-Noise Ratio − dBFS
SFDR − Spurious-Free Dynamic Range − dBc
fIN = 100 MHz
65.5
fIN = 100 MHz
80
fIN = 300 MHz
75
70
65
65
fIN = 300 MHz
64
63
62
61
fS = 500 MSPS
fS = 500 MSPS
60
60
0
1
2
3
4
5
0
Clock Common Mode − V
1
2
3
4
5
Clock Common Mode − V
G025
G024
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SFDR
vs
AVDD5 ACROSS TEMPERATURE
SNR
vs
AVDD5 ACROSS TEMPERATURE
67.0
SNR − Signal-to-Noise Ratio − dBFS
SFDR − Spurious-Free Dynamic Range − dBc
80
75
70
TA = 05C
TA = 405C
65
TA = 655C
TA = 255C
TA = −405C
60
TA = 855C
55
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
AVDD − Supply Voltage − V
TA = 255C
TA = 405C
65.0
64.5
TA = 655C
64.0
TA = 855C
TA = 1005C
AVDD − Supply Voltage − V
G026
SFDR
vs
AVDD3 ACROSS TEMPERATURE
SNR
vs
AVDD3 ACROSS TEMPERATURE
66.5
TA = 255C
78
TA = 05C
76
TA = 655C
74
TA = 855C
TA = 1005C
70
TA = −405C
2.9
fS = 500 MSPS
fIN= 100 MHz
3.1
3.3
AVDD − Supply Voltage − V
3.5
66.0
TA = −405C
TA = 05C
65.5
TA = 255C
TA = 405C
65.0
TA = 655C
64.5
TA = 855C
64.0
fS = 500 MSPS
fIN= 100 MHz
3.7
63.5
2.7
G028
Figure 30.
18
G027
Figure 29.
SNR − Signal-to-Noise Ratio − dBFS
SFDR − Spurious-Free Dynamic Range − dBc
65.5
Figure 28.
TA = 405C
68
2.7
TA = 05C
63.0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
80
72
TA = −405C
66.0
63.5
fS = 500 MSPS
fIN= 100 MHz
TA = 1005C
66.5
fS = 500 MSPS
fIN= 100 MHz
2.9
TA = 1005C
3.1
3.3
AVDD − Supply Voltage − V
3.5
3.7
G029
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SFDR
vs
DVDD3 ACROSS TEMPERATURE
SNR
vs
DVDD3 ACROSS TEMPERATURE
66.5
TA = 255C
SNR − Signal-to-Noise Ratio − dBFS
SFDR − Spurious-Free Dynamic Range − dBc
80
78
TA = 405C
TA = 05C
76
TA = 655C
74
TA = 855C
72
TA = −405C
70
TA = 1005C
66.0
TA = −405C
TA = 05C
65.5
TA = 255C
TA = 405C
65.0
TA = 655C
64.5
TA = 855C
64.0
fS = 500 MSPS
fIN= 100 MHz
68
2.7
2.9
3.1
3.3
3.5
DVDD − Supply Voltage − V
TA = 1005C
63.5
2.7
3.7
2.9
3.1
3.3
3.5
3.7
DVDD − Supply Voltage − V
G030
Figure 32.
Figure 33.
PSRR
vs
SUPPLY INJECTED FREQUENCY
CMRR
vs
COMMON-MODE INPUT FREQUENCY
100
G031
100
CMRR − Common-Mode Rejection Ratio − dB
PSRR − Power Supply Rejection Ratio − dB
fS = 500 MSPS
fIN= 100 MHz
AVDD3
90
80
AVDD5
70
60
50
fS = 500 MSPS
fIN= None
40
0.01
0.1
1
10
100
Frequency − MHz
90
fS = 500 MSPS
80
70
60
50
40
30
20
10
0
0.1
1
10
100
1000
Common-Mode Input Frequency − MHz
G032
Figure 34.
G033
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SNR
vs
INPUT FREQUENCY AND SAMPLING FREQUENCY
550
63
64
64
65
61
62
63
fS - Sampling Frequency - MHz
500
65
450
64
400
63
62
350
300
65
64
63
62
250
61
200
170
10
58
59
65
100
200
300
400
500
600
700
800
900
1000
64
65
66
67
fIN - Input Frequency - MHz
57
58
59
60
61
62
63
SNR - dBFS
M0048-09
Figure 36.
20
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SFDR
vs
INPUT FREQUENCY AND SAMPLING FREQUENCY
550
70
75
80
500
fS - Sampling Frequency - MHz
60
75
55
65
80
80
450
400
70
75
65
80
350
55
60
80
300
85
250
60
200
170
10
70
75
85
100
300
200
55
65
80
500
400
600
700
800
900
1000
fIN - Input Frequency - MHz
45
50
55
60
65
70
SFDR - dBc
75
80
85
90
M0048-10
Figure 37.
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APPLICATION INFORMATION
Theory of Operation
The ADS5463 is a 12-bit, 500-MSPS, monolithic-pipeline, analog-to-digital converter. Its bipolar analog core
operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs.
The conversion process is initiated by the rising edge of the external input clock. At that instant, the differential
input signal is captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a
series of lower resolution stages, with the outputs combined in a digital correction logic block. Both the rising and
the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This
process results in a data latency of 3.5 clock cycles, after which the output data is available as a 12-bit parallel
word, coded in offset binary format.
Input Configuration
The analog input for the ADS5463 consists of an analog pseudodifferential buffer followed by a bipolar transistor
track-and-hold. The analog buffer isolates the source driving the input of the ADC from any internal switching.
The input common mode is set internally through a 500-Ω resistor connected from 2.4 V to each of the inputs.
This results in a differential input impedance of 1 kΩ.
For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings
symmetrically between 2.4 V + 0.55 V and 2.4 V – 0.55 V. This means that each input has a maximum signal
swing of 1.1 Vpp for a total differential input signal swing of 2.2 Vpp. The maximum swing is determined by the
internal reference voltage generator, eliminating the need for any external circuitry for this purpose.
The ADS5463 obtains optimum performance when the analog inputs are driven differentially. The circuit in
Figure 38 shows one possible configuration using an RF transformer with termination either on the primary or on
the secondary of the transformer. In addition, the evaluation module is configured with two back-to-back
transformers, which also demonstrates good performance. If voltage gain is required, a step-up transformer can
be used.
Besides the transformer configurations, Texas Instruments offers a wide selection of single-ended operational
amplifiers that can be selected depending on the application. An RF gain-block amplifier, such as Texas
Instruments' THS9001, can also be used for high-input-frequency applications. For large voltage gains at
intermediate-frequencies in the 50-MHz to 500-MHz range, the configuration shown in Figure 39 can be used.
The component values can be tuned for different intermediate frequencies. The example shown is located on the
evaluation module and is tuned for an IF of 170 MHz. More information regarding this configuration can be found
in the ADS5463 EVM User Guide (SLAU194) and the THS9001 50 MHz to 350 MHz Cascadeable Amplifier data
sheet (SLOS426).
R0
50 W
Z0
50 W
AIN
1:1
R
50 W
AC Signal
Source
Mini-Circuits
JTX4-10T
ADS5463
AIN
S0176-03
Figure 38. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer
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1000 pF
VIN
1000 pF
AIN
THS9001
50 W
18 mH
39 pF
ADS5463
50 W
VIN
0.1 mF
AIN
THS9001
1000 pF
1000 pF
S0177-03
Figure 39. Using the THS9001 IF Amplifier With the ADS5463
From
50 W
Source
VIN
348 W
100 W
78.9 W
+5V
49.9 W
0.22 mF
100 W
AIN
THS4509
ADS5463
49.9 W 18 pF
AIN
VREF
CM
49.9 W
0.22 mF
78.9 W
49.9 W
0.22 mF
0.1 mF
0.1 mF
348 W
S0193-02
Figure 40. Using the THS4509 With the ADS5463
For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier like
the THS4509 (see Figure 40) is a good solution, as it minimizes board space and reduces the number of
components.
In this configuration, the THS4509 amplifier circuit provides 10-dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5463. The 50-Ω resistors and 18-pF
capacitor between the THS4509 outputs and ADS5463 inputs (along with the input capacitance of the ADC) limit
the bandwidth of the signal to about 70 MHz (–3 dB). Input termination is accomplished via the 78.9-Ω resistor
and 0.22-μF capacitor to ground, in conjunction with the input impedance of the amplifier circuit. A 0.22-μF
capacitor and 49.9-Ω resistor are inserted to ground across the 78.9-Ω resistor and 0.22-μF capacitor on the
alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348-Ω
feedback resistor. See the THS4509 data sheet for further component values to set proper 50-Ω termination for
other common gains. Because the ADS5463 recommended input common-mode voltage is 2.4 V, the THS4509
is operated from a single power supply input with V S+ = 5 V and V S– = 0 V (ground). This maintains maximum
headroom on the internal transistors of the THS4509.
Clock Inputs
The ADS5463 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. In low-input-frequency applications, where
jitter may not be a big concern, the use of a single-ended clock (see Figure 41) could save some cost and board
space without any trade-off in performance. When clocked with this configuration, it is best to connect CLK to
ground with a 0.01-μF capacitor, while CLK is ac-coupled with a 0.01-μF capacitor to the clock source, as shown
in Figure 41.
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Square Wave or
Sine Wave
CLK
0.01 mF
ADS5463
CLK
0.01 mF
S0168-05
Figure 41. Single-Ended Clock
0.1 mF
Clock
Source
CLK
ADS5463
CLK
S0194-02
Figure 42. Differential Clock
For jitter-sensitive applications, the use of a differential clock has some advantages (as with any other ADC) at
the system level. The differential clock allows for common-mode noise rejection at the PCB level. With a
differential clock, the signal-to-noise ratio of the ADC is better for high intermediate frequency applications
because the board clock jitter is superior.
A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum
ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise
on jitter. Figure 42 shows this approach. See Clocking High Speed Data Converters (SLYT075) for more details.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking,
the ADS5463 features good tolerance to clock common-mode variation (see Figure 26 and Figure 27).
Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50%
duty-cycle clock signal should be provided.
Digital Outputs
The ADC provides 12 data outputs (D11 to D0, with D11 being the MSB and D0 the LSB), a data-ready signal
(DRY), and an overrange indicator (OVR) that equals a logic high when the output reaches the full-scale limits.
The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the
ADS5463. DRY is source-synchronous to the DATA/OVR bits and operates at the same frequency, creating a
half-rate DDR interface that updates data on both the rising and falling edges of DRY. The ADS5463 digital
outputs are LVDS-compatible. Due to the high data rates, care should be taken not to overload the digital outputs
with too much capacitance, which shortens the data-valid timing window. The values given for timing were
obtained with a measured 14-pF parasitic board capacitance to ground on each LVDS line (or 7-pF differential
parasitic capacitance).
Power Supplies
The ADS5463 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5
and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power
supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched
supplies tend to generate more noise components that can be coupled to the ADS5463. The user may be able to
supply power to the device with a less-than-ideal supply and still achieve good performance. It is not possible to
make a single recommendation for every type of supply and level of decoupling for all systems.
24
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The power consumption of the ADS5463 does not change substantially over clock rate or input frequency as a
result of the architecture and process.
Because there are two diodes connected in reverse between AVDD3 and DVDD3 internally, a power-up
sequence is recommended. When there is a delay in power up between these two supplies, the one that lags
could have current sinking through an internal diode before it powers up. The sink current can be large or small
depending on the impedance of the external supply and could damage the device or affect the supply source.
The best power up sequence is one of the following options (regardless of when AVDD5 powers up):
• Power up both AVDD3 and DVDD3 at the same time (best scenario), OR
• Keep the voltage difference less than 0.8 V between AVDD3 and DVDD3 during the power up (0.8 V is not a
hard specification - a smaller delta between supplies is safer).
If the above sequences are not practical then the sink current from the supply needs to be controlled or
protection added externally. The max transient current (on the order of msec) for the DVDD3 or AVDD3 pin is
500 mA to avoid potential damage to the device or reduce its lifetime.
The values for the analog and clock inputs given in the Absolute Maximum Ratings are valid when the supplies
are on. When the power supplies are off and the clock or analog inputs are still being actively driven, the input
voltage and current need to be limited to avoid device damage. If the ADC supplies are off, max/min continuous
dc voltage is ±0.95 V and max dc current is 20 mA for each input pin (clock or analog), relative to ground.
Layout Information
The evaluation board represents a good guideline of how to lay out the board to obtain the maximum
performance from the ADS5463. General design rules, such as the use of multilayer boards, single ground plane
for ADC ground connections, and local decoupling ceramic chip capacitors, should be applied. The input traces
should be isolated from any external source of interference or noise, including the digital outputs as well as the
clock traces. The clock signal traces also should be isolated from other signals, especially in applications where
low jitter is required like high IF sampling. Besides performance-oriented rules, care must be taken when
considering the heat dissipation of the device. The thermal heat sink should be soldered to the board as
described in the PowerPad Package section. See ADS5463 EVM User Guide (SLAU194) on the TI Web site for
the evaluation board schematic.
PowerPAD Package
The PowerPAD package is a thermally enhanced standard-size IC package designed to eliminate the use of
bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using
standard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standard
repair procedures.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of
the IC. This provides an extremely low thermal resistance path between the die and the exterior of the package.
The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using
the PCB as a heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in
the Mechanical Data section.
2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13-mils in diameter. The
small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25-mil diameter holes under the package, but outside the
thermal pad area, to provide an additional heat path.
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a
ground plane).
5. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
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For more detailed information regarding the PowerPAD package and its thermal properties, see either the
PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application
report (SLMA002).
26
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low-frequency value
Aperture Delay
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay
Clock Pulse Duration/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
duration) to the period of the clock signal, expressed
as a percentage.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1 LSB apart. DNL is the
deviation of any single step from this ideal value,
measured in units of LSB.
Common-Mode Rejection Ratio (CMRR)
CMRR measures the ability to reject signals that are
presented to both analog inputs simultaneously. The
injected common-mode frequency level is translated
into dBFS, the spur in the output FFT is measured in
dBFS, and the difference is the CMRR in dB.
Effective Number of Bits (ENOB)
ENOB is a measure in units of bits of a converter's
performance as compared to the theoretical limit
based on quantization noise
ENOB = (SINAD – 1.76)/6.02
Gain Error
Gain error is the deviation of the ADC actual input
full-scale range from its ideal value, given as a
percentage of the ideal input full-scale range.
Integral Nonlinearity (INL)
INL is the deviation of the ADC transfer function from
a best-fit line determined by a least-squares curve fit
of that transfer function. The INL at each analog input
value is the difference between the actual transfer
function and this best-fit line, measured in units of
LSB.
Offset Error
Offset error is the deviation of output code from
mid-code when both inputs are tied to
common-mode.
Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of the ability to reject frequencies
present on the power supply. The injected frequency
level is translated into dBFS, the spur in the output
FFT is measured in dBFS, and the difference is the
PSRR in dB. The measurement calibrates out the
benefit of the board supply decoupling capacitors.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and in the first five harmonics.
P
SNR + 10log 10 S
PN
(2)
SNR is given either in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
dc.
PS
SINAD + 10log 10
PN ) PD
(3)
SINAD is given either in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
Temperature Drift
Temperature drift (with respect to gain error and
offset error) specifies the change from the value at
the nominal temperature to the value at TMIN or TMAX.
It is computed as the maximum variation the
parameters over the whole temperature range divided
by TMIN – TMAX.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS)
to the power of the first five harmonics (PD).
P
THD + 10log 10 S
PD
(4)
THD is typically given in units of dBc (dB to carrier).
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Two-Tone Intermodulation Distortion (IMD3)
IMD3 is the ratio of the power of the fundamental (at
frequencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 – f2 or 2f2 – f1).
IMD3 is given in units of either dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
ADS5463MPFPEP
ACTIVE
HTQFP
PFP
80
96
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
ADS5463MEP
V62/07607-01XE
ACTIVE
HTQFP
PFP
80
96
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
ADS5463MEP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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