ADS5547
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SLWS192A – NOVEMBER 2006 – REVISED MAY 2007
14-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
FEATURES
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•
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•
•
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Maximum Sample Rate: 210 MSPS
14-Bit Resolution
No Missing Codes
Total Power Dissipation 1.23 W
Internal Sample and Hold
73.3-dBFS SNR at 70-MHz IF
85-dBc SFDR at 70-MHz IF, 0-dB gain
High Analog Bandwidth up to 800 MHz
Double Data Rate (DDR) LVDS and Parallel
CMOS Output Options
Programmable Gain up to 6 dB for SNR/SFDR
Trade-Off at High IF
Reduced Power Modes at Lower Sample
Rates
Supports Input Clock Amplitude Down to
400 mVPP
Clock Duty Cycle Stabilizer
No External Reference Decoupling Required
Internal and External Reference Support
Programmable Output Clock Position to Ease
Data Capture
3.3-V Analog and Digital Supply
48-QFN Package (7 mm × 7 mm)
DESCRIPTION
ADS5547 is a high performance 14-bit, 210-MSPS
A/D converter. It offers state-of-the art functionality
and performance using advanced techniques to
minimize board space. With high analog bandwidth
and low jitter input clock buffer, the ADC supports
both high SNR and high SFDR at high input
frequencies. It features programmable gain options
that can be used to improve SFDR performance at
lower full-scale analog input ranges.
In a compact 48-pin QFN, the device offers fully
differential LVDS DDR (Double Data Rate) interface
while parallel CMOS outputs can also be selected.
Flexible output clock position programmability is
available to ease capture and trade-off setup for hold
times. At lower sampling rates, the ADC can be
operated at scaled down power with no loss in
performance. The ADS5547 includes an internal
reference, while eliminating the traditional reference
pins and associated external decoupling. The device
also supports an external reference mode.
The device is specified over
temperature range (-40°C to 85°C).
the
industrial
ADS5547 PRODUCT FAMILY
210 MSPS
190 MSPS
170 MSPS
14 bit
ADS5547
ADS5546
ADS5545
12 bit
ADS5527
-
ADS5525
APPLICATIONS
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Wireless Communications Infrastructure
Software Defined Radio
Power Amplifier Linearization
802.16d/e
Test and Measurement Instrumentation
High Definition Video
Medical Imaging
Radar Systems
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
ADS5547
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SLWS192A – NOVEMBER 2006 – REVISED MAY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
CLKP
DRGND
DRVDD
AGND
AVDD
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
CLKOUTP
CLOCKGEN
CLKM
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
Digital
Encoder
and
Serializer
INP
14-Bit
ADC
SHA
INM
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
VCM
Control
Interface
Reference
D12_D13_P
D12_D13_M
OVR
MODE
OE
DFS
RESET
SEN
SDATA
SCLK
IREF
ADS5547
LVDS MODE
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
ADS5547
QFN-48 (2)
(1)
(2)
2
PACKAGE
DESIGNATOR
RGZ
SPECIFIED
TEMPERATURE
RANGE
–40°C to 85°C
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA,
QUANTITY
ADS5547IRGZT
Tape and Reel,
250
ADS5547IRGZR
Tape and Reel,
2500
AZ5547
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 25.41°C/W (0 LFM air flow),
θJC = 16.5°C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in x 3 in (7.62 cm x 7.62
cm) PCB.
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SLWS192A – NOVEMBER 2006 – REVISED MAY 2007
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
Supply voltage range, AVDD
–0.3 V to 3.9
V
Supply voltage range, DRVDD
–0.3 V to 3.9
V
Voltage between AGND and DRGND
-0.3 to 0.3
V
Voltage between AVDD to DRVDD
-0.3 to 3.3
V
Voltage applied to VCM pin (in external reference mode)
-0.3 to 1.8
V
–0.3 V to minimum (3.6, AVDD + 0.3 V)
V
Voltage applied to analog input pins, INP and INM
Voltage applied to input clock pins, CLKP and CLKM
TA
Operating free-air temperature range
TJ
Operating junction temperature range
Tstg
Storage temperature range
(1)
-0.3 V to AVDD + 0.3 V
V
–40 to 85
°C
125
°C
–65 to 150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
Analog supply voltage, AVDD
3
3.3
3.6
V
Digital supply voltage, DRVDD
3
3.3
3.6
V
SUPPLIES
ANALOG INPUTS
Differential input voltage range
2
VPP
1.5 ±0.1
Input common-mode voltage
Voltage applied on VCM in external reference mode
1.45
1.5
V
1.55
V
CLOCK INPUT
Input clock sample rate
(1)
MSPS
DEFAULT SPEED mode
50
210
1
60
LOW SPEED mode
MSPS
Input clock amplitude differential (V(CLKP) - V(CLKM))
Sine wave, ac-coupled
0.4
1.5
VPP
LVPECL, ac-coupled
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
3.3
V
Input clock duty cycle (See Figure 30)
35%
50%
65%
DIGITAL OUTPUTS
CL
Maximum external load capacitance from each output pin to DRGND (LVDS and CMOS modes)
Without internal termination (default after
reset)
With 100 Ω internal termination
RL
(2)
Differential load resistance between the LVDS output pairs (LVDS mode)
Operating free-air temperature
(1)
(2)
–40
5
pF
10
pF
100
Ω
85
°C
See the section on Low Sampling Frequency Operation for more information.
See the section on LVDS Buffer Internal termination for more information.
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ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 210 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, 0 db gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
14
bits
Differential input voltage range
2
VPP
Differential input capacitance
7
pF
ANALOG INPUT
Analog input bandwidth
800
MHz
Analog input common mode current
(per input pin)
342
µA
V
REFERENCE VOLTAGES
V(REFB)
Internal reference bottom voltage
Internal reference mode
0.5
V(REFT)
Internal reference top voltage
Internal reference mode
2.5
∆V(REF)
Internal reference error
V(REFT) - V(REFB)
VCM
Common mode output voltage
Internal reference mode
1.5
V
VCM output current capability
Internal reference mode
±4
mA
-60
± 25
V
60
mV
DC ACCURACY
No Missing Codes
DNL
Differential non-linearity
INL
Integral non-linearity
Assured
Offset error
-0.95
0.5
2.5
LSB
-5
3.5
5
LSB
-10
5
10
mV
Offset temperature coefficient
Gain error due to internal reference
error alone
0.002
(∆V(REF) / 2.0V) %
Gain error excluding internal reference
error (1)
Gain temperature coefficient
PSRR
DC Power supply rejection ratio
ppm/°C
-3
±1
3
%FS
-2
± 0.5
2
%FS
0.01
∆%/°C
0.6
mV/V
POWER SUPPLY
I(AVDD)
I(DRVDD)
ICC
(1)
4
Analog supply current
Digital supply current
306
mA
LVDS mode, IO = 3.5 mA,
RL = 100 Ω, CL = 5 pF
66
mA
CMOS mode, FIN = 2.5 MHz,
CL = 5 pF
47
mA
mA
Total supply current
LVDS mode
372
Total power dissipation
LVDS mode
1.23
1.375
Standby power
In STANDBY mode with clock stopped
100
150
mW
Clock stop power
With input clock stopped
100
150
mW
Gain error is specified from design and characterization; it is not tested in production.
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SLWS192A – NOVEMBER 2006 – REVISED MAY 2007
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 210 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, 0 db gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC CHARACTERISTICS
FIN = 20 MHz
73.6
FIN = 70 MHz
71
FIN = 100 MHz
72.9
FIN = 170 MHz
SNR
Signal to noise ratio
FIN = 230 MHz
FIN = 300 MHz
FIN = 400 MHz
RMS output noise
71.7
0 dB gain, 2 VPP FS (1)
71
3 dB gain, 1.4 VPP FS
69.1
0 dB gain, 2 VPP FS
3 dB gain, 1.4 VPP FS
68.6
0 dB gain, 2 VPP FS
68.5
3 dB gain, 1.4 VPP FS
67.7
Inputs tied to common-mode
1.18
76
FIN = 100 MHz
FIN = 300 MHz
FIN = 400 MHz
79
0 dB gain, 2 VPP FS
75
3 dB gain, 1.4 VPP FS
78
0 dB gain, 2 VPP FS
74
3 dB gain, 1.4 VPP FS
76
0 dB gain, 2 VPP FS
68
3 dB gain, 1.4 VPP FS
70
FIN = 20 MHz
70
FIN = 100 MHz
Signal to noise and distortion ratio
FIN = 300 MHz
FIN = 400 MHz
70.7
0 dB gain, 2 VPP FS
69
3 dB gain, 1.4 VPP FS
68.7
0 dB gain, 2 VPP FS
67.8
3 dB gain, 1.4 VPP FS
67.6
0 dB gain, 2 VPP FS
63.5
3 dB gain, 1.4 VPP FS
64.3
FIN = 20 MHz
76
FIN = 100 MHz
Second harmonic
FIN = 300 MHz
FIN = 400 MHz
(1)
90
90
FIN = 170 MHz
HD2
dBFS
92
FIN = 70 MHz
FIN = 230 MHz
72.6
71.1
FIN = 170 MHz
SINAD
dBc
73
FIN = 70 MHz
FIN = 230 MHz
85
78
FIN = 170 MHz
FIN = 230 MHz
LSB
87
FIN = 70 MHz
Spurious free dynamic range
dBFS
70
FIN = 20 MHz
SFDR
73.3
88
0 dB gain, 2 VPP FS
86
3 dB gain, 1.4 VPP FS
88
0 dB gain, 2 VPP FS
78
3 dB gain, 1.4 VPP FS
80
0 dB gain, 2 VPP FS
69
3 dB gain, 1.4 VPP FS
71
dBc
FS = Full scale range
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ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 210 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, 0 db gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
FIN = 20 MHz
76
FIN = 100 MHz
FIN = 230 MHz
FIN = 300 MHz
FIN = 400 MHz
Worst harmonic (other than HD2, HD3)
Total harmonic distortion
79
75
3 dB gain, 1.4 VPP FS
78
0 dB gain, 2 VPP FS
74
3 dB gain, 1.4 VPP FS
76
0 dB gain, 2 VPP FS
68
3 dB gain, 1.4 VPP FS
70
FIN = 20 MHz
95
FIN = 70 MHz
92
FIN = 100 MHz
92
FIN = 170 MHz
90
FIN = 230 MHz
90
FIN = 300 MHz
88
FIN = 400 MHz
87
FIN = 20 MHz
83
74
IMD
PSRR
6
Effective number of bits
77
FIN = 170 MHz
77
FIN = 230 MHz
74
FIN = 300 MHz
72
Two-tone intermodulation distortion
FIN = 70 MHz
FIN1 = 50.03 MHz, FIN2 = 46.03 MHz,
-7 dBFS each tone
FIN1 = 190.1 MHz, FIN2 = 185.02 MHz,
-7 dBFS each tone
AC power supply rejection ratio
30 MHz, 200 mVPP signal on 3.3-V supply
Voltage overload recovery time
Recovery to 1% (of final value) for 6-dB overload
with sine-wave input at Nyquist frequency
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dBc
dBc
82
FIN = 100 MHz
FIN = 400 MHz
ENOB
85
0 dB gain, 2 VPP FS
FIN = 70 MHz
THD
UNIT
78
FIN = 170 MHz
Third harmonic
MAX
87
FIN = 70 MHz
HD3
TYP
dBc
65
11.3
11.8
bits
91.1
dBFS
86.5
35
dBc
1
Clock
cycles
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SLWS192A – NOVEMBER 2006 – REVISED MAY 2007
DIGITAL CHARACTERISTICS
(1)
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
33
µA
Low-level input current
–33
µA
4
pF
High-level output voltage
3.3
V
Low-level output voltage
0
V
2
pF
1375
mV
Input capacitance
DIGITAL OUTPUTS – CMOS MODE
Output capacitance
Output capacitance inside the device, from each output to
ground
DIGITAL OUTPUTS – LVDS MODE
High-level output voltage
Low-level output voltage
1025
Output differential voltage, |VOD|
225
VOS Output offset voltage, single-ended
Common-mode voltage of OUTP and OUTM
Output capacitance
Output capacitance inside the device, from either output to
ground
(1)
(2)
350
mV
425
mV
1200
mV
2
pF
All LVDS and CMOS specifications are characterized, but not tested at production.
IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair.
TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA,
RL = 100 Ω (3), no internal termination, unless otherwise noted.
For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data
sheet.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ta
Aperture delay
1.2
ns
tj
Aperture jitter
150
fs rms
Wake-up time
Time to valid data after coming out of
STANDBY mode
100
Time to valid data after stopping and
restarting the input clock
100
µs
14
clock
cycles
1.0
1.5
ns
0.35
0.8
ns
Latency
DDR LVDS MODE (4)
tsu
th
(1)
(2)
(3)
(4)
(5)
(6)
Data setup time (5)
Data valid
(6)
Data hold time (5)
Zero-cross of CLKOUTP to data becoming
invalid (6)
to zero-cross of CLKOUTP
Timing parameters are specified by design and characterization and not tested in production.
CL is the effective external single-ended load capacitance between each output pin and ground.
IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.
Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load.
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear
as reduced timing margin.
Data valid refers to logic high of +50 mV and logic low of –50 mV.
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data
sheet.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.7
4.4
5.1
45%
50%
55%
UNIT
Clock propagation delay (7)
Input clock rising edge zero-cross to
output clock rising edge zero-cross
LVDS bit clock duty cycle
Duty cycle of differential clock,
(CLKOUTP-CLKOUTM)
80 ≤ Fs ≤ 210 MSPS
tr ,
tf
Data rise time,
Data fall time
Rise time measured from –50 mV to 50
mV
Fall time measured from 50 mV to –50 mV
1 ≤ Fs ≤ 210 MSPS
50
100
200
ps
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from –50 mV to 50
mV
Fall time measured from 50 mV to –50 mV
1 ≤ Fs ≤ 210 MSPS
50
100
200
ps
Output clock jitter
Cycle-to-cycle jitter
Output enable (OE) to valid data
delay
Time to valid data after OE becomes
active
tPDI
tOE
120
ns
ps pp
1
µs
PARALLEL CMOS MODE
Data valid (8) to 50% of CLKOUT rising
edge
1.8
2.6
50% of CLKOUT rising edge to data
becoming invalid (10)
0.4
0.8
Clock propagation delay (11)
Input clock rising edge zero-cross to 50%
of CLKOUT rising edge
2.6
3.4
Output clock duty cycle
Duty cycle of output clock (CLKOUT)
80 ≤ Fs ≤ 210 MSPS
Data rise time,
Data fall time
Rise time measured from 20% to 80% of
DRVDD
Fall time measured from 80% to 20% of
DRVDD
1 ≤ Fs ≤ 210 MSPS
0.8
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from 20% to 80% of
DRVDD
Fall time measured from 80% to 20% of
DRVDD
1 ≤ Fs ≤ 210 MSPS
0.4
tOE
Output enable (OE) to valid data
delay
Time to valid data after OE becomes
active
tsu
Data setup time
th
Data hold time
tPDI
tr ,
tf
(5)
(9)
(7)
ns
ns
4.2
ns
1.5
2.0
ns
0.8
1.2
ns
50
ns
45%
To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay (tD) to get the desired setup and hold
times. Use either of these equations to calculate tD:
Desired setup time = tD - (tPDI - tsu )
Desired hold time = (tPDI + th ) - tD
(8) Data valid refers to logic high of 2 V and logic low of 0.8 V
(9) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear
as reduced timing margin.
(10) Data valid refers to logic high of 2 V and logic low of 0.8 V
(11) To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay (tD) to get the desired setup and hold
times. Use either of these equations to calculate tD:
Desired setup time = tD - (tPDI - tsu )
Desired hold time = (tPDI + th ) - tD
8
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N+4
N+3
N+2
N+1
Sample
N
N+17
N+16
N+15
N+14
Input
Signal
ta
Input
Clock
CLKP
CLKM
CLKOUTM
CLKOUTP
tsu
Output Data
DXP, DXM
E
O
E – Even Bits D0,D2,D4,D6,D8,D10,D12
O – Odd Bits D1,D3,D5,D7,D9,D11,D13
E
O
N–14
E
O
N–13
E
O
N–12
E
tPDI
th
14 Clock Cycles
DDR
LVDS
O
N–11
E
N–10
O
E
O
E
O
N
N–1
E
E
O
O
N+2
N+1
tPDI
CLKOUT
tsu
Parallel
CMOS
14 Clock Cycles
Output Data
D0–D13
N–14
N–13
N–12
N–11
th
N–10
N–1
N
N+1
N+2
Figure 1. Latency
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CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUTP
CLKOUTM
tsu
th
tsu
Output
Data Pair
(1)
(2)
Dn
Dn_Dn+1_P,
Dn_Dn+1_M
th
Dn
(1)
Dn+1
– Bits D0, D2, D4, D6, D8, D10, D12
Dn+1 – Bits D1, D3, D5, D7, D9, D11, D13
Figure 2. LVDS Mode Timing
CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
th
tsu
Output
Data
Dn
Dn
(1)
(1)
Dn – Bits D0–D13
Figure 3. CMOS Mode Timing
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DEVICE PROGRAMMING MODES
ADS5547 offers flexibility with several programmable features that are easily configured.
The device can be configured independently using either parallel interface control or serial interface
programming.
In addition, the device supports a third configuration mode, where both the parallel interface and the serial
control registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a
priority table (Table 2). If this additional level of flexibility is not required, the user can select either the serial
interface programming or the parallel interface control.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using parallel interface, keep RESET tied to high (DRVDD). Pins DFS, MODE, SEN,
SCLK, and SDATA are used to directly control certain modes of the ADC. The device is configured by
connecting the parallel pins to the correct voltage levels (as described in Table 3 to Table 7). There is no need
to apply reset.
In this mode, SEN, SCLK, and SDATA function as parallel interface control pins. Frequently used functions are
controlled in this mode—standby, selection between LVDS/CMOS output format, internal/external reference,
two's complement/straight binary output format, and position of the output clock edge.
Table 1 has a description of the modes controlled by the four parallel pins.
Table 1. Parallel Pin Definition
PIN
DFS
MODE
CONTROL MODES
DATA FORMAT and the LVDS/CMOS output interface
Internal or external reference
SEN
CLKOUT edge programmability
SCLK
LOW SPEED mode control for low sampling frequencies (< 50 MSPS)
SDATA
STANDBY mode – Global (ADC, internal references and output buffers are powered down)
USING SERIAL INTERFACE PROGRAMMING ONLY
To program using the serial interface, the internal registers must first be reset to their default values, and the
RESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are
used to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESET
pin, or by a high setting on the bit (D1 in register 0x6C). The serial interface section describes the
register programming and register reset in more detail.
Since the parallel pins DFS and MODE are not used in this mode, they must be tied to ground.
USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (DFS, MODE) can
also be used to configure the device.
The serial registers must first be reset to their default values and the RESET pin must be kept low. In this mode,
SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.
The registers are reset either by applying a pulse on RESET pin or by a high setting on the bit (D1 in
register 0x6C). The serial interface section describes the register programming and register reset in more detail.
The parallel interface control pins DFS and MODE are used and their function is determined by the appropriate
voltage levels as described in Table 6 and Table 7. The voltage levels are derived by using a resistor string as
illustrated in Figure 4. Since some functions are controlled using both the parallel pins and serial registers, the
priority between the two is determined by a priority table (Table 2).
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Table 2. Priority Between Parallel Pins and Serial Registers
PIN
MODE
FUNCTIONS SUPPORTED
PRIORITY
Internal/External reference
When using the serial interface, bit (register 0x6D, bit D4) controls this mode, ONLY
if the MODE pin is tied low.
DATA FORMAT
When using the serial interface, bit (register 0x63, bit D3) controls this mode, ONLY if
the DFS pin is tied low.
LVDS/CMOS
When using the serial interface, bit (register 0x6C, bits D3-D4) controls LVDS/CMOS
selection independent of the state of DFS pin
DFS
AVDD
(2/3) AVDD
R
(2/3) AVDD
GND
R
AVDD
(1/3) AVDD
(1/3) AVDD
R
To Parallel Pin
Figure 4. Simple Scheme to Configure Parallel Pins
12
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DESCRIPTION OF PARALLEL PINS
Table 3. SCLK Control Pin
SCLK (Pin 29)
DESCRIPTION
0
LOW SPEED mode Disabled - Use for sampling frequencies above 50 MSPS.
DRVDD
LOW SPEED mode Enabled - Use for sampling frequencies below 50 MSPS.
Table 4. SDATA Control Pin
SDATA (Pin 28)
0
DRVDD
DESCRIPTION
Normal operation (Default)
STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down.
Table 5. SEN Control Pin
SEN (Pin 27)
0
(1);
LVDS mode: CLKOUT edge aligned with data transition
(1/3)DRVDD
CMOS mode: CLKOUT edge later by (2/12)Ts ; LVDS mode: CLKOUT edge aligned with data transition
(2/3)DRVDD
CMOS mode: CLKOUT edge later by (1/12)Ts ; LVDS mode: CLKOUT edge earlier by (1/12)Ts
DRVDD
(1)
DESCRIPTION
CMOS mode: CLKOUT edge later by (3/12)Ts
Default CLKOUT position
Ts = 1/Sampling Frequency
Table 6. DFS Control Pin
DFS (Pin 6)
0
DESCRIPTION
2's complement data and DDR LVDS output (Default)
(1/3)DRVDD
2's complement data and parallel CMOS output
(2/3)DRVDD
Offset binary data and parallel CMOS output
DRVDD
Offset binary data and DDR LVDS output
Table 7. MODE Control Pin
MODE (Pin 23)
DESCRIPTION
0
Internal reference
(1/3)AVDD
External reference
(2/3)AVDD
External reference
AVDD
Internal reference
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device
power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET
(of width greater than 10 ns).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in
multiples of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits form the register data. The interface can work
with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty
cycle.
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REGISTER INITIALIZATION
After power-up, the internal registers must be reset to their default values. This is done in one of two ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns)
as shown in Figure 5.
OR
2. By applying software reset. Using the serial interface, set the bit (D1 in register 0x6C) to high.
This initializes the internal registers to their default values and then self-resets the bit to low. In
this case the RESET pin is kept low.
Register Address
SDATA
A7
A6
A5
A4
A3
A2
Register Data
A1
A0
D7
t(SCLK)
D6
D5
D4
D3
D2
D1
D0
t(DH)
t(DSU)
SCLK
t(SLOADH)
t(SLOADS)
SEN
RESET
Figure 5. Serial Interface Timing Diagram
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
MIN
TYP
UNIT
20
MHz
fSCLK
SCLK frequency
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
14
> DC
MAX
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RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t1
Power-on delay
Delay from power-up of AVDD and DRVDD to RESET pulse active
MIN
t2
Reset pulse width
t3
tPO
TYP
MAX
UNIT
5
ms
Pulse width of active RESET signal
10
ns
Register write delay
Delay from RESET disable to SEN active
25
ns
Power-up time
Delay from power-up of AVDD and DRVDD to output stable
6.5
ms
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 6. Reset Timing Diagram
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SERIAL REGISTER MAP
Table 8 gives a summary of all the modes that can be programmed through the serial interface.
Table 8. Summary of Functions Supported by Serial Interface (1) (2)
REGISTER
ADDRESS
IN HEX
A7 - A0
REGISTER FUNCTIONS
D7
65
D5
D4
OUTPUT DATA
POSITION
PROGRAMMABILITY
62
63
D6
D3
ENABLE LOW
SAMPLING
FREQUENCY
OPERATION
GLOBAL
POWER
DOWN
DATA FORMAT 2's COMP or
STRAIGHT
BINARY
GAIN PROGRAMMING - 1 dB to 6 dB
CUSTOM PATTERN (D7 TO D0)
6A
CUSTOM PATTERN (D13 TO D8)
6B
INPUT CLOCK BUFFER GAIN PROGRAMMABILITY
OUTPUT DATA INTERFACE
- DDR LVDS or PARALLEL CMOS
6C
6D
POWER SCALING
7E
INTERNAL TERMINATION – DATA
OUTPUTS
7F
D0
– ALL 0S, ALL 1s,
TOGGLE, RAMP, CUSTOM PATTERN
69
16
D1
OUTPUT CLOCK POSITION PROGRAMMABILITY
68
(1)
(2)
D2
SOFTWARE
RESET
INTERNAL or
EXTERNAL
REFERENCE
INTERNAL TERMINATION – OUTPUT CLOCK
LVDS CURRENT
DOUBLE
The unused bits in each register (shown by blank cells in above table) must be programmed as ‘0’.
Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
Each register function is explained in detail below.
Table 9. Serial Register A
A7 - A0 (hex)
62
D7
D6
D5
OUTPUT DATA
POSITION
PROGRAMMABILITY
D4
D3
D2
D1
D0
OUTPUT CLOCK POSITION PROGRAMMABILITY
D4 - D0
Output Clock Position Programmability
00001
Default CLKOUT position after reset. Setup/hold timings with this clock
position are specified in the timing characteristics table.
XX011
CMOS – Rising edge later by (1/12) Ts
LVDS – Rising edge earlier by (1/12) Ts
XX101
CMOS – Rising edge later by (3/12) Ts
LVDS – Rising edge aligned with data transition
XX111
CMOS – Rising edge later by (2/12) Ts
LVDS – Rising edge aligned with data transition
01XX1
CMOS – Rising edge later by (1/12) Ts
LVDS – Rising edge earlier by (1/12) Ts
10XX1
CMOS – Rising edge later by (3/12) Ts
LVDS – Rising edge aligned with data transition
11XX1
CMOS – Rising edge later by (2/12) Ts
LVDS – Rising edge aligned with data transition
D6 – D5
Output Switching Noise and Data Position
Programmability (in CMOS mode ONLY) (Only in CMOS mode)
00
Data Position 1 - Default output data position after reset. Setup/hold
timings with this data position are specified in the timing
characteristics table.
01
Data Position 2 - Setup time increases by (2/36) Ts
10
Data Position 3 - Setup time increases by (5/36) Ts
11
Data Position 4 - Setup time decreases by (6/36) Ts
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Table 10. Serial Register B
A7 - A0 (hex)
63
D7
D6
D5
GLOBAL
POWER
DOWN
D4
D3
ENABLE LOW
SAMPLING
FREQUENCY
OPERATION
DATA
FORMAT
2's COMP or
STRAIGHT
BINARY
D2
D3
Output Data Format
0
2's complement
1
Straight binary
D4
Low Sampling Frequency Operation
0
Default SPEED mode for 50 < Fs ≤ 190 MSPS
1
Low SPEED mode 1≤ Fs ≤ 50 MSPS
D7
Global Power Down
0
Normal operation
1
Global power down (includes ADC, internal references and output buffers)
D1
D0
Table 11. Serial Register C
A7 - A0 (hex)
65
D7
D6
D5
D4
D3
D2
— ALL 0S, ALL 1s,
TOGGLE, RAMP, CUSTOM PATTERN
D7 - D5
Outputs selected test pattern on data lines
000
Normal operation
001
All 0s
010
All 1s
011
Toggle pattern – alternate 1s and 0s on each data output and across
data outputs
100
Ramp pattern – Output data ramps from 0x0000 to 0x3FFF by one
code every clock cycle
101
Custom pattern – Outputs the custom pattern in CUSTOM PATTERN
registers A and B
111
Unused
18
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D0
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Table 12. Serial Register D
A7 - A0 (hex)
D7
D6
D5
D4
D3
68
D2
D1
D0
GAIN PROGRAMMING - 1 dB to 6 dB
D3 - D0
Gain programmability
1000
0 dB gain, default after reset
1001
1 dB
1010
2 dB
1011
3 dB
1100
4 dB
1101
5 dB
1110
6 dB
Table 13. Serial Register E
A7 - A0 (hex)
D7
D6
D5
69
D4
D3
D2
D1
D0
CUSTOM PATTERN (D7 TO D0)
6A
CUSTOM PATTERN (D13 TO D8)
Reg 69
D7 – D0
Program bits D7 to D0 of custom pattern
Reg 6A
D5 – D0
Program bits D13 to D8 of custom pattern
Table 14. Serial Register F
A7 - A0 (hex)
D7
D6
D5
6B
D4
D3
D2
D1
D0
INPUT CLOCK BUFFER GAIN PROGRAMMABILITY
D5 - D0
Clock Buffer Gain
110010
Gain 4, maximum gain
101010
Gain 3
100110
Gain 2
100000
Gain1, default after reset
100011
Gain 0 minimum gain
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Table 15. Serial Register G
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
OUTPUT DATA
INTERFACE - DDR LVDS OR
PARALLEL CMOS
6C
D1
Software resets the ADC
1
Resets all registers to default values
D4 - D3
Output Interface
00
DDR LVDS outputs, default after reset
01
DDR LVDS outputs
11
Parallel CMOS outputs
D1
D0
SOFTWARE
RESET
Table 16. Serial Register H
A7 - A0
6D
D7
D6
D5
POWER SCALING
D4
D3
D2
D1
D0
D1
D0
INTERNAL or
EXTERNAL REFERENCE
D4
Reference
0
Internal reference
1
External reference mode, force voltage on Vcm to set reference.
D7 - D5
Power Scaling Modes
001
Use for Fs > 150 MSPS, default after reset
011
Power Mode 1, use for 105 < Fs ≤ 150 MSPS
101
Power Mode 2, use for 50 < Fs ≤ 105
111
Power Mode 3, use for Fs ≤ 50 MSPS
Table 17. Serial Register I
A7 - A0
7E
D7
D6
D5
INTERNAL TERMINATION –
DATA OUTPUTS
D4
D3
INTERNAL
TERMINATION – OUTPUT CLOCK
D1 - D0
LVDS Buffer Current Programmability
00
3.5 mA, default
01
2.5 mA
10
4.5 mA
11
1.75 mA
20
D2
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D4 - D2
LVDS Internal Termination for Output
Clock Pin (CLKOUT)
000
No internal termination
001
325
010
200
011
125
100
170
101
120
110
100
111
75
D7 - D5
LVDS Internal Termination for Output
Data Pins
000
No internal termination
001
325
010
200
011
125
100
170
101
120
110
100
111
75
Table 18. Serial Register J
A7 - A0
7F
D7
D6
D5
D4
D3
D2
D1
D0
LVDS
CURRENT DOUBLE
D7 - D6
LVDS Buffer Current Double
00
Value specified by
01
2x data, 2x clockout currents
10
1x data, 2x clockout currents
11
2x data, 4x clockout currents
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PIN CONFIGURATION (LVDS MODE)
37 D2_D3_M
38 D2_D3_P
39 D4_D5_M
40 D4_D5_P
41 D6_D7_M
42 D6_D7_P
43 D8_D9_M
44 D8_D9_P
45 D10_D11_M
46 D10_D11_P
47 D12_D13_M
48 D12_D13_P
RGZ PACKAGE
(TOP VIEW)
DRGND 1
36 DRGND
Thermal Pad
DRVDD 2
35 DRVDD
OVR 3
34 D0_D1_P
CLKOUTM 4
33 D0_D1_M
CLKOUTP 5
32 NC
DFS 6
31 NC
OE 7
30 RESET
AVDD 8
29 SCLK
AGND 9
28 SDATA
AVDD 24
MODE 23
AVDD 22
IREF 21
AVDD 20
AGND 19
AVDD 18
25 AGND
AGND 17
AGND 12
INM 16
26 AVDD
INP 15
CLKM 11
AGND 14
27 SEN
VCM 13
CLKP 10
Figure 7. LVDS Mode Pinout
PIN ASSIGNMENTS – LVDS Mode
PIN NAME
DESCRIPTION
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
AVDD
Analog power supply
I
8, 18, 20,
22, 24, 26
6
AGND
Analog ground
I
9, 12, 14,
17, 19, 25
6
CLKP, CLKM
Differential clock input
I
10, 11
2
INP, INM
Differential analog input
I
15, 16
2
VCM
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets
the internal references.
I/O
13
1
IREF
Current-set resistor, 56.2-kΩ resistor to ground.
I
21
1
RESET
Serial interface RESET input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using
the software reset option. See the SERIAL INTERFACE section.
In parallel interface mode, the user has to tie the RESET pin permanently HIGH.
(SDATA and SEN are used as parallel pin controls in this mode)
The pin has an internal 100-kΩ pull-down resistor.
I
30
1
22
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PIN CONFIGURATION (LVDS MODE) (continued)
PIN ASSIGNMENTS – LVDS Mode (continued)
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
I
29
1
I
28
1
SEN
This pin functions as serial interface enable input when RESET is low. It functions
as CLKOUT edge programmability when RESET is tied high. See Table 5 for
detailed information.
The pin has an internal 100-kΩ pull-up resistor to DRVDD.
I
27
1
OE
Output buffer enable input, active high. The pin has an internal 100-kΩ pull-up
resistor to DRVDD.
I
7
1
DFS
Data Format Select input. This pin sets the DATA FORMAT (Twos complement or
Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed
information.
I
6
1
MODE
Mode select input. This pin selects the Internal or External reference mode. See
Table 7 for detailed information.
I
23
1
CLKOUTP
Differential output clock, true
O
5
1
CLKOUTM
Differential output clock, complement
O
4
1
D0_D1_P
Differential output data D0 and D1 multiplexed, true
O
34
1
D0_D1_M
Differential output data D0 and D1 multiplexed, complement.
O
33
1
D2_D3_P
Differential output data D2 and D3 multiplexed, true
O
38
1
D2_D3_M
Differential output data D2 and D3 multiplexed, complement
O
37
1
D4_D5_P
Differential output data D4 and D5 multiplexed, true
O
40
1
D4_D5_M
Differential output data D4 and D5 multiplexed, complement
O
39
1
D6_D7_P
Differential output data D6 and D7 multiplexed, true
O
42
1
D6_D7_M
Differential output data D6 and D7 multiplexed, complement
O
41
1
D8_D9_P
Differential output data D8 and D9 multiplexed, true
O
44
1
D8_D9_M
Differential output data D8 and D9 multiplexed, complement
O
43
1
D10_D11_P
Differential output data D10 and D11 multiplexed, true
O
46
1
D10_D11_M
Differential output data D10 and D11 multiplexed, complement
O
45
1
D12_D13_P
Differential output data D12 and D13 multiplexed, true
O
48
1
D12_D13_M
Differential output data D12 and D13 multiplexed, complement
O
47
1
OVR
Out-of-range indicator, CMOS level signal
O
3
1
DRVDD
Digital and output buffer supply
I
2, 35
2
DRGND
Digital and output buffer ground
I
1, 36
2
NC
Do not connect
31, 32
2
PAD
Connect the pad to the ground plane. See Board Design Considerations in
application information section.
0
1
PIN NAME
SCLK
DESCRIPTION
This pin functions as serial interface clock input when RESET is low.
It functions as LOW SPEED control pin when RESET is tied high. Tie SCLK to
LOW for Fs > 50 MSPS and SCLK to HIGH for Fs ≤ 50 MSPS. See Table 3.
The pin has an internal 100-kΩ pull-down resistor.
This pin functions as serial interface data input when RESET is low. It functions
as STANDBY control pin when RESET is tied high.
SDATA
See Table 4 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
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PIN CONFIGURATION (CMOS MODE)
37 D2
38 D3
39 D4
40 D5
41 D6
42 D7
43 D8
44 D9
45 D10
46 D11
47 D12
48 D13
RGZ PACKAGE
(TOP VIEW)
DRGND 1
36 DRGND
DRVDD 2
35 DRVDD
Thermal Pad
OVR 3
34 D1
UNUSED 4
33 D0
CLKOUT 5
32 NC
DFS 6
31 NC
OE 7
30 RESET
AVDD 8
29 SCLK
AGND 9
28 SDATA
AVDD 24
MODE 23
AVDD 22
IREF 21
AVDD 20
AGND 19
AVDD 18
25 AGND
AGND 17
AGND 12
INM 16
26 AVDD
INP 15
CLKM 11
AGND 14
27 SEN
VCM 13
CLKP 10
Figure 8. CMOS Mode Pinout
PIN ASSIGNMENTS – CMOS Mode
PIN NAME
DESCRIPTION
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
AVDD
Analog power supply
I
8, 18, 20,
22, 24, 26
6
AGND
Analog ground
I
9, 12, 14, 17,
19, 25
6
CLKP, CLKM Differential clock input
I
10, 11
2
INP, INM
Differential analog input
I
15, 16
2
VCM
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets
the internal references.
I/O
13
1
IREF
Current-set resistor, 56.2-kΩ resistor to ground.
I
21
1
I
30
1
I
29
1
Serial interface RESET input.
RESET
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using
the software reset option. See the SERIAL INTERFACE section.
In parallel interface mode, the user has to tie RESET pin permanently HIGH.
(SDATA and SEN are used as parallel pin controls in this mode).
The pin has an internal 100-kΩ pull-down resistor.
SCLK
24
This pin functions as serial interface clock input when RESET is low.
It functions as LOW SPEED control pin when RESET is tied high. Tie SCLK to
LOW for Fs > 50 MSPS and SCLK to HIGH for Fs ≤ 50 MSPS. See Table 3.
The pin has an internal 100-kΩ pull-down resistor.
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PIN CONFIGURATION (CMOS MODE) (continued)
PIN ASSIGNMENTS – CMOS Mode (continued)
PIN NAME
DESCRIPTION
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
I
28
1
I
27
1
This pin functions as serial interface data input when RESET is low. It functions as
STANDBY control pin when RESET is tied high.
SDATA
See Table 4 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
SEN
This pin functions as serial interface enable input when RESET is low. It functions
as CLKOUT edge programmability when RESET is tied high. See Table 5 for
detailed information.
The pin has an internal 100-kΩ pull-up resistor to DRVDD.
OE
Output buffer enable input, active high. The pin has an internal 100-kΩ pull-up
resistor to DRVDD.
I
7
1
DFS
Data Format Select input. This pin sets the DATA FORMAT (Twos complement or
Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed
information.
I
6
1
MODE
Mode select input. This pin selects the internal or external reference mode. See
Table 7 for detailed information.
I
23
1
CLKOUT
CMOS output clock
O
5
1
D0
CMOS output data D0
O
33
1
D0
CMOS output data D1
O
34
1
D2
CMOS output data D2
O
37
1
D2
CMOS output data D3
O
38
1
D4
CMOS output data D4
O
39
1
D4
CMOS output data D5
O
40
1
D6
CMOS output data D6
O
41
1
D7
CMOS output data D7
O
42
1
D8
CMOS output data D8
O
43
1
D9
CMOS output data D9
O
44
1
D10
CMOS output data D10
O
45
1
D11
CMOS output data D11
O
46
1
D12
CMOS output data D12
O
47
1
D13
CMOS output data D13
O
48
1
OVR
Out-of-range indicator, CMOS level signal
O
3
1
DRVDD
Digital and output buffer supply
I
2, 35
2
DRGND
Digital and output buffer ground
I
1, 36
2
UNUSED
Unused pin in CMOS mode
4
1
NC
Do not connect
31, 32
2
PAD
Connect the pad to the ground plane. See Board Design Considerations in
application information section.
0
1
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TYPICAL CHARACTERISTICS
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 70 MHz INPUT SIGNAL
Figure 9.
Figure 10.
FFT for 100 MHz INPUT SIGNAL
FFT for 170 MHz INPUT SIGNAL
0
0
SFDR = 81.74 dBc,
SNR = 72.46 dBFS,
SINAD = 71.37 dBFS
-40
SFDR = 82.82 dBc,
SNR = 71.6 dBFS,
SINAD = 70.83 dBFS
-20
Amplitude - dB
Amplitude - dB
-20
-60
-80
-100
-120
-40
-60
-80
-100
-120
-140
-140
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
f - Frequency - MHz
60
70
80
90
100
90
100
Figure 12.
FFT for 220 MHz INPUT SIGNAL
FFT for 300 MHz INPUT SIGNAL
0
0
SFDR = 80.98 dBc,
SNR = 70.86 dBFS,
SINAD = 70.16 dBFS
-20
-40
-60
-80
-100
-120
SFDR = 74.68 dBc,
SNR = 69.48 dBFS,
SINAD = 67.47 dBFS
-20
Amplitude - dB
Amplitude - dB
50
f - Frequency - MHz
Figure 11.
-40
-60
-80
-100
-120
-140
-140
0
10
20
30
40
50
60
70
80
90
100
0
10
f - Frequency - MHz
20
30
40
50
60
70
f - Frequency - MHz
Figure 13.
26
40
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
FFT for 400 MHz INPUT SIGNAL
FFT for 600 MHz INPUT SIGNAL
0
0
SFDR = 70.92 dBc,
SNR = 68.19 dBFS,
SINAD = 64.82 dBFS
SFDR = 65.5 dBc,
SNR = 65.29 dBFS,
SINAD = 61 dBFS
-20
-40
Amplitude - dB
Amplitude - dB
-20
-60
-80
-100
-120
-40
-60
-80
-100
-120
-140
-140
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
f - Frequency - MHz
60
70
80
100
90
Figure 15.
Figure 16.
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
fIN1 = 50.03 MHz, -7 dBFS,
fIN2 = 46.03 MHz, -7 dBFS,
SFDR = 88.5 dBc,
2-Tone IMD, 91.1 dBFS
-40
fIN1 = 190.1 MHz, -7 dBFS,
fIN2 = 185.02 MHz, -7 dBFS,
SFDR = 87.1 dBc,
2-Tone IMD, 86.5 dBFS
-20
Amplitude - dB
-20
Amplitude - dB
50
f - Frequency - MHz
0
-60
-80
-100
-120
-40
-60
-80
-100
-120
-140
-140
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
f - Frequency - MHz
40
50
60
70
80
90
100
f - Frequency - MHz
Figure 17.
Figure 18.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
75
90
74
SNR − dBFS
86
82
SFDR - dBc
40
78
74
LVDS Mode
73
72
71
70
69
70
68
66
67
62
66
0
50
100
150
200
250
300
350
400
0
fIN - Input Frequency - MHz
Figure 19.
50
100
150
200
250
300
350
400
fIN − Input Frequency − MHz
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
SNR vs INPUT FREQUENCY
96
DDR LVDS
CMOS Data
Position 4
1 dB
2 dB
3 dB
92
88
SFDR − dBc
SNR − dBFS
75
74
73
72
71
70
69
68
67
66
65
64
63
10
SFDR vs GAIN
CMOS Data
Position 3
CMOS Data
Position 2
CMOS Data
Position 1
20
30
40
50
84
80
6 dB
5 dB 4 dB
76
0 dB
72
68
70 100 130 170 230 300
0
50
fIN − Input Frequency − MHz
100
150
200
250
300
350
400
fIN − Input Frequency − MHz
Figure 21.
Figure 22.
SNR vs GAIN
PERFORMANCE vs AVDD
76
92
75
90
74.5
1 dB
2 dB
3 dB
SFDR - dBc
SNR − dBFS
74
72
70
68
74
FIN = 70 MHz
DRVDD = 3.3 V
73.5
86
SNR
73
84
5 dB
66
4 dB
82
3
6 dB
64
SFDR
88
0
50
100
SNR - dBFS
0 dB
150
200
250
300
350
72.5
3.1
3.2
3.3
3.4
3.5
3.6
AVDD - Supply Voltage - V
400
fIN − Input Frequency − MHz
Figure 23.
Figure 24.
PERFORMANCE vs DRVDD
PERFORMANCE vs TEMPERATURE
75
92
75.0
fIN = 70 MHz
74.5
73.5
86
SNR
73
84
SFDR − dBc
74
SNR − dBFS
fIN = 70 MHz
AVDD = 3.3 V
88
74.5
90
SFDR
88
74.0
86
73.5
84
73.0
SNR
72.5
82
3.0
3.1
3.2
3.3
3.4
3.5
3.6
82
−40
−15
10
50
35
o
TA − Free-Air Temperature − C
DRVDD − Supply Voltage − V
Figure 25.
28
Figure 26.
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85
SNR − dBFS
SFDR
90
SFDR − dBc
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
SNR vs SAMPLING FREQUENCY
ACROSS POWER SCALING MODES
105
73
SNR − dBFS
75.5
95
72
Default
71
Power Mode 1
70
Power Mode 3
69
68
75
SFDR (dBFS)
85
75
73.5
65
73
55
SFDR (dBc)
45
80
100
120
140
160
180
200
72.5
72
25
−60
60
74
SNR (dBFS)
35
Power Mode 2
67
66
40
74.5
SNR − dBFS
fIN = 70 MHz
SFDR − dBc, dBFS
75
74
PERFORMANCE vs INPUT AMPLITUDE
fIN = 70 MHz
−50
71.5
−40
220
−30
−20
−10
0
Input Amplitude − dBFS
FS − Sampling Frequency − MSPS
Figure 27.
Figure 28.
PERFORMANCE vs CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
88
88
76
77
fIN = 10 MHz
73
78
0.3
0.5
0.8
1.1
1.3
1.5
1.8
2.1
2.3
2.5
74
82
SNR
72
80
71
2.8
78
fIN = 70 MHz
Sine Wave Input Clock
75
84
73
72
35
40
Clock Amplitude - VPP
45
50
65
Figure 30.
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
PERFORMANCE IN EXTERNAL REFERENCE MODE
88
40
35
76
75
86
SFDR − dBc
30
25
20
15
10
SFDR
84
74
82
73
SNR
80
8252
8251
8250
8249
8248
8247
8246
8245
8244
8243
5
8242
Occurence − %
60
Input Clock Duty Cycle − %
Figure 29.
0
55
78
1.4
SNR − dBFS
80
SFDR
SNR − dBFS
SNR
82
SFDR − dBc
74
SNR - dBFS
SFDR - dBc
SFDR
84
76
86
75
86
72
71
1.45
1.5
1.55
1.6
Voltage Forced on the CM Pin − V
Output Code
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
POWER DISSIPATION vs
SAMPLING FREQUENCY (DDR LVDS)
COMMON-MODE REJECTION RATIO vs FREQUENCY
-35
1.24
PD − Power Dissipation − W
CMRR − dBc
-40
-45
-50
-55
-60
-65
-70
0
20
40
60
80
LVDS Mode
1.18
1.12
Default
1.06
1.00
0.94
0.88
Power Mode 1
0.82
0.76
0.70
0.64
100
Power Mode 2
Power Mode 3
0
20
40
60
80 100 120 140 160 180 200 220
FS − Sampling Frequency − MSPS
f - Frequency of AC Common-Mode Voltage - MHz
Figure 33.
Figure 34.
DRVDD current vs
SAMPLING FREQUENCY (Parallel CMOS)
DRVDD Current − mA
100
CMOS
10-pF Load Cap
90
80
70
60
50
40
DDR LVDS
CMOS
0-pF Load Cap
30
20
10
0
10
CMOS
5-pF Load Cap
30
50
70
90 110 130 150 170 190 210
f − Frequency − MSPS
Figure 35.
30
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
fS - Sampling Frequency - MSPS
210
200
180
160
140
120
100
80
65
100
200
300
400
500
600
700
fIN - Input Frequency - MHz
62
63
64
65
66
67
68
69
70
71
72
73
SNR - dBFS
Figure 36. SNR Contour in dBFS
fS - Sampling Frequency - MSPS
210
200
180
160
140
120
100
80
65
100
200
300
400
500
600
700
80
85
90
fIN - Input Frequency - MHz
55
60
65
70
75
SFDR - dBc
Figure 37. SFDR Contour in dBc
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APPLICATION INFORMATION
THEORY OF OPERATION
ADS5547 is a low power 14-bit 210 MSPS pipeline ADC in a CMOS process. ADS5547 is based on switched
capacitor technology and runs off a single 3.3-V supply. The conversion process is initiated by a rising edge of
the external input clock. Once the signal is captured by the input sample and hold, the input sample is
sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction
logic block. At every clock edge, the sample propagates through the pipeline resulting in a data latency of 14
clock cycles. The output is available as 14-bit data, in DDR LVDS or CMOS and coded in either straight offset
binary or binary 2’s complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in
Figure 38.
This differential topology results in good ac-performance even for high input frequencies at high sampling rates.
The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V available on VCM
pin 13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM +
0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The maximum swing is determined by the
internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).
Sampling
Switch
Lpkg
6 nH
Sampling
Capacitor
R-C-R Filter
INP
Cbond
2 pF
10 W
50 W
Resr
200 W
1.6 pF
Lpkg
6 nH
Cpar2
1 pF
Ron
15 W
Ron
10 W
Cpar1
0.8 pF
50 W
Ron
15 W
10 W
Csamp
2.4 pF
Csamp
2.4 pF
INM
Cbond
2 pF
Resr
200 W
Sampling
Capacitor
Cpar2
1 pF
Sampling
Switch
Figure 38. Input Stage
The input sampling circuit has a high 3-dB bandwidth that extends up to 800 MHz (measured from the input pins
to the voltage across the sampling capacitors)
Drive Circuit Requirements
The input sampling circuit of the ADS5547 has a high 3-dB analog bandwidth of 800 MHz making it possible to
sample input signals up to very high frequencies. To get best performance, it is recommended to have an
external R-C-R filter across the input pins (Figure 39). This helps to filter the glitches due to the switching of the
sampling capacitors. The R-C-R filter has to be designed to provide adequate filtering (for good performance)
and at the same time ensure sufficient bandwidth over the desired frequency range.
In addition, it is recommended to have a 15-Ω series resistor on each input line to damp out ringing caused by
the package parasitics. At higher input frequencies (> 100 MHz), a lower series resistance around 5 Ω to 10 Ω
should be used. It is also necessary to present low impedance (< 50 Ω) for the common-mode switching
currents. For example, this could be achieved by using two resistors from each input terminated to the
common-mode voltage (Vcm).
Using 10-Ω series resistance and 25 Ω-3.3 pF-25 Ω as the R-C-R filter, high effective bandwidth (700 MHz) can
be achieved, as shown in Figure 40.
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APPLICATION INFORMATION (continued)
In addition to the above ADC requirements, the drive circuit may have to be designed to provide a low insertion
loss over the desired frequency range and matched impedance to the source. For this, the ADC input
impedance has to be taken into account (Figure 41).
Example Drive Circuits
A suitable configuration using RF transformers and including the R-C-R filter is shown in Figure 39. Note the
15-Ω series resistors and the low common-mode impedance (using 33-Ω resistors terminated to VCM).
ADS5547
Zi and TFADC
0.1 mF
WBC1-1TLB
15 W
(Note A)
WBC1-1TLB
INP
100 W
25 W
33 W
0.1 mF
3.3 pF
33 W
25 W
100 W
INM
1:1
15 W
(Note A)
1:1
VCM
A.
Use lower series resistance (≈ 5 Ω to 10 Ω) at high input frequencies (> 100 MHz)
Figure 39. Example Drive Circuit With RF Transformers
2
500
450
400
0
Magnitude − W
Magnitude − dB
1
-1
-2
-3
-4
300
250
200
150
100
-5
-6
350
0
100
200
300
400
500
600
700
800
900
1000
50
0
0
100
f − Frequency − MHz
200
300
400
500
600
700
800
900
1000
f − Frequency − MHz
Figure 40. Analog Input Bandwidth, TFADC (Actual
Silicon Data)
Figure 41. Input Impedance, ZI
Using RF transformers
For optimum performance, the analog inputs have to be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection. The single-ended signal is fed to the primary winding of the
RF transformer. The transformer is terminated on the secondary side. Putting the termination on the secondary
side helps to shield the kickbacks caused by the sampling circuit from the RF transformer’s leakage
inductances. The termination is accomplished by two resistors connected in series, with the center point
connected to the 1.5 V common-mode (VCM pin 13).
At higher input frequencies, the mismatch in the transformer parasitic capacitance (between the windings)
results in degraded even-order harmonic performance. Connecting two identical RF transformers back to back
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APPLICATION INFORMATION (continued)
helps minimize this mismatch and good performance is obtained for high frequency input signals. An additional
termination resistor pair (Figure 39) may be required between the two transformers to improve the balance
between the P and M sides. The center point of this termination must be connected to ground. (Note that the
drive circuit has to be tuned to account for this additional termination, to get the desired S11 and impedance
match).
Using Differential Amplifier Drive Circuits
Figure 42 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to
differential output that can be interface to the ADC analog input pins. In addition to the single-ended to
differential conversion, the amplifier also provides gain (10 dB in Figure 42). RFIL helps to isolate the amplifier
outputs from the switching input of the ADC. Together with CFIL it also forms a low-pass filter that band-limits the
noise (& signal) at the ADC input. As the amplifier output is ac-coupled, the common-mode voltage of the ADC
input pins is set using two 200 Ω resistors connected to VCM.
The amplifier output can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC
input pins can be biased to 1.5V. In this case, use +4 V and -1 V supplies for the THS4509 so that its output
common-mode voltage (1.5V) is at mid-supply.
RF
+VS
500 W
0.1 mF
RS
0.1 mF 10 mF
RFIL
0.1 mF
5W
INP
RG
0.1 mF
RT
CFIL
200 W
CFIL
200 W
CM THS4509
RG
RFIL
INM
RS || RT
0.1 mF
5W
0.1 mF
500 W
VCM
–VS
0.1 mF 10 mF
0.1 mF
RF
Figure 42. Drive Circuit Using the THS4509
See the EVM User Guide (SLWU028) for more information.
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APPLICATION INFORMATION (continued)
Input Common-Mode
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC
sinks a common-mode current in the order of 342 µA (at 210 MSPS). Equation 1 describes the dependency of
the common-mode current and the sampling frequency.
(342 mA) x Fs
210 MSPS
(1)
This equation helps to design the output capability and impedance of the CM driving circuit accordingly.
Reference
ADS5547 has built-in internal references REFP and REFM, requiring no external components. Design schemes
are used to linearize the converter load seen by the references; this and the integration of the requisite
reference capacitors on-chip eliminates the need for external decoupling. The full-scale input range of the
converter can be controlled in the external reference mode as explained below. The internal or external
reference modes can be selected by controlling the MODE pin 23 (see Table 7 for details) or by programming
the serial interface register bit (Table 16).
INTREF
Internal
Reference
VCM
INTREF
EXTREF
REFM
REFP
ADS5547
Figure 43. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.
Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog
input pins.
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APPLICATION INFORMATION (continued)
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on
the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential
input voltage corresponding to full-scale is given by Equation 2.
Full−scale differential input pp + (Voltage forced on VCM) 1.33
(2)
In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. There is no
change in performance compared to internal reference mode.
Low Sampling Frequency Operation
For best performance at high sampling frequencies, ADS5547 uses a clock generator circuit to derive internal
timing for the ADC. The clock generator operates from 210 MSPS down to 50 MSPS in the DEFAULT SPEED
mode. The ADC enters this mode after applying reset (with serial interface configuration) or by tying SCLK pin to
low (with parallel configuration).
For low sampling frequencies (below 50 MSPS), the ADC must be put in the LOW SPEED mode. This mode
can be entered by:
• setting the register bit (Table 10) through the serial interface, OR
• tying the SCLK pin to high (see Table 3) using the parallel configuration.
Clock Input
ADS5547 clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between configurations. The common-mode voltage of the clock inputs is
set to VCM using internal 5-kΩ resistors as shown in Figure 44. This allows the use of transformer-coupled drive
circuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources (Figure 45 and Figure 46)
VCM
VCM
5 kW
5 kW
CLKP
CLKM
ADS5547
Figure 44. Internal Clock Buffer
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APPLICATION INFORMATION (continued)
For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to
common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with
0.1-µF capacitors, as shown in Figure 45.
0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS
Clock Input
0.1 mF
CLKM
ADS5547
Figure 45. Differential Clock Driving Circuit
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground with
a 0.1-µF capacitor, as shown in Figure 46.
0.1 mF
CMOS Clock Input
CLKP
0.1 mF
CLKM
ADS5547
Figure 46. Single-Ended Clock Driving Circuit
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, the use a clock source with very low jitter is recommended. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input. Figure 30 shows the performance variation of the ADC versus clock duty cycle
Clock Buffer Gain
When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is
increased. Therefore, using a large amplitude clock is recommended. In addition, the clock buffer has a
programmable gain option to amplify the input clock. The clock buffer gain can be set by programming the
register bits (Table 14). The clock buffer gain decreases monotonically from Gain 4 to Gain 0
settings.
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APPLICATION INFORMATION (continued)
Programmable Gain
ADS5547 has programmable gain from 0 dB to 6 dB in steps of 1 dB. The corresponding full-scale input range
varies from 2 VPP down to 1 VPP, with 0 dB being the default gain. At high IF, this is especially useful as the
SFDR improvement is significant with marginal degradation in SNR.
The gain can be programmed using the chapter bits (Table 12).
Table 19. Full-scale Range Across Gains
Gain
Corresponding full-scale range, Vpp
0 dB
2.00
1 dB
1.78
2 dB
1.59
3 dB
1.42
4 dB
1.26
5 dB
1.12
6 dB
1.00
Power Down
ADS5547 has three power-down modes – global standby, output buffer disabled, and input clock stopped.
Global Standby
This mode can be initiated by controlling SDATA (pin 28) or by setting the register bit (Table 10)
through the serial interface. In this mode, the A/D converter, reference block and the output buffers are powered
down and the total power dissipation reduces to about 100 mW. The output buffers are in high impedance state.
The wake-up time from the global power down to data becoming valid normal mode is maximum 100 µs.
Output Buffer Disable
The output buffers can be disabled using OE pin 7 in both the LVDS and CMOS modes, reducing the total
power by about 100 mW. With the buffers disabled, the outputs are in high impedance state. The wake-up time
from this mode to data becoming valid in normal mode is maximum 1 µs in LVDS mode and 50 ns in CMOS
mode.
Input Clock Stop
The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation is
about 100 mW and the wake-up time from this mode to data becoming valid in normal mode is maximum
100 µs.
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Power Scaling Modes
ADS5547 has a power scaling mode in which the device can be operated at reduced power levels at lower
sampling frequencies with no difference in performance. (See Figure 27) (1) There are four power scaling modes
for different sampling clock frequency ranges, using the serial interface register bits (Table 16).
Only the AVDD power is scaled, leaving the DRVDD power unchanged.
Table 20. Power Scaling vs Sampling Speed
Sampling Frequency
MSPS
(1)
Power Scaling Mode
Analog Power
(Typical)
Analog Power in Default Mode
> 150
Default
1010 mW at 210 MSPS
1010 mW at 210 MSPS
105 to 150
Power Mode 1
841 mW at 150 MSPS
917 mW at 150 MSPS
50 to 105
Power Mode 2
670 mW at 105 MSPS
830 mW at 105 MSPS
< 50
Power Mode 3
525 mW at 50 MSPS
760 mW at 50 MSPS
The performance in the power scaling modes is from characterization and not tested in production.
Power Supply Sequence
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated inside the device. Externally, they can be driven from separate supplies or from a single supply.
Digital Output Information
ADS5547 provides 14-bit data, an output clock synchronized with the data and an out-of-range indicator that
goes high when the output reaches the full-scale limits. In addition, output enable control (OE pin 7) is provided
to power down the output buffers and put the outputs in high-impedance state.
Output Interface
Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be
selected using the DFS (see Table 6) or the serial interface register bit (Table 15).
DDR LVDS Outputs
In this mode, the 14 data bits and the output clock are available as LVDS (Low Voltage Differential Signal)
levels. Two successive data bits are multiplexed and output on each LVDS differential pair as shown in
Figure 47. So, there are 7 LVDS output pairs for the 14 data bits and 1 LVDS output pair for the output clock.
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Pins
CLKOUTP
Output Clock
CLKOUTM
D0_D1_P
Data Bits D0. D1
D0_D1_M
D2_D3_P
Data Bits D2, D3
D2_D3_M
D4_D5_P
Data Bits D4, D5
D4_D5_M
D6_D7_P
Data Bits D6, D7
D6_D7_M
D8_D9_P
Data Bits D8, D9
D8_D9_M
D10_D11_P
Data Bits D10, D11
D10_D11_M
D12_D13_P
Data Bits D12, D13
D12_D13_M
OVR
Out-of-Range Indicator
ADS5547
Figure 47. DDR LVDS Outputs
Even data bits D0, D2, D4, D6, D8, D10, and D12 are output at the falling edge of CLKOUTP and the odd data
bits D1, D3, D5, D7, D9, D11, and D13 are output at the rising edge of CLKOUTP. Both the rising and falling
edges of CLKOUTP have to be used to capture all the 14 data bits (see Figure 48).
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CLKOUTP
CLKOUTM
D0_D1_P,
D0_D1_M
D0
D1
D0
D1
D2_D3_P,
D2_D3_M
D2
D3
D2
D3
D4_D5_P,
D4_D5_M
D4
D5
D4
D5
D6_D7_P,
D6_D7_M
D6
D7
D6
D7
D8_D9_P,
D8_D9_M
D8
D9
D8
D9
D10_D11_P,
D10_D11_M
D10
D11
D10
D11
D12_D13_P,
D12_D13_M
D12
D13
D12
D13
Sample N
Sample N+1
Figure 48. DDR LVDS Interface
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV
single-ended voltage swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to
2.5 mA, 4.5 mA, and 1.75 mA (register bits , Table 17). In addition, there exists a current double
mode, where this current is doubled for the data and output clock buffers (register bits ,
Table 18).
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistances available are – 325, 200, and 170 Ω (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistances. This results in eight effective terminations from open (no
termination) to 75 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode. Figure 49 shows the eye diagram of one of the LVDS data outputs with a 10-pF load capacitance (from
each pin to ground) and 100-Ω internal termination enabled. The terminations can be programmed using register
bits and (Table 17).
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Figure 49. Eye Diagram of LVDS Data Output With Internal Termination
Parallel CMOS
In this mode, the 14 data outputs and the output clock are available as 3.3-V CMOS voltage levels. Each data
bit and the output clock is available on a separate pin in parallel. By default, the data outputs are valid during the
rising edge of the output clock. The output clock is CLKOUT (pin 5).
CMOS Mode Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin (see Figure 35). The maximum DRVDD current occurs when each output bit toggles between 0 and 1
every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be
determined by the average number of output bits switching, which is a function of the sampling frequency and
the nature of the analog input signal.
Digital current due to CMOS output switching = CL x VDRVDD x (N x FAVG)
where CL = load capacitance, N x FAVG = average number of output bits switching
Figure 35 shows the current with various load capacitances across sampling frequencies at 2MHz analog input
frequency.
Output Switching Noise and Data Position Programmability (in CMOS mode ONLY)
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant
of sampling and degrade the SNR. To minimize this, the device includes programmable options to move the
output data transitions with respect to the output clock. This can be used to position the data transitions at the
optimum place away from the sampling instant and improve the SNR. Figure 21 shows the variation of SNR for
different CMOS output data positions at 190 MSPS.
Note that the optimum output data position varies with the sampling frequency. The data position can be
programmed using the register bits (Table 9).
It is recommended to put series resistors (50 to 100 Ω) on each output line placed very close to the converter
pins. This helps to isolate the outputs from seeing large load capacitances and in turn reduces the amount of
switching noise. For example, the data in Figure 21 was taken with 50 Ω series resistors on each output line.
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Output Clock Position Programmability
In both the LVDS and CMOS modes, the output clock can be moved around its default position. This can be
done using SEN pin 27 (as described in Table 5) or using the serial interface register bits
(Table 9). Using this allows to trade-off the setup and hold times leading to reliable data capture. There also
exists an option to align the output clock edge with the data transition.
Note that programming the output clock position also affects the clock propagation delay times.
Output Data Format
Two output data formats are supported – 2's complement and offset binary. They can be selected using the DFS
(pin 6) or the serial interface register bit (Table 10).
Out-of-range Indicator (OVR)
When the input voltage exceeds the full-scale range of the ADC, OVR (pin 3) goes high, and the output code is
clamped to the appropriate full-scale level for the duration of the overload. For a positive overdrive, the output
code is 0x3FFF in offset binary output format, and 0x1FFF in 2's complement output format. For a negative input
overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2's complement output format.
Figure 50 shows the behavior of OVR during the overload. Note that OVR and the output code react to the
overload after a latency of 14 clock cycles.
Figure 50. OVR During Input Overvoltage
Output Timing
For the best performance at high sampling frequencies, ADS5547 uses a clock generator circuit to derive
internal timing for ADC. This results in optimal setup and hold times of the output data and 50% output clock
duty cycle for sampling frequencies from 80 MSPS to 210 MSPS. See Table 21 for timing information above 80
MSPS.
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Table 21. Timing Characteristics (80 MSPS to 210 MSPS)
Fs, MSPS
tsu DATA SETUP TIME, ns
MIN
TYP
190
1.2
170
1.3
150
th DATA HOLD TIME, ns
MAX
MIN
TYP
1.7
0.4
1.8
0.5
1.6
2.1
130
2.0
80
(1)
tPDI CLOCK PROPAGATION DELAY, ns
MAX
MIN
TYP
MAX
0.9
4.0
4.7
5.4
1.0
3.9
4.6
5.3
0.6
1.1
4.3
5.0
5.7
2.5
0.8
1.3
4.5
5.2
5.9
3.6
4.1
1.6
2.1
4.7
5.7
6.7
190
2.2
3.0
0.5
0.9
2.4
3.2
4.0
170
2.5
3.3
0.8
1.2
1.9
2.7
3.5
150
2.8
3.6
1.2
1.6
1.7
2.5
3.3
130
3.3
4.1
1.7
2.1
1.1
1.9
2.7
80
6.0
7.0
3.7
4.1
10.8
12
13.2
DDR LVDS
PARALLEL CMOS
(1)
Timing parameters are specified by design and characterization and not tested in production.
Below 80 MSPS, the setup and hold times do not scale with the sampling frequency. The output clock duty cycle
also progressively moves away from 50% as the sampling frequency is reduced from 80 MSPS.
See Table 22 for timings at sampling frequencies below 80 MSPS. Figure 51 shows the clock duty cycle across
sampling frequencies in the DDR LVDS and CMOS modes.
Table 22. Timing Characteristics (1 MSPS to 80 MSPS)
Fs, MSPS
tsu DATA SETUP TIME, ns
MIN
TYP
th DATA HOLD TIME, ns
MAX
MIN
TYP
(1)
tPDI CLOCK PROPAGATION DELAY, ns
MAX
MIN
TYP
MAX
DDR LVDS
1 to 80
3.6
1.6
5.7
6
3.7
12
PARALLEL CMOS
1 to 80
Timing parameters are specified by design and characterization and not tested in production.
Output Clock Duty Cycle − %
(1)
100
90
80
70
60
DDR LVDS
50% Duty Cycle
50
40
CMOS
45% Duty Cycle
30
20
10
0
0
20
40
60
80
100 120 140 160 180 210
Sampling Frequency − MHz
Figure 51. Output Clock Duty Cycle (Typical) vs Sampling Frequency
The latency of ADS5547 is 14 clock cycles from the sampling instant (input clock rising edge). In the LVDS
mode, the latency remains constant across sampling frequencies. In the CMOS mode, the latency is 14 clock
cycles above 80 MSPS and 13 clock cycles below 80 MSPS.
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Board Design Considerations
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital and clock sections of
the board are cleanly partitioned. See the EVM User Guide (SLWU028) for details on layout and grounding.
Supply Decoupling
As the ADS5546 already includes internal decoupling, minimal external decoupling can be used without loss in
performance. Note that decoupling capacitors can help to filter external power supply noise, so the optimum
number of capacitors would depend on the actual application. The decoupling capacitors should be placed very
close to the converter supply pins.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching
noise from sensitive analog circuitry. In case only a single 3.3V supply is available, it should be routed first to
AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before
being routed to DRVDD.
Series Resistors on Data Outputs
It is recommended to put series resistors (50 to 100 Ω) on each output line placed very close to the converter
pins. This helps to isolate the outputs from seeing large load capacitances and in turn reduces the amount of
switching noise.
Exposed Thermal Pad
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and
QFN/SON PCB Attachment (SLUA271).
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low
frequency value.
Aperture Delay
The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling
occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width)
to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential
sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate
The maximum sampling rate at which certified operation is given. All parametric testing is performed at this
sampling rate unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the
deviation of any single step from this ideal value, measured in units of LSBs
Integral Nonlinearity (INL)
The INL is the deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit
of that transfer function, measured in units of LSBs.
Gain Error
The gain error is the deviation of the ADC’s actual input full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Offset Error
The offset error is the difference, given in number of LSBs, between the ADC’s actual average idle channel
output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift
The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree
Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter
across the TMIN to TMAX range by the difference TMAX–TMIN.
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DEFINITION OF SPECIFICATIONS (continued)
Signal-to-Noise Ratio
SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc
and the first nine harmonics.
P
SNR + 10Log 10 s
PN
(4)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding dc.
Ps
SINAD + 10Log 10
PN ) PD
(5)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Effective Number of Bits (ENOB)
The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization
noise.
ENOB + SINAD * 1.76
6.02
(6)
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD).
P
THD + 10Log 10 s
PN
(7)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic).
SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral
component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the
fundamental is extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR)
The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is
typically given in units of mV/V.
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DEFINITION OF SPECIFICATIONS (continued)
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If ∆VSUP is the change in
the supply voltage and ∆VOUT is the resultant change in the ADC output code (referred to the input), then
DVOUT
PSRR = 20Log 10
(Expressed in dBc)
DVSUP
(8)
Common Mode Rejection Ratio (CMRR)
CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If ∆Vcm is the
change in the input common-mode voltage and ∆VOUT is the resultant change in the ADC output code (referred
to the input), then
DVOUT
CMRR = 20Log10
(Expressed in dBc)
DVCM
(9)
Voltage Overload Recovery
The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A
6-dBFS sine wave at Nyquist frequency is used as the test stimulus.
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Changes from Original (November 2006) to A Revision ............................................................................................... Page
•
•
•
•
•
•
•
Changed SERIAL REGISTER MAP format ........................................................................................................................
Added Thermal Pad to Figure 7 .........................................................................................................................................
Added Thermal Pad to Figure 8 .........................................................................................................................................
Changed SNR vs INPUT FREQUENCY.............................................................................................................................
Added Using Differential Amplifier Drive Circuits................................................................................................................
Added CMOS Mode Power Dissipation..............................................................................................................................
Added Output Switching Noise and Data Position Programmability (in CMOS mode ONLY) ...........................................
16
22
24
28
34
42
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ADS5547IRGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ5547
Samples
ADS5547IRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ5547
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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