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ADS58J89
SBAS659 – NOVEMBER 2014
ADS58J89 Quad Channel 14-Bit 250/500 MSPS Receiver and Feedback IC
1 Features
3 Description
•
The ADS58J89 is a high-linearity, quad-channel, 14bit, 250/500-MSPS IF (intermediate frequency)
receiver. The four channels contain 500MSPS 14-bit
ADCs followed by signal processing for wireless
infrastructure systems. The channels can be
configured in various modes depending on
bandwidth, resolution and sample time requirements.
The signal processing block contains selectable
modes for decimation filters, SNR Boost filters,
resolution versus time and time-division duplex (TDD)
burst mode. Designed for high antenna count
systems, the 4 channels provides high bandwidth and
linearity to multi-channel receivers in a small footprint.
The device can be dual function as traffic receiver
and power amplifier linearization feedback path in
TDD systems.
1
•
•
•
•
•
4-Ch, 14-Bit 500MSPS With Digital Signal
Processing
Power Amplifier Linearization (Feedback) Modes
– 14-Bits Every Other Sample at 250MSPS
– Programmable Resolution vs Duty Cycle
– Duty Cycle 3:2 (60% 11-Bit, 40% 9-Bit)
– Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit)
– Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit)
Traffic Receiver Modes
– 14-Bit 250MSPS: Decimate by 2 Filter,
High/Low Pass
– 9-Bit SNR-Boost Filter (150-MHz Max
Bandwidth)
– 9-to-14-Bit TDD Burst (200-MHz Max
Bandwidth)
Flexible Input Clock Buffer With Divide by 1/2/4
JESD204B Digital Interface up to 5.0Gbps
– 1 or 2 Lanes per Channel, With Subclass 1
64-Pin VQFN Package (9 × 9 mm)
2 Applications
•
•
•
•
•
Multi-Carrier, Multi-Mode, Multi-Band Cellular
Receivers
– TDD-LTE
– FDD-LTE
– CDMA, WCMDA, CMDA2k
– GSM
RF and Microwave Backhaul
– Point-to-Point Backhaul
– Point-to-Multi-Point Backhaul
Wireless Repeaters
Distributed Antenna Systems (DAS)
Broadband Wireless
Key Specifications:
• Power Dissipation: 875 mW/ch
• Input Bandwidth (3dB): 900 MHz
• Aperture Jitter: 98 fs rms
• Channel Isolation: 85 dB
• Performance at ƒin = 170 MHz at 1.25 Vpp,
–1 dBFS
– SNR: 65.8 dBFS
– SFDR: 85 dBc HD2,3; 95 dBFS non-HD2,3
Device Information(1)
PART NUMBER
PACKAGE
ADS58J89
MAX OUTPUT RATE
VQFN (64)
500 MSPS
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
OVRA
INAP/M
14-bit
ADC
2x Dec
Burst Mode
SNR Boost
INBP/M
14-bit
ADC
2x Dec
Burst Mode
SNR Boost
JESD204B
DA[0,1]P/M
JESD204B
DB[0,1]P/M
OVRB
SYSREFABP/M
Divide by
1, 2, 4
CLKINP/M
SYNCbAB
PLL
x10/x20
SYNCbCD
SYSREFCDP/M
OVRC
INCP/M
14-bit
ADC
2x Dec
Burst Mode
SNR Boost
INDP/M
14-bit
ADC
2x Dec
Burst Mode
SNR Boost
VCM
Common
Mode
JESD204B
DC[0,1]P/M
JESD204B
DD[0,1]P/M
OVRD
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS58J89
SBAS659 – NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
7
Detailed Description ............................................ 22
7.1
7.2
7.3
7.4
7.5
7.6
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 5
Handling Ratings....................................................... 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Electrical Characteristics: 250 MSPS Output, 2x
Decimation Filter ........................................................ 8
6.7 Electrical Characteristics: 500 MSPS Output............ 9
6.8 Electrical Characteristics: Sample Clock Timing
Characteristics ......................................................... 10
6.9 Electrical Characteristics: Digital Outputs ............... 10
6.10 Timing Requirements ............................................ 11
6.11 Reset Timing ......................................................... 11
6.12 Typical Characteristics .......................................... 15
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
22
22
23
31
39
41
Application and Implementation ........................ 64
8.1 Application Information............................................ 64
8.2 Typical Application .................................................. 65
9 Power Supply Recommendations...................... 67
10 Layout................................................................... 67
10.1 Layout Guidelines ................................................. 67
10.2 Layout Example .................................................... 67
11 Device and Documentation Support ................. 69
11.1 Trademarks ........................................................... 69
11.2 Electrostatic Discharge Caution ............................ 69
11.3 Glossary ................................................................ 69
12 Mechanical, Packaging, and Orderable
Information ........................................................... 69
4 Revision History
2
DATE
REVISION
NOTES
November 2014
*
Initial release.
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5 Pin Configuration and Functions
AVDD33
INAP
INAM
AVDD33
AVDD18
INBM
INBP
AVDD18
DVDD
DA0P
DA0M
IOVDD
DA1P
DA1M
OVRA
OVRB
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SDOUT
1
48
SYNCbABM
SDATA
2
47
SYNCbABP
SCLK
3
46
DB0P
SDENb
4
45
DB0M
SYSREFABM
5
44
IOVDD
SYSREFABP
6
43
DB1P
AVDDC
7
42
DB1M
CLKINM
8
41
PLLVDD
CLKINP
9
40
PLLVDD
AVDDC
10
39
DD1M
SYSREFCDP
11
38
DD1P
SYSREFCDM
12
37
IOVDD
SRESETb
13
36
DD0M
ENABLE
14
35
DD0P
34
SYNCbCDP
33
SYNCbCDM
VREF
15
VCM
16
ADS58J89
GND PAD (backside)
AVDD18
INDM
27
28
29
30
31
32
OVRD
AVDD33
26
OVRC
INCM
25
DC1M
INCP
24
DC1P
AVDD33
23
IOVDD
22
DC0M
21
DC0P
20
DVDD
19
AVDD18
18
INDP
17
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
INPUT OR REFERENCE
INAP, INAM
63, 62
I
Differential analog input for channel A
INBP, INBM
58, 59
I
Differential analog input for channel B
INCP, INCM
18, 19
I
Differential analog input for channel C
INDP, INDM
23, 22
I
Differential analog input for channel D
VCM
16
O
Common mode output voltage to bias analog inputs, Vcm = 2.0 V
VREF
15
O
Voltage reference output. A 0.1-µF bypass capacitor to ground close to the pin is recommended
CLKINP,
CLKINM
9, 8
I
Differential clock input for channel
SYSREFABP,
SYSREFABM
6, 5
I
LVDS input with internal 100-Ω termination. External SYSREF input for channels A, B, C, and D
CLOCK/SYNC
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Pin Functions (continued)
PIN
NAME
SYSREFCDP,
SYSREFCDM
NO.
11, 12
I/O
DESCRIPTION
I
LVDS input with internal 100-Ω termination. External SYSREF input for channels C and D if output
rate of channel A/B is different from channel C/D.
Can be configured to trigger input for burst modes with SPI register write. Can be used as
differential input or two single-ended inputs (SYSREFCDP becomes TRIGGERAB and
SYSREFCDM becomes TRIGGERCD) for channel A/B and channel C/D.
I
Chip enable. Active high. Power down functionality can be configured through SPI register setting
and exercised using the ENABLE pin. Internal 51-kΩ pulldown resistor.
I
Serial interface clock input
CONTROL OR SERIAL
ENABLE
14
SCLK
3
SDATA
2
SDENb
4
I
Serial interface enable
SDOUT
1
O
Serial interface data output
SRESETb
13
I
Hardware reset. Active low. Initializes internal registers during high to low transition. This pin has
an internal 51-kΩ pullup resistor.
I/O Bidirectional serial data in 3-pin mode. In 4-pin interface, the SDATA pin is an input only.
DATA OUTPUT INTERFACE
DA[0,1]P,
DA[0,1]M
55, 54, 52, 51
O
JESD204B output interface for channel A
DB[0,1]P,
DB[0,1]M
46, 45, 43, 42
O
JESD204B output interface for channel B
DC[0,1]P,
DC[0,1]M
26, 27, 29, 30
O
JESD204B output interface for channel C
DD[0,1]P,
DD[0,1]M
35, 36, 38, 39
O
JESD204B output interface for channel D
OVRA
50
I/O Fast over-range indicator channel A. In burst mode can be configured to TRIGGERAB input.
OVRB
49
O
OVRC
31
I/O Fast over-range indicator channel C. In burst mode can be configured to TRIGGERCD input.
OVRD
32
O
Fast over-range indicator channel D. In burst mode can be configured to TRDY output.
SYNCbABP,
SYNCbABM
47, 48
I
SYNCb input for JESD204B interface for channel A/B, internal 100-Ω termination
SYNCbCDP,
SYNCbCDM
34, 33
I
SYNCb input for JESD204B interface for channel C/D, internal 100-Ω termination
AVDDC
7, 10
I
Clock 1.8-V power supply
AVDD18
21, 24, 57, 60
I
Analog 1.9-V power supply
AVDD33
17, 20, 61, 64
I
Analog 3.3-V power supply
Fast over-range indicator channel B. In burst mode can be configured to TRDY output.
POWER SUPPLY
DVDD
25, 56
I
Digital 1.8-V power supply
GND
PowerPAD™
I
Ground
IOVDD
28, 37, 44, 53
I
JESD204B output interface 1.8-V power supply
40, 41
I
PLL 1.8-V power supply
PLLVDD
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
Supply voltage
MIN
MAX
AVDD33
–0.3
3.6
AVDD18
–0.3
2.1
AVDDC
–0.3
2.1
DVDD
–0.3
2.1
IOVDD
–0.3
2.1
PLLVDD
–0.3
2.1
–0.3
0.3
Voltage between AGND and DGND
Voltage applied to input pins
V
–0.3
3
CLKINP, CLKINM
–0.3
AVDD18 + 0.3 V
SYNCbABP, SYNCbABM, SYNCbCDP, SYNCbCDM
–0.3
AVDD18 + 0.3 V
SYSREFABP, SYSREFABM, SYSREFCDP, SYSREFCDM
–0.3
AVDD18 + 0.3 V
DVDD + 0.5 V
SCLK, SDENb, SDATA, SRESETb, ENABLE
–0.3
Operating free-air temperature
–40
TJ
Operating junction temperature (2)
(2)
V
INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM
TA
(1)
UNIT
V
85
ºC
125
ºC
Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated as recommended operating conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.
6.2 Handling Ratings
Tstg
Storage temperature
VESD
Electrostatic
discharge
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(1)
MIN
MAX
UNIT
–65
150
°C
–2
2
kV
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
ADC clock frequency
NOM
250
Resolution
14
MAX
UNIT
500
MSPS
14
bits
AVDD33
3.15
3.3
3.45
AVDD18
1.8
1.9
2.0
AVDDC
1.7
1.8
1.9
DVDD
1.7
1.8
1.9
IOVDD
1.7
1.8
1.9
PLLVDD
1.7
1.8
1.9
TA
Operating free-air temperature
–40
TJ
Operating junction temperature
Supply
85
°C
125
°C
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6.4 Thermal Information
Thermal Metric (1)
RGC (64 PINS)
RΘJA
Junction-to-ambient thermal resistance
23.5
RΘJC(top)
Junction-to-case, top
7.0
RΘJB
Junction-to-board thermal resistance
2.6
φJT
Junction-to-top of package
0.1
φJB
Junction-to-board characterization parameter
2.6
RΘJC(bot)
Junction-to-case, bottom
0.3
(1)
6
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50%
clock duty cycle, AVDD33 = 3.3 V; AVDD18 = 1.9 V; AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V, –1-dBFS differential input,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
IAVDD33
3.3-V analog supply current
500
mA
IAVDD18
1.9-V analog supply current
320
mA
IAVDDC
1.8-V clock supply current
18
mA
IDVDD
1.8-V digital supply current
IIOVDD
I/O voltage supply current
IPLLVDD
PLL voltage supply current
Pdis
Total power dissipation
4-channel SNR boost
472
4-channel decimation filter
323
4-channel burst mode
324
2-channel burst mode, 2-channel SNR boost
398
2-channel decimation filter, 2-channel burst mode
324
2-channel decimation filter, 2-channel, discard every
other sample
289
2 lanes per ADC
373
1 lane per ADC
185
4-channel SNR boost
3.94
4-channel Burst mode
3.67
4-channel decimation filter
3.34
4-channel decimation filter, 1 lane per ADC
3.27
2-channel SNR Boost, 2-channel burst mode
3.81
2-channel decimation filter, 2-channel burst mode
3.51
2-channel decimation filter, 2-channel, discard every
other sample
3.28
SNR > 60 dB
Light sleep mode power
Wake-up time from light sleep mode
mA
42
Deep sleep mode power
Wake-up time from deep sleep mode
mA
SNR > 60 dB
mA
3.5
W
791
mW
1.4
ms
1.68
W
8
µs
ANALOG INPUTS
Differential input full-scale
1.0
1.25
1.5
Vpp
Vcm ±
50 mV
V
1
kΩ
Input
Each input to GND
capacitance
2.75
pF
VCM
2.18
V
900
MHz
Input common mode voltage
Input
resistance
Differential at DC
Common mode voltage output
Analog input bandwidth (–3 dB)
CHANNEL-TO-CHANNEL ISOLATION
Crosstalk (1)
Near channel
ƒIN = 170 MHz
85
Far channel
ƒIN = 170 MHz
95
dB
CLOCK INPUT
2000 (2)
Input clock frequency
250
Input clock amplitude
0.4
1.5
Input clock duty cycle
45%
50%
Internal clock biasing
(1)
(2)
MHz
Vpp
55%
0.9
V
Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on victim channel.
CLK / 4 mode
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6.6 Electrical Characteristics: 250 MSPS Output, 2x Decimation Filter
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50%
clock duty cycle, AVDD33 = 3.3 V; AVDD18 = 1.9 V; AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V, –1-dBFS differential input,
unless otherwise noted.
PARAMETER
SNR
Signal-to-noise ratio
TEST CONDITIONS
MIN
68.3
ƒIN = 100 MHz
68.2
ƒIN = 170 MHz
65
67.6
ƒIN = 450 MHz
66.8
HD3
Third harmonic distortion
SFDR
Spur free dynamic range
(Non-HD2,
(excluding HD2 and HD3)
Non-HD3)
IMD3
8
2F1-F2, 2F2-F1, Ain = –7 dBFS
ƒIN = 170 MHz
85
85
ƒIN = 450 MHz
75
ƒIN = 10 MHz
85
ƒIN = 100 MHz
85
75
85
ƒIN = 310 MHz
85
ƒIN = 450 MHz
85
ƒIN = 10 MHz
95
ƒIN = 100 MHz
ƒIN = 170 MHz
dBFS
dBc
dBc
95
75
95
ƒIN = 310 MHz
90
ƒIN = 450 MHz
85
FIN = 169 and 171 MHz
93
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UNIT
85
75
ƒIN = 310 MHz
ƒIN = 170 MHz
MAX
85
ƒIN = 100 MHz
Second harmonic distortion
68.2
ƒIN = 310 MHz
ƒIN = 10 MHz
HD2
TYP
ƒIN = 10 MHz
dBc
dBFS
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6.7 Electrical Characteristics: 500 MSPS Output
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50%
clock duty cycle, AVDD33 = 3.3 V; AVDD18 = 1.9 V; AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V, –1-dBFS differential input,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
SNR Boost (150-MHz
bandwidth)
Signal-to-Noise Ratio
Burst Mode (14 bit)
HD2
HD3
Second Harmonic Distortion
Third Harmonic Distortion
SFDR
Spur Free Dynamic Range
(Non-HD2,
(excluding HD2 and HD3)
Non-HD3)
IMD3
2F1-F2, 2F2-F1, Ain = –7 dBFS
TYP
65.7
ƒIN = 170 MHz
65.7
ƒIN = 350 MHz
SNR
MIN
ƒIN = 100 MHz
MAX UNIT
dBFS
65
ƒIN = 10 MHz
65.3
ƒIN = 100 MHz
65.2
ƒIN = 170 MHz
65.1
ƒIN = 370 MHz
64.7
ƒIN = 450 MHz
64.6
ƒIN = 10 MHz
85
ƒIN = 100 MHz
85
ƒIN = 170 MHz
85
ƒIN = 370 MHz
75
ƒIN = 450 MHz
75
ƒIN = 10 MHz
85
ƒIN = 100 MHz
85
ƒIN = 170 MHz
85
ƒIN = 370 MHz
78.3
ƒIN = 450 MHz
85
ƒIN = 10 MHz
85
ƒIN = 100 MHz
85
ƒIN = 170 MHz
85
ƒIN = 370 MHz
83
ƒIN = 450 MHz
83
FIN = 169 and 171 MHz
87
dBFS
dBc
dBc
dBFS
dBFS
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6.8 Electrical Characteristics: Sample Clock Timing Characteristics
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50%
clock duty cycle, AVDD33 = 3.3 V; AVDD18 = 1.9 V; AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V, –1 dBFS differential input,
unless otherwise noted.
PARAMETER
MIN
98
Data latency
38
Fast over-range (OVR) latency
tPDI
TYP
Aperture jitter, RMS
MAX
Sample clock cycles
6
Clock aperture delay
UNIT
fs rms
1.1
ns
6.9 Electrical Characteristics: Digital Outputs
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD33 = 3.3 V; AVDD18 = 1.9 V; AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V.
PARAMETER
MIN
TYP
MAX
UNIT
450
577
750
mV
DIGITAL OUTPUTS: JESD204B INTERFACE
(DA[0,1], DB[0,1], DC[0,1], DD[0,1])
Output differential voltage, |VOD|
Transmitter short circuit current
Transmitter terminals shorted to any voltage between
–0.25 and 1.45 V
Single ended output impedance
Output capacitance
Output capacitance inside the device, from either
output to ground
Unit interval, UI
5.0 Gbps
Rise and fall times
45
mA
50
Ω
2
pF
200
ps
110
ps
Output jitter
57
ps
Serial output data rate
5.0
Gbps
10
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6.10 Timing Requirements
MIN
TYP
MAX
UNIT
DIGITAL INPUTS:
SRESETb, SCLK, SDENb, SDATA, ENABLE, OVRA, OVRC, SYSREFCDP, SYSREFCDM
High-level input voltage
1.2
All digital inputs support 1.8-V and 3.3-V logic
levels
Low-level input voltage
V
0.4
V
High-level input current
50
µA
Low-level input current
–50
µA
4
pF
Input capacitance
DIGITAL OUTPUTS:
SDOUT, OVRA, OVRB, OVRC, OVRD
High-level output voltage
ILoad = –100 µA
DVDD – 0.2
DVDD
Low-level output voltage
V
0.2
V
350
450
mV
0.9
1.4
DIGITAL INPUTS:
SYNCbABP/M, SYNCbCDP/M, SYSREFABP/M, SYSREFCDP/M
Input voltage VID
250
Input common mode voltage VCM
0.4
V
tS_SYSREFxx
Referenced to rising edge of input clock
100
ps
tH_SYSREFxx
Referenced to rising edge of input clock
100
ps
6.11 Reset Timing
PARAMETER
TEST CONDITIONS
MIN
t1
Power-on delay
Delay from power up to active-low RESET pulse
t2
Reset pulse duration
Active-low RESET pulse duration
t3
Register write delay
Delay from RESET disable to SDENb active
TYP
MAX
UNIT
3
ms
20
ns
100
ns
Power Supplies
t1
SRESETb
t2
t3
SDENb
Figure 1. Reset Timing Diagram
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N+1
N+2
N
SAMPLE
tPD
Data Latency: x Clock Cycles
CLKINM
CLKINP
DA0P/M
DB0P/M
DC0P/M
DD0P/M
D
20
D
1
SAMPLE N ± 1
A.
SAMPLE N
D
20
SAMPLE N + 1
tPD is the propagation delay from sample clock input edge to serial data output transition
Figure 2. Timing Diagram: 250 MSPS Output Data Rate
12
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N+
2
N+1
N
SAMPLE
N+3
tPD
Data Latency: x Clock Cycles
CLKINM
CLKINP
DA0P/M
DB0P/M
DC0P/M
DD0P/M
D
20
SAMPLE N ± 1
DA1P/M
DB1P/M
DC1P/M
DD1P/M
D
10
D D
11 20
D
20
SAMPLE N
SAMPLE N ± 1
B.
D
11
SAMPLE N + 1
D
1
D
10
SAMPLE N
SAMPLE N + 2
D
1
SAMPLE N + 1
D
10
SAMPLE N + 2
tPD is the propagation delay from sample clock input edge to serial data output transition
Figure 3. Timing Diagram: 500 MSPS Output Data Rate
Sample N
ts_SYSREFxx_min
ts_SYSREFxx_max
th_SYSREFxx_min
CLKIN
SYSREFxx
Figure 4. Timing Using SYSREF (Subclass 1)
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tS_TRIGGER
tH_TRIGGER
CLKIN
OVRA/C
SYSREFCDP/M
C.
Trigger is allowed to be asynchronous to the sample clock. If the trigger input does not meet setup and hold timing
around one clock cycle, then the trigger will be caught on the next cycle.
Figure 5. Timing for External Manual Trigger Input
14
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6.12 Typical Characteristics
0
0
-20
-20
-40
-40
Attenuation (dB)
Attenuation (dB)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
-60
-80
-60
-80
-100
-100
-120
-120
0
25
Fin = 10 MHz
50
75
Frequency (MHz)
100
0
125
25
50
75
Frequency (MHz)
D001
1-lane 2x decimation
SNR = 65.29 dBFS
Ain = –1 dBFS
SFDR = 84.72 dBc
Fin = 100 MHz
125
D002
1-lane 2x decimation
SNR = 65.40 dBFS
Figure 6. FFT 10 MHz
Ain = –1 dBFS
SFDR = 82.50 dBc
Figure 7. FFT 100 MHz
0
0
-20
-20
-40
-40
Attenuation (dB)
Attenuation (dB)
100
-60
-80
-100
-60
-80
-100
-120
-120
0
25
Fin = 170 MHz
50
75
Frequency (MHz)
100
125
0
25
50
75
Frequency (MHz)
D003
1-lane 2x decimation
SNR = 65.34 dBFS
Ain = –1 dBFS
SFDR = 91.62 dBc
Fin = 230 MHz
100
D004
1-lane 2x decimation
SNR = 65.16 dBFS
Figure 8. FFT 170 MHz
125
Ain = –1 dBFS
SFDR = 76.83 dBc
Figure 9. FFT 230 MHz
96
70.0
93
90
68.0
84
SNR (dBFS)
SFDR (dBc)
87
81
78
75
72
66.0
64.0
69
66
63
62.0
0
100
200
300
1-lane 2x decimation
400 500 600
Fin (MHz)
700
800
900 1000
0
100
200
D006
Ain = –1 dBFS
1-lane 2x decimation
Figure 10. SFDR vs Frequency
300
400 500 600
Fin (MHz)
700
800
900 1000
Figure 11. SNR vs. Frequency
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Typical Characteristics (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
110
71
-40qC
0qC
105
25qC
55qC
85qC
-40qC
0qC
25qC
55qC
85qC
70
SNR (dBFS)
SFDR (dBFS)
100
95
90
69
68
85
67
80
75
-90
-80
-70
-60
-50
-40
-30
Input Amplitude (dBFS)
1-lane 2x decimation
-20
-10
66
-90
0
-80
-70
Fin = –170 MHz
1-lane 2x decimation
Figure 12. SFDR vs. Amplitude
70
90
69
85
68
80
67
75
70
65
60
-10
0
D009
Fin = –170 MHz
66
65
64
63
55
50
62
45
61
40
1.5
1.7
1.9
2.1
2.3
1-lane 2x decimation
60
1.5
2.5
VCM (V)
1.7
1.9
Fin = –170 MHz
2.1
2.3
2.5
VCM (V)
D010
1-lane 2x decimation
Figure 14. SFDR vs. VCM
D011
Fin = –170 MHz
Figure 15. SNR vs VCM
100
72
VREF=1.35V
VREF=1.5V
95
VREF=1.15V
VREF=1.0V
VREF=1.25V
VREF=1.35V
VREF=1.5V
70
90
SNR (dBFS)
SFDR (dBc)
-20
Figure 13. SNR vs. Amplitude
95
SNR (dBFS)
SFDR (dBc)
-60
-50
-40
-30
Input Amplitude (dBFS)
D008
85
VREF=1.15V
VREF=1.0V
68
66
80
64
75
70
62
0
100
200
300 400 500 600 700
Input Frequency (MHz)
1-lane 2x decimation
800
Ain = –1 dBFS
900 1000
0
100
D012
300 400 500 600 700
Input Frequency (MHz)
1-lane 2x decimation
Figure 16. SFDR vs. VREF
16
200
800
900 1000
D013
Ain = –1 dBFS
Figure 17. SNR vs. VREF
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Typical Characteristics (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
94
70
-40qC
0qC
25qC
55qC
85qC
-40qC
0qC
25qC
55qC
85qC
92
68
88
SNR (dBFS)
SFDR (dBc)
90
86
84
82
66
64
80
78
1.7
1.8
1.9
2.0
AVDD18 Supply Voltage (V)
1-lane 2x decimation
62
1.7
2.1
1.8
1.9
2.0
AVDD18 Supply Voltage (V)
D014
Ain = –1 dBFS
Fin = 170 MHz
1-lane 2x decimation
Figure 18. SFDR vs. AVDD18
D015
Fin = 170 MHz
Figure 19. SNR vs. AVDD18
70
96
94
Ain = –1 dBFS
2.1
-40qC
0qC
25qC
55qC
-40qC
85qC
0qC
25qC
55qC
85qC
92
68
88
SNR (dBFS)
SFDR (dBc)
90
86
84
82
66
80
64
78
76
74
72
3.0
3.1
3.2
3.3
3.4
AVDD33 Supply Voltage (V)
1-lane 2x decimation
3.5
Ain = –1 dBFS
62
3.0
3.6
3.1
3.2
3.3
3.4
AVDD33 Supply Voltage (V)
D016
Fin = 170 MHz
1-lane 2x decimation
Figure 20. SFDR vs. AVDD33
Ain = –1 dBFS
3.5
3.6
D017
Fin = 170 MHz
Figure 21. SNR vs. AVDD33
70
94
-40qC
0qC
25qC
55qC
85qC
-40qC
0qC
25qC
55qC
85qC
92
88
SNR (dBFS)
SFDR (dBc)
90
86
84
68
66
82
80
78
1.6
1.7
1.8
1.9
PLLVDD Supply Voltage (V)
1-lane 2x decimation
Ain = –1 dBFS
2.0
64
1.6
D018
Fin = 170 MHz
1.7
1.8
1.9
PLLVDD Supply Voltage (V)
1-lane 2x decimation
Figure 22. SFDR vs. PLLVDD
Ain = –1 dBFS
2.0
D019
Fin = 170 MHz
Figure 23. SNR vs PLLVDD
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Typical Characteristics (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
80
100
90
70
80
SNR (dBFS)
SFDR (dBc)
70
60
50
60
50
40
40
30
30
20
0.0
0.5
1.0
1.5
2.0
2.5
Clock Amplitude (V peak to peak)
1-lane 2x decimation
3.0
20
0.0
3.5
0.5
1.0
1.5
2.0
2.5
Clock Amplitude (V peak to peak)
D020
Ain = –1 dBFS
Fin = 170 MHz
1-lane 2x decimation
Figure 24. SFDR vs. Clock Amplitude
Ain = –1 dBFS
3.0
3.5
D021
Fin = 170 MHz
Figure 25. SNR vs. Clock Amplitude
0
4.5
Every Other Sample
Decimation Filter
-20
SNR Boost
Burst
4.0
Power (W)
Attenuation (dB)
-40
-60
3.5
-80
3.0
-100
-120
60
65
70
75
80
85
Frequency (MHz)
Fin = 170 MHz
90
95
2.5
250.0
100
300.0
D005
1-MHz spacing
Ain = –7 dBFS
1-lane 2x decimation
60 to 100 MHz shown
AVDD18 = 1.9 V
Ain = –1 dBFS
Attenuation (dB)
-40
-60
-80
-120
D023
1-lane 2x decimation
Ain = –1 dBFS
0
25
50
75
100 125 150 175
Frequency (MHz)
200
225
Fin = 170 MHz
2-lane burst mode
SNR = 65.26 dBFS
Figure 28. Crosstalk by Channel
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Ain = –1 dBFS
SFDR = 90.42 dBc
250
D024
C
hD
to
C
hC
C
hB
C
hA
C
hD
to
C
hD
hD
C
C
hC
to
to
C
hB
C
hA
to
C
hC
C
hC
to
C
C
to
C
hB
to
hB
C
hD
hC
hA
C
hD
to
hB
C
C
hA
to
C
C
C
hC
-100
hA
C
D022
Other supplies = 1.8 V
-20
to
to
hA
C
550.0
0
Channel to Channel
18
AVDD33 = 3.3 V
Fin = 170 MHz
500.0
Figure 27. Power vs. Sample Frequency
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
hB
Crosstalk (dBFS)
Figure 26. 2-Tone FFT
350.0
400.0
450.0
Sample Frequency (MHz)
Fin = 170 MHz
Figure 29. Burst Mode FFT 170 MHz
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Typical Characteristics (continued)
66.0
90
88
86
84
82
80
78
76
74
72
70
68
66
64
65.0
SNR (dBFS)
SFDR (dBc)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
64.0
63.0
62.0
61.0
60.0
0
100
200
300
2-lane burst mode
400 500 600
Fin (MHz)
700
800
0
900 1000
Ain = –1 dBFS
400 500 600
Fin (MHz)
700
800
900 1000
D007
D026
Ain = –1 dBFS
Figure 31. Burst Mode SNR vs Frequency
Attenuation (dB)
-20
-40
-60
-80
C
hB
-100
C
hA
to
to
300
0
C
C
hA hC
to
C
C
hB hD
to
C
C
hA
hB
to
C
C
hB hC
to
C
C
hC hD
to
C
C
hC hA
to
C
C
hB
hC
to
C
C
hD hD
to
C
C
hD hA
to
C
C
hB
hD
to
C
hC
Crosstalk (dBFS)
Figure 30. Burst Mode SFDR vs. Frequency
-120
2-lane burst mode
Ain = –1 dBFS
0
D027
Channel to Channel
Fin = 170 MHz
25
50
75
2-lane SNR boost mode
Blackman-Harris filter
100 125 150 175
Frequency (MHz)
Ain = –1 dBFS
200
225
250
D028
Fin = 170 MHz
Figure 33. SNRBoost FFT 170MHz
Figure 32. Burst Mode Crosstalk by Channel
67.0
90
88
86
84
82
80
78
76
74
72
70
68
66
64
66.0
SNR (dBFS)
SFDR (dBc)
200
2-lane burst mode
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
C
hA
100
D025
65.0
64.0
63.0
62.0
0
100
200
300
2-lane SNR boost mode
Blackman-Harris filter
400 500 600
Fin (MHz)
700
800
900 1000
0
100
200
300
D029
Ain = –1 dBFS
2-lane SNR boost mode
Blackman-Harris filter
Figure 34. SNR Boost SFDR vs. Frequency
400 500 600
Fin (MHz)
700
800
900 1000
Figure 35. SNR Boost SNR vs Frequency
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Typical Characteristics (continued)
hD
C
hC hA
to
C
C
hB
hC
to
C
C
hD hD
to
C
C
hD hA
to
C
C
hB
hD
to
C
hC
to
C
hC
to
D031
C
hC
hA
C
to
hB
C
hB
hB
C
hD
C
to
C
C
C
hA
to
C
C
C
hA
to
to
hA
C
C
hC
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
hB
Crosstalk (dBFS)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
Channel to Channel
2-lane SNR boost mode
Ain = –1 dBFS
Fin = 170 MHz
Figure 36. SNR Boost Crosstalk by Channel
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Typical Characteristics (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
SPACE
Figure 37. SNR Contour Plot
Figure 38. SFDR Contour Plot
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7 Detailed Description
7.1 Overview
The ADS58J89 is a pin-to-pin compatible, very-low power, wide bandwidth 14-bit 250 or 500 MSPS quad
channel receiver and feedback IC. It supports the JESD204B serial interface with data rates up to 5.0 Gbps
supporting 1 or 2 lanes per channel. The buffered analog input provides uniform input impedance across a wide
frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility
for system clock architecture design. The ADS58J89 provides excellent SFDR over a large input frequency range
with very-low power consumption.
7.2 Functional Block Diagram
OVRA
INAP/M
14-bit
ADC
2x Dec
Burst Mode
SNR Boost
JESD204B
DA[0,1]P/M
INBP/M
14-bit
ADC
2x Dec
Burst Mode
SNR Boost
JESD204B
DB[0,1]P/M
OVRB
SYSREFABP/M
Divide
by 1,2,4
CLKINP/M
SYNCbAB
PLL
x10/x20
SYNCbCD
SYSREFCDP/M
OVRC
INCP/M
14-bit
ADC
2x Dec
Burst Mode
SNR Boost
JESD204B
DC[0,1]P/M
INDP/M
14-bit
ADC
2x Dec
Burst Mode
SNR Boost
JESD204B
DD[0,1]P/M
VCM
22
OVRD
Common
Mode
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7.3 Feature Description
7.3.1 Decimation by 2 (250 MSPS Output)
Each channel has a digital filter in the data path as shown in Figure 39. The filter can be programmed as a lowpass or high-pass filter and the normalized frequency response of both filters is shown in Figure 40.
Lowpass/
Highpass
selection
500 MSPS
Low Latency Filter
250 MSPS
ADC
2
0, Fs/2
Figure 39. 2x Decimation Filter
The decimation filter response has a 0.1-dB pass band ripple with approximately 41% pass-band bandwidth. The
stop-band attenuation is approximately 40 dB.
10
0.1
0
0.05
Attenuation (dB)
Attenuation (dB)
-10
-20
-30
-40
0
-0.05
-50
-60
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
0.06
0.12
0.18
0.24
0.3
0.36
0.42
0.48
D00C
Figure 40. Decimation Filter Response
D00D
Figure 41. Decimation Filter Response Passband Ripple
Detail
7.3.2 Over-Range Indication
The ADS58J89 provides a fast over-range indication on the OVRA, OVRB, OVRC, and OVRD pins. The fast
OVR is triggered if the input voltage exceeds the programmable over-range threshold and is output after just 6
clock cycles, enabling a quicker reaction to an over-range event. The OVR threshold can be configured using
SPI register writes.
The input voltage level at which the overload is detected is referred to as the threshold and is programmable
using the over-range threshold bits.
The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the FAST OVR THRESH bits] /
8). After reset, the default value of the over-range threshold is set to 7 (decimal), which corresponds to a
threshold of 1.12 dB below full scale (20 × log(7/8)).
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Table 1. Fast Over Range
Threshold Settings
OVR Setting
(decimal)
OVR Threshold
(dBFS)
1
–18.1
2
–12.0
3
–8.5
4
–6.0
5
–4.1
6
–2.5
7 (default)
–1.1
Because the fast over-range indicator is single-ended LVCMOS logic, the ADS58J89 device can be configured
through the SPI register write to keep the over-range indicator asserted high for an extra one, two, or four clock
cycles. This longer assertion of the signal ensures the processor can capture the over-range event.
Sampling
Clock
Internal
Over-Range
Event
OVRA, OVRB,
OVRC, OVR D
Terminal Output
Normal
Hold 1 extra clock cycle
Hold 2 extra clock cycles
Figure 42. Fast Over Range Output Timing
The ADS58J89 device also provides the fast over-range indication bit in the JESD204B output data stream.
14-Bit Data Output
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OVR
HRES
16-bit data going into 8b/10b encoder
Figure 43. Sample Data and Status Bit Format
7.3.3 JESD204B Interface
The ADS58J89 supports device subclass 1 with a maximum output data rate of 5.0 Gbps for each serial
transmitter. It allows independent JESD204B format configuration for channel A and B and channel C and D.
An external SYSREF signal is used to align all internal clock phases and the local multi-frame clock to a specific
sampling clock edge. This allows synchronization of multiple devices in a system and minimizes timing and
alignment uncertainty. SYNCbAB input is used to control all the JESD204B SerDes blocks for channel A and B
while SYNCbCD is used to control channel C and D. If the same LMFS configuration is used for all four
channels, the SYNCbAB and SYNCbCD signals can be tied together externally and driven from the same
source.
24
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Depending on the channel output data rate, the JESD204B output interface can be operated with either 1 or 2
lanes per single channel. The JESD204B setup and configuration of the frame assembly parameters are
controlled via SPI interface.
The JESD204B transmitter block consists of the transport layer, the data scrambler and the link layer. The
transport layer maps the channel output data into the selected JESD204B frame data format and manages if the
channel output data or test patterns are being transmitted. The link layer performs the 8b/10b data encoding as
well as the synchronization and initial lane alignment using the SYNCb input signal. Optionally, data from the
transport layer can be scrambled.
SYSREF
AB
SYNCb
AB
INA
JESD
204B
JESD204B
D0/D1
INB
JESD
204B
JESD204B
D0/D1
INC
JESD
204B
JESD204B
D0/D1
IND
JESD
204B
JESD204B
D0/D1
Sample
Clock
SYSREF
CD
SYNCb
CD
Figure 44. JESD204B Lane Assignment
Transport Layer
Frame Data
Mapping
Link Layer
8b/10b
encoding
Scrambler
1+x14+x15
Comma characters
Initial lane alignment
Test Patterns
D0
D1
SYNCb
Figure 45. JESD204B Block
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7.3.3.1 JESD204B Initial Lane Alignment (ILA)
The ILA process is started by the receiving device by deasserting the SYNCb signal. Upon detecting a logic low
on the SYNCbAB input pins, the ADS58J89 device starts transmitting comma (K28.5) characters on channels A
and B to establish code group synchronization. Upon detecting a logic high on the SYNCbCD input pins, the
ADS58J89 device starts transmitting comma (K28.5) characters on channels C and D to establish code group
synchronization.
After synchronization is completed, the receiving device asserts the SYNCb signal and the ADS58J89 starts the
ILA sequence with the next local multi-frame clock boundary. The ADS58J89 device transmits 4 multi-frames
each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame start and end
symbols and the second multi-frame also contains the JESD204 link configuration data.
SYSREF
LMFC Clock
LMFC Boundary
Multi
Frame
SYNCb
Transmit Data
xxx
K28.5
K28.5
Code Group
Synchronization
ILA
ILA
Initial Lane
Alignment
DATA
DATA
Data Transmission
Figure 46. Initial Lane Assignment Format
7.3.3.2 JESD204B Test Patterns
There are three different test patterns available in the transport layer of the JESD204B interface. The ADS58J89
supports a RAMP, 1555/2AAA and different PRBS patterns. They can be enabled through SPI register write and
are located in address 0x1D and 0x32/33.
7.3.3.3 JESD204B Frame Assembly
The JESD204B standard defines the following parameters:
• L = number of lanes per link
• M = number of converters for device
• F = number of octets per frame clock period
• S = number of samples per frame
• HD = high density mode
The ADS58J89 supports independent configuration of the JESD204B format for channel A and B and channel C
and D. Table 2 lists the available JESD204B formats and valid ranges for the ADS58J89. The ranges are limited
by the SerDes line rate and the maximum channel sample frequency.
Table 2. Permissible LMFS Settings
26
L
M
F
S
HD
Max Channel
Output Rate
(MSPS)
Max ƒSerDes
(Gsps)
8
4
1
1
1
500
5.0
4
4
2
1
0
250
5.0
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The detailed frame assembly is shown in Table 3.
Table 3. LMFS Data Formats
LMFS = 8411
A1[13:6]
A0[13:6]
Lane
DA1
A0[5:0], 00 A1[5:0], 00 A2[5:0], 00 A3[5:0], 00
Lane
DB0
B0[13:6]
Lane
DB1
B0[5:0], 00 B1[5:0], 00 B2[5:0], 00 B3[5:0], 00
Lane
DC0
C0[13:6]
Lane
DC1
C0[5:0], 00 C1[5:0], 00 C2[5:0], 00 C3[5:0], 00
Lane
DD0
D0[13:6]
Lane
DD1
D0[5:0], 00 D1[5:0], 00 D2[5:0], 00 D3[5:0], 00
B1[13:6]
C1[13:6]
D1[13:6]
A2[13:6]
LMFS = 4421
Lane
DA0
B2[13:6]
C2[13:6]
D2[13:6]
A3[13:6]
B3[13:6]
C3[13:6]
D3[13:6]
A0[13:6]
A0[5:0], 00 A1[13:6]
A1[5:0], 00 A2[13:6]
A2[5:0], 00
B0[13:6]
B0[5:0], 00 B1[13:6]
B1[5:0], 00 B2[13:6]
B2[5:0], 00
C0[13:6]
C0[5:0], 00 C1[13:6]
C1[5:0], 00 C2[13:6]
C2[5:0], 00
D0[13:6]
D0[5:0], 00 D1[13:6]
D1[5:0], 00 D2[13:6]
D2[5:0], 00
7.3.4 SYSREF Clocking Schemes
Periodic: The SYSREF signal is always on. This mode is supported, but not recommended as the continuous
SYSREF signal appears like an additional clock input, which can cause clock mixing spurs in the channel output
spectrum.
Gapped-Periodic (recommended): A periodic SYSREF signal is presented to the ADS58J89 SYSREF inputs
for a very short period of time. This configuration requires a DC-coupled SYSREF connection for proper
operation. Most of the time the SYSREF signal is in a logic-low state, and thus cannot cause any glitches and
spurs in the channel output spectrum.
Pulse/One Shot (recommended): A single SYSREF reset pulse is used to synchronize the ADS58J89. The
ADS58J89 device requires a minimum of 3 SYSREF pulses to complete the synchronization phase. The
SYSREF signal is in a logic-low state most of the time, and thus cannot cause any glitches and spurs in the
channel output spectrum. Special attention should be given to ensure the single pulse meets required the
SYSREF input setup and hold time.
7.3.5 Split-Mode Operation
The ADS58J89 provides several different options to interface it to the digital processor or processors. If the
ADS58J89 device is operated in split sampling rate (2 channels at 500-MSPS output rate and 2 channels at 250MSPS output rate), then it requires dual SYSREF (SYSREFAB and SYSREFCD) and dual SYNC (SYNCbAB
and SYNCbCD).
Subclass 1 – Deterministic Latency: The device clock and synchronous SYSREF signal are provided by the
timing unit to the ADS58J89 and the processor. The processor controls the SYNCb input signals for the
JESD204B state machine for all four channels. In case the ADS58J89 is connected to two different processors,
the differential SYNCb inputs of the ADS58J89 can be configured to two single-ended inputs where each pin
controls the JESD204B state machine of the two corresponding channels.
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CLKIN
SYSREF
JESD204B
D0/D1
JESD204B
D0/D1
INA
JESD
204B
INA
JESD
204B
INB
JESD
204B
INB
JESD
204B
SYSREFAB
SYSREFAB
SYNCbAB
SYNCbAB
ADS58J8x
ADS58J8x
SYNCbCD
CLKIN
INC
JESD
204B
IND
JESD
204B
FPGA
ASIC
DSP
FPGA
ASIC
DSP
SYNCbCD
CLKIN
INC
JESD
204B
IND
JESD
204B
CLKIN
Timing Unit
For Example
LMK04828
CLKIN
Timing Unit
For Example
LMK04828
SYSREF
FPGA
ASIC
DSP
SYSREF
Figure 47. Four Channel and Dual Two Channel Usage
Split Mode Operation: If the ADS58J89 device is operated with 2-channel output at 500 MSPS and 2-channel
output at 250 MSPS, then dual SYSREF (SYSREFAB for channel A and B, SYSREFCD for channel C and D) as
well as dual SYNC (SYNCbAB for channel A and B, SYNCbCD for channel C and D) is required to ensure
normal operation because the JESD204B link configuration is different for the two channel pairs.
JESD204B
D0/D1
INA
JESD
204B
INB
JESD
204B
SYSREFAB
SYNCbAB
FPGA
ASIC
DSP
ADS58J89
Timing Unit
For Example
LMK04828
SYSREFCD
CLKIN
SYNCbCD
INC
JESD
204B
IND
JESD
204B
SYSREF
CLKIN
Figure 48. Dual SYSREF Usage
7.3.6 Eye Diagram Information
Figure 49 and Figure 50 is the measured eye diagram at 2.5 and 5Gbps output data rate, respectively. These are
overlaid with the JESD204B LV-OIF-6G-SR specification.
28
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800 mV
800 mV
0 mV
0 mV
±800 mV
±800 mV
0 ps
133.33 ps
266.67 ps
400 ps
533.33 ps
666.67 ps
0 ps
66.67 ps
Figure 49. 2.5 Gbps Eye Diagram
133.33 ps
200 ps
266.67 ps
333.33 ps
Figure 50. 5.0 Gbps Eye Diagram
7.3.7 Analog Inputs
The ADS58J89 analog signal inputs are designed to be driven differentially. The analog input pins have internal
analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a highimpedance input across a very-wide frequency range to the external driving source, which enables great
flexibility in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer
also helps isolate the external driving circuit from the internal switching currents of the sampling circuit, which
results in a more constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to 2 V using 500-Ω resistors, which allows for
AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +
0.3125 V) and (VCM – 0.3125 V), resulting in a 1.25-Vpp (default) differential input swing. The input sampling
circuit has a 3-dB bandwidth that extends up to 900 MHz.
2
1 nH
0.1
30
INxP
0
360 fF
500
Gain (dB)
-2
3.4 pF
Vcm
1 nH
-4
0.1
30
500
INxM
-6
360 fF
3.4 pF
-8
-10
-12
1E+7 2E+7
5E+7 1E+8 2E+8
5E+8 1E+9 2E+9
Input Frequency (Hz)
Figure 51. Normalized Input Bandwidth
5E+9
D00E
Figure 52. Equivalent Analog Input Circuit
7.3.8 Clock Inputs
The ADS58J89 clock input can be driven differentially with a sine wave or LVPECL source with little or no
difference in performance. The common mode voltage of the clock input is set to 0.9 V using internal 2-kΩ
resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close as
possible to the clock inputs in order to minimize signal reflections and jitter degradation.
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CLKINP
2 k
0.9 V
2 k
CLKINN
Figure 53. Equivalent Clock Input Circuit
7.3.9 Input Clock Divider
The ADS58J89 is equipped with two internal dividers on the clock input – one on channel AB and one on
channel CD. The clock divider allows operation with a faster input clock simplifying the system clock distribution
design. The clock dividers can be bypassed (/1) for operation with a 500-MHz clock while /2 option supports a
maximum input clock of 1 GHz and the /4 option a maximum input clock frequency of 2 GHz. Different divider
options can be selected for channel AB and channel CD clock output. By default the divider output of channel AB
block is routed to all 4 channels but the configuration can be customized with different SPI register settings to
use either the channel AB or CD divider blocks for any two channels.
ChAB
Divide by
1, 2, 4
Phase Select
ADC A
ADC B
CLKIN
Divide by
1, 2, 4
Phase Select
ADC C
ADC D
ChCD
Figure 54. Input Clock Divider
7.3.10 Power-Down Control
The power down functions of the ADS58J89 can be controlled either through the parallel control pin (ENABLE) or
through a SPI register setting. Power-down modes for the different channels as well as for the JESD204B
interface are supported.
The ADS58J89 supports the following power-down modes. The analog sleep mode configurations are in register
0x05/06 and the JESD204b sleep mode configurations are in register 0x1E and 0x1F.
30
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Table 4. Low-Power Mode Power Consumption and Wake-Up Times
Configuration
Power Consumption
Wake-Up Time
Global power down
24 mW
Needs JESD resynch
Standby
31 mW
Needs JESD resynch
Deep sleep
791 mW
1.4 ms
Light sleep
1.68 W
8 µs
Control power-down function through ENABLE pin:
1. Configure power-down mode in register 0x05 and 0x1E
2. Normal operation: ENABLE pin high
3. Power-down mode: ENABLE pin low
Control power-down function through SPI (ENABLE pin always high):
1. Assign power-down mode in register 0x06 and 0x1F
2. Normal operation: 0x06 and 0x1F are 0xFFFF
3. Power-down mode: configure power down mode in register 0x06 and 0x1F
7.3.11 Device Configuration
The serial interface (SIF) included in the ADS58J89 is a simple 3- or 4-pin interface. In normal mode, 3 pins are
used to communicate with the device. There is an enable (SDENb), a clock (SCLK), and a bidirectional IO port
(SDATA). If the user would like to use the 4-pin interface, one write must be implemented in the 3-pin mode to
enable 4-pin communications. In this mode, the SDOUT pin becomes the dedicated output. The serial interface
has an 8-bit address word and a 16-bit data word. The first rising edge of SCLK after SDENb goes low will latch
the read or write bit. If a high is registered, then a read is requested, if it is low, then a write is requested. SDENb
must be brought high again before another transfer can be requested.
7.3.12 JESD204B Interface Initialization Sequence
After power-up, the internal JESD204B digital block must be initialized with the following sequence of steps:
1. Set JESD RESET AB/CD and JESD INIT AB/CD to 0 (address 0x0D, value 0x0000)
2. Set JESD INIT AB/CD to 1 (0x0D, 0x0202)
3. Set JESD RESET AB/CD to 1 (0x0D, 0x0303)
4. Configure all other JESD register and clock settings. If those settings change later on, this initialization
sequence must be repeated.
5. Set JESD RESET AB/CD to 0 (0x0D, 0x0202)
6. Set JESD RESET AB/CD to 1 (0x0D, 0x0303)
7. Wait for two SYSREF pulses
8. Set JESD INIT AB/CD to 0 (0x0D, 0x0101)
7.3.13 Device and Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a low pulse on the SRESETb pin (of width greater than 10 ns), as shown in Figure 1. If required later
during operation, the serial interface registers can be cleared by applying:
• Another hardware reset using the SRESETb pin
• A software reset (bit D0 in register 0x00). This setting resets the internal registers to the default values and
then self-resets the RESET bit (D0) back to 0. In this case, the RESET pin is kept high.
7.4 Device Functional Modes
7.4.1 Operating Modes
Table 5 details the five different operating modes. A pair of channels (channel A and B and channel C and D)
can be configured in the same operating mode.
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Device Functional Modes (continued)
Table 5. Operating Modes Information
Channel
Sampling Rate
(MSPS)
500
500
Output Data
Rate (MSPS)
Output
Resolution
Output SerDes
Rate (GSPS)
Number of Lanes
per Channel
Decimation by 2
250
14 bit
5.0
1
Burst mode of every other sample
250
11 to 14 bit
5.0
1
SNR boost (150-MHz BW)
500
9 bit
5.0
2
Burst mode
500
9 to 14 bit
5.0
2
TDD-burst mode
500
9 to 14 bit
5.0
2
Digital Feature
7.4.2 Mode Configuration
Table 6 shows examples for different mode configurations for channel A/B and channel C/D regarding input
options for SYSREF as well as the trigger for the different burst mode options. Each channel pair (A/B and C/D)
can support each mode for 250-MSPS and 500-MSPS output.
Table 6. SYSREF and Trigger Options by Operating Mode
32
Channel
Output Rate
Mode
SYSREF Input
2
500 MSPS
SNR boost
SYSREFAB
2
500 MSPS
SNR boost
2
500 MSPS
TDD burst mode
2
500 MSPS
TDD burst mode
2
500 MSPS
TDD burst mode
2
500 MSPS
Burst mode
2
500 MSPS
SNR boost
2
500 MSPS
Burst mode
2
500 MSPS
SNR boost
SYSREFAB
2
250 MSPS
Burst mode of every other sample
SYSREFCD
2
500 MSPS
Burst mode
SYSREFAB
2
250 MSPS
Decimation by 2
SYSREFCD
2
250 MSPS
Decimation by 2
2
250 MSPS
Burst mode of every other sample
2
250 MSPS
Decimation by 2
2
250 MSPS
Decimation by 2
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SYSREFAB
Trigger Input
–
SYSREFP/M
OVRA/C
SYSREFAB
SYSREFCDP/M
SYSREFAB
SYSREFCDP/M
OVRA/C
OVRA/C
SYSREFAB
SYSREFAB
OVRA/C
OVRA/C
SYSREFCDP/M
OVRA/C
–
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7.4.3 Output Format
Table 7 provides detailed information on how the MSB or LSB get aligned for the different output data rates and resolution in the different operating
modes.
Table 7. Output Data Formats
Function
Output
Rate
Mode
Resolutio
n
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX
250
MSPS
Decimate
by 2
14 bit
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OVR
0
FB
250
MSPS
Burst
Mode
14 bit
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OVR
HRES
RX
500
MSPS
SNR
Boost
9 bit
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
OVR
0
11 bit
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
OVR
HRES
FB
500
MSPS
Burst
Mode
12 bit
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
OVR
HRES
14 bit
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OVR
HRES
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7.4.4 Burst Mode of Every Other Sample (250 MSPS Output)
In this mode, the channel is sampling at full sampling rate but the output only transmits every other sample with
burst mode. During burst mode operation the output is alternated between low resolution 11-bit and high
resolution 12- or 14-bit output. The burst mode operation can be configured to auto or manual trigger (see Burst
Mode).
N+1
N+2
N
SAMPLE
N+3
TPD
Data Latency: x Clock Cycles
CLKINM
CLKINP
DA0P/M
DB0P/M
DC0P/M
DD0P/M
D
20
D
1
SAMPLE N ± 2
SAMPLE N
D
20
SAMPLE N + 2
Figure 55. Timing Diagram Burst Mode of Every Other Sample
7.4.5 SNR Boost (500 MSPS Output)
In this mode, the channel output data is truncated to 9-bit resolution and the quantization noise is shaped using
TI SNR Boost 3G technology. The SNR Boost passband bandwidth maximum is 150 MHz at 500 MSPS centered
at the mid-point of the Nyquist zone.
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
0
25
50
75
100 125 150 175
Frequency (MHz)
200
225
250
D00B
Figure 56. SNR Boost Noise Shape Response
34
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7.4.6 Burst Mode
The ADS58J89 supports TI’s next generation burst mode technology which can be used for the DPD feedback
path as well for the receive path (TDD burst mode) in TDD applications. In receive mode, the TDD burst mode is
used to support very wide band and high resolution or duty cycle operation. Both modes can also be used
simultaneously where two channels operate in burst mode and two channels in TDD burst mode.
In burst mode operation, the ADS58J89 alternatively transmits low resolution (11 bit for 250 MSPS operation and
9 bit for 500 MSPS operation, LSBs are set to 0) and high resolution (11-, 12-, or 14-bit) output data and can be
configured via SPI register writes. The number of low and high resolution samples is configured through
programmable counters.
7.4.6.1 Burst Mode Counters
The ADS58J89 provides eight independent counters each for channel A and B and channel C and D for burst
mode operation. The TDD burst mode employs all eight counters (four for the low resolution samples and four for
the high resolution samples) while the normal burst mode uses only H1 and L1. Each count corresponds to four
samples and each counter can be programmed through a 22-bit register entry (1 to 4194303).
The counter values can be updated at any time, but the update does not go into effect until the start of the next
burst mode cycle with low resolution output data (L1). After programming the counters, the ADS58J89 calculates
the corresponding duty cycle for the selected high resolution output. If the duty cycle violates the limits, the digital
outputs are limited to low resolution output.
H1( H2 H3 H4 )
Duty Cycle
L1( L2 L3 L 4 )
(1)
The duty cycle limits per selected high resolution output is shown in Table 8.
Table 8. Burst Mode Maximum Allowed Duty Cycle
Maximum Allowed Duty Cycle
(High : Low Resolution Output)
500 MSPS
250 MSPS
14 bit
1/3
1/1
12 bit
2/3
4/1
11 bit
3/2
–
7.4.6.2 Burst Mode
The number of high and low resolution samples is H1 × 22 and L1 × 22. The maximum number of low resolution
samples is 22 × 222 = 224 while the maximum number of high resolution samples depends on the duty cycle.
7.4.6.3 TDD Burst Mode
The number of high and low resolution samples per cycle is (H1 + H2 + H3 + H4) × 22 and (L1 + L2 + L3 + L4) × 22.
In
TDD
burst
mode,
the
output
L1, H1, L2, H2, L3, H3, L4, H4, L1, H1, and so forth
data
gets
transmitted
in
the
following
order:
7.4.6.4 Trigger Input
The burst mode can be operated in auto trigger or manual trigger mode while the TDD burst mode supports only
the manual trigger mode.
In manual trigger mode, the trigger input releases the first high resolution data (H1) burst after the low resolution
data counter L1 has timed out. The OVRB outputs can be configured via SPI (address 0x6F) as output flags
TRDY for channel A and B. The OVRD outputs can be configured via SPI (address 0x6F) as output flags TRDY
for channel C and D. Both these configurations indicate that counter L1 timed out and the high resolution output
data burst can be triggered.
The ADS58J89 provides a lot of flexibility for the configuration of the trigger input. In default operation, the singleended input pin TRIGGERAB controls all four channels. Alternatively, the trigger input can be changed to the
OVRA pin as single-ended input or as a differential input with TRIGGERAB as positive and TRIGGERCD as
negative input (differential input requires external 100-Ω termination).
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For simultaneous receive and DPD feedback applications, it may be more useful to split the control where the
TRIGGERAB or OVRA pin controls channel A and B and the TRIGGERCD or OVRC pin controls channel C and
D. In addition, the OVRB and OVRD pins can be configured to output the TRDY flag for channel A and B and
channel C and D, respectively.
The trigger input for channel A/B and channel C/D can each be selected with 2 register bits (address 0x2C and
0x3A) as shown in Table 9.
Table 9. Burst Mode Trigger Sources
Register Setting
Trigger Source
00
TRIGGERAB (= pin SYSREFCDP)
01
TRIGGERCD (= pin SYSREFCDM)
10
OVRA (for channel A/B)
OVRC (for channel C/D)
11
TRIGGERAB/CD (as differential LVDS input, single trigger input for all 4 channels)
7.4.6.5 Manual Trigger Mode
Upon enabling manual trigger mode, the ADS58J89 starts transmission of low resolution data. As soon as the L1
counter is finished, the manual trigger is unlocked and the high resolution output H1 or burst mode sequence of
H1, L2, H2, L3, H3, L4, H4, L1 can be triggered. After the low resolution counter L1 is finished, the next high
resolution output or burst mode sequence can be triggered again. The HRES flag is embedded in the JESD204B
output data stream. The counter values can be updated until a new burst mode cycles starts with transmission of
low resolution samples.
See Figure 57 for an example of normal burst mode with manual trigger.
Enable Burst
Mode
L1 times out
Ready for trigger
DA[0,1]
DB[0,1]
DC[0,1]
DD[0,1]
Trigger Event
New Cycle Starts
Again
H1
L1
L1
H1
Update Counter Values
TRDY
TRIGGER
HRES
11- to 14-bit high resolution
9-bit low resolution
D
13
D
12
D D
11 10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
OVR HR
0
16-bit data going into 8b/10b encoder
Figure 57. Burst Mode Duty Cycle Timing
36
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See Figure 58 for an example of TDD burst mode with manual trigger:
L1 times out
Ready for trigger
Enable TDD
Burst Mode
DA[0,1]
DB[0,1]
DC[0,1]
DD[0,1]
New Cycle
Starts Again
Trigger Event
L2
H1
L1
H2
L3
H3
L4
H4
L1
H1
L2
Update Counter Values
TRDY
TRIGGER
HRES
Figure 58. TDD Burst Mode Duty Cycle Timing
7.4.6.6 Auto Trigger Mode
This mode is primarily intended for the DPD observation path. Upon enabling auto trigger mode, the ADS58J89
starts transmission of low resolution data. As soon as the L1 counter is finished, the ADS58J89 immediately
begins transmitting the high resolution output H1. The HRES flag can also be embedded in the JESD204B output
data stream. The counter values can be updated until a new burst mode cycles starts with transmission of low
resolution samples. Any input on the trigger input pins is ignored.
See Figure 59 for an example of normal burst mode with automatic trigger:
Enable
Burst Mode
New Cycle
Starts Again
L times out
DA[0,1]
DB[0,1]
DC[0,1]
DD[0,1]
H1
L1
L1
H1
Update Counter Values
HRES
11- to 14-bit high resolution
9-bit low resolution
D
13
D
12
D D
11 10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
OVR HR
0
16-bit data going into 8b/10b encoder
Figure 59. Auto-Trigger Mode Duty Cycle Timing
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7.4.6.7 TDD-Burst Mode
This mode is intended for the receive path in TDD LTE receivers. The individual counters for high and low
resolution output data can be programmed so that the high resolution samples line up with receive (uplink)
frames and the low resolution samples line up with transmit (downlink) and setup frames where no data is
present in the receive path.
Table 10. TDD Burst Mode Duty Cycle
Number of Downlink
Frames
Number of Uplink
Frames
Duty Cycle
High Resolution
Output (500 MSPS)
8
1
1:9 (0.11)
14 bit
7
2
2:8 (0.25)
14 bit
6
3
3:7 (0.43)
12 bit
4
5
4
4:6 (0.67)
11/12 bit
5
1 to 4
5 to 8
(1+)
11 bit
6
6
2
2:8 (0.25)
14 bit
7
5
3
3:7 (0.43)
12 bit
4
4
4:6 (0.67)
11/12 bit
1 to 3
5 to 7
>1
11 bit
Option
Number of Setup
Frames
1
2
3
1
2
8
9
7.4.6.7.1 TDD Burst Mode Examples
Following are two examples to illustrate the intention for the TDD burst mode. The TDD frame has 10 equal size
sub frames. For the downlink-uplink (DL-UL) configuration number 2 for example, the high and low resolution
counters can be set for a given channel sampling rate to match the downlink-uplink profile as shown in Figure 60.
The manual trigger is used to initiate the high resolution output data, which maintains synchronization. The
counter L1 covers the low resolution data across two consecutive TDD frames and most of setup frame.
For configuration number 2, a duty cycle of approximately 2 / 8 can be achieved; with a sampling rate of 500
MSPS, the high resolution output of 14 bit can be used.
DL-UL
Config
2
Subframe Number
0
1
2
3
4
5
6
7
8
9
D
S
U
D
D
D
S
U
D
D
Trigger
Ready
L1
Trigger
H1
L2
H2
L1
L3 = 0
H3 = 0
L4 = 0
H4 = 0
Figure 60. TDD Burst Mode Example 1
For configuration number 3, a duty cycle of approximately 3 / 7 can be achieved and only two counters have to
be programmed. With a sampling rate of 500 MSPS, a high resolution output of 12 bit can be used.
38
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Subframe Number
DL-UL
Config
3
0
1
2
3
4
5
6
7
8
9
D
S
U
U
U
D
D
D
D
D
Trigger
Ready
Trigger
H1
L1
L2 = 0
H2 = 0
L3 = 0
H3 = 0
L4 = 0
H4 = 0
L1
Figure 61. TDD Burst Mode Example 2
7.5 Programming
7.5.1 Serial Register Write
The internal register of the ADS58J89 can be programmed following these steps:
1. Drive SDENb pin low.
2. Set the R/W bit to ‘0’ (bit A7 of the 8 bit address).
3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be
written.
4. Write 16-bit data which is latched on the rising edge of SCLK.
Table 11. Serial Register Read or Write Timing (1)
PARAMETER
MIN
TYP
MAX
UNIT
10
MHz
ƒSCLK
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SDENb to SCLK setup time
50
ns
tSLOADH
SCLK to SDENb hold time
50
ns
tDSU
SDATA setup time
50
ns
tDH
SDATA hold time
50
ns
(1)
>DC
Typical values at 25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD33 = 3.3
V; AVDD18, AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V, unless otherwise noted.
SCLK
SDENb
SDATA
RWB
Read = 1
Write = 0
A6
A5
A4
A3
A2
A1
A0
D15
D14 D13 D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
7-bit address space
16-bit data: D15 is MSB, D0 is LSB
Figure 62. Serial Register Write Timing Diagram
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7.5.2 Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back using the SDOUT and
SDATA pins. This read-back mode may be useful as a diagnostic check to verify the serial interface
communication between the external controller and the channel.
1. Drive SDENb pin low.
2. Set the RW bit (A7) to 1. This setting disables any further writes to the registers.
3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be
read.
4. The device outputs the contents (D15 to D0) of the selected register on the SDOUT/SDATA pin.
5. The external controller can latch the contents at the SCLK rising edge.
6. To enable register writes, reset the RW register bit to 0.
SCLK
SDENb
SDATA
RWB
Read = 1
Write = 0
A6
A5
A4
A3
A2
7-bit address space
A1
A0
D15
D14 D13 D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit data: D15 is MSB, D0 is LSB
Figure 63. Serial Register Read Timing Diagram
40
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7.6 Register Maps
Register
Address
Register Data
A7 to A0
in hex
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
3/4
WIRE
FORMAT
DEC EN
AB
HP/LP
AB
0
DEC EN
CD
HP/LP
CD
0
SNRB
EN AB
SNRB
EN CD
0
0
0
0
0
RESET
1
MODE 1
0
1
0
1
0
0
0
FOVR THRESH AB
2
0
1
BM RES
DISCAR
D AB
3
0
CLK SEL
CD
CLK DIV CD
0
4
OVRA
OUT EN
OVRB
OUT EN
OVRC
OUT EN
OVRD
OUT EN
DISCAR
D CD
FOVR LENGTH AB
0
0
CLK PHASE SELECT CD
SYSREF AB
DELAY
5
SYSREF CD
DELAY
0
FOVR THRESH CD
0
0
SYSREF CLK SEL
SEL CD
AB
0
0
FOVR LENGTH CD
0
0
CLK DIV AB
0
0
0
SYNCb
AB EN
0
CLK PHASE SELECT AB
SYNCb
CD EN
1
1
ANALOG SLEEP MODES – ENABLE PIN
6
SYSREF
CD EN
ANALOG SLEEP MODES – SPI
7
0
0
0
0
0
0
CLK SW
AB
1
0
1
0
0
0
1
0
0
8
0
0
0
0
0
0
CLK SW
CD
1
0
1
0
0
0
1
0
0
C
0
0
1
1
0
0
0
1
1
1
D
0
0
0
0
0
0
JESD
INIT CD
JESD
RESET
CD
0
0
E
0
0
0
0
0
0
0
0
F
0
0
0
0
0
0
CTRL F AB
10
0
0
0
0
0
0
CTRL K AB
SYSREF JESD MODE CD
0
0
0
13
0
0
0
0
0
0
0
0
0
INV
SYNCb
AB
16
0
0
0
0
0
0
CTRL F CD
0
0
17
0
0
0
0
0
0
JESD
RESET
AB
0
0
0
0
CTRL M AB
0
0
0
CTRL L AB
TX LANE EN AB
HD AB
SCR EN
AB
0
0
0
0
0
0
0
CTRL M CD
0
0
0
CTRL L CD
SCR EN
CD
0
0
0
0
0
TEST
PATTER
N
0
0
0
CTRL K CD
INV
SYNCb
CD
0
JESD
INIT AB
0
TX LANE EN CD
0
SYSREF JESD MODE AB
1A
0
0
0
0
0
0
0
0
0
HD CD
1D
0
0
0
0
0
0
0
0
0
1E
0
0
0
0
0
0
JESD SLEEP MODES – ENABLE PIN
1F
1
1
1
1
1
1
JESD SLEEP MODES – SPI
TEST
TEST
PATTER PATTER
N EN CD N EN AB
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Register Maps (continued)
Register
Address
A7 to A0
in hex
Register Data
D15
D14
D13
20
21
42
D12
D11
D10
D9
D8
D7
D6
D5
D4
0
0
0
0
0
0
JESD LANE POLARITY INVERT
0
PRBS SEL
0
0
0
D3
D2
D1
D0
PRBS EN
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0
VREF SEL
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Table 12.
Register
Address
A7 to A0
in hex
Register Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
24
TDD BURST MODE COUNTER L1 [15:0] AB
25
TDD BURST MODE COUNTER L2 [15:0] AB
26
TDD BURST MODE COUNTER L3 [15:0] AB
27
TDD BURST MODE COUNTER L4 [15:0] AB
28
TDD BURST MODE COUNTER H1 [15:0] AB
29
TDD BURST MODE COUNTER H2 [15:0] AB
2A
TDD BURST MODE COUNTER H3 [15:0] AB
2B
TDD BURST MODE COUNTER H4 [15:0] AB
D5
D4
D3
D2
D1
2C
BM TRIG AB
TDD BURST MODE COUNTER L2 [21:16] AB
0
0
2D
0
0
TDD BURST MODE COUNTER L4 [21:16] AB
0
0
TDD BURST MODE COUNTER L3 [21:16] AB
2E
0
0
TDD BURST MODE COUNTER H2 [21:16] AB
0
0
TDD BURST MODE COUNTER H1 [21:16] AB
2F
AUTO
TRIG AB
TDD EN
AB
TDD BURST MODE COUNTER H4 [21:16] AB
0
0
TDD BURST MODE COUNTER H3 [21:16] AB
32
TDD BURST MODE COUNTER L1 [15:0] CD
33
TDD BURST MODE COUNTER L2 [15:0] CD
34
TDD BURST MODE COUNTER L3 [15:0] CD
35
TDD BURST MODE COUNTER L4 [15:0] CD
36
TDD BURST MODE COUNTER H1 [15:0] CD
37
TDD BURST MODE COUNTER H2 [15:0] CD
38
TDD BURST MODE COUNTER H3 [15:0] CD
39
TDD BURST MODE COUNTER H4 [15:0] CD
TDD BURST MODE COUNTER L1 [21:16] AB
3A
BM TRIG CD
TDD BURST MODE COUNTER L2 [21:16] CD
0
0
3B
0
0
TDD BURST MODE COUNTER L4 [21:16] CD
0
0
TDD BURST MODE COUNTER L3 [21:16] CD
3C
0
0
TDD BURST MODE COUNTER H2 [21:16] CD
0
0
TDD BURST MODE COUNTER H1 [21:16] CD
3D
AUTO
TRIG CD
TDD EN
CD
TDD BURST MODE COUNTER H4 [21:16] CD
0
0
TDD BURST MODE COUNTER H3 [21:16] CD
63
0
64
0
0
0
0
0
PRE EMP EN AB
PRE EMP SEL CD
PRE EMP EN CD
67
68
0
PRE EMP SEL AB
D0
TDD BURST MODE COUNTER L1 [21:16] CD
TEMP SENSOR
DCC EN AB
0
0
0
0
0
0
0
0
OUTPUT CURRENT CONTROL AB
6B
DCC EN CD
OUTPUT CURRENT CONTROL CD
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Table 12. (continued)
Register
Address
Register Data
A7 to A0
in hex
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
6C
0
0
0
0
0
0
0
0
0
0
TDD
RATIO
CD
TDD
RATIO
AB
BM
RATIO
CD
BM
RATIO
AB
JESD
PLL CD
JESD
PLL AB
6F
0
0
0
0
0
0
0
0
0
TRDY
EN AB
0
0
0
0
0
TRDY
EN CD
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7.6.1 Register Descriptions
7.6.1.1 Register Address 0
Figure 64. Register Address 0, Default 0x0000, Hex = 0
D15
3/4
WIRE
D14
FORMAT
D13
DEC EN
AB
D12
HP/LP
AB
D11
0
D10
DEC EN
CD
D9
HP/LP
CD
D8
0
D7
SNRB
EN AB
D6
SNRB
EN CD
D5
D4
D3
D2
D1
D0
0
0
0
0
0
RESET
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. Register Address 0 Field Descriptions
Bit
Field
Type
Reset
Description
D15
3/4 WIRE
Enables 4-bit serial interface when set
0 = 3-wire SPI (SDATA is bidirectional)
1 = 4-wire SPI (SDOUT is data output)
D14
FORMAT
Selects digital output format
0 = Output is 2s complement
1 = Offset binary
D13
DEC EN AB
Enables decimation filter for channel AB
0 = Normal operation
1 = Decimation filter enabled
D12
HP/LP AB
Determines high-pass or low-pass configuration of decimation
filter for channel AB
0 = Low pass
1 = High pass
D10
DEC EN CD
Enables decimation filter for channel CD
0 = Normal operation
1 = Decimation filter enabled
D9
HP/LP CD
Determines high-pass or low-pass configuration of decimation
filter for channel CD
0 = Low pass
1 = High pass
D7
SNRB EN AB
Enables SNR boost for channel AB
0 = Normal operation
1 = SNR boost enabled
D6
SNRB EN CD
Enables SNR boost for channel CD
0 = Normal operation
1 = SNR boost enabled
D0
RESET
Software reset, self clears to 0
0 = Normal operation
1 = Execute software reset
7.6.1.2 Register Address 1
Figure 65. Register Address 1, Default 0xAF7A, Hex = 1
D15
MODE
1
D14
D13
D12
0
1
0
D11
D10
D9
FOVR THRESH AB
D8
D7
FOVR LENGTH
AB
D6
D5
D4
FOVR THRESH CD
D3
D2
FOVR LENGTH
CD
D1
D0
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. Register Address 1 Field Descriptions
Bit
Field
D15
MODE 1
D13
Type
Reset
Description
Set bit D15 to 0 for optimum performance
Reads back 1
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Table 14. Register Address 1 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Sets fast OVR thresholds for channel A and B
The fast over-range detection is triggered 6 output clock cycles
after the overload condition occurs. The threshold at which the
OVR is triggered is:
Input full scale × [decimal value of ] / 8.
After power-up or reset, the default value is 7 (decimal), which
corresponds to an OVR threshold of 1.16-dB below full scale (20
× log(7/8)).
0
-2
D11:D9
Threshold Set to dBFS
-4
FOVR THRESH AB
-6
-8
-10
-12
-14
-16
-18
-20
0
1
2
3
4
5
6
Programmed Decimal Value
7
8
D00F
Figure 66. OVR Detection Threshold
D8:D7
FOVR LENGTH AB
Determines minimum pulse length for FOVR output
00 = 1 clock cycle
01 = 2 clock cycles
10 = 4 clock cycles
11 = 8 clock cycles
D6:D4
FOVR THRESH CD
Sets fast OVR thresholds for channel C and D See description
for channel A and B
FOVR LENGTH CD
Determines minimum pulse length for FOVR output
00 = 1 clock cycle
01 = 2 clock cycles
10 = 4 clock cycles
11 = 8 clock cycles
D3:D2
D1
Reads back 1
7.6.1.3 Register Address 2
Figure 67. Register Address 2, Default: 0x4000, Hex = 2
D15
0
D14
1
D13
D12
BM RES
D11
DISCARD AB
D10
DISCARD CD
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. Register Address 2 Field Descriptions
Bit
Field
D14
Reset
Description
Reads back 1
D13:D12
46
Type
BM RES
Sets high resolution output for burst mode and TDD burst mode
00 = 14-bit high resolution output
01 = 12-bit high resolution output
10 = 11-bit high resolution output
11 = 9-bit high resolution output (in 500-MSPS operation, burst
mode is disabled)
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Table 15. Register Address 2 Field Descriptions (continued)
Bit
D11
D10
Field
Type
Reset
Description
DISCARD AB
Outputs every other sample with 11-bit resolution for channel A
and B. Burst mode is used if output resolution is set to 12 or 14
bit (bit D13 to D12).
0 = Normal operation
1 = Discard mode enabled
DISCARD CD
Outputs every other sample with 11-bit resolution for channel C
and D. Burst mode is used if output resolution is set to 12 or 14
bit (bit D13 to D12).
0 = Normal operation
1 = Discard mode enabled
7.6.1.4 Register Address 3
Figure 68. Register Address 3, Default: 0x4040, Hex = 3
D15
0
D14
CLK SEL
CD
D13
D12
D11
CLK DIV CD
0
D10
D9
D8
CLK PHASE
SELECT CD
D7
SYSREF
SEL CD
D6
CLK SEL
AB
D5
D4
CLK DIV AB
D3
0
D2
D1
D0
CLK PHASE
SELECT AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. Register Address 3 Field Descriptions
Bit
Field
D14
CLK SEL CD
Clock source selection for channel C and D
0 = Channel CD clock output divider
1 = Channel AB clock output divider (default)
CLK DIV CD
Channel CD clock divider setting
00 = Clock input is up to 500 MHz. Input clock is not divided
(default)
01 = /2
10 = /4
11 = Not used
CLK PHASE SELECT CD
Selects phase of channel divided clock, but depends on clock
divider setting. When clock CD divider is set to:
/1 = 2 phases are available (0º or 180º)
/2 = 4 phases are available (0º, 90º, 180º or 270º)
/4 = 8 phases are available (0º, 45º, 90º, 135º, 180º, 225º, 270º
or 315º)
When switching clock phases, register 0x08, D9 must be
enabled first and then disabled after the switch to ensure glitchfree operation.
D7
SYSREF SEL CD
SYSREF Input selection for channel C and D
0 = Use SYSREFAB inputs (default)
1 = Use SYSREFCD inputs
D6
CLK SEL AB
Clock source selection for channel A and B
0 = Channel CD clock output divider
1 = Channel AB clock output divider (default)
CLK DIV AB
Channel AB clock divider setting
00 = Clock input is up to 500 MHz. Input clock is not divided
(default)
01 = /2
10 = /4
11 = Not used
CLK PHASE SELECT AB
Selects phase of channel AB divided clock, but depends on
clock divider setting. When clock divider is set to:
/1 = 2 phases are available (0º or 180º)
/2 = 4 phases are available (0º, 90º, 180º or 270º)
/4 = 8 phases are available (0º, 45º, 90º, 135º, 180º, 225º, 270º
or 315º)
When switching clock phases, register 0x07, D9 must be
enabled first and then disabled after the switch to ensure glitchfree operation.
D13:D12
D10:D8
D5:D4
D2:D0
Type
Reset
Description
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7.6.1.5 Register Address 4
Figure 69. Register Address 4, Default: 0x000F, Hex = 4
D15
OVRA
OUT EN
D14
OVRB
OUT EN
D13
OVRC
OUT EN
D12
OVRD
OUT EN
D11
D10
SYSREF AB
DELAY
D9
D8
SYSREF CD
DELAY
D7
D6
D5
D4
0
0
0
0
D3
SYNCb
AB EN
D2
SYNCb
CD EN
D1
D0
1
1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. Register Address 4 Field Descriptions
Bit
Field
D15
OVRA OUT EN
OVRA pin output enable
0 = OVRA is an input for burst mode trigger (see register 0x2C)
1 = OVRA is an output
D14
OVRB OUT EN
OVRB pin output enable
0 = Not used (default)
1 = OVRB is an output
D13
OVRC OUT EN
OVRC pin output enable
0 = OVRC is an input for burst mode trigger (see register 0x3A)
1 = OVRC is an output
D12
OVRD OUT EN
OVRD pin output enable
0 = Not used (default)
1 = OVRD is an output
SYSREF AB DELAY
Programmable input delay on SYSREFAB input
00 = 0-ps delay (default)
01 = 200-ps delay
10 = 100-ps delay
11 = 300-ps delay
SYSREF CD DELAY
Programmable input delay on SYSREFCD input
00 = 0-ps delay (default)
01 = 200-ps delay
10 = 100-ps delay
11 = 300-ps delay
D3
SYNCb AB EN
SYNCbAB input buffer enable
0 = Input buffer disabled
1 = Input buffer enabled (default)
D2
SYNCb CD EN
SYNCbCD input buffer enable
0 = Input buffer disabled
1 = Input buffer enabled (default)
D11:D10
D9:D8
Type
Reset
Description
D1
Reads back 1
D0
Reads back 1
7.6.1.6 Register Address 5
Figure 70. Register Address 5, Default: 0x0000, Hex = 5
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
ANALOG SLEEP MODES – ENABLE pin
D4
D3
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. Register Address 5 Field Descriptions
Bit
Field
D15:D0
48
ANALOG SLEEP MODES –
ENABLE pin
Type
Reset
Description
Power-down function assigned to ENABLE pin. When any bit is
set, the corresponding function is always enabled regardless of
status of the ENABLE pin. This assumes address 0x06 is in
default configuration.
D13
Light sleep channel A
D11
Light sleep channel B
D9
Light sleep channel C
D7
Light sleep channel D
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Table 18. Register Address 5 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
D6
Temperature sensor
D4
Clock buffer
D3
Clock divider channel AB
D2
Clock divider channel CD
D1
Buffer SYSREFAB
D0
Buffer SYSREFCD
SPACE
Table 19. Configurations When ENABLE Pin is Low
Description
0000 0000 0000 0000
Global power down
1000 0000 0000 0000
Standby
1000 0000 0001 1111
Deep sleep
1010 1010 1001 1111
Light sleep (if unused, clock divider CD and SYSREFCD can be set to 0 also)
7.6.1.7 Register Address 6
Figure 71. Register Address 6, Default: 0xFFFF, Hex = 6
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
ANALOG SLEEP MODES – SPI
D5
D4
D3
D2
D1
D0
SYSREFCD EN
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. Register Address 6 Field Descriptions
Bit
D15:D1
Field
Type
ANALOG SLEEP MODES – SPI
Reset
Description
Power-down function controlled via SPI. When a bit is set to 0,
the function is powered down when ENABLE pin is high.
However, register 0x05 has higher priority. For example, if D13
(deep sleep channel A) in 0x05 is enabled, it cannot be powered
down with the SPI.
D13
Light sleep channel A
D11
Light sleep channel B
D9
Light sleep channel C
D7
Light sleep channel D
D6
Temperature sensor
D4
Clock buffer
D3
Clock divider channel AB
D2
Clock divider channel CD
D1
Buffer SYSREFAB
D0
Enables SYSREFCD input for dual SYSREF operation
0 = TRIGGER input for burst mode (differential or single ended,
see address 0x2C/3A)
1 = SYSREF input for channel C/D (default)
SYSREFCD EN
SPACE
Table 21. Configurations When ENABLE Pin is High
Description
0000 0000 0000 000
Global power down
1000 0000 0000 000
Standby
1000 0000 0001 111
Deep sleep
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Table 21. Configurations When ENABLE Pin is High (continued)
Description
1010 1010 1001 111
Light sleep
1111 1111 1111 111
Normal operation
Control power down function through ENABLE pin:
1. Configure power-down mode in register 0x05
2. Normal operation: ENABLE pin high
3. Power-down mode: ENABLE pin low
Control power down function through SPI (ENABLE pin always high):
1. Assign power-down mode in register 0x06
2. Normal operation 0x06 is 0xFFFF
3. Power-down mode: configure power down mode in register 0x06
7.6.1.8 Register Address 7
Figure 72. Register Address 7, Default: 0x0124, Hex = 7
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
CLK SW AB
D8
1
D7
0
D6
1
D5
0
D4
0
D3
0
D2
1
D1
0
D0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. Register Address 7 Field Descriptions
Bit
Field
Type
D9
CLK SW AB
Reset
Description
User should set this bit to 1 when changing the clock phase of
the clock divider AB. After the change is complete user needs to
write this bit back to 0.
D8
Reads back 1
D6
Reads back 1
D2
Reads back 1
7.6.1.9 Register Address 8
Figure 73. Register Address 8, Default: 0x0124, Hex = 8
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
CLK SW CD
D8
1
D7
0
D6
1
D5
0
D4
0
D3
0
D2
1
D1
0
D0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. Register Address 8 Field Descriptions
Bit
Field
D9
CLK SW CD
Type
Reset
Description
User should set this bit to 1 when changing the clock phase of
the clock divider CD. After the change is complete user needs to
write this bit back to 0.
D8
Reads back 1
D6
Reads back 1
D2
Reads back 1
7.6.1.10 Register Address 12
50
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Figure 74. Register Address 12, Default: 0x31E4, Hex = C
D15
0
D14
0
D13
1
D12
1
D11
0
D10
0
D9
0
D8
1
D7
1
D6
1
D5
D4
D3
SYSREF JESD MODE CD
D2
D1
D0
SYSREF JESD MODE AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. Register Address 12 Field Descriptions
Bit
Field
Type
Reset
Description
D13
Reads back 1
D12
Reads back 1
D8
Reads back 1
D7
Reads back 1
D6
Reads back 1
D5:D3
SYSREF JESD MODE CD
Determines how SYSREF is used in the JESD block for channel
CD
000 = Ignore SYSREF input
001 = Use all SYSREF pulses
010 = Use only the next SYSREF pulse
011 = Skip one SYSREF pulse then use only the next one
100 = Skip one SYSREF pulse then use all pulses (default)
101 = Skip two SYSREF pulses and then use one
111 = Skip two SYSREF pulses and then use all
D2:D0
SYSREF JESD MODE AB
Determines how SYSREF is used in the JESD block for channel
AB. Same functionality as SYSREF JESD MODE CD
7.6.1.11 Register Address 13
Figure 75. Register Address 13, Default: 0x0202, Hex = D
D15
D14
D13
D12
D11
D10
0
0
0
0
0
0
D9
JESD
INIT CD
D8
JESD
RESET CD
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
D1
JESD
INIT AB
D0
JESD
RESET AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. Register Address 13 Field Descriptions
Bit
Field
Type
Reset
Description
D9
JESD INIT CD
Puts the JESD block in INITIALIZATION state when set high. In
this state the JESD parameters can be programmed and the
outputs will stay at 0. See also JESD start-up sequence.
D8
JESD RESET CD
Resets the JESD block when low
D1
JESD INIT AB
Puts the JESD block in initialization state when set high. In this
state the JESD parameters can be programmed and the outputs
will stay at 0.
D0
JESD RESET AB
Resets the JESD block when low
7.6.1.12 Register Address 14
Figure 76. Register Address 14, Default: 0x00FF, Hex = E
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
0
D8
0
D7
D6
D5
TX LANE EN CD
D4
D3
D2
D1
TX LANE EN AB
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 26. Register Address 14 Field Descriptions
Bit
Field
D7:D4
D3:D0
Type
Reset
Description
TX LANE EN CD
Enables JESD204B transmitter for channel C and D. Set to 1 to
enable.
D7 = Lane DD1
D6 = Lane DD0
D5 = Lane DC1
D4 = Lane DC0
TX LANE EN AB
Enables JESD204B transmitter for channel A and B. Set to 1 to
enable.
D3 = Lane DB1
D2 = Lane DB0
D1 = Lane DA1
D0 = Lane DA0
7.6.1.13 Register Address 15
Figure 77. Register Address 15, Default: 0x0001, Hex = F
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
D8
CTRL F AB
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
CTRL M AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. Register Address 15 Field Descriptions
Bit
Field
Type
Reset
Description
D9:D8
CTRL F AB
Controls number of octets per frame for channel AB.
00 = F = 1 (default)
01 = F = 2
D1:D0
CTRL M AB
Controls number of converters per link for channel AB.
01 = M = 2. This is the only valid option (default)
7.6.1.14 Register Address 16
Figure 78. Register Address 16, Default: 0x03E3, Hex = 10
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
D8
D7
D6
CTRL K AB
D5
D4
0
D3
0
D2
0
D1
D0
CTRL L AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. Register Address 16 Field Descriptions
Bit
Field
Type
Reset
Description
D9:D5
CTRL K AB
Controls number of frames per multi-frame for channel AB.
0: K = 1 30 K = 31
1: K = 2 31 K = 32 (default)
And so forth
D1:D0
CTRL L AB
Controls number of lanes for channel AB.
01: L = 2
11: L = 4 (default)
7.6.1.15 Register Address 19
Figure 79. Register Address 19, Default: 0x0020, Hex = 13
D15
D14
D13
D12
D11
D10
D9
D8
D7
0
0
0
0
0
0
0
0
0
D6
INV SYNCb
AB
D5
HD AB
D4
SCR EN
AB
D3
D2
D1
D0
0
0
0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
52
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Table 29. Register Address 19 Field Descriptions
Bit
Field
Type
Reset
Description
D6
INV SYNCb AB
Inverts polarity of SYNCbAB input
0 = Normal operation
1 = Polarity inverted
D5
HD AB
Enables high density mode for channel AB. This mode is
needed for LMFS = 4221.
0 = High-density mode disabled for mode LMFS = 2221
1 = High-density mode enabled for mode LMFS = 4221 (default)
D4
SCR EN AB
Enables scramble mode for channel AB
0 = Scramble mode disabled (default)
1 = Scramble mode enabled
7.6.1.16 Register Address 22
Figure 80. Register Address 22, Default: 0x0001, Hex = 16
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
D8
CTRL F CD
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
CTRL M CD
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30. Register Address 22 Field Descriptions
Bit
Field
Type
Reset
Description
D9:D8
CTRL F CD
Controls number of octets per frame for channel CD.
00: F = 1 (default)
01: F = 2
D1:D0
CTRL M CD
Controls number of converters per link for channel CD.
01: M = 2. This is the only valid option (default)
7.6.1.17 Register Address 23
Figure 81. Register Address 23, Default: 0x03E3, Hex = 17
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
D8
D7
D6
CTRL K CD
D5
D4
0
D3
0
D2
0
D1
D0
CTRL L CD
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31. Register Address 23 Field Descriptions
Bit
Field
Type
Reset
Description
D9:D5
CTRL K CD
Controls number of frames per multi-frame for channel CD
0: K = 1 30 K = 31
1: K = 2 31 K = 32 (default)
And so forth
D1:D0
CTRL L CD
Controls number of lanes for channel CD
01: L = 2
11: L = 4 (default)
7.6.1.18 Register Address 26
Figure 82. Register Address 26, Default: 0x0020, Hex = 1A
D15
D14
D13
D12
D11
D10
D9
D8
D7
0
0
0
0
0
0
0
0
0
D6
D5
INV SYNCb
HD CD
CD
D4
SCR EN
CD
D3
D2
D1
D0
0
0
0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 32. Register Address 26 Field Descriptions
Bit
Field
Type
Reset
Description
D6
INV SYNCb CD
Inverts polarity of SYNCbCD input
0 = Normal operation
1 = Polarity inverted
D5
HD CD
Enables high density mode for channel CD. This mode is
needed for LMFS = 4221.
0 = High density mode disabled for mode LMFS = 2221
1 = High density mode enabled for mode LMFS = 4221 (default)
D4
SCR EN CD
Enables scramble mode for channel CD
0 = Scramble mode disabled (default)
1 = Scramble mode enabled
7.6.1.19 Register Address 29
Figure 83. Register Address 29, Default: 0x0000, Hex = 1D
D15
D14
D13
D12
D11
D10
D9
D8
D7
0
0
0
0
0
0
0
0
0
D6
TEST
PATTERN
EN CD
D5
TEST
PATTERN
EN AB
D4
D3
D2
D1
D0
0
TEST
PATTERN
0
0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33. Register Address 29 Field Descriptions
Bit
Field
Type
Reset
Description
D6
TEST PATTERN EN CD
Enables test pattern output for channel C and D
0 = Normal operation
1 = Test pattern output enabled
D5
TEST PATTERN EN AB
Enables test pattern output for channel A and B
0 = Normal operation
1 = Test pattern output enabled
D4
TEST PATTERN
Selects test pattern
0 = RAMP pattern
1 = Output alternates between 0x1555 and 0x2AAA
7.6.1.20 Register Address 30
Figure 84. Register Address 30, Default: 0x0000, Hex = 1E
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
JESD SLEEP MODES – ENABLE pin
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34. Register Address 30 Field Descriptions
Bit
Field
D9:D0
54
JESD SLEEP MODES – ENABLE
pin
Type
Reset
Description
Power-down function assigned to ENABLE pin. When any bit is
set, the corresponding function is always enabled regardless of
status of the ENABLE pin.
D9 = JESD PLL channel CD
D8 = JESD PLL channel AB
D7 = Lane DD1
D6 = Lane DD0
D5 = Lane DC1
D4 = Lane DC0
D3 = Lane DB1
D2 = Lane DB0
D1 = Lane DA1
D0 = Lane DA0
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SPACE
Table 35. Configurations
Description
00 0000 0000
Global power down (default)
00 0000 0000
Standby
11 0000 0000
Deep sleep
11 0000 0000
Light sleep
7.6.1.21 Register Address 31
Figure 85. Register Address 31, Default: 0xFFFF, Hex = 1F
D15
1
D14
1
D13
1
D12
1
D11
1
D10
1
D9
D8
D7
D6
D5
D4
D3
JESD SLEEP MODES – SPI
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 36. Register Address 31 Field Descriptions
Bit
D15:D0
Field
Type
Reset
Description
Power-down function controlled via SPI. When a bit is set to 0,
the function is powered down when ENABLE pin is high.
However register 0x1E has higher priority. For example, if D9
(JESD PLL channel CD) in 0x1E is enabled, it cannot be
powered down with the ENABLE pin.
D9 = JESD PLL channel CD
D8 = JESD PLL channel AB
D7 = Lane DD1
D6 = Lane DD0
D5 = Lane DC1
D4 = Lane DC0
D3 = Lane DB1
D2 = Lane DB0
D1 = Lane DA1
D0 = Lane DA0
JESD SLEEP MODES – SPI
SPACE
Table 37. Configurations
Description
00 0000 0000
Global power down
00 0000 0000
Standby
11 0000 0000
Deep sleep
11 0000 0000
Light sleep
11 1111 1111
Normal operation (default)
Control power down function through ENABLE pin:
1. Configure power down mode in register 0x1E
2. Normal operation: ENABLE pin high
3. Power down mode: ENABLE pin low
Control power down function through SPI (ENABLE pin always high):
1. Assign power down mode in register 0x1F
2. Normal operation 0x1F is 0xFFFF
3. Power-down mode: configure power down mode in register 0x1F
7.6.1.22 Register Address 32
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Figure 86. Register Address 32, Default: 0x0000, Hex = 20
D15
D14
D13
D12
D11
D10
JESD LANE POLARITY INVERT
D9
D8
D7
D6
D5
D4
D3
PRBS EN
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 38. Register Address 32 Field Descriptions
Bit
Field
D15:D8
D7:D0
Type
Reset
Description
JESD LANE POLARITY INVERT
Set to 1 for polarity inversion
D15 = Lane DD1
D14 = Lane DD0
D13 = Lane DC1
D12 = Lane DC0
D11 = Lane DB1
D10 = Lane DB0
D9 = Lane DA1
D8 = Lane DA0
PRBS EN
Outputs PRBS pattern selected in address 0x21 on the selected
serial output lanes
D7 = Lane DD1
D6 = Lane DD0
D5 = Lane DC1
D4 = Lane DC0
D3 = Lane DB1
D2 = Lane DB0
D1 = Lane DA1
D0 = Lane DA0
7.6.1.23 Register Address 33
Figure 87. Register Address 33, Default: 0x0000, Hex = 21
D15
D14
D13
PRBS SEL
D12
0
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
D1
D0
VREF SEL
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 39. Register Address 33 Field Descriptions
Bit
Field
D14:D13
D2:D0
Type
Reset
Description
PRBS SEL
Selects different PRBS output pattern (these are not 8b/10b
encoded)
000 = 231 – 1
001 = 27 – 1
010 = 215 – 1
011 = 223 – 1
VREF SEL
Selects different input full-scale amplitude by adjusting voltage
reference setting
000 = Full scale is 1.25 Vpp (default)
001 = Full scale is 1.35 Vpp
010 = Full scale is 1.5 Vpp
011 = External
100 = Full scale is 1.15 Vpp
101 = Full scale is 1.0 Vpp
7.6.1.24 Address: 0x24, 0x25, 0x26, 0x27
Figure 88. Address: 0x24, 0x25, 0x26, 0x27; Default: 0x0000, Hex = 24, 25, 26, 27
D15
56
D14
D13
D12
D11
D10
D9
TDD BURST
TDD BURST
TDD BURST
TDD BURST
D8
D7
MODE COUNTER
MODE COUNTER
MODE COUNTER
MODE COUNTER
D6
D5
L1 [15:0] AB
L2 [15:0] AB
L3 [15:0] AB
L4 [15:0] AB
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D4
D3
D2
D1
D0
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LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 40. Address: 0x24, 0x25, 0x26, 0x27 Field Descriptions
Bit
Field
Type
Reset
Description
Low-resolution counters L1, L2, L3, L4 for channel A and B. L1 is
also used for regular bust mode.
TDD BURST MODE COUNTER L1,
L2, L3, L4 [15:0] AB
Each count equals 4 samples. Upper 6 MSB [21:16] for each
counter are located in address 0x2C and 0x2D
7.6.1.25 Address: 0x28, 0x29, 0x2A, 0x2B
Figure 89. Address: 0x28, 0x29, 0x2A, 0x2B; Default: 0x0000, Hex = 28, 29, 2A, 2B
D15
D14
D13
D12
D11
D10
D9
TDD BURST
TDD BURST
TDD BURST
TDD BURST
D8
D7
MODE COUNTER
MODE COUNTER
MODE COUNTER
MODE COUNTER
D6
D5
H1 [15:0] AB
H2 [15:0] AB
H3 [15:0] AB
H4 [15:0] AB
D4
D3
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 41. Address: 0x28, 0x29, 0x2A, 0x2B Field Descriptions
Bit
Field
Type
Reset
Description
High-resolution counters H1, H2, H3, H4 for channel A and B. H1
is also used for regular bust mode.
TDD BURST MODE COUNTER H1,
H2, H3, H4 [15:0] AB
Each count equals 4 samples. Upper 6 MSB [21:16] for each
counter are located in address 0x2E and 0x2F
7.6.1.26 Register Address 44
Figure 90. Register Address 44, Default: 0x0000, Hex = 2C
D15
D14
BM TRIG AB
D13
D12
D11
D10
D9
D8
TDD BURST MODE COUNTER L2 [21:16] AB
D7
0
D6
0
D5
D4
D3
D2
D1
D0
TDD BURST MODE COUNTER L1 [21:16] AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 42. Register Address 44 Field Descriptions
Bit
Field
Type
Reset
Description
D15:D14
BM TRIG AB
Burst mode trigger source selection for channel A and B
00 = TRIGGERAB input (SYSREFCDP pin)
01 = TRIGGERCD input (SYSREFCDM pin)
10 = OVRA input
11 = TRIGGERAB and TRIGGERCD as differential input
D13:D8
TDD BURST MODE COUNTER L2
[21:16] AB
Low-resolution counter L2 upper 6 MSB, channel AB
D5:D0
TDD BURST MODE COUNTER L1
[21:16] AB
Low-resolution counter L1 upper 6 MSB, channel AB
7.6.1.27 Register Address 45
Figure 91. Register Address 45, Default: 0x0000, Hex = 2D
D15
0
D14
0
D13
D12
D11
D10
D9
D8
TDD BURST MODE COUNTER L4 [21:16] AB
D7
0
D6
0
D5
D4
D3
D2
D1
D0
TDD BURST MODE COUNTER L3 [21:16] AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 43. Register Address 45 Field Descriptions
Bit
Field
Type
Reset
Description
D13:D8
TDD BURST MODE COUNTER L4
[21:16] AB
Low-resolution counter L4 upper 6 MSB, channel AB
D5:D0
TDD BURST MODE COUNTER L3
[21:16] AB
Low-resolution counter L3 upper 6 MSB, channel AB
7.6.1.28 Register Address 46
Figure 92. Register Address 46, Default: 0x0000, Hex = 2E
D15
0
D14
0
D13
D12
D11
D10
D9
D8
TDD BURST MODE COUNTER H2 [21:16] AB
D7
0
D6
0
D5
D4
D3
D2
D1
D0
TDD BURST MODE COUNTER H1 [21:16] AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 44. Register Address 46 Field Descriptions
Bit
Field
Type
Reset
Description
D13:D8
TDD BURST MODE COUNTER H2
[21:16] AB
High-resolution counter H2 upper 6 MSB, channel AB
D5:D0
TDD BURST MODE COUNTER H1
[21:16] AB
High-resolution counter H1 upper 6 MSB, channel AB
7.6.1.29 Register Address 47
Figure 93. Register Address 47, Default: 0x0000, Hex = 2F
D15
AUTO
TRIG AB
D14
TDD EN
AB
D13
D12
D11
D10
D9
D8
TDD BURST MODE COUNTER H4 [21:16] AB
D7
D6
0
0
D5
D4
D3
D2
D1
D0
TDD BURST MODE COUNTER H3 [21:16] AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 45. Register Address 47 Field Descriptions
Bit
Field
Type
Reset
Description
D15
AUTO TRIG AB
Enables auto trigger mode for regular burst mode for channel A
and B
0 = Auto trigger disabled
1 = Auto trigger enabled
D14
TDD EN AB
Enables TDD burst mode
0 = TDD burst mode disabled
1 = TDD burst mode enabled
D13:D8
TDD BURST MODE COUNTER H4
[21:16] AB
High-resolution counter H4 upper 6 MSB, channel AB
D5:D0
D5 to D0 TDD BURST MODE
COUNTER H3 [21:16] AB
High-resolution counter H3 upper 6 MSB, channel AB
7.6.1.30 Address: 0x32, 0x33, 0x34, 0x35
Figure 94. Address: 0x32, 0x33, 0x34, 0x35; Default: 0x0000, Hex = 32, 33, 34, 35
D15
D14
D13
D12
D11
D10
D9
TDD BURST
TDD BURST
TDD BURST
TDD BURST
D8
D7
MODE COUNTER
MODE COUNTER
MODE COUNTER
MODE COUNTER
D6
D5
L1 [15:0] CD
L2 [15:0] CD
L3 [15:0] CD
L4 [15:0] CD
D4
D3
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
58
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Table 46. Address: 0x32, 0x33, 0x34, 0x35 Field Descriptions
Bit
Field
Type
Reset
Description
Low-resolution counters L1, L2, L3, L4 for channel C and D. L1 is
also used for regular bust mode
TDD BURST MODE COUNTER L1,
L2, L3, L4 [15:0] CD
Each count equals 4 samples. Upper 6 MSB [21:16] for each
counter are located in address 0x3A and 0x3B
7.6.1.31 Address: 0x36, 0x37, 0x38, 0x39
Figure 95. Address: 0x36, 0x37, 0x38, 0x39; Default: 0x0000, Hex = 36, 37, 38, 39
D15
D14
D13
D12
D11
D10
D9
TDD BURST
TDD BURST
TDD BURST
TDD BURST
D8
D7
MODE COUNTER
MODE COUNTER
MODE COUNTER
MODE COUNTER
D6
D5
H1 [15:0] CD
H2 [15:0] CD
H3 [15:0] CD
H4 [15:0] CD
D4
D3
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 47. Address: 0x36, 0x37, 0x38, 0x39 Field Descriptions
Bit
Field
Type
Reset
Description
High-resolution counters H1, H2, H3, H4 for channel C and D. H1
is also used for regular bust mode
TDD BURST MODE COUNTER H1,
H2, H3, H4 [15:0] CD
Each count equals 4 samples. Upper 6 MSB [21:16] for each
counter are located in address 0x3C and 0x3D
7.6.1.32 Register Address 58
Figure 96. Register Address 58, Default: 0x0000, Hex = 3A
D15
D14
BM TRIG CD
D13
D12
D11
D10
D9
D8
TDD BURST MODE COUNTER L2 [21:16] CD
D7
0
D6
0
D5
D4
D3
D2
D1
D0
TDD BURST MODE COUNTER L1 [21:16] CD
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 48. Register Address 58 Field Descriptions
Bit
Field
Type
Reset
Description
D15:D14
BM TRIG CD
Burst mode trigger source selection for channel C and D
00 = TRIGGERAB input (SYSREFCDP pin)
01 = TRIGGERCD input (SYSREFCDM pin)
10 = OVRC input
11 = TRIGGERAB and TRIGGERCD as differential input
D13:D8
TDD BURST MODE COUNTER L2
[21:16] CD
Low-resolution counter L2 upper 6 MSB, channel AB
D5:D0
TDD BURST MODE COUNTER L1
[21:16] CD
Low-resolution counter L1 upper 6 MSB, channel AB
7.6.1.33 Register Address 59
Figure 97. Register Address 59, Default: 0x0000, Hex = 3B
D15
0
D14
0
D13
D12
D11
D10
D9
D8
TDD BURST MODE COUNTER L4 [21:16] CD
D7
0
D6
0
D5
D4
D3
D2
D1
D0
TDD BURST MODE COUNTER L3 [21:16] CD
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 49. Register Address 59 Field Descriptions
Bit
Field
Type
Reset
Description
D13:D8
TDD BURST MODE COUNTER L4
[21:16] CD
Low-resolution counter L4 upper 6 MSB, channel CD
D5:D0
TDD BURST MODE COUNTER L3
[21:16] CD
Low-resolution counter L3 upper 6 MSB, channel CD
7.6.1.34 Register Address 60
Figure 98. Register Address 60, Default: 0x0000, Hex = 3C
D15
0
D14
0
D13
D12
D11
D10
D9
D8
TDD BURST MODE COUNTER H2 [21:16] CD
D7
0
D6
0
D5
D4
D3
D2
D1
D0
TDD BURST MODE COUNTER H1 [21:16] CD
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 50. Register Address 60 Field Descriptions
Bit
Field
Type
Reset
Description
D13:D8
TDD BURST MODE COUNTER H2
[21:16] CD
High-resolution counter H2 upper 6 MSB, channel CD
D5:D0
TDD BURST MODE COUNTER H1
[21:16] CD
High-resolution counter H1 upper 6 MSB, channel
7.6.1.35 Register Address 61
Figure 99. Register Address 61, Default: 0x0000, Hex = 3D
D15
AUTO
TRIG CD
D14
TDD EN
CD
D13
D12
D11
D10
D9
D8
TDD BURST MODE COUNTER H4 [21:16] CD
D7
0
D6
0
D5
D4
D3
D2
D1
D0
TDD BURST MODE COUNTER H3 [21:16] CD
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 51. Register Address 61 Field Descriptions
Bit
Field
Type
Reset
Description
D15
AUTO TRIG CD
Enables auto trigger mode for regular burst mode for channel C
and D
0 = Auto trigger disabled
1 = Auto trigger enabled
D14
TDD EN CD
Enables TDD burst mode for channel C and D
0 = TDD burst mode disabled
1 = TDD burst mode enabled
D13:D8
TDD BURST MODE COUNTER H4
[21:16] CD
High-resolution counter H4 upper 6 MSB, channel CD
D5:D0
TDD BURST MODE COUNTER H3
[21:16] CD
High-resolution counter H3 upper 6 MSB, channel CD
7.6.1.36 Register Address 99
Figure 100. Register Address 99, Default: 0x0000, Hex = 63
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
0
D8
D7
D6
D5
D4
D3
TEMP SENSOR
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
60
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Table 52. Register Address 99 Field Descriptions
Bit
Field
D8:D0
Type
Reset
Description
Value of on chip temperature sensor (read only). Value is 2s
complement of die temperature sensor in °C
For example: 0x0032 equals 50°C
TEMP SENSOR
7.6.1.37 Register Address 100
Figure 101. Register Address 100, Default: 0x0000, Hex = 64
D15
D14
D13
D12
PRE EMP SEL AB
D11
D10
D9
PRE EMP EN AB
D8
D7
D6
D5
DCC EN AB
D4
D3
0
D2
0
D1
0
D0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 53. Register Address 100 Field Descriptions
Bit
Field
D15:D12
D11:D8
D7:D4
Type
Reset
Description
PRE EMP SEL AB
Selects pre-emphasis of serializers for channel A and B
0 = Pre-emphasis
1 = De-emphasis
PRE EMP EN AB
Enables pre-emphasis, 0 = disabled, 1 = enabled
D11 = Lane DB1
D10 = Lane DB0
D9 = Lane DA1
D8 = Lane DA0
DCC EN AB
Enables the duty cycle correction circuit for each of the
serializers
D7 = Lane DB1
D6 = Lane DB0
D5 = Lane DA1
D4 = Lane DA0
7.6.1.38 Register Address 103
Figure 102. Register Address 103, Default: 0x0000, Hex = 67
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
OUTPUT CURRENT CONTROL AB
D5
D4
D3
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 54. Register Address 103 Field Descriptions
Bit
D15:D0
Field
Type
OUTPUT CURRENT CONTROL AB
Reset
Description
Selects pre-emphasis current for the serializers. There are 4 bit
per serializer of channel A and B.
D15:D12 = Lane DB1
D11:D8 = Lane DB0
D7:D4 = Lane DA1
D3:D0 = Lane DA0
Table 55. Pre-Emphasis Level is: Decimal Value / 30
Description
0000
Normal operation
0001
1 / 30
0010
2 / 30
and so forth
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7.6.1.39 Register Address 104
Figure 103. Register Address 104, Default: 0x0000, Hex = 68
D15
D14
D13
D12
PRE EMP SEL CD
D11
D10
D9
PRE EMP EN CD
D8
D7
D6
D5
DCC EN CD
D4
D3
0
D2
0
D1
0
D0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 56. Register Address 104 Field Descriptions
Bit
Field
D15:D12
D11:D8
D7:D4
Type
Reset
Description
PRE EMP SEL CD
Selects pre-emphasis of serializers for channel C and D
0 = Pre-emphasis
1 = De-emphasis
PRE EMP EN CD
Enables pre-emphasis, 0 = disabled, 1 = enabled
D11 = Lane DD1
D10 = Lane DD0
D9 = Land DC1
D8 = Lane DC0
DCC EN CD
Enables the duty cycle correction circuit for each of the
serializers
D7 = Lane DD1
D6 = Lane DD0
D5 = Land DC1
D4 = Lane DC0
7.6.1.40 Register Address 107
Figure 104. Register Address 107, Default: 0x0000, Hex = 6B
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
OUTPUT CURRENT CONTROL CD
D5
D4
D3
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 57. Register Address 107 Field Descriptions
Bit
Field
D15:D0
Type
Reset
Description
Selects pre-emphasis current for the serializers. There are 4 bit
per serializer of channel C and D.
D15:D12 = Lane DD1
D11:D8 = Lane DD0
D7:D4 = Land DC1
D3:D0 = Lane DC0
OUTPUT CURRENT CONTROL CD
Table 58. Pre-Emphasis Level is: Decimal Value / 30
Description
0000
Normal operation
0001
1 / 30
0010
2 / 30
And so forth
7.6.1.41 Register Address 108
Figure 105. Register Address 108, Hex = 6C
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
0
0
0
0
0
0
0
0
0
0
TDD
RATIO CD
TDD
RATIO AB
D3
BM
RATIO
CD
D2
D1
D0
BM
RATIO AB
JESD
PLL CD
JESD
PLL AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 59. Register Address 108 Field Descriptions (1)
(1)
Bit
Field
Type
Reset
Description
D5
TDD RATIO CD
TDD burst mode high-to-low resolution duty cycle for channel
CD is invalid when flag is set
D4
TDD RATIO AB
TDD burst mode high-to-low resolution duty cycle for channel
AB is invalid when flag is set
D3
BM RATIO CD
Burst mode high-to-low resolution duty cycle for channel CD is
invalid when flag is set
D2
BM RATIO CD
Burst mode high-to-low resolution duty cycle for channel AB is
invalid when flag is set
D1
JESD PLL CD
JESD PLL for channel CD lost lock when flag is set high
D0
JESD PLL CD
JESD PLL for channel AB lost lock when flag is set high
Register values in address 0x6C are read only alarms
7.6.1.42 Register Address 111
Figure 106. Register Address 111, Default: 0x0000, Hex = 6F
D15
D14
D13
D12
D11
D10
D9
D8
D7
0
0
0
0
0
0
0
0
0
D6
TRDY EN
AB
D5
D4
D3
D2
D1
0
0
0
0
0
D0
TRDY EN
CD
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 60. Register Address 111 Field Descriptions
Bit
D6
D0
Field
Type
Reset
Description
TRDY EN AB
Selects to output TRDY flag in burst mode operation on OVRB
pin for channel A/B
0 = Fast overrange indicator for channel B is output on OVRB
pin
1 = Trigger ready flag output on OVRB pin
TRDY EN CD
Selects to output TRDY flag in burst mode operation on OVRD
pin for channel C/D
0 = Fast overrange indicator for channel D is output on OVRD
pin
1 = Trigger ready flag output on OVRD pin
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
In the design of any application involving a high-speed data converter, particular attention should be paid the
design of the analog input, the clocking solution, and careful layout of the clock and analog signals. In addition,
the JESD204B interface means there now are high-speed serial lines that should be handled to preserve
adequate signal integrity at the device that receives the sample data. The ADS58J89 evaluation module (EVM) is
one practical example of the design of the analog input circuit and clocking solution, as well as a practical
example of good circuit board layout practices around the ADC.
8.1.1 SNR and Clock Jitter
The signal-to-noise ratio of the channel is limited by three different factors: the quantization noise is typically not
noticeable in pipeline converters and is 84 dB for a 14-bit channel. The thermal noise limits the SNR at low input
frequencies while the clock jitter sets the SNR for higher input frequencies.
SNRADC [dBc]
SNR
§
Quantizatoin Noise
¨
20
20 log ¨10
¨
©
2
SNR
· §
Thermal Noise
¸ ¨10
20
¸ ¨
¨
¸
¹ ©
2
· § SNRJitter
¸ ¨10
20
¸ ¨
¸ ¨
¹ ©
·
¸
¸
¸
¹
2
(2)
Calculate the SNR limitation due to sample clock jitter using the following:
SNRJitter [dBc] 20 log(2S fin TJitter )
(3)
The total clock jitter (tJitter) has two components – the internal aperture jitter (85 fs for ADS58J89), which is set by
the noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. Calculate
total clock jitter using the following:
TJitter
(TJitter,Ext.Clock _ Input )2 (TAperture _ ADC )2
(4)
External clock jitter can be minimized by using high quality clock sources and jitter cleaners, as well as bandpass
filters at the clock input while a faster clock slew rate improves the channel aperture jitter.
The ADS58J89 has a thermal noise of 66 dBFS and internal aperture jitter of 98 fs. The SNR depending on
amount of external jitter for different input frequencies is shown in Figure 107.
67
35 fs
50 fs
100 fs
150 fs
200 fs
SNR (dBFS)
66
65
64
63
62
61
10
20
30
40
50
60 70 80
100
Fin (MHz)
200
300
400
500 600 700800 1000
D00A
Figure 107. SNR vs Input Frequency and External Clock Jitter
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8.2 Typical Application
The analog inputs of the ADS58J89 must be fully differential and biased to a desired common mode voltage,
VCM. Therefore, there will be a signal conditioning circuit for each of the analog inputs. If the amplitude of the
input circuit is such that no gain is needed to make full use of the full-scale range of the ADC, then a transformer
coupled circuit as in Figure 108 may be used with good results. The transformer coupling is inherently low-noise,
and inherently AC-coupled so that the signal may be biased to VCM after the transformer coupling. If signal gain
is required, or the input bandwidth is to include the spectrum all the way down to DC such that AC coupling is not
possible, then an amplifier-based signal conditioning circuit would be required.
By using the simple drive circuit of Figure 108, uniform performance can be obtained over a wide frequency
range. The buffers present at the analog inputs of the device help isolate the external drive source from the
switching currents of the sampling circuit.
0.1 F
0.1 F
T2
T1
5
CHx_INP
25
0.1 F
RIN
25
0.1 F
1:1
CIN
5
CHx_INM
1:1
Device
Figure 108. Input Drive Circuit
0.1 µF
CLKINP
RT
0.1 µF
RT
CLKINN
0.1 µF
Figure 109. Recommended Differential Clock Driving Circuit
8.2.1 Design Requirements
The ADS58J89 requires a fully differential analog input with a full-scale range not to exceed 1.25 V peak to peak,
biased to a common mode voltage of 2.0 V. In addition the input circuit must provide proper transmission line
termination (or proper load resistors in an amplifier-based solution) so the input of the impedance of the ADC
analog inputs should be considered as well.
The clocking solution will have a direct impact on performance in terms of SNR, as shown in Figure 107. The
ADS58J89 is capable of a typical SNR of 66 dBFS for input frequencies of about 100 MHz (in 14-bit burst mode),
so we will want to have a clocking solution that can preserve this level of performance.
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Typical Application (continued)
8.2.2 Detailed Design Procedure
The ADS58J89 has an input bandwidth of approximately 900 MHz, but we will consider an application involving
the first or second Nyquist zones, so we will limit the frequency bandwidth here to be under 250 MHz. We will
also consider a 50-ohm signal source, so the proper termination would be 50-Ω differential. As seen in
Figure 110 and Figure 111, the input impedance of the analog input at 250 MHz is large compared to 50 Ω, so
the proper termination can be 50-Ω differential as shown in Figure 108. Splitting the termination into two 25-Ω
resistors with an AC capacitor to ground provides a path to filter out any ripple on the common mode that may
result from any amplitude or phase imbalance of the differential input, improving SFDR performance. The
ADS58J89 provides a VCM output that may be used to bias the input to the desired level, but as seen in
Figure 52 the signal is internally biased inside the ADC so an external biasing to VCM is not required. If an
external biasing to VCM were to be employed, the VCM voltage may be applied to the mid-point of the two 25-Ω
termination resistors in Figure 108.
For the clock input, Figure 107 shows the SNR of the device above 100 MHz begins to degrade with external
clock jitter of greater than 100 fs rms, so we will recommend the clock source be limited to approximately 100 fS
of rms jitter. For the ADS58J89 EVM, the LMK04828 clock device is capable of providing a low-jitter sample
clock as well as providing the SYSREF signal required as shown in Figure 47 and Figure 48, so that clocking
device is one good choice for the clocking solution for the ADS58J89.
8.2.3 Application Curves
Figure 110 and Figure 111 show the differential impedance between the channel INP and INM pins. The
impedance is modeled as a parallel combination of RIN and CIN (RIN || 1 / jwCIN).
550
3.4E-12
500
3.3E-12
3.2E-12
400
Equivalent C (F)
Equivalent R (Ohms)
450
350
300
250
200
3.1E-12
3E-12
2.9E-12
2.8E-12
150
2.7E-12
100
2.6E-12
50
2.5E-12
0
0
500
1000
1500 2000 2500
Frequency (MHz)
3000
3500
4000
0
D032
Figure 110. Equivalent R
66
500
1000
1500 2000 2500
Frequency (MHz)
3000
3500
4000
D033
Figure 111. Equivalent C
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SBAS659 – NOVEMBER 2014
9 Power Supply Recommendations
The device requires a 1.8-V nominal supply for AVDDC, IOVDD, PLLVDD, and DVDD. The device also requires
a 1.9-V supply for AVDD18 and a 3.3-V supply for AVDD33. There are no specific sequence power-supply
requirements during device power-up. AVDD, DVDD, IOVDD, PLLVDD, and AVDD33 can power up in any order.
10 Layout
10.1 Layout Guidelines
The Device EVM layout can be used as a reference layout to obtain the best performance. A layout diagram of
the EVM top layer is provided in . Some important points to remember during laying out the board are:
• Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package
level. To minimize crosstalk on-board, the analog inputs should exit the pinout in opposite directions, as
shown in the reference layout of as much as possible.
• In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling between them. This configuration is also maintained on the reference layout of as much as
possible.
• Digital outputs should be kept away from the analog inputs. When these digital outputs exit the pinout, the
digital output traces should not be kept parallel to the analog input traces because this configuration may
result in coupling from digital outputs to analog inputs and degrade performance. The digital sample data rate
can be as high as 5.0 Gsps, so care must be taken to maintain the signal integrity of these signals. A low-loss
dielectric circuit board is recommended or else these traces should be kept as short as possible. These
traces should be kept away from the analog inputs ad n clock input to the device as well.
• At each power-supply pin (AVDD, DRVDD, or AVDDD3V), a 0.1-μF decoupling capacitor should be kept
close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-μF,
1-μF, and 0.1-μF capacitors can be kept close to the supply source.
10.1.1 CML SerDes Transmitter Interface
Each of the 5 Gbps SerDes CML transmitter outputs requires AC coupling between transmitter and receiver. The
differential pair should be terminated with a 100-Ω resistor as close to the receiving device as possible to avoid
unwanted reflections and signal degradation.
10.2 Layout Example
Figure 112. Layout Example Schematic
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ADS58J89
SBAS659 – NOVEMBER 2014
www.ti.com
Layout Example (continued)
Figure 113. Top and Bottom Layers
68
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SBAS659 – NOVEMBER 2014
11 Device and Documentation Support
11.1 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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69
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS58J89IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ58J89
ADS58J89IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ58J89
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Dec-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS58J89IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS58J89IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Dec-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS58J89IRGCR
VQFN
RGC
64
2000
336.6
336.6
28.6
ADS58J89IRGCT
VQFN
RGC
64
250
213.0
191.0
55.0
Pack Materials-Page 2
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