ADS62P23IRGCR

ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com DUAL CHANNEL, 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS Check for Samples: ADS62P24, ADS62P25, ADS62P22, ADS62P23 FEATURES 1 • • • • • • • • • • • Maximum Sample Rate: 125 MSPS 12-Bit Resolution with No Missing Codes 95 dB Crosstalk Parallel CMOS and DDR LVDS Output Options 3.5 dB Coarse Gain and Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off Digital Processing Block with: – Offset Correction – Fine Gain Correction, in Steps of 0.05 dB – Decimation by 2/4/8 – Built-in and Custom Programmable 24-Tap Low-/High-/Band-Pass Filters Supports Sine, LVPECL, LVDS, and LVCMOS Clocks and Amplitude Down to 400 mVPP Clock Duty Cycle Stabilizer Internal Reference; Supports External Reference also 64-QFN Package (9mm × 9mm) Pin Compatible 14-Bit Family (ADS62P4X) APPLICATIONS • • • • • Wireless Communications Infrastructure Software Defined Radio Power Amplifier Linearization 802.16d/e Test and Measurement Instrumentation • • • High Definition Video Medical Imaging Radar Systems DESCRIPTION ADS62P2X is a dual channel 12-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. ADS62P2X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled. Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P2X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C). Table 1. ADS62P2X Performance Summary SFDR, dBc SINAD, dBFS ADS62P25 ADS62P24 ADS62P23 ADS62P22 Fin = 10 MHz (0 dB gain) 88 92 93 94 Fin = 190 MHz (3.5 dB gain) 84 86 87 85 Fin = 10 MHz (0 dB gain) Fin = 190 MHz (3.5 dB gain) Analog power, mW 71 71.3 71.5 71.5 69.5 69.5 69.7 69.2 799 710 594 515 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. DRGND DRVDD AGND AVDD ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Digital Processing Block DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 Channel A INA_P INA_M SHA CLKP CLKM 12-Bit ADC Output Buffers 12 Bit 12 Bit SHA 12-Bit ADC Channel A Output Clock Buffer CLOCKGEN INB_P INB_M Digital Encoder Digital Encoder 12 Bit 12 Bit CLKOUT DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 Output Buffers Channel B Digital Processing Block Channel B VCM Reference Control Interface CTRL1 CTRL2 CTRL3 RESET SCLK SEN SDAATA CMOS Interface B0286-02 ADS62PXX Family 2 125 MSPS 105 MSPS 80 MSPS 65 MSPS ADS62P4X 14 Bits ADS62P45 ADS62P44 ADS62P43 ADS62P42 ADS62P2X 12 Bits ADS62P25 ADS62P24 ADS62P23 ADS62P22 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS62P25 QFN-64 (2) RGC –40°C to 85°C AZ62P25 ADS62P24 QFN-64 (2) RGC –40°C to 85°C AZ62P24 ADS62P23 QFN-64 (2) RGC –40°C to 85°C AZ62P23 ADS62P22 (1) (2) QFN-64 (2) RGC –40°C to 85°C AZ62P22 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS62P25IRGCT Tape and Reel, 250 ADS62P25IRGCR Tape and Reel, 2500 ADS62P24IRGCT Tape and Reel, 250 ADS62P24IRGCR Tape and Reel, 2500 ADS62P23IRGCT Tape and Reel, 250 ADS62P23IRGCR Tape and Reel, 2500 ADS62P22IRGCT Tape and Reel, 250 ADS62P22IRGCR Tape and Reel, 2500 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM air flow), θJC = 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in × 3 in (7.62 cm × 7.62 cm) PCB. ABSOLUTE MAXIMUM RATINGS (1) VI VALUE UNIT Supply voltage range, AVDD –0.3 to 3.9 V Supply voltage range, DRVDD –0.3 to 3.9 V Voltage between AGND and DRGND –0.3 to 0.3 V Voltage between AVDD to DRVDD –0.3 to 3.3 V –0.3 to 2 V –0.3 to minimum ( 3.6, AVDD + 0.3) V Voltage applied to VCM pin (in external reference mode) Voltage applied to analog input pins, INP and INM Voltage applied to analog input pins, CLKP and CLKM TA Operating free-air temperature range TJ Operating junction temperature range Tstg Storage temperature range (1) –0.3 to (AVDD + 0.3) V –40 to 85 °C 125 °C –65 to 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Copyright © 2007–2011, Texas Instruments Incorporated 3 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage (1) DRVDD Output buffer supply voltage CMOS interface LVDS interface 3 3.3 3.6 V 1.65 1.8 to 3.3 3.6 V 3 3.3 3.6 V ANALOG INPUTS Differential input voltage range VIC 2 Vpp 1.5 ± 0.1 Input common-mode voltage Voltage applied on VCM in external reference mode 1.45 1.5 V 1.55 V CLOCK INPUT Input clock sample rate, FS ADS62P25 1 125 ADS62P24 1 105 ADS62P23 1 80 ADS62P22 1 Sine wave, ac-coupled Input clock amplitude differential (VCLKP – VCLKM) 0.4 65 1.5 ± 0.8 LVPECL, ac-coupled Vpp ± 0.35 LVDS, ac-coupled LVCMOS, ac-coupled MSPS 3.3 Input Clock duty cycle 35% 50% 65% DIGITAL OUTPUTS Output buffer drive strength (2) for CLOAD ≤ 5 pF and DRVDD ≥ 2.2 V DEFAULT strength for CLOAD > 5 pF and DRVDD ≥ 2.2 V MAXIMUM strength for DRVDD < 2.2 V MAXIMUM strength CMOS interface, maximum buffer strength CLOAD Maximum external load capacitance from each output pin to DRGND 10 LVDS interface, without internal termination 5 LVDS interface, with internal termination RLOAD Differential load resistance (external) between the LVDS output pairs TA Operating free-air temperature (1) (2) 4 pF 10 Ω 100 -40 85 °C For easy migration to the next generation, higher sampling speed devices (> 125 MSPS), use 1.8 V DRVDD supply. See Output Buffer Strength Programmability in application section Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V to 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V, unless otherwise noted. ADS62P25 FS = 125 MSPS PARAMETER MIN TYP RESOLUTION ADS62P24 FS = 105 MSPS MAX MIN TYP ADS62P23 FS = 80 MSPS MAX MIN TYP ADS62P22 FS = 65 MSPS MAX MIN TYP UNIT MAX 12 12 12 12 Bits 2 2 2 2 VPP >1 >1 >1 >1 MΩ 7 7 7 7 pF Analog input bandwidth 450 450 450 450 MHz Analog input common mode current (per input pin of each ADC) 1.3 1.3 1.3 1.3 μA/MSPS 1 1 1 1 V V ANALOG INPUT Differential input voltage range Differential input resistance (dc) see Figure 83 Differential input capacitance see Figure 84 REFERENCE VOLTAGES VREFB Internal reference bottom voltage VREFT Internal reference top voltage VCM Common mode output voltage VCM output current capability 2 2 2 2 1.5 1.5 1.5 1.5 4 4 4 4 V mA DC ACCURACY No missing codes EO Specified Offset error -10 Offset error temperature coefficient ±2 Specified 10 -10 0.05 ±2 Specified 10 -10 0.05 ±2 Specified 10 -10 0.05 ±2 10 0.05 mV mV/°C There are two sources of gain error – internal reference inaccuracy and channel gain error EGREF EGCHAN Gain error due to internal reference inaccuracy alone, (ΔVREF /2) % ±0.2 5 2 -2 ±0.2 5 2 -2 ±0.2 5 2 -2 ±0.2 5 2 % FS -1 ±0.3 1 -1 ±0.3 1 -1 ±0.3 1 -1 ±0.3 1 % FS -2 (1) Gain error of channel alone across devices & across channels within a device Channel gain error temperature coefficient DNL Differential nonlinearity INL Integral nonlinearity 0.00 5 0.00 5 0.00 5 0.00 5 -0.75 ±0.3 - ±0.3 0.75 - ±0.3 0.75 - ±0.3 0.75 Δ%/°C LSB -2 ±0.6 2 -2 ±0.6 2 -2 ±0.6 2 -2 ±0.6 2 LSB 240 275 212 240 177 200 153 175 mA POWER SUPPLY IAVDD IDRVDD Analog supply current Digital supply current, CMOS interface DRVDD = 1.8 V FIN= 2 MHZ (2) No external load capacitance 15 13 11.5 10 mA 10 pF external load capacitance 28 25 21 18 mA 73 73 73 73 mA IDRVDD Digital supply current, LVDS interface DRVDD = 3.3 V with 100 Ω external termination PAVDD Analog power dissipation PDRVDD Digital power dissipation CMOS interface DRVDD = 1.8 V (3) 799 (3) 710 792 594 660 515 578 mW 27 24 21 18 mW 10 pF external load capacitance 51 45 38 32 mW Global powerdown (1) (2) 908 No external load capacitance 50 75 50 75 50 75 50 75 mW This is specified by design and characterization; it is not tested in production. In CMOS mode, the DRVDD current scales with the sampling frequency, load capacitance on output pins, input frequency and supply voltage (see Figure 80 and CMOS power dissipation in the application section). The maximum DRVDD current depends on the actual load capacitance on the digital output lines. Note that the maximum recommended load capacitance is 10 pF. Copyright © 2007–2011, Texas Instruments Incorporated 5 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V to 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS ADS62P25 FS = 125 MSPS MIN TYP MAX ADS62P24 FS = 105 MSPS MIN TYP MAX ADS62P23 FS = 80 MSPS MIN TYP MAX ADS62P22 FS = 65 MSPS MIN TYP UNIT MAX DYNAMIC AC CHARACTERISTICS Fin = 10 MHz Fin = 50 MHz SNR Signal to Noise Ratio RMS Output Noise 68.5 Fin = 70 MHz Fin = 190 MHz ENOB Effective Number of Bits 71.3 71.4 69 71.3 70.3 69.9 3.5 dB coarse gain 69.5 69.5 69.7 69.2 Fin = 50 MHz Fin = 70 MHz Fin = 190 MHz 71 71.3 70.5 70.9 70.7 71.3 71.1 69.9 69.8 69.7 3.5 dB coarse gain 69.2 69.3 69.5 69.4 11.4 11.1 11.0 76 92 80 83 76 68.5 11.1 93 79 71.1 89 87 79 89 81 83 83 81 3.5 dB coarse gain 84 86 87 85 88 90 92 93 79 82 84.5 75 76 86 84 88 88 79 80 80 79 3.5 dB coarse gain 81 82 82 82 94 93 95 98 92 93 Fin = 50 MHz 76 Fin = 70 MHz 92 76 79 94 93 94 96 86 86 85 86 3.5 dB coarse gain 88 88 88 89 88 92 93 94 Fin = 50 MHz 76 Fin = 70 MHz 80 86 83 76 79 87 85 89 dBc 87 79 89 0 dB gain 81 83 83 81 3.5 dB coarse gain 84 86 87 85 Fin = 10 MHz 95 96 97 99 Fin = 50 MHz 94 95 96 98 Fin = 70 MHz 94 95 96 97 Fin = 190 MHz 90 93 95 92 Fin = 190 MHz dBc 97 79 0 dB gain Fin = 10 MHz dBc 86 77 0 dB gain Fin = 10 MHz Bits 94 87 85 11.5 0 dB gain 74 dBFS 11.6 11.5 88 86 Fin = 70 MHz Fin = 190 MHz 71.5 71.3 70.9 Fin = 70 MHz Fin = 190 MHz 71.5 69.6 11.0 68 68.5 0 dB gain Fin = 50 MHz dBFS LSB 68 Fin = 50 MHz 6 71.2 70.2 Fin = 10 MHz Worst Spur (Other than HD2, HD3) 71.6 71.4 Inputs tied to common-mode SFDR Fin = 70 MHz Spurious Free Dynamic Range Fin = 190 MHz HD3 Third Harmonic Distortion 68.5 71.6 69 70.2 Fin = 50 MHz HD2 Second Harmonic Distortion 71.3 0 dB gain Fin = 10 MHz THD Total Harmonic Distortion 71.5 71.1 71 Fin = 10 MHz SINAD Signal to Noise and Distortion Ratio 71.3 dBc dBc Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V to 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS ADS62P25 FS = 125 MSPS MIN TYP ADS62P24 FS = 105 MSPS MAX MIN TYP MAX ADS62P23 FS = 80 MSPS MIN TYP MAX ADS62P22 FS = 65 MSPS MIN TYP UNIT MAX IMD 2-Tone Intermodulation Distortion F1 = 185 MHz, F2 = 190 MHz each tone at -7 dBFS 88 87 92 92 dBFS Crosstalk Up to 100 MHz 95 95 95 95 dB Input Overload Recovery Recovery to within 1% (of final value) for 6-dB overload with sine wave input 1 1 1 1 clock cycles PSRR AC Power Supply Rejection Ratio for 100 mVpp signal on AVDD supply 35 35 35 35 dBc DIGITAL CHARACTERISTICS (1) The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = 3.0 V to 3.6 V. PARAMETER TEST CONDITIONS ADS62P25/ADS62P24 ADS62P23/ADS62P22 MIN DIGITAL INPUTS RESET, CTRL1, CTRL2, CTRL3, SCLK, SDATA, SEN TYP UNIT MAX (2) (3) High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 33 μA Low-level input current –33 μA 4 pF High-level output voltage DRVDD V Low-level output voltage 0 V 2 pF High-level output voltage 1375 mV Low-level output voltage 1025 mV 350 mV 1200 mV 2 pF Input capacitance DIGITAL OUTPUTS CMOS INTERFACE, DRVDD = 1.65 V to 3.6 V Output capacitance Output capacitance inside the device, from each output to ground DIGITAL OUTPUTS LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V, IO = 3.5 mA, RL = 100 Ω (4) Output differential voltage, |VOD| 225 VOS Output offset voltage, single-ended Common-mode voltage of OUTP, OUTM Output capacitance Output capacitance inside the device, from either output to ground (1) (2) (3) (4) All LVDS and CMOS specifications are characterized, but not tested at production. SCLK and SEN function as digital input pins when they are used for serial interface programming. When used as parallel control pins, analog voltage needs to be applied as per Table 4 and Table 5. All digital input pins are referred to AVDD supply. IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair. Copyright © 2007–2011, Texas Instruments Incorporated 7 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) Typical values are specified at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V, unless otherwise specified. PARAMETER TEST CONDITIONS Aperture delay ta Aperture delay variation ADS62P25 FS = 125 MSPS Wake-up time (to valid data) UNIT MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 from global powerdown ns ±80 ±80 ±80 ±80 ps 150 150 150 150 fs rms 15 50 15 50 15 50 15 50 μs 15 50 15 50 15 50 15 50 μs CMOS 100 200 100 200 100 200 100 200 ns LVDS 200 500 200 500 200 500 200 500 ns from standby Default, after reset Latency ADS62P22 FS = 65 MSPS TYP channel-to-channel within a device from output buffer disable ADS62P23 FS = 80 MSPS MIN Aperture jitter tj ADS62P24 FS = 105 MSPS 14 14 14 14 clock cycles with low latency mode enabled 10 10 10 10 clock cycles with digital filter enabled 15 15 15 15 clock cycles DDR LVDS MODE (4), DRVDD = 3.0 V to 3.6V tsu Data setup time (5) Data valid (6) to zero-cross of CLKOUTP 0.6 1.5 1.0 2.3 2.4 3.8 3.8 5.2 ns th Data hold time (5) Zero-cross of CLKOUTP to data becoming invalid (6) 1.0 2.3 1.0 2.3 1.0 2.3 1.0 2.3 ns tPDI Input clock rising Clock edge zero-cross to propagation output clock rising delay edge zero-cross 3.5 5.5 7.5 3.5 5.5 7.5 3.5 5.5 7.5 3.5 5.5 7.5 46% 50% 53% 46% 50% 53% 46% 50% 53% 46% 50% 53% ns LVDS bit clock duty cycle Duty cycle of differential clock, (CLKOUTPCLKOUTM) 10 ≤ Fs ≤ 125 MSPS tr tf Data rise time, Data fall time Rise time measured from –50 mV to 50 mV Fall time measured from 50 mV to –50 mV 1 ≤ Fs ≤ 125 MSPS 70 100 170 70 100 170 70 100 170 70 100 170 ps tCLKRISE tCLKFALL Output clock rise time, Output clock fall time Rise time measured from –50 mV to 50 mV Fall time measured from 50 mV to –50 mV 1 ≤ Fs ≤ 125 MSPS 70 100 170 70 100 170 70 100 170 70 100 170 ps (1) (2) (3) (4) (5) (6) 8 Timing parameters are specified by design and characterization and not tested in production. CL is the effective external single-ended load capacitance between each output pin and ground. IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair. Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Data valid refers to logic high of +100 mV and logic low of –100 mV. Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1) (continued) Typical values are specified at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF(2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V, unless otherwise specified. PARAMETER TEST CONDITIONS ADS62P25 FS = 125 MSPS MIN TYP ADS62P24 FS = 105 MSPS MAX MIN TYP PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.6 V, default output buffer drive strength ADS62P23 FS = 80 MSPS MAX MIN TYP ADS62P22 FS = 65 MSPS MAX MIN TYP UNIT MAX (7) tsu Data setup time (8) Data valid (9) to 50% of CLKOUT rising edge th Data hold time (8) 50% of CLKOUT rising edge to data becoming invalid (9) 2.0 3.5 tPDI Input clock rising Clock edge zero-cross to propagation 50% of CLKOUT delay rising edge 5.8 7.3 8.8 5.8 7.3 8.8 5.8 7.3 8.8 5.8 7.3 8.8 2.0 3.5 2.8 4.3 4.3 5.8 5.7 7.2 ns 2.7 4.2 4.2 5.7 5.6 7.1 ns ns Output clock duty cycle Duty cycle of output clock (CLKOUT) 10 ≤ Fs ≤ 125 MSPS 45% 53% 60% 45% 53% 60% 45% 53% 60% 45% 53% 60% tr tf Data rise time Data fall time Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD 1 ≤ Fs ≤ 125 MSPS 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 ns tCLKRISE tCLKFALL Output clock rise time Output clock fall time Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD 1 ≤ Fs ≤ 125 MSPS 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 ns 3.6 ns PARALLEL CMOS INTERFACE, DRVDD = 1.8 V, maximum buffer drive strength tSTART Input clock rising edge to data valid (11) (10) 8.5 7.5 5.5 (12) tDV Width of valid data window 3.3 6.0 5.0 7.5 8.0 10.5 10.5 13.5 ns For DRVDD < 2.2 V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See Parallel CMOS interface in application section. (8) Setup and hold time specifications take into account the effect of jitter on the output data and clock. (9) Data valid refers to logic high of 2 V (1.7 V) and logic low of 0.8 V (0.7 V) for DRVDD = 3.3 V (2.5 V). (10) For DRVDD < 2.2 V, output clock cannot be used for data capture. A delayed version of the input clock can be used, that gives the desired setup and hold times at the receiving chip. (11) Data valid refers to logic high of 1.26V and logic low of 0.54V for DRVDD = 1.8V. (12) Measured from zero-crossing of input clock having 50% duty cycle. (7) Copyright © 2007–2011, Texas Instruments Incorporated 9 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) Typical values are specified at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V, unless otherwise specified. PARAMETER FS = 65 MSPS TEST CONDITIONS MIN PARALLEL CMOS INTERFACE, DRVDD = 1.8 V, MULTIPLEXED MODE, maximum buffer drive strength tSTART_CHA Input clock falling edge to channel A data getting valid tDV_CHA Width of valid data window tSTART_CHB Input clock falling edge to channel A data getting valid tDV_CHB Width of valid data window (1) (2) (3) (4) (5) (6) FS = 40 MSPS TYP (5) 0.8 MAX MIN TYP MAX 8 9.5 UNIT (4) 2.3 ns (6) 5.4 6.4 (5) 1.1 10.3 2.4 11.3 8.4 ns 9.7 ns (6) 5 6 9.7 10.7 ns Timing parameters are specified by design and characterization and not tested in production. CL is the effective external single-ended load capacitance between each output pin and ground. IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair. For DRVDD < 2.2 V, output clock cannot be used for data capture. A delayed version of the input clock can be used, that gives the desired setup and hold times at the receiving chip Data valid refers to logic high of 1.26V and logic low of 0.54V for DRVDD = 1.8V. Measured from zero-crossing of input clock having 50% duty cycle. Table 2. Timing Characteristics at Lower Sampling Frequencies SAMPLING FREQUENCY, MSPS tsu DATA SETUP TIME, ns MIN TYP MAX tPDI CLOCK PROPAGATION DELAY, ns th DATA HOLD TIME, ns MIN TYP MAX MIN TYP MAX 5.8 7.3 8.8 3.5 5.5 7.5 CMOS INTERFACE, DRVDD = 2.5 V TO 3.6 V 40 10.5 12 10.3 11.8 20 23 24.5 23 24.5 LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V 10 40 8.5 10 1 2.3 20 21 22.5 1 2.3 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com N+4 N+3 N+2 N+16 N+15 N+1 Sample N N+14 Input Signal ta CLKM Input Clock CLKP CLKOUTM CLKOUTP tsu 14 Clock Cycles DDR LVDS Output Data DXP, DXM O E E O O E O E E – Even Bits D0,D2,D4,D6,D8,D10 O – Odd Bits D1,D3,D5,D7,D9,D11 (1) E O tPDI th E O N–10 E O N–1 N–9 E O N E O E O N+1 N+2 tPDI CLKOUT tsu Parallel CMOS 14 Clock Cycles Output Data D0–D11 (1) th N–10 N–9 N–1 N N+1 N+2 T0105-07 (1) Latency is 10 clock cycles in low-latency mode. Figure 1. Latency Input Clock CLKM CLKP tPDI Output Clock CLKOUTM CLKOUTP th tsu tsu Output Data Pair (1) (2) Dn Dn_Dn+1_P, Dn_Dn+1_M th Dn (1) Dn+1 (2) – Bits D0, D2, D4, D6, D8, D10 Dn+1 – Bits D1, D3, D5, D7, D9, D11 T0106-05 Figure 2. LVDS Mode Timing Copyright © 2007–2011, Texas Instruments Incorporated 11 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 Input Clock www.ti.com CLKM CLKP tPDI Output Clock CLKOUT th tsu Output Data Input Clock DAn, DBn Dn (1) CLKM CLKP tSTART tDV Output Data DAn, DBn Dn (1) (1) Dn – Bits D0, D1, D2, ... of Channels A and B T0107-03 Figure 3. CMOS Mode Timing Input Clock CLKP CLKM tSTART_CHA tSTART_CHB tDV_CHA Output Data PIN DBn tDV_CHB (1) (1) Dn – Bits D0, D1, D2, ... T0107-06 Figure 4. Multiplexed Mode Timing (CMOS Only) 12 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com DEVICE CONFIGURATION ADS62P2X can be configured independently using either parallel interface control or serial interface programming. USING PARALLEL INTERFACE CONTROL ONLY To control the device using the parallel interface, keep RESET tied to high (AVDD). Pins SEN, SCLK, CTRL1, CTRL2 and CTRL3 can be used to directly control certain modes of the ADC. After power-up, the device will automatically get configured as per the parallel pin voltage settings (Table 4 to Table 6). In this mode, SEN and SCLK function as parallel analog control pins, which can be configured using a simple resistor divider (Figure 5). Table 3 has a brief description of the modes controlled by the parallel pins. Table 3. Parallel Pin Definition PIN SCLK SEN CTRL1 CTRL2 CTRL3 TYPE OF PIN Analog control pins (controlled by analog voltage levels, see ) Digital control pins (controlled by digital logic levels) CONTROLS MODES Coarse gain and internal/external reference LVDS/CMOS interface and output data format Together control various power down modes and MUX mode. USING SERIAL INTERFACE PROGRAMMING ONLY To program the device using the serial interface, keep RESET low. Pins SEN, SDATA, and SCLK function as serial interface digital pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by setting bit = 1. After reset, the RESET pin must be kept low. The serial interface section describes the register programming and register reset in more detail. Since the parallel pins (CTRL1, CTRL2, CTRL3) are not used in this mode, they must be tied to ground. USING BOTH SERIAL INTERFACE and PARALLEL CONTROLS For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3) can also be used to configure the device. To allow this, keep RESET low. The parallel interface control pins CTRL1 to CTRL3 are available. After power-up, the device will automatically get configured as per the voltage settings on these pins (Table 6). SEN, SDATA, and SCLK function as serial interface digital pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by setting bit = 1. After reset, the RESET pin must be kept low. The serial interface section describes the register programming and register reset in more detail. Since the power down modes can be controlled using both the parallel pins and serial registers, the priority between the two is determined by bit. When bit = 0, pins CTRL1 to CTRL3 control the power down modes. With = 1, register bits control these modes, over-riding the pin settings. Copyright © 2007–2011, Texas Instruments Incorporated 13 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com DETAILS OF PARALLEL CONFIGURATION ONLY The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is shown in Figure 5. Table 4. SCLK (Analog Control Pin) SCLK DESCRIPTION 0 0dB gain and internal reference (3/8)AVDD 0dB gain and external reference (5/8)2AVDD 3.5dB coarse gain and external reference AVDD 3.5dB coarse gain and internal reference Table 5. SEN (Analog Control Pin) SEN DESCRIPTION 0 2s complement format and DDR LVDS output (3/8)AVDD Straight binary and DDR LVDS output (5/8)AVDD Straight binary and parallel CMOS output AVDD 2s complement format and parallel CMOS output Table 6. CTRL1, CTRL2 and CTRL3 (Digital Control Pins) CTRL1 CTRL2 CTRL3 LOW LOW LOW Normal operation DESCRIPTION LOW LOW HIGH Channel A output buffer disabled LOW HIGH LOW Channel B output buffer disabled LOW HIGH HIGH Channel A and B output buffer disabled HIGH LOW LOW Channel A and B powered down HIGH LOW HIGH Channel A standby HIGH HIGH LOW Channel B standby HIGH HIGH HIGH MUX mode of operation (only with CMOS interface Channel A and B data is multiplexed and output on DB11 to DB0 pins . See multiplexed output mode for detailed description. AVDD (5/8) AVDD 3R (5/8) AVDD GND AVDD 2R (3/8) AVDD (3/8) AVDD 3R To Parallel Pin GND S0321-01 Figure 5. Simple Scheme to Configure Parallel Pins 14 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com SERIAL INTERFACE The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN (Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data). Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The first 8 bits form the register address and the remaining 8 bits the register data. The interface can work with SCLK frequency from 20 MHz down to low speeds (few Hertz), and also with a non-50% SCLK duty cycle. Register Initialization After power-up, the internal registers must be initialized to their default values. This can be done in one of two ways: 1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as shown in Figure 6. OR 2. By applying software reset. Using the serial interface, set the bit to high. This initializes internal registers to their default values and then self-resets the bit to low. In this case the RESET pin is kept low. SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V to 3.3 V, unless otherwise noted. PARAMETER MIN > DC TYP MAX UNIT 20 MHz fSCLK SCLK frequency tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDATA setup time 25 ns tDH SDATA hold time 25 ns Copyright © 2007–2011, Texas Instruments Incorporated 15 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Register Address SDATA A7 A6 A5 A4 A3 A2 Register Data A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 t(DH) t(SCLK) t(DSU) SCLK t(SLOADH) t(SLOADS) SEN RESET T0109-01 Figure 6. Serial Interface Timing RESET TIMING Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, unless otherwise noted. PARAMETER CONDITIONS MIN t1 Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active t2 Reset pulse width t3 tPO TYP MAX UNIT 5 ms Pulse width of active RESET signal 10 ns Register write delay Delay from RESET disable to SEN active 25 Power-up time Delay from power-up of AVDD and DRVDD to output stable ns 7 ms Power Supply AVDD, DRVDD t1 RESET t2 t3 SEN T0108-01 NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET has to be tied permanently HIGH. Figure 7. Reset Timing Diagram 16 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com SERIAL REGISTER MAP Table 7. Summary of Functions Supported by Serial Interface (1) REGISTER ADDRESS REGISTER FUNCTIONS A7–A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0 00 0 0 0 0 0 0 Software Reset 0 0 0 0 0 0 0 10 LVDS buffer current double 0 0 12 0 0 13 0 0 0 0 3.5 dB gain Internal/External reference and MUX mode Bit/Byte wise (LVDS only) Internal termination programmability 14 Over-ride bit 0 LVDS or CMOS interface 16 0 0 0 2s complement or straight binary 17 0 0 0 0 19 0 0 1A 1B Other correction enable 1D 0 1E to 2F 0 0 0 0 to 6 dB gain in 0.5 dB steps Lower 6 bits 18 (1) LVDS buffer current programmability 11 Upper 6 bits Offset correction time constant 0 to 0.5 dB, steps of 0.05 dB 0 In-built or custom coefficients Enable digital filtering 0 0 0 0 Decimate by 2, 4, 8 0 12 coefficients, each 12 bit signed Multiple functions in a register can be programmed in a single write operation. Copyright © 2007–2011, Texas Instruments Incorporated 17 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com DESCRIPTION OF SERIAL REGISTERS Table 8. A7–A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0 00 0 0 0 0 0 0 Software Reset 0 Software reset applied – resets all internal registers and self-clears to 0. D1 1 Table 9. A7–A0 (hex) 10 D7–D6 01 00 11 10 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D1 D0 Output clock buffer drive strength control WEAKER than default drive DEFAULT drive strength STRONGER than default drive strength (recommended for load capacitances > 5 pF) MAXIMUM drive strength (recommended for load capacitances > 5 pF) Table 10. A7–A0 (hex) D7 D6 11 0 0 D5 D4 LVDS buffer current double D3 D2 LVDS CURRENT> LVDS buffer current programmability D1–D0 01 00 11 10 Output data buffer drive strength control WEAKER than default drive DEFAULT drive strength STRONGER than default drive strength (recommended for load capacitances > 5 pF) MAXIMUM drive strength (recommended for load capacitances > 5 pF) D3–D2 00 01 10 11 LVDS Current programmability 3.5 mA 2.5 mA 4.5 mA 1.75 mA D5–D4 00 01 10 11 CURRENT DOUBLE> LVDS Current double control default current, set by LVDS clock buffer current is doubled, 2x LVDS data and clock buffers current are doubled, 2x unused 18 DATAOUT STRENGTH> Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Table 11. A7–A0 (hex) D7 D6 12 0 0 D5 D4 D3 D2 D1 D0 Internal termination programmability D5–D3 000 001 010 011 100 101 110 111 Internal termination control for data outputs No internal termination 300 Ω 180 Ω 110 Ω 150 Ω 100 Ω 81 Ω 60 Ω D2–D0 000 001 010 011 100 101 110 111 Internal termination control for clock output No internal termination 300 Ω 180 Ω 110 Ω 150 Ω 100 Ω 81 Ω 60 Ω Table 12. A7–A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0 13 0 0 0 0 0 0 0 D4 0 1 Offset correction becomes inactive and the last estimated offset value is used to cancel the offset Offset correction active Offset correction inactive Copyright © 2007–2011, Texas Instruments Incorporated 19 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Table 13. A7–A0 (hex) D7 D6 D5 D4 D3 14 Over-ride bit 0 LVDS or CMOS interface 3.5 dB gain Internal / External reference D2 D1 D0 D2-D0 000 001 010 011 100 101 110 111 Normal operation Channel A output buffer disabled Channel B output buffer disabled Channel A and B output buffers disabled Global power down Channel A standby Channel B standby Multiplexed mode, MUX– (only with CMOS interface) Channel A and B data is multiplexed and output on DB11 to DB0 pins. D3 0 1 Reference mode Internal reference enabled External reference enabled D4 0 1 Coarse gain control 0 dB coarse gain 3.5 dB coarse gain D5 0 1 Output interface selection Parallel CMOS data outputs DDR LVDS data outputs D7 Over-ride bit – the LVDS/CMOS selection, power down and MUX modes can also be controlled using parallel pins. By setting = 1, register bits LVDS and will over-ride the settings of the parallel pins. Disable over-ride Enable over-ride 0 1 Table 14. 20 A7–A0 (hex) D7 D6 D5 D4 D3 16 0 0 0 DATA FORMAT> 2s complement or straight binary Bit / Byte wise (LVDS only) D2 D1 D0 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com D2–D0 000 001 010 011 100 101 110 111 Test Patterns to verify capture Normal ADC operation Outputs all zeros Outputs all ones Outputs toggle pattern Outputs digital ramp Outputs custom pattern Unused Unused D3 0 1 Bit-wise/Byte-wise selection (DDR LVDS mode ONLY) Bit wise – Odd bits (D1, D3, D5, D7, D9) on CLKOUT rising edge and even bits (D0, D2, D4, D6, D8, D10) on CLKOUT falling edge Byte wise – Lower 7 bits (D0-D6) at CLKOUT rising edge and upper 4 bits (D7-D10) at CLKOUT falling edge D4 0 1 Data format selection 2s complement Straight binary Copyright © 2007–2011, Texas Instruments Incorporated 21 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Table 15. A7–A0 (hex) D7 D6 D5 D4 17 0 0 0 0 D2–D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Others D3 D2 D1 D0 0 to 6 dB gain in 0.5 dB steps Gain programmability in 0.5 dB steps 0 dB gain, default after reset 0.5 dB gain 1.0 dB gain 1.5 dB gain 2.0 dB gain 2.5 dB gain 3.0 dB gain 3.5 dB gain 4.0 dB gain 4.5 dB gain 5.0 dB gain 5.5 dB gain 6.0 dB gain Unused Table 16. A7–A0 (hex) D7 D6 0 0 D4 D3 D1 D0 Upper 6 bits D7-D2 6 lower bits of custom pattern available at the output instead of ADC data. D5-D0 6 upper bits of custom pattern available at the output instead of ADC data. 22 D2 Lower 6 bits 18 19 D5 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Table 17. A7–A0 (hex) D7 1A D6 D5 D4 D3 Offset correction time constant D2 D1 D0 0 to 0.5 dB, steps of 0.05 dB D2–D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Enables fine gain correction in steps of 0.05 dB (same correction applies to both channels) 0 dB gain, default after reset +0.5 dB gain +0.10 dB gain +0.15 dB gain +0.20 dB gain +0.25 dB gain +0.30 dB gain +0.35 dB gain +0.40 dB gain +0.45 dB gain +0.5 dB gain D6-D4 000 001 010 011 100 101 110 111 Time constant of offset correction in number of clock cycles (seconds, for sampling frequency = 125 MSPS) 227 (1.1 s) 226 (0.55 s) 225 (0.27 s) 224 (0.13 s) 228 (2.15 s) 229 (4.3 s) 227 (1.1 s) 227 (1.1 s) D7 0 1 Default latency, 14 clock cycles Low latency enabled, 10 clock cycles – Digital Processing Block is bypassed. Table 18. A7–A0 (hex) D7 1B Offset correction enable D6 D5 D4 D3 0 In-built or custom coefficients Enable digital filtering Copyright © 2007–2011, Texas Instruments Incorporated D2 D1 D0 Decimate by 2,4,8 23 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com D2-D0 000 001 011 100 Decimation filters Decimate by 2 (pre-defined or user coefficients can be used) Decimate by 4 (pre-defined or user coefficients can be used) No decimation (pre-defined coefficients are disabled, only custom coefficients are available) Decimate by 8 (only custom coefficients are available) D3 0 1 Even taps enabled (24 coefficients) 0 Odd taps enabled (23 coefficients) D4 0 1 Digital filter bypassed Digital filtering enabled D5 0 1 Pre-defined coefficients are loaded in the filter User-defined coefficients are loaded in the filter (coefficients have to be loaded in registers – to - ) D7 0 1 Offset correction disabled Offset correction enabled Table 19. A7–A0 (hex) D7 D6 D5 D4 D3 D2 1D 0 0 0 0 0 0 00 01 10, 11 Decimation filters With decimate by 2, = 000: Low-pass filter (–6 dB frequency at Fs/4) High-pass filter (–6 dB frequency at Fs/4) Unused 00 01 10 11 With decimate by 4, = 001: Low-pass filter (-3 dB frequency at Fs/8) Band-pass filter (center frequency at 3Fs/16) Band-pass filter (center frequency at 5Fs/16) High-pass filter (-3 dB frequency at 3Fs/8) D1-D0 24 D1 D0 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com PIN CONFIGURATION (CMOS MODE) DRVDD DRGND DA6 DA7 DA8 DA9 DA10 DA11 NC CLKOUT DRVDD DRGND NC NC DB0 DB1 DRGND RGC PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 DRVDD DB2 2 47 DA5 DB3 3 46 DA4 DB4 4 45 DA3 DB5 5 44 DA2 DB6 6 43 DA1 DB7 7 42 DA0 DB8 8 41 NC DB9 9 40 NC PAD (Connected to DRGND) 35 CTRL1 SEN 15 34 AVDD 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD AGND AVDD AGND 14 AGND SDATA INP_A CTRL2 INM_A CTRL3 36 AGND 37 13 AGND 12 SCLK CLKM RESET CLKP DRVDD AGND 38 VCM 11 AGND DB11 AGND DRGND INP_B 39 INM_B 10 AGND DB10 P0056-11 Pin Assignments (CMOS INTERFACE) PIN NAME DESCRIPTION PIN NUMBER NUMBER OF PINS 16, 33, 34 3 17, 18, 21, 22, 24, 27, 28, 31, 32 9 Differential input clock 25, 26 2 Differential input signal – channel A. When not used, the analog input pins (INP_A, INM_A) MUST be tied to VCM and CANNOT be floated. 29, 30 2 INM_B, INP_B Differential input signal – channel B. When not used, the analog input pins (INP_A, INM_A) MUST be tied to VCM and CANNOT be floated. 19, 20 2 VCM Internal reference mode – Common-mode voltage output. External reference mode – Reference input. The voltage forced on this pin sets the ADC internal references. 23 1 RESET Serial interface RESET input. In serial interface mode, the user must initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset (refer to Serial Interface section). In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK, SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100 kΩ pull-down resistor. 12 1 SCLK This pin functions as serial interface clock input when RESET is low. It functions as analog control pin when RESET is tied high and controls coarse gain and internal/external reference selection. See Table 4 for details. The pin has an internal pull-down resistor to ground. 13 1 SDATA This pin functions as serial interface data input when RESET is low. The pin has an internal pull-down resistor to ground. 14 1 AVDD Analog power supply AGND Analog ground CLKP, CLKM INM_A, INP_A Copyright © 2007–2011, Texas Instruments Incorporated 25 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Pin Assignments (CMOS INTERFACE) (continued) DESCRIPTION PIN NUMBER NUMBER OF PINS SEN PIN NAME This pin functions as serial interface enable input when RESET is low. It functions as analog control pin when RESET is tied high and controls the output interface (LVDS/CMOS) and data format selection. See Table 5 for details. The pin has an internal pull-up resistor to AVDD. 15 1 CTRL1 These are digital logic input pins. Together they control various power down and multiplexed mode. see Table 6 for details 35 1 36 1 CTRL2 CTRL3 37 1 DA11 to DA0 Channel A 12-bit data outputs, CMOS 42-47, 50-55 12 DB11 to DB0 Channel B 12-bit data outputs, CMOS 62-63, 2-11 12 CLKOUT CMOS output clock 57 1 DRVDD Digital supply 1, 38, 48, 58 4 DRGND Digital ground 39, 49, 59, 64 and PAD 4 PAD Digital ground. Solder the pad to the digital ground on the board using multiple vias for good electrical and thermal performance. – 1 NC Do not connect 40,41,60,61,56 5 26 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com PIN CONFIGURATION (LVDS MODE) DRVDD DRGND DA6M DA6P DA8M DA8P DA10M DA10P CLKOUTM CLKOUTP DRVDD DRGND NC NC DB0M DB0P DRGND RGC PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 DRVDD DB2M 2 47 DA4P DB2P 3 46 DA4M DB4M 4 45 DA2P DB4P 5 44 DA2M DB6M 6 43 DA0P DB6P 7 42 DA0M DB8M 8 41 NC DB8P 9 40 NC PAD (Connected to DRGND) CTRL2 SDATA 14 35 CTRL1 SEN 15 34 AVDD 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD AGND AVDD AGND 36 AGND 13 INP_A SCLK INM_A CTRL3 AGND 37 AGND 12 CLKM RESET CLKP DRVDD AGND 38 VCM 11 AGND DB10P AGND DRGND INP_B 39 INM_B 10 AGND DB10M P0056-12 Pin Assignments (LVDS INTERFACE) PIN NAME DESCRIPTION PIN NUMBER NUMBER OF PINS AVDD Analog power supply 16, 33, 34 3 AGND Analog ground 17, 18, 21, 22, 24, 27, 28, 31,32 9 CLKP, CLKM Differential input clock 25, 26 2 INM_A, INP_A Differential input signal – Channel A. When not used, the analog input pins (INP_A, INM_A) MUST be tied to VCM and CANNOT be floated. 29, 30 2 INM_B, INP_B Differential input signal – Channel B. When not used, the analog input pins (INP_B, INM_B) MUST be tied to VCM and CANNOT be floated 19, 20 2 VCM Internal reference mode – Common-mode voltage output. External reference mode – Reference input. The voltage forced on this pin sets the ADC internal references. 23 1 RESET Serial interface RESET input. In serial interface mode, the user must initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset (refer to Serial Interface section). In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK, SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100 kΩ pull-down resistor. 12 1 Copyright © 2007–2011, Texas Instruments Incorporated 27 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Pin Assignments (LVDS INTERFACE) (continued) PIN NAME DESCRIPTION PIN NUMBER NUMBER OF PINS SCLK This pin functions as serial interface clock input when RESET is low. It functions as analog control pin when RESET is tied high and controls coarse gain and internal/external reference selection. See Table 4 for details. The pin has an internal pull-down resistor to ground. 13 1 SDATA This pin functions as serial interface data input when RESET is low. The pin has an internal pull-down resistor to ground. 14 1 SEN This pin functions as serial interface enable input when RESET is low. It functions as analog control pin when RESET is tied high and controls the output interface (LVDS/CMOS) and data format selection. See Table 5 for details. The pin has an internal pull-up resistor to AVDD. 15 1 CTRL1 These are digital logic input pins. Together they control various power down and multiplexed mode. See Table 6 for details. 35 1 36 1 37 1 CTRL2 CTRL3 DA0P Channel A Differential output data D0 and D1 multiplexed, true 43 1 DA0M Channel A Differential output data D0 and D1 multiplexed, complement 42 1 DA2P Channel A Differential output data D2 and D3 multiplexed, true 45 1 DA2M Channel A Differential output data D2 and D3 multiplexed, complement 44 1 DA4P Channel A Differential output data D4 and D5 multiplexed, true 47 1 DA4M Channel A Differential output data D4 and D5 multiplexed, complement 46 1 DA6P Channel A Differential output data D6 and D7 multiplexed, true 51 1 DA6M Channel A Differential output data D6 and D7 multiplexed, complement 50 1 DA8P Channel A Differential output data D8 and D9 multiplexed, true 53 1 DA8M Channel A Differential output data D8 and D9 multiplexed, complement 52 1 DA10P Channel A Differential output data D10 and D11 multiplexed, true 55 1 DA10M Channel A Differential output data D10 and D11 multiplexed, complement 54 1 CLKOUTP Differential output clock, true 57 1 CLKOUTM Differential output clock, complement 56 1 DB0P Channel B Differential output data D0 and D1 multiplexed, true 63 1 DB0M Channel B Differential output data D0 and D1 multiplexed, complement 62 1 DB2P Channel B Differential output data D2 and D3 multiplexed, true 3 1 DB2M Channel B Differential output data D2 and D3 multiplexed, complement 2 1 DB4P Channel B Differential output data D4 and D5 multiplexed, true 5 1 DB4M Channel B Differential output data D4 and D5 multiplexed, complement 4 1 DB6P Channel B Differential output data D6 and D7 multiplexed, true 7 1 DB6M Channel B Differential output data D6 and D7 multiplexed, complement 6 1 DB8P Channel B Differential output data D8 and D9 multiplexed, true 9 1 DB8M Channel B Differential output data D8 and D9 multiplexed, complement 8 1 DB10P Channel B Differential output data D10 and D11 multiplexed, true 11 1 DB10M Channel B Differential output data D10 and D11 multiplexed, complement 10 1 DRVDD Digital supply 1, 38, 48, 58 4 DRGND Digital ground 39, 49, 59, 64 and PAD 4 PAD Digital ground. Solder the pad to the digital ground on the board using multiple vias for good electrical and thermal performance. – 1 NC Do not connect 40, 41, 60, 61 4 28 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - ADS62P25 (FS= 125 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 88.31 dBc SINAD = 70.95 dBFS SNR = 71.03 dBFS THD = 87.1 dBc −20 −40 Amplitude − dB Amplitude − dB −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 40 50 60 f − Frequency − MHz 0 10 20 30 50 60 G002 Figure 8. Figure 9. FFT for 190 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 SFDR = 78.88 dBc SINAD = 69.49 dBFS SNR = 70.11 dBFS THD = 77.27 dBc −20 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = –88.5 dBFS SFDR = –96.08 dBFS −20 −40 Amplitude − dB −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 40 50 60 f − Frequency − MHz 0 10 20 30 40 50 60 f − Frequency − MHz G003 Figure 10. G004 Figure 11. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 74 94 92 73 Gain = 3.5 dB 90 72 88 SNR − dBFS SFDR − dBc 40 f − Frequency − MHz G001 0 Amplitude − dB SFDR = 86.51 dBc SINAD = 70.88 dBFS SNR = 71.01 dBFS THD = 85.12 dBc −20 86 84 82 70 Gain = 3.5 dB 69 68 Gain = 0 dB 80 Gain = 0 dB 71 67 78 76 66 0 25 50 75 100 125 150 fIN − Input Frequency − MHz Figure 12. Copyright © 2007–2011, Texas Instruments Incorporated 175 200 G005 0 25 50 75 100 125 150 fIN − Input Frequency − MHz 175 200 G006 Figure 13. 29 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - ADS62P25 (FS= 125 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY (LVDS interface) SFDR vs INPUT FREQUENCY ACROSS GAIN 94 94 92 92 4 dB Input adjusted to get −1dBFS input 90 88 88 SFDR − dBc 86 84 86 84 82 5 dB 82 Gain = 0 dB 80 78 78 76 76 0 25 50 75 100 125 150 175 200 fIN − Input Frequency − MHz 6 dB 1 dB 0 dB 0 25 50 G007 Figure 14. SINAD vs INPUT FREQUENCY ACROSS GAIN Input adjusted to get −1dBFS input 0 dB 89 71 SINAD − dBFS 150 175 200 G009 PERFORMANCE vs AVDD 1 dB 2 dB SFDR − dBc 3 dB 70 69 68 67 4 dB 66 5 dB 0 20 40 60 76 fIN = 70.1 MHz DRVDD = 3.3 V 75 SFDR 88 74 87 73 86 80 85 71 84 70 83 69 82 3.0 100 120 140 160 180 200 fIN − Input Frequency − MHz 3.1 3.2 PERFORMANCE vs DRVDD fIN = 70.1 MHz AVDD = 3.3 V G011 89 75 fIN = 70.1 MHz 75 88 74 73 86 72 SNR 85 71 84 70 83 69 3.4 DRVDD − Supply Voltage − V Figure 18. 3.5 68 3.6 SFDR − dBc 87 SNR − dBFS 74 SFDR 3.3 68 3.6 3.5 PERFORMANCE vs TEMPERATURE 76 3.2 3.4 Figure 17. 90 3.1 3.3 AVDD − Supply Voltage − V G010 Figure 16. 88 72 SNR 6 dB 65 SFDR − dBc 125 90 72 30 100 Figure 15. 73 82 3.0 75 fIN − Input Frequency − MHz SNR − dBFS 80 89 3 dB 2 dB 87 86 72 SNR 85 71 84 70 83 −40 G012 73 SFDR SNR − dBFS SFDR − dBc Gain = 3.5 dB 90 69 −20 0 20 40 T − Temperature − °C 60 80 G013 Figure 19. Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - ADS62P25 (FS= 125 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE 94 85 92 90 80 90 74 80 75 88 73 70 SNR (dBFS) 60 65 50 SFDR (dBc) 40 30 −60 fIN = 20.1 MHz −50 −40 −30 −20 −10 72 SNR 71 60 82 70 55 80 69 50 78 0.5 0 1.0 1.5 2.0 2.5 Figure 20. Figure 21. PERFORMANCE vs INPUT CLOCK DUTY CYCLE OUTPUT NOISE HISTOGRAM (INPUTS TIED TO COMMON-MODE) fIN = 20.1 MHz 90 68 3.0 Input Clock Amplitude − VPP G014 94 77 70 76 60 G015 75 88 74 86 73 84 72 SNR 82 71 80 70 78 69 76 SNR − dBFS SFDR SFDR − dBc 75 SFDR 84 Input Amplitude − dBFS 92 fIN = 20.1 MHz 86 Occurence − % SFDR − dBc, dBFS 70 76 SNR − dBFS SFDR (dBFS) 100 SFDR − dBc 90 SNR − dBFS 110 50 40 30 20 10 68 30 35 40 45 50 55 60 65 0 70 Input Clock Duty Cycle − % 2040 2041 2042 2043 2044 2045 2046 2047 2048 Output Code G016 Figure 22. G017 Figure 23. PERFORMANCE IN EXTERNAL REFERENCE MODE 93 78 fIN = 20.1 MHz External Reference Mode SFDR 76 89 74 87 72 SNR 85 83 1.35 SNR − dBFS SFDR − dBc 91 70 1.40 1.45 1.50 1.55 VVCM − VCM Voltage − V 1.60 68 1.65 G018 Figure 24. Copyright © 2007–2011, Texas Instruments Incorporated 31 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - ADS62P24 (FS= 105 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 88.38 dBc SINAD = 71.02 dBFS SNR = 71.09 dBFS THD = 87.61 dBc −20 −40 Amplitude − dB Amplitude − dB −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 40 50 f − Frequency − MHz 0 10 20 30 40 50 f − Frequency − MHz G019 G020 Figure 25. Figure 26. FFT for 190 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 0 SFDR = 82.51 dBc SINAD = 69.71 dBFS SNR = 70.04 dBFS THD = 80.13 dBc −20 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = –87 dBFS SFDR = –90 dBFS −20 −40 Amplitude − dB −40 Amplitude − dB SFDR = 84.17 dBc SINAD = 70.8 dBFS SNR = 71.01 dBFS THD = 83 dBc −20 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 40 50 f − Frequency − MHz 0 10 20 30 40 50 f − Frequency − MHz G021 Figure 27. G022 Figure 28. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 74 98 96 Gain = 3.5 dB 73 94 SNR − dBFS SFDR − dBc 92 90 88 86 84 72 Gain = 0 dB 71 70 Gain = 3.5 dB 82 80 69 Gain = 0 dB 78 68 76 0 25 50 75 100 125 150 fIN − Input Frequency − MHz Figure 29. 32 175 200 G023 0 25 50 75 100 125 150 fIN − Input Frequency − MHz 175 200 G024 Figure 30. Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - ADS62P24 (FS= 105 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY (LVDS interface) SFDR vs INPUT FREQUENCY ACROSS GAIN 96 96 94 94 Gain = 3.5 dB 92 86 88 86 84 84 80 80 78 78 25 50 75 100 125 150 175 200 fIN − Input Frequency − MHz 6 dB 0 25 50 G025 SINAD vs INPUT FREQUENCY ACROSS GAIN 125 150 175 200 G027 PERFORMANCE vs AVDD 88 Input adjusted to get −1dBFS input 0 dB 72 87 1 dB 2 dB 3 dB 70 69 68 67 4 dB 66 5 dB 25 50 75 SFDR 74 85 73 84 72 SNR 83 71 82 70 81 69 6 dB 80 3.0 65 0 76 fIN = 70.1 MHz DRVDD = 3.31 V 86 SFDR − dBc 71 SINAD − dBFS 100 Figure 32. 73 75 100 125 150 fIN − Input Frequency − MHz 175 200 3.1 3.2 3.3 3.4 68 3.6 3.5 AVDD − Supply Voltage − V G028 Figure 33. G029 Figure 34. PERFORMANCE vs DRVDD 90 PERFORMANCE vs TEMPERATURE 77 fIN = 70.1 MHz AVDD = 3.31 V 76 89 75 88 74 87 74 SFDR 86 73 85 72 SNR 84 71 83 70 3.1 3.2 3.3 3.4 DRVDD − Supply Voltage − V Figure 35. Copyright © 2007–2011, Texas Instruments Incorporated 3.5 SFDR − dBc 75 SNR − dBFS 88 SFDR − dBc 75 fIN − Input Frequency − MHz Figure 31. 82 3.0 1 dB 0 dB 87 73 SFDR 86 72 SNR 85 71 84 SNR − dBFS 0 4 dB 82 Gain = 0 dB SNR − dBFS 82 89 3 dB 90 SFDR − dBc 88 2 dB 5 dB 92 90 SFDR − dBc Input adjusted to get −1dBFS input 70 fIN = 70.1 MHz 69 3.6 83 −40 G030 69 −20 0 20 40 T − Temperature − °C 60 80 G031 Figure 36. 33 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - ADS62P24 (FS= 105 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE 90 94 100 85 92 90 80 90 77 70 70 SNR (dBFS) 60 65 50 SFDR (dBc) 40 30 −60 fIN = 20.1 MHz −50 −40 −30 −20 −10 75 SFDR 74 86 73 84 72 SNR 82 71 55 80 70 50 78 0.0 0.5 1.0 1.5 2.0 2.5 Figure 37. Figure 38. PERFORMANCE vs INPUT CLOCK DUTY CYCLE OUTPUT NOISE HISTOGRAM WITH INPUTS TIED TO COMMON-MODE 79 60 50 76 86 75 84 74 82 73 80 72 SNR 78 Occurence − % 77 88 76 40 30 20 10 71 70 40 G033 78 SFDR 90 35 69 3.0 Input Clock Amplitude − VPP G032 fIN = 20.1 MHz 30 76 88 0 94 92 fIN = 20.1 MHz 60 Input Amplitude − dBFS SFDR − dBc SFDR − dBc 75 SNR − dBFS 80 SNR − dBFS SFDR − dBc, dBFS SFDR (dBFS) SNR − dBFS 110 45 50 55 60 65 0 70 Input Clock Duty Cycle − % 2040 2041 2042 2043 2044 2045 2046 2047 2048 Output Code G034 Figure 39. G035 Figure 40. PERFORMANCE IN EXTERNAL REFERENCE MODE 95 79 fIN = 20.1 MHz External Reference Mode 77 SFDR − dBc SFDR 91 75 89 73 SNR − dBFS 93 SNR 87 85 1.35 71 1.40 1.45 1.50 1.55 VVCM − VCM Voltage − V 1.60 69 1.65 G036 Figure 41. 34 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - ADS62P23 (FS= 80 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 89.61 dBc SINAD = 71.22 dBFS SNR = 71.44 dBFS THD = 83.3 dBc −20 −40 Amplitude − dB Amplitude − dB −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 40 f − Frequency − MHz 0 10 20 30 40 f − Frequency − MHz G037 G038 Figure 42. Figure 43. FFT for 190 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 0 SFDR = 84.12 dBc SINAD = 70.22 dBFS SNR = 70.45 dBFS THD = 82.11 dBc −20 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = –93 dBFS SFDR = –98 dBFS −20 −40 Amplitude − dB −40 Amplitude − dB SFDR = 90.05 dBc SINAD = 71.19 dBFS SNR = 71.25 dBFS THD = 89.09 dBc −20 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 40 f − Frequency − MHz 0 10 20 30 40 f − Frequency − MHz G039 Figure 44. G040 Figure 45. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 74 98 96 73 Gain = 3.5 dB 92 SNR − dBFS SFDR − dBc 94 90 88 72 Gain = 0 dB 71 70 86 Gain = 3.5 dB Gain = 0 dB 84 69 82 80 68 0 25 50 75 100 125 150 fIN − Input Frequency − MHz Figure 46. Copyright © 2007–2011, Texas Instruments Incorporated 175 200 G041 0 25 50 75 100 125 150 fIN − Input Frequency − MHz 175 200 G042 Figure 47. 35 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - ADS62P23 (FS= 80 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY (LVDS interface) SFDR vs INPUT FREQUENCY ACROSS GAIN 98 98 96 96 94 88 90 88 86 86 6 dB Gain = 0 dB 84 84 82 82 80 80 1 dB 2 dB 0 dB 50 75 100 125 150 175 200 fIN − Input Frequency − MHz 0 25 50 G043 Figure 48. SINAD vs INPUT FREQUENCY ACROSS GAIN 94 0 dB 1 dB 175 200 G045 69 68 4 dB 5 dB 6 dB 25 50 75 100 125 75 150 fIN − Input Frequency − MHz 175 90 74 88 73 86 200 72 SNR 84 71 82 70 80 3.0 65 0 76 SFDR 70 66 77 fIN = 70.1 MHz DRVDD = 3.31 V 92 3 dB SFDR − dBc SINAD − dBFS 2 dB 71 67 3.1 3.2 3.3 3.4 69 3.6 3.5 AVDD − Supply Voltage − V G046 Figure 50. G047 Figure 51. PERFORMANCE vs DRVDD 96 PERFORMANCE vs TEMPERATURE 77 fIN = 70.1 MHz AVDD = 3.31 V 92 76 76 fIN = 70.1 MHz SFDR 90 75 90 74 SFDR 88 73 86 72 SNR 84 71 82 70 3.1 3.2 3.3 3.4 DRVDD − Supply Voltage − V Figure 52. 3.5 SFDR − dBc 75 SNR − dBFS 92 SFDR − dBc 150 PERFORMANCE vs AVDD Input adjusted to get −1dBFS input 72 36 125 96 73 80 3.0 100 Figure 49. 74 94 75 fIN − Input Frequency − MHz SNR − dBFS 25 88 74 86 73 84 72 SNR − dBFS 0 3 dB 92 SFDR − dBc 90 5 dB 4 dB 94 Gain = 3.5 dB 92 SFDR − dBc Input adjusted to get −1dBFS input SNR 82 69 3.6 80 −40 G048 71 70 −20 0 20 40 T − Temperature − °C 60 80 G049 Figure 53. Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - ADS62P23 (FS= 80 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE 92 80 90 75 SNR (dBFS) fIN = 20.1 MHz 76 75 SFDR 88 74 86 73 70 70 60 65 50 60 82 71 55 80 70 50 78 0.0 SFDR (dBc) 40 fIN = 20.1 MHz 30 −60 −50 −40 −30 −20 −10 1.0 1.5 2.0 2.5 Figure 55. PERFORMANCE vs INPUT CLOCK DUTY CYCLE OUTPUT NOISE HISTOGRAM WITH INPUTS TIED TO COMMON-MODE SFDR 90 78 90 77 80 76 70 75 88 74 86 73 84 72 SNR Occurence − % 92 50 40 30 71 20 80 70 10 78 69 0 35 40 45 50 55 60 65 70 75 Input Clock Duty Cycle − % G051 60 82 30 69 3.0 Input Clock Amplitude − VPP G050 fIN = 20.1 MHz 25 0.5 72 Figure 54. 96 94 SNR 84 0 Input Amplitude − dBFS SFDR − dBc 77 SNR − dBFS 80 85 SNR − dBFS SFDR − dBc, dBFS 90 94 SFDR − dBc SFDR (dBFS) 100 90 SNR − dBFS 110 2040 2041 2042 2043 2044 2045 2046 2047 2048 Output Code G052 Figure 56. G053 Figure 57. PERFORMANCE IN EXTERNAL REFERENCE MODE 92 80 fIN = 20.1 MHz External Reference Mode 78 SFDR 88 76 86 74 84 82 1.35 72 SNR 1.40 1.45 SNR − dBFS SFDR − dBc 90 1.50 1.55 VVCM − VCM Voltage − V 1.60 70 1.65 G054 Figure 58. Copyright © 2007–2011, Texas Instruments Incorporated 37 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - ADS62P22 (FS= 65 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 87.17 dBc SINAD = 71.33 dBFS SNR = 71.43 dBFS THD = 86.73 dBc −20 −40 Amplitude − dB Amplitude − dB −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 f − Frequency − MHz 0 10 20 30 f − Frequency − MHz G055 G056 Figure 59. Figure 60. FFT for 190 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 0 SFDR = 81.79 dBc SINAD = 69.64 dBFS SNR = 69.89 dBFS THD = 81.28 dBc −20 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.3 MHz, –7 dBFS 2-Tone IMD = –92 dBFS SFDR = –94.5 dBFS −20 −40 Amplitude − dB −40 Amplitude − dB SFDR = 87.71 dBc SINAD = 71.21 dBFS SNR = 71.29 dBFS THD = 87.42 dBc −20 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 10 20 30 f − Frequency − MHz 0 10 20 30 f − Frequency − MHz G057 Figure 61. G058 Figure 62. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 74 98 96 73 Gain = 3.5 dB 92 SNR − dBFS SFDR − dBc 94 90 88 72 Gain = 0 dB 71 70 86 84 Gain = 0 dB Gain = 3.5 dB 69 82 80 68 0 25 50 75 100 125 150 fIN − Input Frequency − MHz Figure 63. 38 175 200 G059 0 25 50 75 100 125 150 fIN − Input Frequency − MHz 175 200 G060 Figure 64. Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - ADS62P22 (FS= 65 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY (LVDS interface) 98 96 96 94 94 90 88 Input adjusted to get −1dBFS input 4 dB 5 dB 92 SFDR − dBc Gain = 3.5 dB 92 SFDR − dBc SFDR vs INPUT FREQUENCY ACROSS GAIN 98 3 dB 90 88 86 86 6 dB 84 Gain = 0 dB 82 82 80 80 25 50 75 100 125 150 175 200 fIN − Input Frequency − MHz 0 25 50 G061 SINAD vs INPUT FREQUENCY ACROSS GAIN 150 175 200 G063 PERFORMANCE vs AVDD Input adjusted to get −1dBFS input 0 dB 94 1 dB SFDR − dBc 70 69 68 4 dB 5 dB 6 dB 25 50 75 100 125 150 fIN − Input Frequency − MHz 75 175 90 74 88 73 86 200 71 82 70 3.1 3.2 PERFORMANCE vs DRVDD fIN = 70.1 MHz AVDD = 3.31 V 76 fIN = 70.1 MHz 91 75 SFDR 74 89 73 72 SNR 87 71 86 70 3.4 DRVDD − Supply Voltage − V Figure 69. Copyright © 2007–2011, Texas Instruments Incorporated 3.5 SFDR − dBc 90 SNR − dBFS 75 SFDR 3.3 G065 92 76 3.2 69 3.6 3.5 PERFORMANCE vs TEMPERATURE 77 3.1 3.4 Figure 68. 93 88 3.3 AVDD − Supply Voltage − V G064 Figure 67. 91 72 SNR 84 80 3.0 66 0 76 SFDR 3 dB 67 77 fIN = 70.1 MHz DRVDD = 3.31 V 92 2 dB 71 SINAD − dBFS 125 96 72 SFDR − dBc 100 Figure 66. 73 85 3.0 75 fIN − Input Frequency − MHz Figure 65. 92 2 dB 1 dB SNR − dBFS 0 0 dB 90 74 89 73 88 72 SNR 87 69 3.6 86 −40 G066 SNR − dBFS 84 71 70 −20 0 20 40 T − Temperature − °C 60 80 G067 Figure 70. 39 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - ADS62P22 (FS= 65 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE SFDR (dBFS) 85 92 SNR (dBFS) 80 75 70 70 60 65 50 SFDR (dBc) 40 −50 −40 −30 −20 −10 73 SNR 86 72 71 60 82 70 55 80 69 50 78 0.0 0.5 1.0 1.5 2.0 2.5 Figure 72. PERFORMANCE vs INPUT CLOCK DUTY CYCLE OUTPUT NOISE HISTOGRAM WITH INPUTS TIED TO COMMON-MODE fIN = 20.1 MHz 78 80 77 70 76 75 92 74 90 73 88 72 SNR 50 40 30 86 71 20 84 70 10 69 0 82 30 35 40 45 50 55 60 65 70 75 Input Clock Duty Cycle − % G069 60 Occurence − % SFDR 94 68 3.0 Input Clock Amplitude − VPP G068 Figure 71. 96 SFDR − dBc 88 0 100 25 74 84 Input Amplitude − dBFS 98 75 SFDR fIN = 20.1 MHz fIN = 20.1 MHz 30 −60 76 90 SFDR − dBc 80 SNR − dBFS 90 94 SNR − dBFS SFDR − dBc, dBFS 100 90 SNR − dBFS 110 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 Output Code G070 Figure 73. G071 Figure 74. PERFORMANCE IN EXTERNAL REFERENCE MODE 95 80 fIN = 20.1 MHz External Reference Mode 93 78 91 76 89 74 SNR 87 85 1.35 1.40 1.45 1.50 SNR − dBFS SFDR − dBc SFDR 72 1.55 VVCM − VCM Voltage − V 1.60 70 1.65 G072 Figure 75. 40 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS - LOW SAMPLING FREQUENCIES All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FS = 25 MSPS SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 110 78 76 74 Gain = 3.5 dB SNR − dBFS SFDR − dBc 100 90 80 Gain = 0 dB Gain = 0 dB 72 70 Gain = 3.5 dB 68 70 66 60 64 0 25 50 75 100 125 150 175 fIN − Input Frequency − MHz 200 0 25 50 75 100 125 150 fIN − Input Frequency − MHz G075 Figure 76. 175 200 G076 Figure 77. COMMON PLOTS All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) POWER DISSIPATION vs SAMPLING FREQUENCY (DDR LVDS and CMOS) COMMON-MODE REJECTION RATIO vs FREQUENCY 0.8 0.7 PD − Power Dissipation − W 0 −10 −20 CMRR − dBc −30 −40 −50 −60 −70 −80 fIN = 2.5 MHz CL = 5 pF 0.6 0.5 LVDS 0.4 0.3 CMOS 0.2 0.1 −90 0.0 −100 0 50 100 150 200 f − Frequency − MHz Figure 78. Copyright © 2007–2011, Texas Instruments Incorporated 250 300 G077 0 25 50 75 100 fS − Sampling Frequency − MSPS 125 G078 Figure 79. 41 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com COMMON PLOTS (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) DRVDD current (CMOS interface) vs SAMPLING FREQUENCY across load capacitance 30 1.8 V, No Load DRVDD Current − mA 25 1.8 V, 5 pF 20 3.3 V, No Load 3.3 V, 5 pF 15 3.3 V, 10 pF 10 5 0 0 25 50 75 100 fS − Sampling Frequency − MSPS 125 G079 Figure 80. 42 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION ADS62P2X is a low power 12-bit dual channel pipeline ADC family fabricated in a CMOS process using switched capacitor techniques. The conversion process is initiated by a rising edge of the external input clock. Once the signal is captured by the input sample and hold, the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline resulting in a data latency of 14 clock cycles. The output is available as 12-bit data, in DDR LVDS or CMOS and coded in either straight offset binary or binary 2s complement format. ANALOG INPUT The analog input consists of a switched-capacitor based differential sample and hold architecture. This differential topology results in very good AC performance even for high input frequencies at high sampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM pin 13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2 VPP differential input swing. The maximum swing is determined by the internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal). Sampling Switch Lpkg » 2 nH Sampling Capacitor RCR Filter INP Cbond » 1 pF 25 W Resr 100 W Cpar2 1 pF 50 W 3.2 pF Ron 15 W Cpar1 0.8 pF Csamp 4 pF Ron 10 W 50 W Lpkg » 2 nH Ron 15 W 25 W Csamp 4 pF INM Cbond » 1 pF Resr 100 W Sampling Capacitor Cpar2 1 pF Sampling Switch S0322-01 Figure 81. Analog Input Equivalent Circuit The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins to the sampled voltage). Copyright © 2007–2011, Texas Instruments Incorporated 43 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com 1 0 Magnitude − dB −1 −2 −3 −4 −5 −6 −7 0 100 200 300 400 500 fI − Input Frequency − MHz 600 G080 Figure 82. ADC Analog Bandwidth Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection. A < 5 Ω resistor in series with each input pin is recommended to damp out ringing caused by the package parasitics. It is also necessary to present low impedance (50 Ω) for the common mode switching currents. This can be achieved by using two resistors from each input terminated to the common mode voltage (VCM). In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While doing this, the ADC input impedance must be considered. Figure 83 and Figure 84 show the impedance (Zin = Rin || Cin) looking into the ADC input pins. R − Resistance − kΩ 100 10 1 0.1 0.01 0 100 200 300 400 f − Frequency − MHz 500 600 G081 Figure 83. ADC Analog Input Resistance (Rin) Across Frequency 44 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com 9 C − Capacitance − pF 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 f − Frequency − MHz 600 G082 Figure 84. ADC Analog Input Capacitance (Cin) Across Frequency Using RF-Transformer Based Drive Circuits Figure 85 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that can be used for low input frequencies (about 100 MHz). The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two resistors connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the termination resistors (connected to common mode) has to be low ( < 100 Ω) to provide a low-impedance path for the ADC common-mode switching currents. ADS62P2x 0.1 mF INP 0.1 mF 25 W 25 W INM 1:1 VCM S0163-04 Figure 85. Drive Circuit at Low Input Frequencies At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 86 shows an example using two transformers (Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the shaded box) may be required between the two transformers to improve the balance between the P and M sides. The center point of this termination must be connected to ground. Copyright © 2007–2011, Texas Instruments Incorporated 45 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com ADS62P2x 0.1 mF INP 50 W 0.1 mF 50 W 50 W 50 W INM 1:1 1:1 VCM S0164-07 Figure 86. Drive Circuit at High Input Frequencies Using Differential Amplifier Drive Circuits Figure 87 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to differential output that can be interface to the ADC analog input pins. In addition to the single-ended to differential conversion, the amplifier also provides gain (10 dB). RFIL helps to isolate the amplifier outputs from the switching input of the ADC. Together with CFIL it also forms a low-pass filter that band-limits the noise (and signal) at the ADC input. As the amplifier output is ac-coupled, the common-mode voltage of the ADC input pins is set using two 200 Ω resistors connected to VCM. The amplifier output can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC input pins can be biased to 1.5 V. In this case, use +4 V and –1 V supplies for the THS4509 so that its output common-mode voltage (1.5 V) is at mid-supply. RF +VS 500 W 0.1 mF RS 0.1 mF 10 mF RFIL ADS62P2x 0.1 mF 5W INP RG 0.1 mF RT CFIL 200 W CFIL 200 W CM THS4509 RG RFIL INM RS || RT 0.1 mF 5W 0.1 mF 500 W VCM –VS 0.1 mF 10 mF 0.1 mF RF S0259-04 Figure 87. Drive Circuit Using the THS4509 46 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Input Common-Mode To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1 μF low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC sinks a common-mode current in the order of 165 μA (at 125 MSPS). Equation 1 describes the dependency of the common-mode current and the sampling frequency. 165 mA Fs 125 MSPS (1) This equation helps to design the output capability and impedance of the CM driving circuit accordingly. REFERENCE ADS62P2X has built-in internal references REFP and REFM, requiring no external components. Design schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the requisite reference capacitors eliminates the need for external decoupling. The full-scale input range of the converter can be controlled in the external reference mode as explained below. The internal or external reference modes can be selected by programming the serial interface register bit ( REF). INTREF Internal Reference VCM 1 kW INTREF 4 kW EXTREF REFM REFP ADS62P2x S0165-07 Figure 88. Reference Section Internal Reference When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog input pins. External Reference When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential input voltage corresponding to full-scale is given in Equation 2. Full-scale differential input pp = (Voltage forced on VCM) × 1.33 Copyright © 2007–2011, Texas Instruments Incorporated (2) (2) 47 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. COARSE GAIN AND PROGRAMMABLE FINE GAIN ADS62P2X includes gain settings that can be used to get improved SFDR performance (over 0 dB gain mode). For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 20. The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The fine gain is programmable in 0.5 dB steps from 0 to 6 dB; however the SFDR improvement is achieved at the expense of SNR. So, the programmable fine gain makes it possible to trade-off between SFDR and SNR. The coarse gain makes it possible to get best SFDR but without losing SNR significantly. The gains can be programmed using the serial interface (bits COARSE GAIN and FINE GAIN). Note that the default gain after reset is 0 dB. Table 20. Full-Scale Range Across Gains GAIN, dB TYPE FULL-SCALE, VPP 0 Default after reset 2V 3.5 Coarse (fixed) 1.34 0.5 1.89 1.0 1.78 1.5 1.68 2.0 1.59 2.5 1.50 3.0 3.5 Fine (programmable) 1.42 1.34 4.0 1.26 4.5 1.19 5.0 1.12 5.5 1.06 6.0 1.00 CLOCK INPUT The clock inputs can be driven differentially (sine, LVPECL or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5 kΩ resistors as shown in Figure 89. This allows using transformer-coupled drive circuits for sine wave clock or ac-coupling for LVPECL, LVDS clock sources (Figure 91 and Figure 92). 48 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Clock Buffer Lpkg » 2 nH 10 W CLKP Cbond » 1 pF Ceq Ceq 5 kW Resr » 100 W VCM 6 pF 5 kW Lpkg » 2 nH 10 W CLKM Cbond » 1 pF Resr » 100 W Ceq » 1 to 3 pF, equivalent input capacitance of clock buffer S0275-02 Figure 89. Internal Clock Buffer 100k Impedance − Ω 10k 1k 100 10 5 25 45 65 85 105 fS − Sampling Frequency − MSPS 125 G083 Figure 90. Clock Input Impedance Copyright © 2007–2011, Texas Instruments Incorporated 49 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com 0.1 mF CLKP Differential Sine-Wave or PECL or LVDS Clock Input 0.1 mF CLKM ADS62P2x S0167-07 Figure 91. Differential Clock Driving Circuit Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 92. 0.1 mF CMOS Clock Input CLKP 0.1 mF CLKM ADS62P2x S0168-11 Figure 92. Single-Ended Clock Driving Circuit For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input. 50 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com POWER DOWN ADS62P2X has three powerdown modes – powerdown global, individual channel standby and individual channel output buffer disable. These can be set using either the serial register bits or using the control pins CTRL1 to CTRL3. Table 21. Power Down Modes CONFIGURE USING POWERDOWN MODES SERIAL INTERFACE PARALLEL CONTROL PINS WAKE-UP TIME CTRL1 CTRL2 CTRL3 Normal operation 000 low low low — Channel A output buffer disabled 001 low low high Fast (100 ns) Channel B output buffer disabled 010 low high low Fast (100 ns) Channel A and B output buffer disabled 011 low high high Fast (100 ns) Channel A and B powered down 100 high low low Slow (15 μS) Channel A standby 101 high low high Fast (100 ns) Channel B standby 110 high high low Fast (100 ns) Multiplexed (MUX) mode – Output data of channel A and B is multiplexed and available on DB11 to DB0 pins. 111 high high high — PowerDown Global In this mode, the entire chip including both the A/D converters, internal reference and the output buffers are powered down resulting in reduced total power dissipation of about 50 mW. The output buffers are in high impedance state. The wake-up time from the global power down to data becoming valid in normal mode is typically 15 μs. Channel Standby (Individual or Both Channels) This mode allows the individual ADCs to be powered down. The internal references are active and this results in fast wake-up time, about 100 ns. The total power dissipation in standby is about 482 mW. Output Buffer Disable (Individual or Both Channels) Each channel’s output buffer can be disabled and put in high impedance state -- wakeup time from this mode is fast, about 100 ns. Input Clock Stop In addition to the above, the converter enters a low-power mode when the input clock frequency falls below 1 MSPS. The power dissipation is about 140 mW. POWER SUPPLY SEQUENCE During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated in the device. Externally, they can be driven from separate supplies or derived from a single supply. Copyright © 2007–2011, Texas Instruments Incorporated 51 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com DIGITAL OUTPUT INFORMATION ADS62P2X provides 12 bit data per channel and a common output clock synchronized with the data. The output interface can be either parallel CMOS or DDR LVDS voltage levels and can be selected using serial register bit or parallel pin SEN. Parallel CMOS Interface In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V (typical). Each data bit is output on separate pin as CMOS voltage level, every clock cycle (see Figure 93). For DRVDD > 2.2 V, it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving chip. The rising edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed. It is recommended to minimize the load capacitance seen by data and clock output pins by using short traces to the receiver. Also, match the output data and clock traces to minimize the skew between them. For DRVDD < 2.2 V, it is recommended to use external clock (for example, input clock delayed to get desired setup/hold times). CMOS Output Buffers DA0 DA1 DA2 12-Bit Channel-A Data DA3 · · · DA10 DA11 CLKOUT DB0 DB1 DB2 12-Bit Channel-B Data DB3 · · · DB10 DB11 B0287-02 Figure 93. CMOS Output Interface Output Buffer Strength Programmability Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this, ADS62P2X CMOS output buffers are designed with controlled drive strength to get best SNR. The default drive strength also ensures wide data stable window for load capacitances up to 5 pF and DRVDD supply voltage > 2.2 V. To ensure wide data stable window for load capacitance > 5 pF, there exists option to increase the output data and clock drive strengths using the serial interface ( DATAOUT STRENGTH and CLKOUT STRENGTH). Note that for DRVDD supply voltage < 2.2 V, it is recommended to use maximum drive strength (for any value of load capacitance). 52 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com CMOS Mode Power Dissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. Digital current due to CMOS output switching = CL × DRVDD × (N × FAVG), where CL = load capacitance, N × FAVG = average number of output bits switching. Figure 80 shows the current with various load capacitances across sampling frequencies at 2 MHz analog input frequency. DDR LVDS Interface The LVDS interface works only with 3.3 V DRVDD supply. In this mode, the 12 data bits of each channel and a common output clock are available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits are multiplexed and output on each LVDS differential pair every clock cycle (DDR – Double Data Rate, Figure 95). LVDS Buffers 12-Bit Channel-A Data Pins DA0P DA0M Data Bits D0, D1 DA2P DA2M Data Bits D2, D3 · · · · · · DA10P DA10M 12-Bit Channel-B Data Data Bits D10, D11 CLKOUTP CLKOUTM Output Clock DB0P DB0M Data Bits D0, D1 DB2P DB2M Data Bits D2, D3 · · · · · · DB10P DB10M Data Bits D10, D11 B0288-02 Figure 94. DDR LVDS Outputs Even data bits D0, D2, D4, D6, D8, D10 are output at the rising edge of CLKOUTP and odd data bits D1, D3, D5, D7, D9, D11 are output at the falling edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be used to capture all the data bits. Copyright © 2007–2011, Texas Instruments Incorporated 53 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com CLKOUTM CLKOUTP DA0 (DB0) D0 D1 D0 D1 DA2 (DB2) D2 D3 D2 D3 DA4 (DB4) D4 D5 D4 D5 DA6 (DB6) D6 D7 D6 D7 DA8 (DB8) D8 D9 D8 D9 DA10 (DB10) D10 D11 D10 D11 Sample N Sample N+1 T0110-03 Figure 95. DDR LVDS Interface LVDS Buffer Current Programmability The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV single-ended voltage swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to 2.5 mA, 4.5 mA, and 1.75 mA ( LVDS CURRENT). In addition, there exists a current double mode, where this current is doubled for the data and output clock buffers (register bits CURRENT DOUBLE). LVDS Buffer Internal Termination An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially terminated inside the device. The termination resistances available are – 300 Ω, 185 Ω, and 150 Ω (nominal with ±20% variation). Any combination of these three terminations can be programmed; the effective termination is the parallel combination of the selected resistances. This results in eight effective terminations from open (no termination) to 60 Ω. The internal termination helps to absorb any reflections coming from the receiver end, improving the signal integrity. With 100 Ω internal and 100 Ω external termination, the voltage swing at the receiver end is halved (compared to no internal termination). The voltage swing can be restored by using the LVDS current double mode. Figure 96 and Figure 97 compare the LVDS eye diagrams without and with 100 Ω internal termination. With internal termination, the eye looks clean even with 10 pF load capacitance (from each output pin to ground). The terminations can be programmed using register bits ( LVDS TERMINATION). 54 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Figure 96. LVDS Eye Diagram – No Internal Termination, External Termination = 100 Ω Figure 97. LVDS Eye Diagram – With 100 Ω Internal Termination, External termination = 100 Ω and LVDS current Double Mode Enabled Copyright © 2007–2011, Texas Instruments Incorporated 55 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Output Data Format Two output data formats are supported – 2s complement and straight binary. They can be selected using the serial interface register bit or controlling the SEN pin in parallel configuration mode. In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive overdrive, the output code is 0x7FF in offset binary output format, and 0x3FF in 2s complement output format. For a negative input overdrive, the output code is 0x000 in offset binary output format and 0x400 in 2s complement output format. Multiplexed Output mode This mode is available only with CMOS interface. In this mode, the digital outputs of both the channels are multiplexed and output on a single bus (DB0 - DB11 pins), as per the timing diagram shown in Figure 98. The channel A output pins (DA0 - DA11) are three-stated. Since the output data rate on the DB bus is effectively doubled, this mode is recommended only for low sampling frequencies (< 65 MSPS). This mode can be enabled using register bits or using the parallel pins CTRL1, CTRL2, and CTRL3. CLKOUT DB0 DA0 DB0 DA0 DB0 DB1 DA1 DB1 DA1 DB1 DB2 DA2 DB2 DA2 DB2 DB11 DA11 DB11 DA11 DB11 Sample N Sample N+1 T0297-02 Figure 98. Multiplexed Mode – Output Timing Low Latency Mode The default latency of ADS62P2X is 14 clock cycles. For applications, which cannot tolerate large latency, ADS62P2X includes a special mode with 10 clock cycles latency. In the low latency condition, the Digital Processing block is bypassed and its features (offset correction, fine gain, decimation filters) are not available. 56 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com DETAILS OF DIGITAL PROCESSING BLOCK CLIPPER From ADC Output 12 Bits 12 Bits 12 Bits 12 Bits 12 Bits To output buffers LVDS or CMOS Fine Gain (0 to 6 dB 0.05 dB Steps) 24 TAP FILTER - LOW PASS - HIGH PASS - BAND PASS Gain Correction (0.05 dB Steps) DECIMATION BY 2/4/8 12 Bits 0 OFFSET ESTIMATION BLOCK Filter Select Disable Offset Correction Freeze Offset Correction OFFSET CORRECTION Bypass Filter Bypass Decimation FINE GAIN DIGITAL FILTER and DECIMATION GAIN CORRECTION DIGITAL PROCESSING BLOCK B0289-02 Figure 99. Digital Processing Block Diagram Offset Correction ADS62P2X has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV. The correction can be enabled using the serial register bit ( OFFSET LOOP EN). Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using register bits ( OFFSET LOOP TC) as described in Table 22. Table 22. Time Constant of Offset Correction Algorithm (1) D6-D5-D4 TIME CONSTANT (TCCLK), Number of clock cycles TIME CONSTANT, sec (= TCCLK × 1/Fs) (1) 000 227 1.1 001 26 2 0.55 010 225 0.27 011 224 0.13 100 28 2 2.15 101 229 4.3 110 227 1.1 111 227 1.1 Sampling frequency, Fs = 125 MSPS It is also possible to freeze the offset correction using the serial interface (). Once frozen, the offset estimation becomes inactive and the last estimated value is used for correction every clock cycle. Note that the offset correction is disabled by default after reset. Figure 100 shows the time response of the offset correction algorithm, after it is enabled (for clarity, an example with no applied input signal is shown). A few time constants after the correction is enabled, the offset gets cancelled and the output code approaches the ideal value of 2048. Copyright © 2007–2011, Texas Instruments Incorporated 57 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com 2065 2060 Device With Offset Cancelled Code − LSB 2055 2050 2045 Offset Loop Enabled Here 2040 Device With Initial Offset 2035 2030 0 2 4 6 8 10 12 14 t − Time − s G084 Figure 100. Time Response of Offset Correction Gain Correction ADS62P2X has ability to make fine corrections to the ADC channel gain. The corrections can be done in steps of 0.05 dB, up to a maximum of 0.5 dB, using the register bits ( GAIN CORRECTION). Only positive corrections are supported and the same correction applies to both the channels. Table 23. Gain Correction Values 58 D3-D2-D1-D0 AMOUNT OF CORRECTION, dB 0000 0 0001 +0.05 0010 +0.1 0011 +0.15 0100 +0.20 0101 +0.25 0110 +0.30 0111 +0.35 1000 +0.40 1001 +0.45 1010 +0.5 Other combinations Unused Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Decimation Filters ADS62P2X includes option to decimate the ADC output data with in-built low-pass, high-pass, or band-pass filters. The decimation rate and type of filter can be selected using register bits ( DECIMATION RATE) and ( DECIMATION FILTER TYPE). Decimation rates of 2, 4, or 8 are available and either low-pass, high-pass, or band-pass filters can be selected (see Table 24). By default, the decimation filter is disabled – use register bit to enable it. Table 24. Decimation Filter Modes COMBINATION OF DECIMATION RATES AND FILTER TYPES DECIMATION TYPE OF FILTER Decimate by 2 In-built low-pass filter (pass band = 0 to Fs/4) 0 0 0 0 0 0 1 In-built high-pass filter (pass band = Fs/4 to Fs/2) 0 0 0 0 1 0 1 In-built low-pass filter (pass band = 0 to Fs/8) 0 0 1 0 0 0 1 In-built 2nd band-pass filter (pass band = Fs/8 to Fs/4) 0 0 1 0 1 0 1 In-built 3 band-pass filter (pass band = Fs/4 to 3Fs/8) 0 0 1 1 0 0 1 In-built last band-pass filter (pass band = 3Fs/8 to Fs/2) 0 0 1 1 1 0 1 Decimate by 2 Custom filter (user programmable coefficients) 0 0 0 X X 1 1 Decimate by 4 Custom filter (user programmable coefficients) 0 0 1 X X 1 1 Decimate by 8 Custom filter (user programmable coefficients) 1 0 0 X X 1 1 NO decimation Custom filter (user programmable coefficients) 0 1 1 X X 1 0 Decimate by 4 rd Decimation Filter Equation The decimation filter is implemented as 24-tap FIR with symmetrical coefficients (each coefficient is 12-bit signed). The filter equation is: y(n) + ǒ21 Ǔ 11 [h0 x(n) ) h1 x(n * 1) ) h2 x(n * 2) ) AAA ) h11 x(n * 11) ) h11 x(n * 12) ) AAA ) h1 x(n * 22) ) h0 x(n * 23)] (3) By setting the register bit = 1, a 23-tap FIR is implemented: y(n) + ǒ21 Ǔx[h0 11 x(n) ) h1 x(n * 1) ) h2 x(n * 2) ) AAA ) h10 x(n * 10) ) h11 x(n * 11) ) h10 x(n * 12) ) AAA ) h1 x(n * 21) ) h0 x(n * 22)] (4) In the above equations, h0, h1 …h11 are 12-bit signed representation of the coefficients, x(n) is the input data sequence to the filter y(n) is the filter output sequence Pre-defined Coefficients The in-built filter types (low-pass, high-pass, and band-pass) use pre-defined coefficients. The frequency response of the in-built filters is shown in Figure 101 and Figure 102. Copyright © 2007–2011, Texas Instruments Incorporated 59 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com 5 0 Magnitude − dB −5 −10 Low Pass High Pass −15 −20 −25 −30 −35 −40 −45 0.0 0.1 0.2 0.3 0.4 0.5 Normalized Frequency − f/fS G085 Figure 101. Decimate by 2 Filter Response 5 0 Magnitude − dB −5 −10 Low Pass High Pass −15 −20 −25 −30 −35 −40 −45 0.0 0.1 0.2 0.3 0.4 Normalized Frequency − f/fS 0.5 G086 Figure 102. Decimate by 4 Filter Response 5 0 Magnitude − dB −5 −10 −15 −20 −25 −30 −35 −40 −45 0.0 1st Bandpass 2nd Bandpass 0.1 0.2 0.3 Normalized Frequency − f/fS 0.4 0.5 G087 Figure 103. Decimate by 4 Band-Pass Response 60 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Table 25. Predefined Coefficients for Decimation by 2 Filters COEFFICIENTS DECIMATE BY 2 LOW-PASS FILTER HIGH-PASS FILTER h0 23 -22 h1 -37 -65 h2 -6 -52 h3 68 30 h4 -36 66 h5 -61 -35 h6 35 -107 h7 118 38 h8 -100 202 h9 -197 -41 h10 273 -644 h11 943 1061 Table 26. Predefined Coefficients for Decimation by 4 Filters COEFFICIENTS DECIMATE BY 4 LOW-PASS FILTER 1st BAND-PASS FILTER 2ND BAND-PASS FILTER HIGH-PASS FILTER h0 -17 -7 -34 32 h1 -50 19 -34 -15 h2 71 -47 -101 -95 h3 46 127 43 22 h4 24 73 58 -8 h5 -42 0 -28 -81 h6 -100 86 -5 106 h7 -97 117 -179 -62 h8 8 -190 294 -97 h9 202 -464 86 310 h10 414 -113 -563 -501 h11 554 526 352 575 Custom Filter Coefficients with Decimation The filter coefficients can also be programmed by the user (custom). For custom coefficients, set the register bit ( FILTER COEFF SELECT) and load the coefficients (h0 to h11) in registers 1E to 2F using the serial interface (Table 27) as: Register content = 12 bit signed representation of [real coefficient value × 211] Copyright © 2007–2011, Texas Instruments Incorporated 61 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com Custom Filter Coefficients without Decimation The filter with custom coefficients can also be used with the decimation mode disabled. In this mode, the filter implementation is 12-tap FIR: y(n) + ǒ21 Ǔx[h6 11 x(n) ) h7 x(n * 1) ) h8 x(n * 2) ) AAA ) h11 x(n * 5) ) h11 x(n * 6) ) AAA ) h7 x(n * 10) ) h6 x(n * 11)] (5) Table 27. Register Map of Custom Coefficients A7–A0 (hex) D7 D6 D5 Coefficient h1 Coefficient h4 Coefficient h5 Coefficient h4 26 Coefficient h5 27 Coefficient h6 Coefficient h7 Coefficient h6 29 Coefficient h7 2A Coefficient h8 Coefficient h9 Coefficient h8 2C Coefficient h9 2D Coefficient h10 2E 2F 62 Coefficient h2 Coefficient h3 24 2B D0 Coefficient h0 Coefficient h3 23 28 D1 Coefficient h2 21 25 D2 Coefficient h1 20 22 D3 Coefficient h0 1E 1F D4 Coefficient h11 Coefficient h10 Coefficient h11 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 www.ti.com SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the EVM User Guide (SLAU237) for details on layout and grounding. Supply Decoupling As ADS62P2X already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power supply noise, so the optimum number of capacitors would depend on the actual application. The decoupling capacitors should be placed very close to the converter supply pins. It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching noise from sensitive analog circuitry. In case only a single 3.3-V supply is available, it should be routed first to AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being routed to DRVDD. Exposed Thermal Pad It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271). Copyright © 2007–2011, Texas Instruments Incorporated 63 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs Integral Nonlinearity (INL) The INL is the deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error Gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error due to reference inaccuracy and error due to the channel. Both these errors are specified independently as EGREF and EGCHAN. To a first order approximation, the total gain error will be ETOTAL ~ EGREF + EGCHAN For example, if ETOTAL = ±0.5%, the full-scale input varies from (1-0.5/100) x FSideal to (1+0.5/100) x FSideal. Offset Error The offset error is the difference, given in number of LSBs, between the ADC’s actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. Temperature Drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN. 64 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 www.ti.com SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 Signal-to-Noise Ratio SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first nine harmonics. P SNR + 10Log 10 s PN (6) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. Ps SINAD + 10Log 10 PN ) PD (7) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Effective Number of Bits (ENOB) The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization noise. ENOB + SINAD * 1.76 6.02 (8) Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). P THD + 10Log 10 s PN (9) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. DC Power Supply Rejection Ratio (DC PSRR) The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. Copyright © 2007–2011, Texas Instruments Incorporated 65 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com AC Power Supply Rejection Ratio (AC PSRR) AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If ΔVSUP is the change in the supply voltage and ΔVOUT is the resultant change in the ADC output code (referred to the input), then DVOUT PSRR = 20Log 10 (Expressed in dBc) DVSUP (10) Common Mode Rejection Ratio (CMRR) CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If ΔVcm is the change in the input common-mode voltage and ΔVOUT is the resultant change in the ADC output code (referred to the input), then DVOUT CMRR = 20Log10 (Expressed in dBc) DVCM (11) Voltage Overload Recovery The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A 6-dBFS sine wave at Nyquist frequency is used as the test stimulus. 66 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY Changes from Revision A (February 2008) to Revision B Page • Changed Data setup time from 1.7 to 0.6 ............................................................................................................................ 8 • Changed Data setup time from 2.3 to 1.5 ............................................................................................................................ 8 • Changed Data setup time from 2.5 to 1.0 ............................................................................................................................ 8 • Changed Data setup time from 3.1 to 2.3 ............................................................................................................................ 8 • Changed Data setup time from 3.9 to 2.4 ............................................................................................................................ 8 • Changed Data setup time from 4.5 to 3.8 ............................................................................................................................ 8 • Changed Data setup time from 5.4 to 3.8 ............................................................................................................................ 8 • Changed Data setup time from 6.0 to 5.2 ............................................................................................................................ 8 • Changed Data hold time from 0.7 to 1.0 .............................................................................................................................. 8 • Changed Data hold time from 1.7 to 2.3 .............................................................................................................................. 8 • Changed Data hold time from 0.7 to 1.0 .............................................................................................................................. 8 • Changed Data hold time from 1.7 to 2.3 .............................................................................................................................. 8 • Changed Data hold time from 0.7 to 1.0 .............................................................................................................................. 8 • Changed Data hold time from 1.7 to 2.3 .............................................................................................................................. 8 • Changed Data hold time from 0.7 to 1.0 .............................................................................................................................. 8 • Changed Data hold time from 1.7 to 2.3 .............................................................................................................................. 8 • Changed Clock propagation delay from 4.3 to 3.5 ............................................................................................................... 8 • Changed Clock propagation delay from 5.8 to 5.5 ............................................................................................................... 8 • Changed Clock propagation delay from 7.3 to 7.5 ............................................................................................................... 8 • Changed Clock propagation delay from 4.3 to 3.5 ............................................................................................................... 8 • Changed Clock propagation delay from 5.8 to 5.5 ............................................................................................................... 8 • Changed Clock propagation delay from 7.3 to 7.5 ............................................................................................................... 8 • Changed Clock propagation delay from 4.3 to 3.5 ............................................................................................................... 8 • Changed Clock propagation delay from 5.8 to 5.5 ............................................................................................................... 8 • Changed Clock propagation delay from 7.3 to 7.5 ............................................................................................................... 8 • Changed Clock propagation delay from 4.3 to 3.5 ............................................................................................................... 8 • Changed Clock propagation delay from 5.8 to 5.5 ............................................................................................................... 8 • Changed Clock propagation delay from 7.3 to 7.5 ............................................................................................................... 8 • Changed LVDS bit clock duty cycle from 40% to 46% ......................................................................................................... 8 • Changed LVDS bit clock duty cycle from 47% to 50% ......................................................................................................... 8 • Changed LVDS bit clock duty cycle from 55% to 53% ......................................................................................................... 8 • Changed LVDS bit clock duty cycle from 40% to 46% ......................................................................................................... 8 • Changed LVDS bit clock duty cycle from 47% to 50% ......................................................................................................... 8 • Changed LVDS bit clock duty cycle from 55% to 53% ......................................................................................................... 8 • Changed LVDS bit clock duty cycle from 40% to 46% ......................................................................................................... 8 • Changed LVDS bit clock duty cycle from 47% to 50% ......................................................................................................... 8 • Changed LVDS bit clock duty cycle from 55% to 53% ......................................................................................................... 8 • Changed LVDS bit clock duty cycle from 40% to 46% ......................................................................................................... 8 • Changed LVDS bit clock duty cycle from 47% to 50% ......................................................................................................... 8 • Changed LVDS bit clock duty cycle from 55% to 53% ......................................................................................................... 8 • Changed Data setup time from 2.9 to 2.0 ............................................................................................................................ 9 • Changed Data setup time from 4.4 to 3.5 ............................................................................................................................ 9 • Changed Data setup time from 3.6 to 2.8 ............................................................................................................................ 9 • Changed Data setup time from 5.1 to 4.3 ............................................................................................................................ 9 Copyright © 2007–2011, Texas Instruments Incorporated 67 ADS62P24, ADS62P25 ADS62P22, ADS62P23 SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 www.ti.com • Changed Data setup time from 5.1 to 4.3 ............................................................................................................................ 9 • Changed Data setup time from 6.6 to 5.8 ............................................................................................................................ 9 • Changed Data setup time from 6.5 to 5.7 ............................................................................................................................ 9 • Changed Data setup time from 8.0 to 7.2 ............................................................................................................................ 9 • Changed Data hold time from 1.3 to 2.0 .............................................................................................................................. 9 • Changed Data hold time from 2.7 to 3.5 .............................................................................................................................. 9 • Changed Data hold time from 2.1 to 2.7 .............................................................................................................................. 9 • Changed Data hold time from 3.5 to 4.2 .............................................................................................................................. 9 • Changed Data hold time from 3.6 to 4.2 .............................................................................................................................. 9 • Changed Data hold time from 5.0 to 5.7 .............................................................................................................................. 9 • Changed Data hold time from 5.1 to 5.6 .............................................................................................................................. 9 • Changed Data hold time from 6.5 to 7.1 .............................................................................................................................. 9 • Changed Clock propagation delay from 5 to 5.8 .................................................................................................................. 9 • Changed Clock propagation delay from 6.5 to 7.3 ............................................................................................................... 9 • Changed Clock propagation delay from 7.9 to 8.8 ............................................................................................................... 9 • Changed Clock propagation delay from 5 to 5.8 .................................................................................................................. 9 • Changed Clock propagation delay from 6.5 to 7.3 ............................................................................................................... 9 • Changed Clock propagation delay from 7.9 to 8.8 ............................................................................................................... 9 • Changed Clock propagation delay from 5 to 5.8 .................................................................................................................. 9 • Changed Clock propagation delay from 6.5 to 7.3 ............................................................................................................... 9 • Changed Clock propagation delay from 7.9 to 8.8 ............................................................................................................... 9 • Changed Clock propagation delay from 5 to 5.8 .................................................................................................................. 9 • Changed Clock propagation delay from 6.5 to 7.3 ............................................................................................................... 9 • Changed Clock propagation delay from 7.9 to 8.8 ............................................................................................................... 9 • Changed Output clock duty cycle from 50% to 53% ............................................................................................................ 9 • Changed Output clock duty cycle from 55% to 60% ............................................................................................................ 9 • Changed Output clock duty cycle from 50% to 53% ............................................................................................................ 9 • Changed Output clock duty cycle from 55% to 60% ............................................................................................................ 9 • Changed Output clock duty cycle from 50% to 53% ............................................................................................................ 9 • Changed Output clock duty cycle from 55% to 60% ............................................................................................................ 9 • Changed Output clock duty cycle from 50% to 53% ............................................................................................................ 9 • Changed Output clock duty cycle from 55% to 60% ............................................................................................................ 9 • Changed Data rise time/Data fall time from 0.8 to 1.0 ......................................................................................................... 9 • Changed Data rise time/Data fall time from 1.5 to 1.8 ......................................................................................................... 9 • Changed Data rise time/Data fall time from 2.4 to 2.5 ......................................................................................................... 9 • Changed Data rise time/Data fall time from 0.8 to 1.0 ......................................................................................................... 9 • Changed Data rise time/Data fall time from 1.5 to 1.8 ......................................................................................................... 9 • Changed Data rise time/Data fall time from 2.4 to 2.5 ......................................................................................................... 9 • Changed Data rise time/Data fall time from 0.8 to 1.0 ......................................................................................................... 9 • Changed Data rise time/Data fall time from 1.5 to 1.8 ......................................................................................................... 9 • Changed Data rise time/Data fall time from 2.4 to 2.5 ......................................................................................................... 9 • Changed Data rise time/Data fall time from 0.8 to 1.0 ......................................................................................................... 9 • Changed Data rise time/Data fall time from 1.5 to 1.8 ......................................................................................................... 9 • Changed Data rise time/Data fall time from 2.4 to 2.5 ......................................................................................................... 9 • Changed Output clock rise time/Output clock fall time from 0.8 to 1.0 ................................................................................ 9 • Changed Output clock rise time/Output clock fall time from 1.5 to 1.8 ................................................................................ 9 • Changed Output clock rise time/Output clock fall time from 2.4 to 2.5 ................................................................................ 9 68 Copyright © 2007–2011, Texas Instruments Incorporated ADS62P24, ADS62P25 ADS62P22, ADS62P23 www.ti.com SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 • Changed Output clock rise time/Output clock fall time from 0.8 to 1.0 ................................................................................ 9 • Changed Output clock rise time/Output clock fall time from 1.5 to 1.8 ................................................................................ 9 • Changed Output clock rise time/Output clock fall time from 2.4 to 2.5 ................................................................................ 9 • Changed Output clock rise time/Output clock fall time from 0.8 to 1.0 ................................................................................ 9 • Changed Output clock rise time/Output clock fall time from 1.5 to 1.8 ................................................................................ 9 • Changed Output clock rise time/Output clock fall time from 2.4 to 2.5 ................................................................................ 9 • Changed Output clock rise time/Output clock fall time from 0.8 to 1.0 ................................................................................ 9 • Changed Output clock rise time/Output clock fall time from 1.5 to 1.8 ................................................................................ 9 • Changed Output clock rise time/Output clock fall time from 2.4 to 2.5 ................................................................................ 9 • Added PARALLEL CMOS INTERFACE, DRVDD = 1.8 V, maximum buffer drive strength timing characteristics .............. 9 • Added PARALLEL CMOS INTERFACE, DRVDD = 1.8 V, MULTIPLEXED MODE, maximum buffer drive strength timing characteristics .......................................................................................................................................................... 10 • Changed DB10 to DB0 pins to DB11 to DB0 pins in Table 6 ............................................................................................. 14 • Changed DA10 to DA0 pins to DB11 to DB0 pins in D2-D0 bit description ....................................................................... 20 • Changed DA13 to DA0 pins to DB11 to DB0 pins in Table 21 ........................................................................................... 51 Changes from Revision B (December 2008) to Revision C Page • Changed pins 19, 20 and 29, 30 ........................................................................................................................................ 25 • Changed pins 19, 20 and 29, 30 ........................................................................................................................................ 27 Copyright © 2007–2011, Texas Instruments Incorporated 69 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS62P22IRGCR ACTIVE VQFN RGC 64 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ62P22 ADS62P22IRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ62P22 ADS62P23IRGCR ACTIVE VQFN RGC 64 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ62P23 ADS62P23IRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ62P23 ADS62P24IRGCR ACTIVE VQFN RGC 64 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ62P24 ADS62P24IRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ62P24 ADS62P25IRGCR ACTIVE VQFN RGC 64 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ62P25 ADS62P25IRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ62P25 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of