ADS7038-Q1
ADS7038-Q1
SBAS981A – MAY 2020 – REVISED NOVEMBER
2020
SBAS981A – MAY 2020 – REVISED NOVEMBER 2020
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ADS7038-Q1 Small, 8-Channel, 12-Bit ADC with SPI Interface, GPIOs, and CRC
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Small package size:
– WQFN 3 mm × 3 mm
– Wettable flanks for visual inspection of solder
joints
8 channels configurable as any combination of:
– Up to 8 analog inputs, digital inputs, or digital
outputs
GPIOs for I/O expansion:
– Open-drain, push-pull digital outputs
Analog watchdog:
– Programmable thresholds per channel
– Event counter for transient rejection
Wide operating ranges:
– AVDD: 2.35 V to 5.5 V
– DVDD: 1.65 V to 5.5 V
Enhanced-SPI digital interface:
– High-speed, 60-MHz interface
CRC for read/write operation:
– CRC on data read/write
– CRC on power-up configuration
Programmable averaging filters:
– Programmable sample size for averaging
– Averaging with internal conversions
– 16-bit resolution
Turbo comparator mode with speeds up to
3.2 MSPS
Battery management systems (BMS)
Automotive cluster displays
Inverter and motor controls
Onboard (OBC) and wireless chargers
3 Description
The ADS7038-Q1 is an easy-to-use, 8-channel,
multiplexed,
12-bit,
1-MSPS,
successive
approximation register analog-to-digital converter
(SAR ADC). The eight channels can be independently
configured as either analog inputs, digital inputs, or
digital outputs. The device has an internal oscillator
for the ADC conversion process.
The ADS7038-Q1 communicates through an SPIcompatible interface and operates in either
autonomous or single-shot conversion mode. The
ADS7038-Q1 implements the analog watchdog
function by event-triggered interrupts per channel
using a digital window comparator with programmable
high and low thresholds, hysteresis, and an event
counter. The ADS7038-Q1 has a built-in cyclic
redundancy check (CRC) for data read/write
operations and the power-up configuration.
Device Information (1)
PART NUMBER
ADS7038-Q1
(1)
PACKAGE
WQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
Example System Architecture
Device Block Diagram
DECAP
AVDD
VCC
AIN0/GPIO0
AIN1/GPIO1
ADC
Programmable
Averaging Filters
DVDD
Digital Window
Comparator
LOAD
AVDD
High/Low Threshold
± 8 x Hysteresis
OVP
AIN2/GPIO2
MUX
AIN3/GPIO3
AIN4/GPIO4
AIN5/GPIO5
AIN6/GPIO6
AIN7/GPIO7
MUX
Sequencer
Pin CFG
GPO Write
SPI Interface
and
CRC
Verification
CS
GPIO
SCLK
OCP
ADC
SDI
SDO
GPI Read
GND
OVP: Over voltage protection
OCP: Over current protection
ADS7038-Q1 Block Diagram and Applications
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2020 Texas Instruments
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SBAS981A – MAY 2020 – REVISED NOVEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................7
7.6 Timing Requirements ................................................. 8
7.7 Switching Characteristics ...........................................8
7.8 Timing Diagrams......................................................... 9
7.9 Typical Characteristics.............................................. 10
8 Detailed Description......................................................14
8.1 Overview................................................................... 14
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................27
8.5 ADS7038-Q1 Registers............................................ 32
9 Application and Implementation.................................. 74
9.1 Application Information............................................. 74
9.2 Typical Applications.................................................. 74
10 Power Supply Recommendations..............................77
10.1 AVDD and DVDD Supply Recommendations......... 77
11 Layout........................................................................... 78
11.1 Layout Guidelines................................................... 78
11.2 Layout Example...................................................... 78
12 Device and Documentation Support..........................79
12.1 Receiving Notification of Documentation Updates..79
12.2 Support Resources................................................. 79
12.3 Trademarks............................................................. 79
12.4 Electrostatic Discharge Caution..............................79
12.5 Glossary..................................................................79
13 Mechanical, Packaging, and Orderable
Information.................................................................... 79
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (May 2020) to Revision A (November 2020)
Page
• Changed document status from advance information to product data............................................................... 1
2
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5 Device Comparison Table
PART
NUMBER
DESCRIPTION
ADS7028
ADS7038
8-channel, 12-bit ADC with SPI
interface and GPIOs
ADS7038-Q1
CRC MODULE
ZERO-CROSSING-DETECT
(ZCD) MODULE
ROOT-MEAN-SQUARE
(RMS) MODULE
Yes
Yes
Yes
Yes
No
No
Yes
No
No
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AIN1/GPIO1
AIN0/GPIO0
SDI
SCLK
15
14
13
8
4
DECAP
AIN5/GPIO5
7
3
AVDD
AIN4/GPIO4
Thermal
Pad
6
2
AIN7 /GPIO7
AIN3/GPIO3
5
1
AIN6/GPIO6
AIN2/GPIO2
16
6 Pin Configuration and Functions
12
SDO
11
CS
10
DVDD
9
GND
Figure 6-1. RTE Package, 16-Pin WQFN, Top View
Pin Functions
PIN
NAME
FUNCTION(1)
DESCRIPTION
AIN0/GPIO0
15
AI, DI, DO
Channel 0; can be configured as either an analog input (default), digital input, or digital output.
AIN1/GPIO1
16
AI, DI, DO
Channel 1; can be configured as either an analog input (default), digital input, or digital output.
AIN2/GPIO2
1
AI, DI, DO
Channel 2; can be configured as either an analog input (default), digital input, or digital output.
AIN3/GPIO3
2
AI, DI, DO
Channel 3; can be configured as either an analog input (default), digital input, or digital output.
AIN4/GPIO4
3
AI, DI, DO
Channel 4; can be configured as either an analog input (default), digital input, or digital output.
AIN5/GPIO5
4
AI, DI, DO
Channel 5; can be configured as either an analog input (default), digital input, or digital output.
AIN6/GPIO6
5
AI, DI, DO
Channel 6; can be configured as either an analog input (default), digital input, or digital output.
AIN7/GPIO7
6
AI, DI, DO
Channel 7; can be configured as either an analog input (default), digital input, or digital output.
AVDD
7
Supply
CS
11
DI
DECAP
8
Supply
Connect a 1-µF decoupling capacitor to GND for the internal power supply.
DVDD
10
Supply
Digital I/O supply voltage; connect a 1-µF decoupling capacitor to GND.
GND
9
Supply
Ground for the power supply; all analog and digital signals are referred to this pin voltage.
SCLK
13
DI
Serial clock for the SPI interface.
SDI
14
DI
Serial data in for the device.
SDO
12
DO
Serial data out for the device.
Thermal pad
—
Supply
(1)
4
NO.
Analog supply input, also used as the reference voltage to the ADC; connect a 1-µF
decoupling capacitor to GND.
Chip-select input pin; active low. The device takes control of the data bus when CS is low.
The device starts converting the active input channel on the rising edge of CS. SDO goes hi-Z
when CS is high.
Exposed thermal pad; connect to GND.
AI = analog input, DI = digital input, and DO = digital output.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
MAX
DVDD to GND
–0.3
5.5
V
AVDD to GND
–0.3
5.5
V
GND – 0.3 AVDD + 0.3
V
GND – 0.3
5.5
V
AINx/GPOx(3)
to GND
Digital input to GND
Current through any pin except supply
pins(2)
UNIT
–10
10
mA
Junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–60
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Pin current must be limited to 10 mA or less.
AINx/GPIOx refers to pins 1, 2, 3, 4, 5, 6, 15, and 16.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±2000
Charged-device model (CDM), per AEC Q100-011; corner pins (1,
4, 5, 8, 9, 12, 13, 16)
±750
Charged-device model (CDM), per AEC Q100-011; all other pins
±500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
AVDD
Analog supply voltage
2.35
3.3
5.5
V
DVDD
Digital supply voltage
1.65
3.3
5.5
V
ANALOG INPUTS
FSR
Full-scale input range
AINX - GND
0
AVDD
V
VIN
Absolute input voltage
AINX - GND
–0.1
AVDD + 0.1
V
125
℃
TEMPERATURE RANGE
TA
(1)
Ambient temperature
–40
25
AINx refers to AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.
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7.4 Thermal Information
ADS7038-Q1
THERMAL
METRIC(1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
49.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
53.4
°C/W
RθJB
Junction-to-board thermal resistance
24.7
°C/W
ΨJT
Junction-to-top characterization parameter
1.3
°C/W
ΨJB
Junction-to-board characterization parameter
24.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
9.3
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
at AVDD = 2.35 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and
maximum values at TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
CSH
Sampling capacitance
12
pF
DC PERFORMANCE
Resolution
DNL
Differential nonlinearity
INL
Integral nonlinearity
V(OS)
GE
No missing codes
Input offset error
Post offset calibration
Input offset thermal drift
Post offset calibration
Gain error
12
bits
–0.75
±0.25
0.75
LSB
–1.4
±0.4
1.4
LSB
–2
±0.08
2
–0.075
Gain error thermal drift
LSB
±1
ppm/°C
±0.05
0.075 %FSR
±1
ppm/°C
AC PERFORMANCE
AVDD = 5 V, fIN = 2 kHz
70.2
72.9
AVDD = 3 V, fIN = 2 kHz
70.2
72.7
AVDD = 5 V, fIN = 2 kHz
71.2
73.1
AVDD = 3 V, fIN = 2 kHz
70.5
72.9
SINAD
Signal-to-noise + distortion ratio
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
fIN = 2 kHz
SFDR
Spurious-free dynamic range
fIN = 2 kHz
Isolation crosstalk
fIN = 100 kHz
dB
dB
–87.5
dB
91
dB
–100
dB
DECAP Pin
Decoupling capacitor on DECAP pin
0.22
1
4.7
µF
0.7 x DVDD
5.5
V
V
SPI INTERFACE (CS, SCLK, SDI, SDO)
VIH
Input high logic level
VIL
Input low logic level
VOH
VOL
Output high logic level
Output low logic level
–0.3
0.3 x DVDD
Source current = 2 mA,
DVDD > 2 V
0.8 x DVDD
DVDD
Source current = 2 mA,
DVDD ≤ 2 V
0.7 x DVDD
DVDD
Sink current = 2 mA, DVDD > 2 V
0
0.4
Sink current = 2 mA, DVDD ≤ 2 V
0
0.2 x DVDD
0.7 x AVDD
AVDD + 0.3
–0.3
0.3 x AVDD
V
100
nA
0.8 x AVDD
AVDD
V
0
0.2 x AVDD
V
V
GPIOs
VIH
Input high logic level
VIL
Input low logic level
Input leakge current
VOH
Output high logic level
GPIO configured as input
GPO_DRIVE_CFG = push-pull, I
= 2 mA
SOURCE
10
V
VOL
Output low logic level
ISINK = 2 mA
IOH
Output high source current
VOH > 0.7 x AVDD
5
mA
V
IOL
Output low sink current
VOL < 0.3 x AVDD
5
mA
POWER-SUPPLY CURRENTS
IAVDD
Analog supply current
Full throughput, AVDD = 5 V
490
600
Full throughput, AVDD = 3 V
455
550
No conversion, AVDD = 5 V
7
25
µA
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7.6 Timing Requirements
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +125°C ; typical values at TA = 25°C
MIN
MAX
UNIT
1000
kSPS
CONVERSION CYCLE
fCYCLE
Sampling frequency
tCYCLE
ADC cycle-time period
1 / fCYCLE
Acquisition time (CONV_MODE = 00b or 01b)
tACQ
tQUIET
s
400
ns
Acquisition time in turbo comparator mode (CONV_MODE = 10b)
90
Quiet acquisition time
10
ns
tWH_CSZ
Pulse duration: CS high
230
ns
tWL_CSZ
Pulse duration: CS low
200
ns
SPI INTERFACE TIMINGS
fCLK
Maximum SCLK frequency
60
MHz
tCLK
Minimum SCLK time period
tPH_CK
SCLK high time
16.67
0.45
0.55
tCLK
tPL_CK
SCLK low time
0.45
0.55
tCLK
tSU_CSCK
Setup time: CS falling to the first SCLK capture edge
tSU_CKDI
Setup time: SDI data valid to the SCLK capture edge
tHT_CKDI
Hold time: SCLK capture edge to data valid on SDI
tD_CKCS
Delay time: last SCLK falling to CS rising
ns
5.5
ns
5
ns
3.5
ns
9
ns
7.7 Switching Characteristics
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +125°C ; typical values at TA = 25°C
PARAMETER
Test Conditions
MIN
MAX
UNIT
CONVERSION CYCLE
tCONV
ADC comparison time in turbo comparator mode
CONV_MODE = 10b
192
ADC conversion time
CONV_MODE - 00b or 01b
600
ns
RESET and ALERT
AVDD ≥ 2.35 V,
CDECAP = 1 µF
tPU
Power-up time for device
5
ms
tRST
Delay time; RST bit = 1b to device reset complete(1)
tALERT_HI
ALERT high period
ALERT_LOGIC[1:0] = 1x
50
5
ms
150
ns
tALERT_LO
ALERT low period
ALERT_LOGIC[1:0] = 1x
50
150
ns
SPI INTERFACE TIMINGS
tDEN_CSDO
Delay time: CS falling to data enable
15
ns
tDZ_CSDO
Delay time: CS rising to SDO going Hi-Z
21
ns
tD_CKDO
Delay time: SCLK launch edge to (next) data valid on SDO
16
ns
(1)
8
RST bit is automatically reset to 0b after tRST.
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7.8 Timing Diagrams
tCYCLE
tCONV
CS
Acquiring
Sample N
tACQ
Acquiring Sample N+1
Converting Sample N
tWH_CSZ
tWL_CSZ
SDI
MSB
MSB-1
MSB-2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+1
LSB
HI-Z
SDO
tQUIET
SCLK
Figure 7-1. Conversion Cycle Timing
tCLK
tPH_CK
CS
tPL_CK
SCLK(A)
tSU_CKDI
tSU_CSCK
tD_CKCS
SCLK(A)
tHT_CKDI
SDI
tDEN_CSDO
SDO
tDZ_CSDO
tD_CKDO
SDO
A. The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.
Figure 7-2. SPI-Compatible Serial Interface Timing
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7.9 Typical Characteristics
at TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS (unless otherwise noted)
0
45000
39581
30000
Amplitude (dB)
-30
Frequency
25955
15000
-60
-90
-120
-150
0
2048
0
2049
Output Code
100
C001
400
C008
Figure 7-4. Typical FFT
Figure 7-3. DC Input Histogram
0.8
Integral Nonlinearity (LSB)
0.8
0.4
0
-0.4
-0.8
0.4
0
-0.4
-0.8
0
1024
2048
Output Code
3072
4095
0
1024
C002
Typical DNL = ±0.5 LSB
2048
Output Code
3072
C004
Figure 7-6. Typical INL
0.5
0.75
Maximum
Minimum
0.3
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
Maximum
Minimum
0.1
-0.1
-0.3
-0.5
-40
4095
Typical INL = ±0.5 LSB
Figure 7-5. Typical DNL
-7
26
59
Temperature (qC)
92
125
0.45
0.15
-0.15
-0.45
-0.75
-40
C003
Figure 7-7. DNL vs Temperature
10
500
fIN = 2 kHz, SNR = 73.2 dB, THD = –92.1 dB
Standard deviation = 0.49 LSB
Differential Nonlinearity (LSB)
200
300
Frequency (kHz)
-7
26
59
Temperature (qC)
92
125
C005
Figure 7-8. INL vs Temperature
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7.9 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS (unless otherwise noted)
0.5
0.75
Maximum
Minimum
0.3
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
Maximum
Minimum
0.1
-0.1
-0.3
-0.5
2.5
3
3.5
4
AVDD (V)
4.5
5
0.45
0.15
-0.15
-0.45
-0.75
2.5
5.5
3
2
0.05
1.2
0.03
0.4
-0.4
-1.2
4.5
5
5.5
C019
0.01
-0.01
-0.03
-2
-40
-7
26
59
Temperature (°C)
92
-0.05
-40
125
-7
C006
Figure 7-11. Offset Error vs Temperature
26
59
Temperature (°C)
92
125
C007
Figure 7-12. Gain Error vs Temperature
2
0.05
1.2
0.03
Gain Error (%FSR)
Offset Error (LSB)
4
AVDD (V)
Figure 7-10. INL vs AVDD
Gain Error (%FSR)
Offset Error (LSB)
Figure 7-9. DNL vs AVDD
0.4
-0.4
-1.2
-2
2.5
3.5
C018
0.01
-0.01
-0.03
3
3.5
4
AVDD (V)
4.5
5
5.5
-0.05
2.5
C016
Figure 7-13. Offset Error vs AVDD
3
3.5
4
AVDD (V)
4.5
5
5.5
C017
Figure 7-14. Gain Error vs AVDD
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7.9 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS (unless otherwise noted)
11.75
73.5
12
11.725
73
11.7
72.9
11.675
-7
26
59
Temperature (°C)
72.5
11.7
72
11.65
125
92
11.85
11.55
71.5
2.5
-90.3
4
AVDD (V)
4.5
11.4
5.5
5
C010
Figure 7-16. Noise Performance vs AVDD
94.8
-82
96
THD
SFDR
94.4
-90.7
94
-90.9
SFDR (dBFS)
-90.5
THD (dBFS)
THD
SFDR(dBFS)
THD (dBFS)
3.5
C009
Figure 7-15. Noise Performance vs Temperature
-91.1
-40
3
-84
94
-86
92
-88
90
-90
88
SFDR (dBFS)
72.8
-40
73
SINAD, SNR (dBFS)
73.1
SINAD
SNR
ENOB
ENOB (Bits)
SINAD, SNR (dBFS)
SINAD
SNR
ENOB
ENOB (Bits)
73.2
93.6
-7
26
59
Temperature (°C)
93.2
125
92
-92
2.5
3
3.5
4
AVDD (V)
C011
Figure 7-17. Distortion Performance vs Temperature
4.5
86
5.5
5
C012
Figure 7-18. Distortion Performance vs AVDD
500
490
484
478
IAVDD (PA)
IAVDD (PA)
480
472
440
466
460
-40
-7
26
59
Temperature (°C)
92
125
420
2.5
C013
Figure 7-19. Analog Supply Current vs Temperature
12
460
3
3.5
4
AVDD (V)
4.5
5
5.5
C014
Figure 7-20. Analog Supply Current vs AVDD
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7.9 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS (unless otherwise noted)
750
500
650
400
IAVDD (µA)
IAVDD (PA)
550
300
200
450
350
100
250
0
150
0
200
400
600
Throughput (kSPS)
800
1000
0
500
1000
1500
2000
2500
Comparison Rate (kSPS)
C015
Figure 7-21. Analog Supply Current vs Throughput
3000
3500
C020
Figure 7-22. Analog Supply Current vs Comparison Rate
(OSC_SEL = 0) in Turbo Comparator Mode
750
40
740
34
IAVDD (µA)
IAVDD (PA)
730
28
22
720
710
16
700
10
0
20
40
60
Comparison Rate (kSPS)
80
690
-40
100
-7
26
59
Temperature (°C)
C021
Figure 7-23. Analog Supply Current vs Comparison Rate
(OSC_SEL = 1) in Turbo Comparator Mode
92
125
C022
Figure 7-24. Analog Supply Current vs Temperature (OSC_SEL
= 0, CLK_DIV = 0) in Turbo Comparator Mode
41.5
IAVDD (µA)
40.7
39.9
39.1
38.3
37.5
-40
-7
26
59
Temperature (°C)
92
125
C023
Figure 7-25. Analog Supply Current vs Temperature
(OSC_SEL = 1, CLK_DIV = 0) in Turbo Comparator Mode
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8 Detailed Description
8.1 Overview
The ADS7038-Q1 is a small, eight-channel, multiplexed, 12-bit, 1-MSPS, analog-to-digital converter (ADC) with
an enhanced-SPI serial interface. The eight channels of the ADS7038-Q1 can be individually configured as
either analog inputs, digital inputs, or digital outputs. The device includes a digital window comparator that can
be used to alert the host when a programmed high or low threshold is crossed on any input channel. The device
uses an internal oscillator for conversion. The ADC can be used in manual mode for reading ADC data over the
SPI interface or in autonomous and turbo comparator modes for monitoring the analog inputs without an active
SPI interface.
The device features a programmable averaging filter that outputs a 16-bit result for enhanced resolution.
8.2 Functional Block Diagram
DECAP
AVDD
High/Low Threshold
± 8 x Hysteresis
AIN0/GPIO0
AIN1/GPIO1
ADC
Programmable
Averaging Filters
DVDD
Digital Window
Comparator
AIN2/GPIO2
AIN3/GPIO3
AIN4/GPIO4
AIN5/GPIO5
AIN6/GPIO6
AIN7/GPIO7
MUX
Sequencer
Pin CFG
GPO Write
SPI Interface
&
CRC
Verification
CS
SCLK
SDI
SDO
GPI Read
GND
14
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8.3 Feature Description
8.3.1 Multiplexer and ADC
The eight channels of the multiplexer can be independently configured as ADC inputs or general-purpose inputs/
outputs (GPIOs). As shown in Figure 8-1, every AINx/GPIOx channel has ESD protection diodes to AVDD and
GND. On power-up or after device reset, all eight multiplexer channels are configured as analog inputs.
Figure 8-1 shows the equivalent circuit for pins configured as analog inputs. The ADC sampling switch is
represented by an ideal switch (SW) in series with the resistor (RSW, typically 150 Ω) and the sampling capacitor
(CSH).
GPO_VALUE[0]
GPIO_CFG[0]
AVDD
GPI_VALUE[0]
PIN_CFG[0]
AIN0 / GPIO0
RSW
SW
MUX
Multiplexer
AVDD
CSH
ADC
AIN7 / GPIO7
PIN_CFG[7]
GPI_VALUE[7]
GPIO_CFG[7]
GPO_VALUE[7]
Figure 8-1. Analog Inputs, GPIOs, and ADC Connections
The switch SW is closed to allow the signal on the selected analog input channel to charge the internal sampling
capacitor during acquisition time. The switch SW is opened to disconnect the sampling capacitor on the CS
rising edge and the analog-to-digital conversion process begins.
The multiplexer channels can be configured as GPIOs using the PIN_CFG register. The direction of a GPIO
(either as an input or an output) can be set in the GPIO_CFG register. The logic level on all device channels can
be read from the GPI_VALUE register. The digital outputs can be configured by writing to the GPO_VALUE
register. The digital outputs can be configured as either open-drain or push-pull in the GPO_DRIVE_CFG
register.
8.3.2 Reference
The device uses the analog supply voltage (AVDD) as the reference for the analog-to-digital conversion process.
TI recommends connecting a 1-µF, low-equivalent series resistance (ESR) ceramic decoupling capacitor
between the AVDD and GND pins.
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8.3.3 ADC Transfer Function
The ADC output is in straight binary format. Equation 1 computes the ADC resolution:
1 LSB = VREF / 2N
(1)
where:
•
•
VREF = AVDD
N = 12
Figure 8-2 and Table 8-1 detail the transfer characteristics for the device.
ADC Code (Hex)
0xFFF
0x801
0x800
0x001
0x000
VIN
1 LSB
AVDD/2
(AVDD/2 + 1 LSB)
(AVDD ± 1 LSB)
Figure 8-2. Ideal Transfer Characteristics
Table 8-1. Transfer Characteristics
INPUT VOLTAGE
CODE
IDEAL OUTPUT CODE
≤1 LSB
Zero
000
001
1 LSB to 2 LSBs
Zero + 1
(AVDD / 2) to (AVDD / 2) + 1 LSB
Mid-scale code
800
(AVDD / 2) + 1 LSB to (AVDD / 2) + 2 LSB
Mid-scale code + 1
801
≥ AVDD – 1 LSB
Full-scale code
FFF
8.3.4 ADC Offset Calibration
The variation in ADC offset error resulting from changes in temperature or AVDD can be calibrated by setting the
CAL bit in the GENERAL_CFG register. The CAL bit is reset to 0 after calibration. The host can poll the CAL bit
to check the ADC offset calibration completion status.
Multiplexer sequencing must be stopped (SEQ_START = 0b) before initiating offset calibration.
8.3.5 Oscillator and Timing Control
The device uses an internal oscillator for conversions. The host initiates the first conversion and subsequent
conversions are generated internally by the device when using the averaging module. However, in the
autonomous mode of operation, the start of the conversion signal is generated by the device. As described in
Table 8-2, the sampling rate can be controlled by the OSC_SEL and CLK_DIV register fields when the device
initiates conversion internally.
The conversion time of the device, given by tCONV in the Switching Characteristics table, is independent of the
OSC_SEL and CLK_DIV configuration.
16
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Table 8-2. Configuring Sampling Rate for Internal Conversion Start Control
OSC_SEL = 0
OSC_SEL = 1
CLK_DIV[3:0]
SAMPLING FREQUENCY, f
CYCLE_OSR (kSPS)
CYCLE TIME, t
CYCLE_OSR (µs)
SAMPLING FREQUENCY, f
CYCLE_OSR (kSPS)
CYCLE TIME, t
CYCLE_OSR (µs)
0000b
1000
1
31.25
32
0001b
666.7
1.5
20.83
48
0010b
500
2
15.63
64
0011b
333.3
3
10.42
96
0100b
250
4
7.81
128
0101b
166.7
6
5.21
192
0110b
125
8
3.91
256
0111b
83
12
2.60
384
1000b
62.5
16
1.95
512
1001b
41.7
24
1.3
768
1010b
31.3
32
0.98
1024
1011b
20.8
48
0.65
1536
1100b
15.6
64
0.49
2048
1101b
10.4
96
0.33
3072
1110b
7.8
128
0.24
4096
1111b
5.2
192
0.16
6144
As shown in Table 8-3, the comparison time in Turbo Comparator Mode can be controlled by the OSC_SEL and
CLK_DIV register fields.
Table 8-3. Configuring Comparison Rate for Turbo Comparator Mode
OSC_SEL = 0
CLK_DIV[3:0]
COMPARISON RATE, f
COMPARISON (kSPS)
OSC_SEL = 1
CYCLE TIME, t
(µs)
CYCLE_COMP
COMPARISON RATE, fCOMPARISON
(kSPS)
CYCLE TIME, t
(µs)
CYCLE_COMP
0000b
3200
0.3125
100
10
0001b
2133.3
0.46875
66.7
15
0010b
1600
0.625
50
20
0011b
1066.7
0.9375
33.3
30
0100b
800
1.25
25
40
0101b
533.3
1.875
16.67
60
0110b
400
2.5
3.91
80
0111b
266.7
3.75
2.60
120
1000b
200
5
1.95
160
1001b
133.3
7.5
1.3
240
1010b
100
10
0.98
320
1011b
66.7
15
0.65
480
1100b
50
20
0.49
640
1101b
33.3
30
0.33
960
1110b
25
40
0.24
1280
1111b
16.67
60
0.16
1920
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8.3.6 General-Purpose I/Os
The eight channels of the ADS7038-Q1 can be independently configured as analog inputs, digital inputs, or
digital outputs. The device channels, as described in Table 8-4, can be configured as analog inputs or GPIOs
using the PIN_CFG and GPIO_CFG registers.
Table 8-4. Configuring Channels as Analog Inputs or GPIOs
PIN_CFG[7:0]
GPIO_CFG[7:0]
GPO_DRIVE_CFG[7:0]
CHANNEL CONFIGURATION
0
x
x
Analog input (default)
1
0
x
Digital input
1
1
0
Digital output; open-drain driver
1
1
1
Digital output; push-pull driver
Digital outputs can be configured to logic 1 or 0 by writing to the GPO_VALUE register. Digital outputs can also
be updated in response to event flags set by the digital window comparator (see the Triggering Digital Outputs
With Digital Window Comparator section for more details). Reading the GPI_VALUE register returns the logic
level for all channels configured as analog inputs, digital inputs, and digital outputs.
8.3.7 Programmable Averaging Filter
The ADS7038-Q1 features a built-in oversampling (OSR) module that can be used to average several samples.
The averaging filter can be enabled by programming the OSR[2:0] bits in the OSR_CFG register. The averaging
filter configuration is common to all analog input channels. As shown in Figure 8-3, the averaging filter module
output is 16 bits long. Only the first conversion for the selected analog input channel must be initiated by the
host. Any remaining conversions for the selected averaging factor are generated internally. The time (t AVG)
required to complete the averaging operation is determined by the sampling speed and number of samples to be
averaged; see the Oscillator and Timing Control section for more details. The 16-bit result can be read out after
the averaging operation completes. For more information about programmable averaging filters and performance
results see the Resolution-Boosting ADS7138 Using Programmable Averaging Filter application report.
Sample
AINx
(start of averaging)
Sample
AINx
Sample
AINx
CS
N ± 1 conversions triggered
internally
Maximum tAVG = N samples x tCYCLE_OSR x 1.06
SCLK
SDO
[15:0] Data
16 clocks
Figure 8-3. Averaged Output Data
In autonomous mode of operation, samples from analog input channels that are enabled in the
AUTO_SEQ_CH_SEL register are averaged sequentially; see the Autonomous Mode section. The digital
window comparator compares the top 12 bits of the 16-bit average result with the thresholds.
Equation 2 provides the LSB value of the 16-bit average result.
1 LSB
18
AVDD
216
(2)
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8.3.8 CRC on Data Interface
The cyclic redundancy check (CRC) is an error checking code that detects errors in communication between the
device and the host. The CRC module is optional and can be enabled by the CRC_EN bit in the
GENERAL_CFG register.
The CRC data byte is the 8-bit remainder of the bitwise exclusive-OR (XOR) operation of the argument by a
CRC polynomial. The CRC polynomial is based on the CRC-8-CCITT: X 8 + X 2 + X + 1. The nine binary
polynomial coefficients are 100000111. The CRC calculation is preset with 0 data values.
8.3.8.1 Input CRC (From Host To Device)
The host must compute and append the appropriate 8-bit CRC to the command string in the same SPI frame
(see Register Read With CRC). The ADC also computes the expected 8-bit CRC corresponding to the 24-bit
payload received from the host and compares the calculated CRC code to the CRC received from the host. If a
communication error is detected, the CRCERR_IN bit in the SYSTEM_STATUS register is set to 1b. The
CRCERR_IN bit is set in the following scenarios:
• The SPI communication frame did not have 32 clocks exactly, corresponding to a 24-bit data payload and an
8-bit CRC.
• The CRC calculated by the ADC over the received 24-bit payload does not match with the corresponding 8bit CRC received from the host.
If a CRC error is detected by the device, the command does not execute and the CRCERR_IN flag is set to 1b.
ADC conversion data read and register read, with a valid CRC from the host, are still supported. The error
condition can be detected, as listed in Table 8-5, by either status flags or by a register read. Further register
writes to the device are blocked until CRCERR_IN flag is cleared to 0b. Register write operation, with valid CRC
from the host, to the SYSTEM_STATUS and GENERAL_CFG registers is still supported.
The device can be configured to set all channels to analog inputs on detecting a CRC error by setting CH_RST
bit to 1b. This would ensure that channels which were configured as digital outputs are not driven by the device
when CRC error is detected. All channels will be reset as per the configuration in the PIN_CFG and GPIO_CFG
registers when CRCERR_IN flag is cleared.
The device can be configured to abort further conversions in autonomous and turbo comparator modes (see the
Autonomous Mode and Turbo Comparator Mode sections), on detecting a CRC error, by setting
CONV_ON_ERR = 1b.
Table 8-5. Configuring Notifications when CRC Error is Detected
CRC ERROR NOTIFICATION
CONFIGURATION
DESCRIPTION
ALERT
ALERT_CRCIN = 1b
ALERT (internal signal) is asserted if a CRC error is detected.
Status flags
APPEND_STATUS = 10b
See Status Flags for details.
Register read
—
Read the CRCERR_IN bit to check if a CRC error was detected.
8.3.8.2 Output CRC (From Device to Host)
The device appends an 8-bit CRC to the output data packet when the CRC module is enabled. The output data
packet length can be one of the following:
•
•
An 8-bit for register reads (see the Register Read With CRC section for more details).
A 16-bit or 24-bit for ADC conversion result reads (see Table 8-6 for more details).
The SPI frame must be exactly 32 bits long when the CRC module is enabled.
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8.3.9 Output Data Format
Figure 8-4 depicts various SPI frames for reading data from the device. The data output is MSB aligned. If
averaging is enabled the output data from the ADC are 16 bits long, otherwise the output data are 12 bits long.
Optionally, a 4-bit channel ID or status flags can be appended at the end of the output data by configuring the
APPEND_STATUS field.
CS
SCLK
1
12
2
13
14
15
16
18
17
19
20
Data output when averaging is disabled
OSR[2:0] = 00b
12 SCLKs minimum. Remaining clocks optional.
SDO
MSB
LSB
12 bit ADC data
Channel ID / Status Flags
4 bits optional
Data output when averaging is enabled
OSR[2:0] > 00b
16 SCLKs minimum. Remaining clocks optional.
SDO
LSB
MSB
Channel ID / Status Flags
16 bit averaged ADC data
4 bits optional
Figure 8-4. SPI Frames for Reading Data
Table 8-6. Output Data Frames
CRC_EN
OSR[2:0]
No averaging
CRC module
disabled
(CRC_EN = 0)
Averaging
enabled
No averaging
CRC module
(1)
enabled
(CRC_EN = 1)
(1)
Averaging
enabled
APPEND_STATUS[1:0]
OUTPUT DATA FRAME
No flags (00b or 11b)
{Conversion result [11:0]}
Channel ID (01b)
{Conversion result [11:0], CHID[3:0]}
Status flags (10b)
{Conversion result [11:0], status flags[3:0]}
No flags (00b or 11b)
{Conversion result [15:0]}
Channel ID (01b)
{Conversion result [15:0], CHID[3:0]}
Status flags (10b)
{Conversion result [15:0], status flags[3:0]}
No flags (00b or 11b)
{Conversion result [11:0], 4'b0, CRC[7:0], 8'b0}
Channel ID (01b)
{Conversion result [11:0], CHID[3:0], CRC[7:0], 8'b0}
Status flags (10b)
{Conversion result [11:0], status flags[3:0], CRC[7:0], 8'b0}
No flags (00b or 11b)
{Conversion result [15:0], CRC[7:0], 8'b0}
Channel ID (01b)
{Conversion result [15:0], CHID[3:0], 4'b0, CRC[7:0]}
Status flags (10b)
{Conversion result [15:0], status flags[3:0], 4'b0, CRC[7:0]}
The SPI frame must be 32 bits long when the CRC module is enabled; see the CRC on Data Interface section for more details.
8.3.9.1 Status Flags
Status flags can be appended to the ADC output by setting APPEND_STATUS = 10b. Status flags are not
appended to data corresponding to a register read operation or when FIX_PAT = 1b. The 4-bit status flag field is
constructed as follows:
Status flag[3:0] = { 1, 0, CRCERR_IN, ALERT }
• CRCERR_IN: This flag is the same as the CRCERR_IN bit in the SYSTEM_STATUS register.
• ALERT: This flag indicates if any of the event flags are set in the EVENT_FLAG register.
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8.3.10 Digital Window Comparator
The digital window comparator (DWC) compares the conversion result for an analog input channel with
programmable high and low thresholds with hysteresis. As shown in Figure 8-5, the DWC sets the
EVENT_HIGH_FLAG and EVENT_LOW_FLAG registers based on the comparison result. The logical OR of the
EVENT_HIGH_FLAG and EVENT_LOW_FLAG registers is available in the EVENT_FLAG register. An internal
ALERT signal is generated when a bit in the EVENT_FLAG register is high and the corresponding bit in the
ALERT_CH_SEL register is enabled. The internal ALERT signal can be output on any one of the digital output
channels by configuring the ALERT_PIN register.
EVENT_RGN[7]
EVENT_FLAG
EVENT_RGN[0]
Digital input CH0
ADC
Programmable
Averaging Filter
EVENT_HIGH_FLAG[0]
MUX
EVENT_LOW_FLAG[0]
Event
Counter
Low threshold +
8 x Hysteresis
PIN_CFG[0]
GPIO_CFG[0]
ALERT
All registers are specific for
individual analog input channels
ALERT_CH_SEL
High threshold ±
8 x Hysteresis
12-bit ADC data
or
[15:4] Average result
Figure 8-5. Digital Window Comparator Block Diagram
The low-side threshold, high-side threshold, event counter, and hysteresis parameters are independently
programmable for each input channel. Figure 8-6 illustrates that the window comparator can monitor events for
every analog input channel.
0xFFF
0xFFF
High threshold ± 8 x Hysteresis
Signal above limit
Digital code
Digital code
High threshold ± 8 x Hysteresis
Low threshold + 8 x Hysteresis
Signal below limit
Low threshold + 8 x Hysteresis
0x000
0x000
Samples
0xFFF
Samples
0xFFF
Signal out of band
High threshold ± 8 x Hysteresis
Digital code
Digital code
High threshold ± 8 x Hysteresis
EVENT_RGN = 0
Signal in band
Low threshold + 8 x Hysteresis
Low threshold + 8 x Hysteresis
EVENT_RGN = 1
Signal out of band
0x000
0x000
Samples
Samples
Figure 8-6. Event Monitoring With the Window Comparator
To enable the digital window comparator, set the DWC_EN bit in the GENERAL_CFG register. By default,
hysteresis = 0, high threshold = 0xFFF, and low threshold = 0x000. Configure the EVENT_RGN register to
detect when a signal is within a band defined by high and low thresholds. In each of the cases shown in Figure
8-6, either or both the EVENT_HIGH_FLAG and EVENT_LOW_FLAG can be set.
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The device features a programmable event counter that counts consecutive threshold violations before either
EVENT_HIGH_FLAG or EVENT_LOW_FLAG are set. An example is shown in Figure 8-7 where the
EVENT_HIGH_FLAG is not set until eight consecutive conversion results of the corresponding analog input
channel exceed the threshold configuration. The event count can be set to a higher value to avoid transients in
the input signal from setting the event flags.
EVENT_COUNT_CHx = 8
(waits for 8 counts to set alert)
1
2 3
2
4
1
High Threshold
5
6
3
7
8
High Threshold t 8 x Hysteresis
0
Event counter is reset because the
high-side-comparator is reset before
8 samples exceed high threshold.
High Side Comparator
(Internal Only Signal)
EVENT_HIGH_FLAG
Figure 8-7. False Trigger Avoidance Using the Event Counter
To assert the ALERT signal, when either or both the EVENT_HIGH_FLAG and EVENT_LOW_FLAG are set for
a particular analog input channel, set the corresponding bit in the ALERT_CH_SEL register.
8.3.10.1 Interrupts From Digital Inputs
Rising edge or falling edge events can be detected on channels configured as digital inputs. As described in
Table 8-7, configure the EVENT_RGN register to select either a rising edge or falling edge event.
Table 8-7. Configuring Interrupts from Digital Inputs
22
PIN_CFG[7:0]
GPIO_CFG[7:0]
EVENT_RGN[7:0]
EVENT DESCRIPTION
1
0
0
A rising edge on the digital input sets the corresponding flag in the
EVENT_HIGH_FLAG register.
1
0
1
A falling edge on the digital input sets the corresponding flag in the
EVENT_LOW_FLAG register.
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8.3.10.2 Triggering Digital Outputs With Digital Window Comparator
As shown in Figure 8-8, the output value of channels configured as digital outputs can be updated in response to
one or more flags being set in the EVENT_FLAG register.
The following procedure enables updating the output value of a digital output in response to event flags:
1. Configure the device channels as either analog inputs (default), digital inputs, or digital outputs.
2. Configure the digital outputs as either open-drain (default) or push-pull outputs.
3. Configure the digital window comparator for the input channels. The digital window comparator updates the
flags in the EVENT_FLAG register corresponding to individual channels. See the Digital Window Comparator
section for more details.
4. Select the bits corresponding to the input channels that are to be enabled for triggering the digital output in
the GPOx_EVENT_SEL register (where x is the digital output channel number).
5. The default output value of the digital output, when no event flag is set, is configured in the GPO_VALUE
register. The output value of the digital output, when event flags are set, is configured in the
GPO_VALUE_ON_EVENT register.
6. Configure the GPO_UPDATE_ON_EVENT register to enable the logic to update the selected digital output in
response to event flags.
The configuration in GPO_VALUE sets the output value of a dgital output when either no event flags are set or
when event flags are reset in the EVENT_FLAG register corresponding to channels selected in the
GPOx_EVENT_SEL register.
Digital output 7
Digital output 0
Select device channels for which corresponding
bits in EVENT_FLAG should trigger GPO0
GPO0_EVENT_SEL[7:0]
trigger
GPO_UPDATE_ON_EVENT [0]
Enable the selected EVENT_FLAG bits to trigger
GPO00
Default
0
GPO_VALUE [0]
1
GPO_VALUE_ON_EVENT [0]
Output value when one of the selected
events is asserted
Figure 8-8. Block Diagram of the Digital Output Logic
8.3.11 Minimum, Maximum, and Latest Data Registers
The ADS7038-Q1 can record the minimum, maximum, and latest conversion result (statistics registers) for every
analog input channel. To enable or re-enable recording statistics, set the STATS_EN bit in the GENERAL_CFG
register. Writing 1b to the STATS_EN bit reinitializes the statistics module. Previous values can be read from the
statistics registers until a new conversion result is available. Set STATS_EN = 0b to prevent any updates to this
block of registers before reading the statistics registers.
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8.3.12 Device Programming
8.3.12.1 Enhanced-SPI Interface
The device features an enhanced-SPI interface that allows the host controller to operate at slower SCLK speeds
and still achieve full throughput. As described in Table 8-8, the host controller can use any of the four SPIcompatible protocols (SPI-00, SPI-01, SPI-10, or SPI-11) to access the device.
Table 8-8. SPI Protocols for Configuring the Device
PROTOCOL
SCLK POLARITY
(At the CS Falling Edge)
SCLK PHASE
(Capture Edge)
CPOL_CPHA[1:0]
DIAGRAM
SPI-00
Low
Rising
00b
Figure 8-9
SPI-01
Low
Falling
01b
Figure 8-10
SPI-10
High
Falling
10b
Figure 8-9
SPI-11
High
Rising
11b
Figure 8-10
On power-up or after coming out of any asynchronous reset, the device supports the SPI-00 protocol for data
read and data write operations. To select a different SPI-compatible protocol, program the CPOL_CPHA[1:0]
field. This first write operation must adhere to the SPI-00 protocol. Any subsequent data transfer frames must
adhere to the newly-selected protocol.
CS
CS
CPOL = 0
CPOL = 0
SCLK
SCLK
CPOL = 1
SDO
CPOL = 1
MSB
MSB-1
MSB-2
LSB+1
LSB
SDO
Figure 8-9. Standard SPI Timing Protocol
(CPHA = 0)
0
MSB
MSB-1
LSB+1
LSB
Figure 8-10. Standard SPI Timing Protocol
(CPHA = 1)
8.3.12.2 Register Read/Write Operation
The device supports the commands listed in Table 8-9 to access the internal configuration registers.
Table 8-9. Opcodes for Commands
OPCODE
24
COMMAND DESCRIPTION
0000 0000b
No operation
0001 0000b
Single register read
0000 1000b
Single register write
0001 1000b
Set bit
0010 0000b
Clear bit
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8.3.12.2.1 Register Write
A 24-bit SPI frame is required for writing data to configuration registers. The 24-bit data on SDI, as shown in
Figure 8-11, consists of an 8-bit write command (0000 1000b), an 8-bit register address, and 8-bit data. The
write command is decoded on the CS rising edge and the specified register is updated with the 8-bit data
specified during the register write operation.
CS
SCLK
1
2
8
9
0000 1000b
(WR_REG)
SDI
10
16
18
17
8-bit Address
24
8-bit Data
Figure 8-11. Register Write Operation
8.3.12.2.2 Register Read
Register read operation consists of two SPI frames: the first SPI frame initiates a register read and the second
SPI frame reads data from the register address provided in the first frame. As shown in Figure 8-12, the 8-bit
register address and the 8-bit dummy data are sent over the SDI pin during the first 24-bit frame with the read
command (0001 0000b). On the rising edge of CS, the read command is decoded and the requested register
data are available for reading during the next frame. During the second frame, the first eight bits on SDO
correspond to the requested register read. During the second frame, SDI can be used to initiate another
operation or can be set to 0.
CS
SCLK
SDI
1
2
0001 0000b
(RD_REG)
8
9
10
8-bit Address
16
17
18
0000 0000b
24
1
2
8
9
Command
10
16
8-bit Address
17
18
24
8-bit Data
Optional; can set SDI = 0
SDO
8-bit Register Data
Figure 8-12. Register Read Operation
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8.3.12.2.2.1 Register Read With CRC
A register read consists of two SPI frames, as described in the Register Read section. As shown in Figure 8-13,
the device appends an 8-bit output CRC byte along with 8-bit register data when the CRC module is enabled
during a register read. The output CRC is computed by the device on 8-bit register data.
CS
SCLK
SDI
1
0001 0000b
(RD_REG)
8
9
16
8-bit
Address
Data payload (24 bit)
24
17
0000
0000b
25
1
32
8
Input
CRC[7:0]
9
16
17
NOP (SDI = 0)
Input CRC is calculated
on 24 bit payload
Data payload (24 bit)
Register
Data
SDO
Data payload (8 bit)
24
25
32
Input
CRC[7:0]
Input CRC is calculated
on 24 bit payload
Output
CRC[7:0]
Output CRC is calculated on 8 bit payload
Figure 8-13. Register Read With CRC
26
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8.4 Device Functional Modes
Table 8-10 lists the functional modes supported by the ADS7038-Q1. The device powers up in manual mode and
can be configured into either of these modes by writing the configuration registers for the desired mode.
Table 8-10. Functional Modes
FUNCTIONAL MODE CONVERSION CONTROL
CONV_MODE[1:0]
SEQ_MODE[1:0]
Manual
CS rising edge
Register write to MANUAL_CHID
MUX CONTROL
00b
00b
On-the-fly
CS rising edge
First 5 bits after the CS falling edge
00b
10b
Auto-sequence
CS rising edge
Channel sequencer
00b
01b
Autonomous
Internal to the device
Channel sequencer
01b
01b
Turbo comparator
Internal to the device
Channel sequencer
10b
01b
8.4.1 Device Power-Up and Reset
On power-up, the BOR bit is set indicating a power-cycle or reset event. The device can be reset by setting the
RST bit or by recycling power on the AVDD pin.
8.4.2 Manual Mode
Manual mode allows the external host processor to directly select the analog input channel. Figure 8-14 shows
the steps for operating the device in manual mode.
Idle
SEQ_MODE = 0b
CONV_MODE = 0b
Configure channels as AIN/GPIO using PIN_CFG
Calibrate offset error (CAL = 1b)
Select Manual mode
(CONV_MODE = 00b, SEQ_MODE = 00b)
Configure desired Channel ID in MANUAL_CHID field
Host starts conversion and reads conversion result
No
Same
Channel ID?
Yes
Figure 8-14. Device Operation in Manual Mode
In manual mode, the command to switch to a new channel (indicated by cycle N in Figure 8-15) is decoded by
the device on the CS rising edge. The CS rising edge is also the start of the conversion signal, and therefore the
device samples the previously selected MUX channel in cycle N+1. The newly selected analog input channel
data are available in cycle N+2. For switching the analog input channel, a register write to the MANUAL_CHID
field requires 24 clocks; see the Register Write section for more details. After a channel is selected, the number
of clocks required for reading the output data depends on the device output data frame size; see the Output
Data Format section for more details.
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Sample
AINx
Sample
AINx
Sample
AINy
tCONV
Sample
AINz
tCYCLE
CS
SCLK
SDI
SDO
100-ns
Switch to AINy
Switch to AINz
Switch to AINx
Data AINx
Data AINx
Data AINy
24 clocks
MUX OUT = AINx
MUX
Cycle N
MUX OUT = AINy
MUX OUT = AINz
Cycle (N + 1)
Cycle (N + 2)
Figure 8-15. Starting Conversions and Reading Data in Manual Mode
8.4.3 On-the-Fly Mode
In the on-the-fly mode of operation, the analog input channel is selected, as shown in Figure 8-16, using the first
five bits on SDI without waiting for the CS rising edge. Thus, the ADC samples the newly selected channel on
the CS rising edge and there is no latency between the channel selection and the ADC output data.
Sample
AINx
Sample
AINx
Sample
AINy
tCONV
Sample
AINz
tCYCLE
CS
SCLK
1
SEQ_MODE =
10b
SDI
SDO
MUX
24
1
1
2
3
100-ns
5
12
1
4-bit AINy ID
1
Data AINx
Data AINx
MUX OUT = AINx
4
2
3
4
5
12
4-bit AINz ID
Data AINy
MUX OUT = AINy
MUX OUT = AINx
MUX OUT = AINz
No Cycle Latency
Figure 8-16. Starting Conversions and Reading Data in On-the-Fly Mode
The number of clocks required for reading the output data depends on the device output data frame size; see
the Output Data Format section for more details.
28
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8.4.4 Auto-Sequence Mode
In auto-sequence mode, the internal channel sequencer switches the multiplexer to the next analog input
channel after every conversion. The desired analog input channels can be configured for sequencing in the
AUTO_SEQ_CH_SEL register. To enable the channel sequencer, set SEQ_START = 1b. After every conversion,
the channel sequencer switches the multiplexer to the next analog input in ascending order. To stop the channel
sequencer from selecting channels, set SEQ_START = 0b.
In the example shown in Figure 8-17, AIN2 and AIN6 are enabled for sequencing in AUTO_SEQ_CH_SEL. The
channel sequencer loops through AIN2 and AIN6 and repeats until SEQ_START is set to 0b. The number of
clocks required for reading the output data depends on the device output data frame size; see the Output Data
Format section for more details.
Sample
AINx
Sample
AIN2
Sample
AIN6
Sample
AIN2
Sample
AIN6
tCYCLE
CS
SCLK
SDI
SDO
MUX
SEQ_START
Data AINx
Data AINx
24 clocks
12 clocks
MUX OUT = AINx
MUX OUT = AIN2
Data AIN2
Data AIN6
Data AIN2
MUX OUT = AIN6
MUX OUT = AIN2
MUX OUT = AIN6
Scan channels AIN2 and AIN6 and repeat
Figure 8-17. Starting Conversions and Reading Data in Auto-Sequence Mode
8.4.5 Autonomous Mode
In autonomous mode, the device can be programmed to monitor the voltage applied on the analog input pins of
the device and generate an ALERT signal internal to the device when the programmable high or low thresholds
are crossed (see the Digital Window Comparator section for more details).
In autonomous mode, the device generates the start of conversion using the internal oscillator. The first start of
conversion must be provided by the host and the device generates the subsequent start of conversions. The
device does not output conversion data when autonomous mode is enabled. Conversion results can be
accessed using the register read operation described in the Minimum, Maximum, and Latest Data Registers
section by configuring STATS_EN = 1b in the GENERAL_CFG register.
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Figure 8-18 shows the steps for configuring the functional mode to autonomous mode. Abort the ongoing
sequence by setting SEQ_START to 0b before changing the functional mode or device configuration.
Idle
SEQ_MODE = 0b
CONV_MODE = 0b
Configure channels as AIN/GPIO using PIN_CFG
Calibrate offset error (CAL = 1b)
Channel
selection
Enable analog inputs for sequencing (AUTO_SEQ_CH_SEL)
Select Auto-sequence mode (SEQ_MODE = 01b)
Configure alert condition using HIGH_TH_CHx,
LOW_TH_CHx,EVENT_COUNT_CHx, HYSTERESIS_CHx, and
EVENT_REGION_CHx fields
Enable analog inputs to trigger ALERT pin using ALERT_CH_SEL
Configuration
Threshold & Alert
configuration
Configure ALERT pin using ALERT_DRIVE and ALERT_LOGIC fields
Configure sampling rate of analog inputs using OSC_SEL and CLK_DIV
Set mode to autonomous monitoring (CONV_MODE = 01b)
Sampling rate
configuration
(optional) Enable averaging and min/max recording (OSR[2:0] and STATS_EN)
Enable threshold comparison (DWC_EN = 1b)
Enable autonomous monitoring (SEQ_START = 1b)
Active Operation
(Digital
communication
interface can be idle)
No
ALERT?
(optional) read conversion results in
MIN_VALUE_CHx, MAX_VALUE_CHx, and
LAST_VALUE_CHx registers
Yes
Stop autonomous monitoring (SEQ_START = 0b)
Disable threshold comparison (DWC_EN = 0b)
ALERT Detected
Read alert flags ± EVENT_FLAG, EVENT_HIGH_FLAG, EVENT_LOW_FLAG
Clear alert flags ± EVENT_HIGH_FLAG, EVENT_LOW_FLAG
Figure 8-18. Configuring the Device in Autonomous Mode
30
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8.4.6 Turbo Comparator Mode
Turbo comparator mode allows fast comparison with high/low thresholds using the digital window comparator.
ADC output data is not available in this mode.
Figure 8-19 lists the comparison start and read frames for turbo comparator mode. The desired analog input
channels can be configured for sequencing in the AUTO_SEQ_CH_SEL register. To enable the channel
sequencer, set SEQ_START to 1b. After every comparison, the channel sequencer switches the multiplexer to
the next analog input in ascending order. To stop the channel sequencer from selecting channels, set
SEQ_START to 0b. See sction on Oscillator and Timing Control for more details on configuring speed in turbo
comparator mode.
Abort the ongoing sequence by setting SEQ_START to 0b before changing the functional mode or device
configuration.
Idle
SEQ_MODE = 0b
CONV_MODE = 0b
Configure channels as AIN/GPIO using PIN_CFG
Calibrate offset error (CAL = 1b)
Channel
selection
Enable analog inputs for sequencing (AUTO_SEQ_CH_SEL)
Select auto-sequence mode (SEQ_MODE = 01b)
Configure alert condition using HIGH_TH_CHx,
LOW_TH_CHx,EVENT_COUNT_CHx, HYSTERESIS_CHx, and
EVENT_REGION_CHx fields
Enable analog inputs to trigger ALERT pin using ALERT_CH_SEL
Threshold & Alert
configuration
Configuration
Configure ALERT pin using ALERT_DRIVE and ALERT_LOGIC fields
Configure sampling rate of analog inputs using OSC_SEL and CLK_DIV
Select turbo comparator mode (CONV_MODE = 10b)
Sampling rate
configuration
Enable threshold comparison (DWC_EN = 1b)
Start turbo comparator mode (SEQ_START = 1b)
Active Operation
(Digital
communication
interface can be idle)
No
ALERT?
Yes
Stop turbo comparator mode (SEQ_START = 0b)
Disable threshold comparison (DWC_EN = 0b)
ALERT Detected
Read alert flags ± EVENT_FLAG, EVENT_HIGH_FLAG, EVENT_LOW_FLAG
Clear alert flags ± EVENT_HIGH_FLAG, EVENT_LOW_FLAG
Figure 8-19. Device Operation in Turbo Comparator Mode
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8.5 ADS7038-Q1 Registers
Table 8-11 lists the memory-mapped registers for the ADS7038-Q1 registers. All register offset addresses not
listed in Table 8-11 should be considered as reserved locations and the register contents should not be modified.
Table 8-11. ADS7038-Q1 Registers
Address
32
Acronym
Register Name
Section
0x0
SYSTEM_STATUS
Section 8.5.1
0x1
GENERAL_CFG
Section 8.5.2
0x2
DATA_CFG
Section 8.5.3
0x3
OSR_CFG
Section 8.5.4
0x4
OPMODE_CFG
Section 8.5.5
0x5
PIN_CFG
Section 8.5.6
0x7
GPIO_CFG
Section 8.5.7
0x9
GPO_DRIVE_CFG
Section 8.5.8
0xB
GPO_VALUE
Section 8.5.9
0xD
GPI_VALUE
Section 8.5.10
0x10
SEQUENCE_CFG
Section 8.5.11
0x11
MANUAL_CH_SEL
Section 8.5.12
0x12
AUTO_SEQ_CH_SEL
Section 8.5.13
0x14
ALERT_CH_SEL
Section 8.5.14
0x16
ALERT_FUNC_SEL
Section 8.5.15
0x17
ALERT_PIN_CFG
Section 8.5.16
0x18
EVENT_FLAG
Section 8.5.17
0x1A
EVENT_HIGH_FLAG
Section 8.5.18
0x1C
EVENT_LOW_FLAG
Section 8.5.19
0x1E
EVENT_RGN
Section 8.5.20
0x20
HYSTERESIS_CH0
Section 8.5.21
0x21
HIGH_TH_CH0
Section 8.5.22
0x22
EVENT_COUNT_CH0
Section 8.5.23
0x23
LOW_TH_CH0
Section 8.5.24
0x24
HYSTERESIS_CH1
Section 8.5.25
0x25
HIGH_TH_CH1
Section 8.5.26
0x26
EVENT_COUNT_CH1
Section 8.5.27
0x27
LOW_TH_CH1
Section 8.5.28
0x28
HYSTERESIS_CH2
Section 8.5.29
0x29
HIGH_TH_CH2
Section 8.5.30
0x2A
EVENT_COUNT_CH2
Section 8.5.31
0x2B
LOW_TH_CH2
Section 8.5.32
0x2C
HYSTERESIS_CH3
Section 8.5.33
0x2D
HIGH_TH_CH3
Section 8.5.34
0x2E
EVENT_COUNT_CH3
Section 8.5.35
0x2F
LOW_TH_CH3
Section 8.5.36
0x30
HYSTERESIS_CH4
Section 8.5.37
0x31
HIGH_TH_CH4
Section 8.5.38
0x32
EVENT_COUNT_CH4
Section 8.5.39
0x33
LOW_TH_CH4
Section 8.5.40
0x34
HYSTERESIS_CH5
Section 8.5.41
0x35
HIGH_TH_CH5
Section 8.5.42
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Table 8-11. ADS7038-Q1 Registers (continued)
Address
Acronym
Register Name
Section
0x36
EVENT_COUNT_CH5
Section 8.5.43
0x37
LOW_TH_CH5
Section 8.5.44
0x38
HYSTERESIS_CH6
Section 8.5.45
0x39
HIGH_TH_CH6
Section 8.5.46
0x3A
EVENT_COUNT_CH6
Section 8.5.47
0x3B
LOW_TH_CH6
Section 8.5.48
0x3C
HYSTERESIS_CH7
Section 8.5.49
0x3D
HIGH_TH_CH7
Section 8.5.50
0x3E
EVENT_COUNT_CH7
Section 8.5.51
0x3F
LOW_TH_CH7
Section 8.5.52
0x60
MAX_CH0_LSB
Section 8.5.53
0x61
MAX_CH0_MSB
Section 8.5.54
0x62
MAX_CH1_LSB
Section 8.5.55
0x63
MAX_CH1_MSB
Section 8.5.56
0x64
MAX_CH2_LSB
Section 8.5.57
0x65
MAX_CH2_MSB
Section 8.5.58
0x66
MAX_CH3_LSB
Section 8.5.59
0x67
MAX_CH3_MSB
Section 8.5.60
0x68
MAX_CH4_LSB
Section 8.5.61
0x69
MAX_CH4_MSB
Section 8.5.62
0x6A
MAX_CH5_LSB
Section 8.5.63
0x6B
MAX_CH5_MSB
Section 8.5.64
0x6C
MAX_CH6_LSB
Section 8.5.65
0x6D
MAX_CH6_MSB
Section 8.5.66
0x6E
MAX_CH7_LSB
Section 8.5.67
0x6F
MAX_CH7_MSB
Section 8.5.68
0x80
MIN_CH0_LSB
Section 8.5.69
0x81
MIN_CH0_MSB
Section 8.5.70
0x82
MIN_CH1_LSB
Section 8.5.71
0x83
MIN_CH1_MSB
Section 8.5.72
0x84
MIN_CH2_LSB
Section 8.5.73
0x85
MIN_CH2_MSB
Section 8.5.74
0x86
MIN_CH3_LSB
Section 8.5.75
0x87
MIN_CH3_MSB
Section 8.5.76
0x88
MIN_CH4_LSB
Section 8.5.77
0x89
MIN_CH4_MSB
Section 8.5.78
0x8A
MIN_CH5_LSB
Section 8.5.79
0x8B
MIN_CH5_MSB
Section 8.5.80
0x8C
MIN_CH6_LSB
Section 8.5.81
0x8D
MIN_CH6_MSB
Section 8.5.82
0x8E
MIN_CH7_LSB
Section 8.5.83
0x8F
MIN_CH7_MSB
Section 8.5.84
0xA0
RECENT_CH0_LSB
Section 8.5.85
0xA1
RECENT_CH0_MSB
Section 8.5.86
0xA2
RECENT_CH1_LSB
Section 8.5.87
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Table 8-11. ADS7038-Q1 Registers (continued)
Address
Acronym
Register Name
Section
0xA3
RECENT_CH1_MSB
Section 8.5.88
0xA4
RECENT_CH2_LSB
Section 8.5.89
0xA5
RECENT_CH2_MSB
Section 8.5.90
0xA6
RECENT_CH3_LSB
Section 8.5.91
0xA7
RECENT_CH3_MSB
Section 8.5.92
0xA8
RECENT_CH4_LSB
Section 8.5.93
0xA9
RECENT_CH4_MSB
Section 8.5.94
0xAA
RECENT_CH5_LSB
Section 8.5.95
0xAB
RECENT_CH5_MSB
Section 8.5.96
0xAC
RECENT_CH6_LSB
Section 8.5.97
0xAD
RECENT_CH6_MSB
Section 8.5.98
0xAE
RECENT_CH7_LSB
Section 8.5.99
0xAF
RECENT_CH7_MSB
Section 8.5.100
0xC3
GPO0_EVENT_CFG
Section 8.5.101
0xC5
GPO1_EVENT_CFG
Section 8.5.102
0xC7
GPO2_EVENT_CFG
Section 8.5.103
0xC9
GPO3_EVENT_CFG
Section 8.5.104
0xCB
GPO4_EVENT_CFG
Section 8.5.105
0xCD
GPO5_EVENT_CFG
Section 8.5.106
0xCF
GPO6_EVENT_CFG
Section 8.5.107
0xD1
GPO7_EVENT_CFG
Section 8.5.108
0xE9
GPO_UPDATE_ON_EVENT
Section 8.5.109
0xEB
GPO_VALUE_ON_EVENT
Section 8.5.110
Complex bit access types are encoded to fit into small table cells. Table 8-12 shows the codes that are used for
access types in this section.
Table 8-12. ADS7038-Q1 Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n
34
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
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Table 8-12. ADS7038-Q1 Access Type Codes
(continued)
Access Type
Code
Description
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
8.5.1 SYSTEM_STATUS Register (Address = 0x0) [Reset = 0x81]
SYSTEM_STATUS is shown in Figure 8-18 and described in Table 8-13.
Return to the Table 8-11.
Figure 8-18. SYSTEM_STATUS Register
7
6
3
2
1
0
RSVD
SEQ_STATUS
5
RESERVED
4
OSR_DONE
CRCERR_FUS
E
CRCERR_IN
BOR
R-1b
R-0b
R-0b
R/W-0b
R-0b
R/W-0b
R/W-1b
Table 8-13. SYSTEM_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RSVD
R
1b
Reads return 1b.
6
SEQ_STATUS
R
0b
Status of the channel sequencer.
0b = Sequence stopped
1b = Sequence in progress
5-4
RESERVED
R
0b
Reserved Bit
3
OSR_DONE
R/W
0b
Averaging status. Clear this bit by writing 1b to this bit.
0b = Averaging in progress or not started; average result is not
ready.
1b = Averaging complete; average result is ready.
2
CRCERR_FUSE
R
0b
Device power-up configuration CRC check status. To re-evaluate this
bit, software reset the device or power cycle AVDD.
0b = No problems detected in power-up configuration.
1b = Device configuration not loaded correctly.
1
CRCERR_IN
R/W
0b
Status of CRC check on incoming data. Write 1b to clear this error
flag.
0b = No CRC error.
1b = CRC error detected. All register writes, except to addresses
0x00 and 0x01, are blocked.
0
BOR
R/W
1b
Brown out reset indicator. This bit is set if brown out condition occurs
or device is power cycled. Write 1b to this bit to clear the flag.
0b = No brown out condition detected from the last time this bit was
cleared.
1b = Brown out condition detected or device power cycled.
8.5.2 GENERAL_CFG Register (Address = 0x1) [Reset = 0x0]
GENERAL_CFG is shown in Figure 8-19 and described in Table 8-14.
Return to the Table 8-11.
Figure 8-19. GENERAL_CFG Register
7
6
5
4
3
2
1
0
RESERVED
CRC_EN
STATS_EN
DWC_EN
RESERVED
CH_RST
CAL
RST
R-0b
R/W-0b
R/W-0b
R/W-0b
R-0b
R/W-0b
R/W-0b
W-0b
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Table 8-14. GENERAL_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0b
Reserved Bit
6
CRC_EN
R/W
0b
Enable or disable the CRC on device interface.
0b = CRC module disabled.
1b = CRC appended to data output. CRC check is enabled on
incoming data.
5
STATS_EN
R/W
0b
Enable or disable the statistics module.
0b = Minimum, maximum, and recent value registers are not
updated.
1b = Clear minimum, maximum, and recent value registers and
conitnue updating with new conversion results.
4
DWC_EN
R/W
0b
Enable or disable the digital window comparator.
0b = Reset or disable the digital window comparator.
1b = Enable digital window comparator.
3
RESERVED
R
0b
Reserved Bit
2
CH_RST
R/W
0b
Force all channels to be analog inputs.
0b = Normal operation.
1b = All channels will be set as analog inputs irrespective of
configuration in other registers.
1
CAL
R/W
0b
Calibrate ADC offset.
0b = Normal operation.
1b = ADC offset is calibrated. After calibration is complete, this bit is
set to 0b by the device.
0
RST
W
0b
Software reset all registers to default values.
0b = Normal operation.
1b = Device is reset. After reset is complete, this bit is set to 0b and
BOR bit is set to 1b by the device.
8.5.3 DATA_CFG Register (Address = 0x2) [Reset = 0x0]
DATA_CFG is shown in Figure 8-20 and described in Table 8-15.
Return to the Table 8-11.
Figure 8-20. DATA_CFG Register
7
6
5
FIX_PAT
RESERVED
APPEND_STATUS[1:0]
4
3
RESERVED
2
1
CPOL_CPHA[1:0]
0
R/W-0b
R-0b
R/W-0b
R-0b
R/W-0b
Table 8-15. DATA_CFG Register Field Descriptions
Bit
36
Field
Type
Reset
Description
7
FIX_PAT
R/W
0b
Device outputs fixed data bits which can be helpful for debugging
communication with the device.
0b = Normal operation.
1b = Device outputs fixed code 0xA5A repeatitively when reading
data from the device.
6
RESERVED
R
0b
Reserved Bit
5-4
APPEND_STATUS[1:0]
R/W
0b
Append 4-bit channel ID or status flags to output data. 00b: 01b: 10b:
11b:
0b = Channel ID and status flags are not appended to ADC data.
1b = 4-bit channel ID is appended to ADC data.
10b = 4-bit status flags are appended to ADC data.
11b = Reserved.
3-2
RESERVED
R
0b
Reserved Bit
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Table 8-15. DATA_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
CPOL_CPHA[1:0]
R/W
0b
This field sets the polarity and phase of SPI communication.
0b = CPOL = 0, CPHA = 0.
1b = CPOL = 0, CPHA = 1.
10b = CPOL = 1, CPHA = 0.
11b = CPOL = 1, CPHA = 1.
8.5.4 OSR_CFG Register (Address = 0x3) [Reset = 0x0]
OSR_CFG is shown in Figure 8-21 and described in Table 8-16.
Return to the Table 8-11.
Figure 8-21. OSR_CFG Register
7
6
5
4
3
2
1
RESERVED
OSR[2:0]
R-0b
R/W-0b
0
Table 8-16. OSR_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
0b
Reserved Bit
2-0
OSR[2:0]
R/W
0b
Selects the oversampling ratio for ADC conversion result.
0b = No averaging
1b = 2 samples
10b = 4 samples
11b = 8 samples
100b = 16 samples
101b = 32 samples
110b = 64 samples
111b = 128 samples
8.5.5 OPMODE_CFG Register (Address = 0x4) [Reset = 0x0]
OPMODE_CFG is shown in Figure 8-22 and described in Table 8-17.
Return to the Table 8-11.
Figure 8-22. OPMODE_CFG Register
7
6
5
4
3
2
1
CONV_ON_ER
R
CONV_MODE[1:0]
OSC_SEL
CLK_DIV[3:0]
R/W-0b
R/W-0b
R/W-0b
R/W-0b
0
Table 8-17. OPMODE_CFG Register Field Descriptions
Bit
7
Field
Type
Reset
Description
CONV_ON_ERR
R/W
0b
Control continuation of autonomous and turbo comparator modes if
CRC error is detected on communication interface.
0b = If CRC error is detected, device continues channel sequencing
and pin configuration is retained. See the CRCERR_IN bit for more
details.
1b = If CRC error is detected, device changes all channels to analog
inputs and channel sequencing is paused until CRCERR_IN flag is
cleared. After clearing CRCERR_IN flag, device resumes channel
sequencing and pin confguration is restored.
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Table 8-17. OPMODE_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6-5
CONV_MODE[1:0]
R/W
0b
These bits set the mode of conversion of the ADC.
0b = Manual mode; conversions are initiated by host.
1b = Autonomous mode; conversions are initiated by the internal
state machine.
10b = Turbo mode; comparisons are initiated by internal state
machine.
OSC_SEL
R/W
0b
Selects the oscillator for internal timing generation.
0b = High-speed oscillator.
1b = Low-power oscillator.
CLK_DIV[3:0]
R/W
0b
Sampling speed control in autonomous monitoring mode
(CONV_MODE = 01b). See the section on Oscillator and Timing
Control for details.
4
3-0
8.5.6 PIN_CFG Register (Address = 0x5) [Reset = 0x0]
PIN_CFG is shown in Figure 8-23 and described in Table 8-18.
Return to the Table 8-11.
Figure 8-23. PIN_CFG Register
7
6
5
4
3
2
1
0
PIN_CFG[7:0]
R/W-0b
Table 8-18. PIN_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PIN_CFG[7:0]
R/W
0b
Configure device channels AIN / GPIO [7:0] as analog inputs or
GPIOs.
0b = Channel is configured as an analog input.
1b = Channel is configured as a GPIO.
8.5.7 GPIO_CFG Register (Address = 0x7) [Reset = 0x0]
GPIO_CFG is shown in Figure 8-24 and described in Table 8-19.
Return to the Table 8-11.
Figure 8-24. GPIO_CFG Register
7
6
5
4
3
2
1
0
GPIO_CFG[7:0]
R/W-0b
Table 8-19. GPIO_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPIO_CFG[7:0]
R/W
0b
Configure GPIO[7:0] as either digital inputs or digital outputs.
0b = GPIO is configured as digital input.
1b = GPIO is configured as digital output.
8.5.8 GPO_DRIVE_CFG Register (Address = 0x9) [Reset = 0x0]
GPO_DRIVE_CFG is shown in Figure 8-25 and described in Table 8-20.
Return to the Table 8-11.
38
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Figure 8-25. GPO_DRIVE_CFG Register
7
6
5
4
3
2
1
0
GPO_DRIVE_CFG[7:0]
R/W-0b
Table 8-20. GPO_DRIVE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO_DRIVE_CFG[7:0]
R/W
0b
Configure digital outputs GPO[7:0] as open-drain or push-pull
outputs.
0b = Digital output is open-drain; connect external pullup resistor.
1b = Push-pull driver is used for digital output.
8.5.9 GPO_VALUE Register (Address = 0xB) [Reset = 0x0]
GPO_VALUE is shown in Figure 8-26 and described in Table 8-21.
Return to the Table 8-11.
Figure 8-26. GPO_VALUE Register
7
6
5
4
3
2
1
0
GPO_VALUE[7:0]
R/W-0b
Table 8-21. GPO_VALUE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO_VALUE[7:0]
R/W
0b
Logic level to be set on digital outputs GPO[7:0].
0b = Digital output is set to logic 0.
1b = Digital output is set to logic 1.
8.5.10 GPI_VALUE Register (Address = 0xD) [Reset = 0x0]
GPI_VALUE is shown in Figure 8-27 and described in Table 8-22.
Return to the Table 8-11.
Figure 8-27. GPI_VALUE Register
7
6
5
4
3
2
1
0
GPI_VALUE[7:0]
R-0b
Table 8-22. GPI_VALUE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPI_VALUE[7:0]
R
0b
Readback the logic level on AIN/GPIO[7:0]. This field returns the
readback value of logic level on all channels configured as analog
inputs, digital inputs, and digital outputs.
0b = GPIO is at logic 0.
1b = GPIO is at logic 1.
8.5.11 SEQUENCE_CFG Register (Address = 0x10) [Reset = 0x0]
SEQUENCE_CFG is shown in Figure 8-28 and described in Table 8-23.
Return to the Table 8-11.
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Figure 8-28. SEQUENCE_CFG Register
7
6
5
4
3
2
1
0
RESERVED
SEQ_START
RESERVED
SEQ_MODE[1:0]
R-0b
R/W-0b
R-0b
R/W-0b
Table 8-23. SEQUENCE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R
0b
Reserved Bit
4
SEQ_START
R/W
0b
Control for start of channel sequence when using auto sequence
mode (SEQ_MODE = 01b).
0b = Stop channel sequencing.
1b = Start channel sequencing in ascending order for channels
enabled in AUTO_SEQ_CH_SEL register.
3-2
RESERVED
R
0b
Reserved Bit
1-0
SEQ_MODE[1:0]
R/W
0b
Selects the mode of scanning of analog input channels.
0b = Manual sequence mode; channel selected by MANUAL_CHID
field.
1b = Auto sequence mode; channel selected by
AUTO_SEQ_CH_SEL.
10b = On-the-fly sequence mode.
11b = Reserved.
8.5.12 MANUAL_CH_SEL Register (Address = 0x11) [Reset = 0x0]
MANUAL_CH_SEL is shown in Figure 8-29 and described in Table 8-24.
Return to the Table 8-11.
Figure 8-29. MANUAL_CH_SEL Register
7
6
5
4
3
2
1
RESERVED
MANUAL_CHID[3:0]
R-0b
R/W-0b
0
Table 8-24. MANUAL_CH_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0b
Reserved Bit
3-0
MANUAL_CHID[3:0]
R/W
0b
In manual mode (SEQ_MODE = 00b), this field contains the 4-bit
channel ID of the analog input channel for next ADC conversion. For
valid ADC data, the selected channel must not be configured as
GPIO in PIN_CFG register. 1xxx = Reserved.
0b = AIN0
1b = AIN1
10b = AIN2
11b = AIN3
100b = AIN4
101b = AIN5
110b = AIN6
111b = AIN7
8.5.13 AUTO_SEQ_CH_SEL Register (Address = 0x12) [Reset = 0x0]
AUTO_SEQ_CH_SEL is shown in Figure 8-30 and described in Table 8-25.
Return to the Table 8-11.
Figure 8-30. AUTO_SEQ_CH_SEL Register
7
40
6
5
4
3
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Figure 8-30. AUTO_SEQ_CH_SEL Register (continued)
AUTO_SEQ_CH_SEL[7:0]
R/W-0b
Table 8-25. AUTO_SEQ_CH_SEL Register Field Descriptions
Bit
Field
Type
7-0
AUTO_SEQ_CH_SEL[7:0] R/W
Reset
Description
0b
Select device channels AIN/GPIO[7:0] for auto sequencing mode.
0b = Device channel is not enabled in scanning sequence.
1b = Device channel is enabled in scanning sequence.
8.5.14 ALERT_CH_SEL Register (Address = 0x14) [Reset = 0x0]
ALERT_CH_SEL is shown in Figure 8-31 and described in Table 8-26.
Return to the Table 8-11.
Figure 8-31. ALERT_CH_SEL Register
7
6
5
4
3
2
1
0
ALERT_CH_SEL[7:0]
R/W-0b
Table 8-26. ALERT_CH_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
ALERT_CH_SEL[7:0]
R/W
0b
Select channels for which the corresponding bits in the
EVENT_FLAG register can assert the internal ALERT signal. The
ALERT signal can be mapped to the digital output channel
configured in the ALERT_PIN[3:0] field.
0b = Event flags for this channel do not assert the ALERT pin.
1b = Event flags for this channel assert the ALERT pin.
8.5.15 ALERT_FUNC_SEL Register (Address = 0x16) [Reset = 0x0]
ALERT_FUNC_SEL is shown in Figure 8-32 and described in Table 8-27.
Return to the Table 8-11.
Figure 8-32. ALERT_FUNC_SEL Register
7
6
5
4
3
2
1
0
RESERVED
ALERT_CRCIN
R-0b
R/W-0b
Table 8-27. ALERT_FUNC_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R
0b
Reserved Bit
ALERT_CRCIN
R/W
0b
Enable or disable the alert notification for CRC error on input data
(CRCERR_IN = 1b).
0b = ALERT signal is not asserted when CRCERR_IN = 1b.
1b = ALERT signal is asserted when CRCERR_IN = 1b. Clear
CRCERR_IN for deasserting the ALERT pin.
0
8.5.16 ALERT_PIN_CFG Register (Address = 0x17) [Reset = 0x0]
ALERT_PIN_CFG is shown in Figure 8-33 and described in Table 8-28.
Return to the Table 8-11.
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Figure 8-33. ALERT_PIN_CFG Register
7
6
5
4
3
2
1
0
ALERT_PIN[3:0]
RESERVED
ALERT_LOGIC[1:0]
R/W-0b
R-0b
R/W-0b
Table 8-28. ALERT_PIN_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
ALERT_PIN[3:0]
R/W
0b
Internal ALERT output of the digital window comparator will be output
on this channel. This channel must be configured as digital output.
3-2
RESERVED
R
0b
Reserved Bit
1-0
ALERT_LOGIC[1:0]
R/W
0b
Configure how the ALERT signal is asserted.
0b = Active low.
1b = Active high.
10b = Pulsed low (one logic low pulse).
11b = Pulsed high (one logic high pulse).
8.5.17 EVENT_FLAG Register (Address = 0x18) [Reset = 0x0]
EVENT_FLAG is shown in Figure 8-34 and described in Table 8-29.
Return to the Table 8-11.
Figure 8-34. EVENT_FLAG Register
7
6
5
4
3
2
1
0
EVENT_FLAG[7:0]
R-0b
Table 8-29. EVENT_FLAG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
EVENT_FLAG[7:0]
R
0b
Event flags indicating digital window comparator status for AIN/
GPIO[7:0]. Clear individual bits of EVENT_HIGH_FLAG or
EVENT_LOW_FLAG registers to clear the corresponding bit in this
register.
0b = Event condition not detected.
1b = Event condition detected.
8.5.18 EVENT_HIGH_FLAG Register (Address = 0x1A) [Reset = 0x0]
EVENT_HIGH_FLAG is shown in Figure 8-35 and described in Table 8-30.
Return to the Table 8-11.
Figure 8-35. EVENT_HIGH_FLAG Register
7
6
5
4
3
2
1
0
EVENT_HIGH_FLAG[7:0]
R/W-0b
Table 8-30. EVENT_HIGH_FLAG Register Field Descriptions
42
Bit
Field
Type
7-0
EVENT_HIGH_FLAG[7:0] R/W
Reset
Description
0b
Event flag corresponding to high threshold of analog input or rising
edge of digital input on AIN/GPIO[7:0]. Write 1b to clear this flag.
0b = No alert condition detected.
1b = Either high threshold was exceeded (analog input) or rising
edge was detected (digital input).
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8.5.19 EVENT_LOW_FLAG Register (Address = 0x1C) [Reset = 0x0]
EVENT_LOW_FLAG is shown in Figure 8-36 and described in Table 8-31.
Return to the Table 8-11.
Figure 8-36. EVENT_LOW_FLAG Register
7
6
5
4
3
2
1
0
EVENT_LOW_FLAG[7:0]
R/W-0b
Table 8-31. EVENT_LOW_FLAG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
EVENT_LOW_FLAG[7:0]
R/W
0b
Event flag corresponding to low threshold of analog input or falling
edge of digital input on AIN/GPIO[7:0]. Write 1b to clear this flag.
0b = No Event condition detected.
1b = Either low threshold was exceeded (analog input) or falling
edge was detected (digital input).
8.5.20 EVENT_RGN Register (Address = 0x1E) [Reset = 0x0]
EVENT_RGN is shown in Figure 8-37 and described in Table 8-32.
Return to the Table 8-11.
Figure 8-37. EVENT_RGN Register
7
6
5
4
3
2
1
0
EVENT_RGN[7:0]
R/W-0b
Table 8-32. EVENT_RGN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
EVENT_RGN[7:0]
R/W
0b
Choice of region used in monitoring analog/digital inputs CH[7:0].
0b = Event flag is set if: (conversion result < low threshold) or
(conversion result > high threshold). For digital inputs, logic 1 sets
the alert flag.
1b = Event flag is set if: (low threshold > conversion result < high
threshold). For digital inputs, logic 0 sets the event flag.
8.5.21 HYSTERESIS_CH0 Register (Address = 0x20) [Reset = 0xF0]
HYSTERESIS_CH0 is shown in Figure 8-38 and described in Table 8-33.
Return to the Table 8-11.
Figure 8-38. HYSTERESIS_CH0 Register
7
6
5
4
3
2
1
HIGH_THRESHOLD_CH0_LSB[3:0]
HYSTERESIS_CH0[3:0]
R/W-1111b
R/W-0b
0
Table 8-33. HYSTERESIS_CH0 Register Field Descriptions
Bit
Field
Type
7-4
HIGH_THRESHOLD_CH0 R/W
_LSB[3:0]
Reset
Description
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
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Table 8-33. HYSTERESIS_CH0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
HYSTERESIS_CH0[3:0]
R/W
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
8.5.22 HIGH_TH_CH0 Register (Address = 0x21) [Reset = 0xFF]
HIGH_TH_CH0 is shown in Figure 8-39 and described in Table 8-34.
Return to the Table 8-11.
Figure 8-39. HIGH_TH_CH0 Register
7
6
5
4
3
2
1
0
HIGH_THRESHOLD_CH0_MSB[7:0]
R/W-11111111b
Table 8-34. HIGH_TH_CH0 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH0 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.23 EVENT_COUNT_CH0 Register (Address = 0x22) [Reset = 0x0]
EVENT_COUNT_CH0 is shown in Figure 8-40 and described in Table 8-35.
Return to the Table 8-11.
Figure 8-40. EVENT_COUNT_CH0 Register
7
6
5
4
3
2
1
LOW_THRESHOLD_CH0_LSB[3:0]
EVENT_COUNT_CH0[3:0]
R/W-0b
R/W-0b
0
Table 8-35. EVENT_COUNT_CH0 Register Field Descriptions
Bit
Field
Reset
Description
7-4
LOW_THRESHOLD_CH0 R/W
_LSB[3:0]
Type
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH0[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples above
threshold before setting alert flag.
8.5.24 LOW_TH_CH0 Register (Address = 0x23) [Reset = 0x0]
LOW_TH_CH0 is shown in Figure 8-41 and described in Table 8-36.
Return to the Table 8-11.
Figure 8-41. LOW_TH_CH0 Register
7
6
5
4
3
2
1
0
LOW_THRESHOLD_CH0_MSB[7:0]
R/W-0b
44
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Table 8-36. LOW_TH_CH0 Register Field Descriptions
Bit
Field
7-0
LOW_THRESHOLD_CH0 R/W
_MSB[7:0]
Type
Reset
Description
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.25 HYSTERESIS_CH1 Register (Address = 0x24) [Reset = 0xF0]
HYSTERESIS_CH1 is shown in Figure 8-42 and described in Table 8-37.
Return to the Table 8-11.
Figure 8-42. HYSTERESIS_CH1 Register
7
6
5
4
3
2
1
HIGH_THRESHOLD_CH1_LSB[3:0]
HYSTERESIS_CH1[3:0]
R/W-1111b
R/W-0b
0
Table 8-37. HYSTERESIS_CH1 Register Field Descriptions
Bit
Field
Reset
Description
7-4
HIGH_THRESHOLD_CH1 R/W
_LSB[3:0]
Type
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
HYSTERESIS_CH1[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.26 HIGH_TH_CH1 Register (Address = 0x25) [Reset = 0xFF]
HIGH_TH_CH1 is shown in Figure 8-43 and described in Table 8-38.
Return to the Table 8-11.
Figure 8-43. HIGH_TH_CH1 Register
7
6
5
4
3
2
1
0
HIGH_THRESHOLD_CH1_MSB[7:0]
R/W-11111111b
Table 8-38. HIGH_TH_CH1 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH1 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.27 EVENT_COUNT_CH1 Register (Address = 0x26) [Reset = 0x0]
EVENT_COUNT_CH1 is shown in Figure 8-44 and described in Table 8-39.
Return to the Table 8-11.
Figure 8-44. EVENT_COUNT_CH1 Register
7
6
5
4
3
2
1
LOW_THRESHOLD_CH1_LSB[3:0]
EVENT_COUNT_CH1[3:0]
R/W-0b
R/W-0b
0
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Table 8-39. EVENT_COUNT_CH1 Register Field Descriptions
Bit
Field
Reset
Description
7-4
LOW_THRESHOLD_CH1 R/W
_LSB[3:0]
Type
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH1[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples above
threshold before setting alert flag.
8.5.28 LOW_TH_CH1 Register (Address = 0x27) [Reset = 0x0]
LOW_TH_CH1 is shown in Figure 8-45 and described in Table 8-40.
Return to the Table 8-11.
Figure 8-45. LOW_TH_CH1 Register
7
6
5
4
3
2
1
0
LOW_THRESHOLD_CH1_MSB[7:0]
R/W-0b
Table 8-40. LOW_TH_CH1 Register Field Descriptions
Bit
Field
Type
7-0
LOW_THRESHOLD_CH1 R/W
_MSB[7:0]
Reset
Description
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.29 HYSTERESIS_CH2 Register (Address = 0x28) [Reset = 0xF0]
HYSTERESIS_CH2 is shown in Figure 8-46 and described in Table 8-41.
Return to the Table 8-11.
Figure 8-46. HYSTERESIS_CH2 Register
7
6
5
4
3
2
1
HIGH_THRESHOLD_CH2_LSB[3:0]
HYSTERESIS_CH2[3:0]
R/W-1111b
R/W-0b
0
Table 8-41. HYSTERESIS_CH2 Register Field Descriptions
Bit
Field
7-4
3-0
Type
Reset
Description
HIGH_THRESHOLD_CH2 R/W
_LSB[3:0]
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
HYSTERESIS_CH2[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.30 HIGH_TH_CH2 Register (Address = 0x29) [Reset = 0xFF]
HIGH_TH_CH2 is shown in Figure 8-47 and described in Table 8-42.
Return to the Table 8-11.
Figure 8-47. HIGH_TH_CH2 Register
7
6
5
4
3
2
1
0
HIGH_THRESHOLD_CH2_MSB[7:0]
R/W-11111111b
46
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Table 8-42. HIGH_TH_CH2 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH2 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.31 EVENT_COUNT_CH2 Register (Address = 0x2A) [Reset = 0x0]
EVENT_COUNT_CH2 is shown in Figure 8-48 and described in Table 8-43.
Return to the Table 8-11.
Figure 8-48. EVENT_COUNT_CH2 Register
7
6
5
4
3
2
1
LOW_THRESHOLD_CH2_LSB[3:0]
EVENT_COUNT_CH2[3:0]
R/W-0b
R/W-0b
0
Table 8-43. EVENT_COUNT_CH2 Register Field Descriptions
Bit
Field
Reset
Description
7-4
LOW_THRESHOLD_CH2 R/W
_LSB[3:0]
Type
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH2[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples above
threshold before setting alert flag.
8.5.32 LOW_TH_CH2 Register (Address = 0x2B) [Reset = 0x0]
LOW_TH_CH2 is shown in Figure 8-49 and described in Table 8-44.
Return to the Table 8-11.
Figure 8-49. LOW_TH_CH2 Register
7
6
5
4
3
2
1
0
LOW_THRESHOLD_CH2_MSB[7:0]
R/W-0b
Table 8-44. LOW_TH_CH2 Register Field Descriptions
Bit
Field
Type
7-0
LOW_THRESHOLD_CH2 R/W
_MSB[7:0]
Reset
Description
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.33 HYSTERESIS_CH3 Register (Address = 0x2C) [Reset = 0xF0]
HYSTERESIS_CH3 is shown in Figure 8-50 and described in Table 8-45.
Return to the Table 8-11.
Figure 8-50. HYSTERESIS_CH3 Register
7
6
5
4
3
2
1
HIGH_THRESHOLD_CH3_LSB[3:0]
HYSTERESIS_CH3[3:0]
R/W-1111b
R/W-0b
0
Table 8-45. HYSTERESIS_CH3 Register Field Descriptions
Bit
Field
7-4
HIGH_THRESHOLD_CH3 R/W
_LSB[3:0]
Type
Reset
Description
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
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Table 8-45. HYSTERESIS_CH3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
HYSTERESIS_CH3[3:0]
R/W
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
8.5.34 HIGH_TH_CH3 Register (Address = 0x2D) [Reset = 0xFF]
HIGH_TH_CH3 is shown in Figure 8-51 and described in Table 8-46.
Return to the Table 8-11.
Figure 8-51. HIGH_TH_CH3 Register
7
6
5
4
3
2
1
0
HIGH_THRESHOLD_CH3_MSB[7:0]
R/W-11111111b
Table 8-46. HIGH_TH_CH3 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH3 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.35 EVENT_COUNT_CH3 Register (Address = 0x2E) [Reset = 0x0]
EVENT_COUNT_CH3 is shown in Figure 8-52 and described in Table 8-47.
Return to the Table 8-11.
Figure 8-52. EVENT_COUNT_CH3 Register
7
6
5
4
3
2
1
LOW_THRESHOLD_CH3_LSB[3:0]
EVENT_COUNT_CH3[3:0]
R/W-0b
R/W-0b
0
Table 8-47. EVENT_COUNT_CH3 Register Field Descriptions
Bit
Field
Reset
Description
7-4
LOW_THRESHOLD_CH3 R/W
_LSB[3:0]
Type
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH3[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples above
threshold before setting alert flag.
8.5.36 LOW_TH_CH3 Register (Address = 0x2F) [Reset = 0x0]
LOW_TH_CH3 is shown in Figure 8-53 and described in Table 8-48.
Return to the Table 8-11.
Figure 8-53. LOW_TH_CH3 Register
7
6
5
4
3
2
1
0
LOW_THRESHOLD_CH3_MSB[7:0]
R/W-0b
48
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Table 8-48. LOW_TH_CH3 Register Field Descriptions
Bit
Field
7-0
LOW_THRESHOLD_CH3 R/W
_MSB[7:0]
Type
Reset
Description
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.37 HYSTERESIS_CH4 Register (Address = 0x30) [Reset = 0xF0]
HYSTERESIS_CH4 is shown in Figure 8-54 and described in Table 8-49.
Return to the Table 8-11.
Figure 8-54. HYSTERESIS_CH4 Register
7
6
5
4
3
2
1
HIGH_THRESHOLD_CH4_LSB[3:0]
HYSTERESIS_CH4[3:0]
R/W-1111b
R/W-0b
0
Table 8-49. HYSTERESIS_CH4 Register Field Descriptions
Bit
Field
Reset
Description
7-4
HIGH_THRESHOLD_CH4 R/W
_LSB[3:0]
Type
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
HYSTERESIS_CH4[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.38 HIGH_TH_CH4 Register (Address = 0x31) [Reset = 0xFF]
HIGH_TH_CH4 is shown in Figure 8-55 and described in Table 8-50.
Return to the Table 8-11.
Figure 8-55. HIGH_TH_CH4 Register
7
6
5
4
3
2
1
0
HIGH_THRESHOLD_CH4_MSB[7:0]
R/W-11111111b
Table 8-50. HIGH_TH_CH4 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH4 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.39 EVENT_COUNT_CH4 Register (Address = 0x32) [Reset = 0x0]
EVENT_COUNT_CH4 is shown in Figure 8-56 and described in Table 8-51.
Return to the Table 8-11.
Figure 8-56. EVENT_COUNT_CH4 Register
7
6
5
4
3
2
1
LOW_THRESHOLD_CH4_LSB[3:0]
EVENT_COUNT_CH4[3:0]
R/W-0b
R/W-0b
0
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Table 8-51. EVENT_COUNT_CH4 Register Field Descriptions
Bit
Field
Reset
Description
7-4
LOW_THRESHOLD_CH4 R/W
_LSB[3:0]
Type
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH4[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples above
threshold before setting alert flag.
8.5.40 LOW_TH_CH4 Register (Address = 0x33) [Reset = 0x0]
LOW_TH_CH4 is shown in Figure 8-57 and described in Table 8-52.
Return to the Table 8-11.
Figure 8-57. LOW_TH_CH4 Register
7
6
5
4
3
2
1
0
LOW_THRESHOLD_CH4_MSB[7:0]
R/W-0b
Table 8-52. LOW_TH_CH4 Register Field Descriptions
Bit
Field
Type
7-0
LOW_THRESHOLD_CH4 R/W
_MSB[7:0]
Reset
Description
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.41 HYSTERESIS_CH5 Register (Address = 0x34) [Reset = 0xF0]
HYSTERESIS_CH5 is shown in Figure 8-58 and described in Table 8-53.
Return to the Table 8-11.
Figure 8-58. HYSTERESIS_CH5 Register
7
6
5
4
3
2
1
HIGH_THRESHOLD_CH5_LSB[3:0]
HYSTERESIS_CH5[3:0]
R/W-1111b
R/W-0b
0
Table 8-53. HYSTERESIS_CH5 Register Field Descriptions
Bit
Field
7-4
3-0
Type
Reset
Description
HIGH_THRESHOLD_CH5 R/W
_LSB[3:0]
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
HYSTERESIS_CH5[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.42 HIGH_TH_CH5 Register (Address = 0x35) [Reset = 0xFF]
HIGH_TH_CH5 is shown in Figure 8-59 and described in Table 8-54.
Return to the Table 8-11.
Figure 8-59. HIGH_TH_CH5 Register
7
6
5
4
3
2
1
0
HIGH_THRESHOLD_CH5_MSB[7:0]
R/W-11111111b
50
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Table 8-54. HIGH_TH_CH5 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH5 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.43 EVENT_COUNT_CH5 Register (Address = 0x36) [Reset = 0x0]
EVENT_COUNT_CH5 is shown in Figure 8-60 and described in Table 8-55.
Return to the Table 8-11.
Figure 8-60. EVENT_COUNT_CH5 Register
7
6
5
4
3
2
1
LOW_THRESHOLD_CH5_LSB[3:0]
EVENT_COUNT_CH5[3:0]
R/W-0b
R/W-0b
0
Table 8-55. EVENT_COUNT_CH5 Register Field Descriptions
Bit
Field
Reset
Description
7-4
LOW_THRESHOLD_CH5 R/W
_LSB[3:0]
Type
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH5[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples above
threshold before setting alert flag.
8.5.44 LOW_TH_CH5 Register (Address = 0x37) [Reset = 0x0]
LOW_TH_CH5 is shown in Figure 8-61 and described in Table 8-56.
Return to the Table 8-11.
Figure 8-61. LOW_TH_CH5 Register
7
6
5
4
3
2
1
0
LOW_THRESHOLD_CH5_MSB[7:0]
R/W-0b
Table 8-56. LOW_TH_CH5 Register Field Descriptions
Bit
Field
Type
7-0
LOW_THRESHOLD_CH5 R/W
_MSB[7:0]
Reset
Description
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.45 HYSTERESIS_CH6 Register (Address = 0x38) [Reset = 0xF0]
HYSTERESIS_CH6 is shown in Figure 8-62 and described in Table 8-57.
Return to the Table 8-11.
Figure 8-62. HYSTERESIS_CH6 Register
7
6
5
4
3
2
1
HIGH_THRESHOLD_CH6_LSB[3:0]
HYSTERESIS_CH6[3:0]
R/W-1111b
R/W-0b
0
Table 8-57. HYSTERESIS_CH6 Register Field Descriptions
Bit
Field
7-4
HIGH_THRESHOLD_CH6 R/W
_LSB[3:0]
Type
Reset
Description
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
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Table 8-57. HYSTERESIS_CH6 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
HYSTERESIS_CH6[3:0]
R/W
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
8.5.46 HIGH_TH_CH6 Register (Address = 0x39) [Reset = 0xFF]
HIGH_TH_CH6 is shown in Figure 8-63 and described in Table 8-58.
Return to the Table 8-11.
Figure 8-63. HIGH_TH_CH6 Register
7
6
5
4
3
2
1
0
HIGH_THRESHOLD_CH6_MSB[7:0]
R/W-11111111b
Table 8-58. HIGH_TH_CH6 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH6 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.47 EVENT_COUNT_CH6 Register (Address = 0x3A) [Reset = 0x0]
EVENT_COUNT_CH6 is shown in Figure 8-64 and described in Table 8-59.
Return to the Table 8-11.
Figure 8-64. EVENT_COUNT_CH6 Register
7
6
5
4
3
2
1
LOW_THRESHOLD_CH6_LSB[3:0]
EVENT_COUNT_CH6[3:0]
R/W-0b
R/W-0b
0
Table 8-59. EVENT_COUNT_CH6 Register Field Descriptions
Bit
Field
Reset
Description
7-4
LOW_THRESHOLD_CH6 R/W
_LSB[3:0]
Type
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH6[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples above
threshold before setting alert flag.
8.5.48 LOW_TH_CH6 Register (Address = 0x3B) [Reset = 0x0]
LOW_TH_CH6 is shown in Figure 8-65 and described in Table 8-60.
Return to the Table 8-11.
Figure 8-65. LOW_TH_CH6 Register
7
6
5
4
3
2
1
0
LOW_THRESHOLD_CH6_MSB[7:0]
R/W-0b
52
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Table 8-60. LOW_TH_CH6 Register Field Descriptions
Bit
Field
7-0
LOW_THRESHOLD_CH6 R/W
_MSB[7:0]
Type
Reset
Description
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.49 HYSTERESIS_CH7 Register (Address = 0x3C) [Reset = 0xF0]
HYSTERESIS_CH7 is shown in Figure 8-66 and described in Table 8-61.
Return to the Table 8-11.
Figure 8-66. HYSTERESIS_CH7 Register
7
6
5
4
3
2
1
HIGH_THRESHOLD_CH7_LSB[3:0]
HYSTERESIS_CH7[3:0]
R/W-1111b
R/W-0b
0
Table 8-61. HYSTERESIS_CH7 Register Field Descriptions
Bit
Field
Reset
Description
7-4
HIGH_THRESHOLD_CH7 R/W
_LSB[3:0]
Type
1111b
Lower 4-bits of high threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
HYSTERESIS_CH7[3:0]
0b
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left
shifted 3 times and applied on the lower 7-bits of the threshold. Total
hysteresis = 7-bits [4-bits, 000b]
R/W
8.5.50 HIGH_TH_CH7 Register (Address = 0x3D) [Reset = 0xFF]
HIGH_TH_CH7 is shown in Figure 8-67 and described in Table 8-62.
Return to the Table 8-11.
Figure 8-67. HIGH_TH_CH7 Register
7
6
5
4
3
2
1
0
HIGH_THRESHOLD_CH7_MSB[7:0]
R/W-11111111b
Table 8-62. HIGH_TH_CH7 Register Field Descriptions
Bit
Field
7-0
HIGH_THRESHOLD_CH7 R/W
_MSB[7:0]
Type
Reset
Description
11111111b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.51 EVENT_COUNT_CH7 Register (Address = 0x3E) [Reset = 0x0]
EVENT_COUNT_CH7 is shown in Figure 8-68 and described in Table 8-63.
Return to the Table 8-11.
Figure 8-68. EVENT_COUNT_CH7 Register
7
6
5
4
3
2
1
LOW_THRESHOLD_CH7_LSB[3:0]
EVENT_COUNT_CH7[3:0]
R/W-0b
R/W-0b
0
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Table 8-63. EVENT_COUNT_CH7 Register Field Descriptions
Bit
Field
Reset
Description
7-4
LOW_THRESHOLD_CH7 R/W
_LSB[3:0]
Type
0b
Lower 4-bits of low threshold for analog input. These bits are
compared with bits 3:0 of ADC conversion result.
3-0
EVENT_COUNT_CH7[3:0 R/W
]
0b
Configuration for checking 'n+1' consecutive samples above
threshold before setting alert flag.
8.5.52 LOW_TH_CH7 Register (Address = 0x3F) [Reset = 0x0]
LOW_TH_CH7 is shown in Figure 8-69 and described in Table 8-64.
Return to the Table 8-11.
Figure 8-69. LOW_TH_CH7 Register
7
6
5
4
3
2
1
0
LOW_THRESHOLD_CH7_MSB[7:0]
R/W-0b
Table 8-64. LOW_TH_CH7 Register Field Descriptions
Bit
Field
Type
7-0
LOW_THRESHOLD_CH7 R/W
_MSB[7:0]
Reset
Description
0b
MSB aligned high threshold for analog input. These bits are
compared with top 8 bits of ADC conversion result.
8.5.53 MAX_CH0_LSB Register (Address = 0x60) [Reset = 0x0]
MAX_CH0_LSB is shown in Figure 8-70 and described in Table 8-65.
Return to the Table 8-11.
Figure 8-70. MAX_CH0_LSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH0_LSB[7:0]
R-0b
Table 8-65. MAX_CH0_LSB Register Field Descriptions
Bit
Field
Type
7-0
MAX_VALUE_CH0_LSB[7 R
:0]
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.54 MAX_CH0_MSB Register (Address = 0x61) [Reset = 0x0]
MAX_CH0_MSB is shown in Figure 8-71 and described in Table 8-66.
Return to the Table 8-11.
Figure 8-71. MAX_CH0_MSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH0_MSB[7:0]
R-0b
54
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Table 8-66. MAX_CH0_MSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH0_MSB[ R
7:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.55 MAX_CH1_LSB Register (Address = 0x62) [Reset = 0x0]
MAX_CH1_LSB is shown in Figure 8-72 and described in Table 8-67.
Return to the Table 8-11.
Figure 8-72. MAX_CH1_LSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH1_LSB[7:0]
R-0b
Table 8-67. MAX_CH1_LSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH1_LSB[7 R
:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.56 MAX_CH1_MSB Register (Address = 0x63) [Reset = 0x0]
MAX_CH1_MSB is shown in Figure 8-73 and described in Table 8-68.
Return to the Table 8-11.
Figure 8-73. MAX_CH1_MSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH1_MSB[7:0]
R-0b
Table 8-68. MAX_CH1_MSB Register Field Descriptions
Bit
Field
Type
7-0
MAX_VALUE_CH1_MSB[ R
7:0]
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.57 MAX_CH2_LSB Register (Address = 0x64) [Reset = 0x0]
MAX_CH2_LSB is shown in Figure 8-74 and described in Table 8-69.
Return to the Table 8-11.
Figure 8-74. MAX_CH2_LSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH2_LSB[7:0]
R-0b
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Table 8-69. MAX_CH2_LSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH2_LSB[7 R
:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.58 MAX_CH2_MSB Register (Address = 0x65) [Reset = 0x0]
MAX_CH2_MSB is shown in Figure 8-75 and described in Table 8-70.
Return to the Table 8-11.
Figure 8-75. MAX_CH2_MSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH2_MSB[7:0]
R-0b
Table 8-70. MAX_CH2_MSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH2_MSB[ R
7:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.59 MAX_CH3_LSB Register (Address = 0x66) [Reset = 0x0]
MAX_CH3_LSB is shown in Figure 8-76 and described in Table 8-71.
Return to the Table 8-11.
Figure 8-76. MAX_CH3_LSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH3_LSB[7:0]
R-0b
Table 8-71. MAX_CH3_LSB Register Field Descriptions
Bit
Field
Type
7-0
MAX_VALUE_CH3_LSB[7 R
:0]
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.60 MAX_CH3_MSB Register (Address = 0x67) [Reset = 0x0]
MAX_CH3_MSB is shown in Figure 8-77 and described in Table 8-72.
Return to the Table 8-11.
Figure 8-77. MAX_CH3_MSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH3_MSB[7:0]
R-0b
56
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Table 8-72. MAX_CH3_MSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH3_MSB[ R
7:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.61 MAX_CH4_LSB Register (Address = 0x68) [Reset = 0x0]
MAX_CH4_LSB is shown in Figure 8-78 and described in Table 8-73.
Return to the Table 8-11.
Figure 8-78. MAX_CH4_LSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH4_LSB[7:0]
R-0b
Table 8-73. MAX_CH4_LSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH4_LSB[7 R
:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.62 MAX_CH4_MSB Register (Address = 0x69) [Reset = 0x0]
MAX_CH4_MSB is shown in Figure 8-79 and described in Table 8-74.
Return to the Table 8-11.
Figure 8-79. MAX_CH4_MSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH4_MSB[7:0]
R-0b
Table 8-74. MAX_CH4_MSB Register Field Descriptions
Bit
Field
Type
7-0
MAX_VALUE_CH4_MSB[ R
7:0]
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.63 MAX_CH5_LSB Register (Address = 0x6A) [Reset = 0x0]
MAX_CH5_LSB is shown in Figure 8-80 and described in Table 8-75.
Return to the Table 8-11.
Figure 8-80. MAX_CH5_LSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH5_LSB[7:0]
R-0b
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Table 8-75. MAX_CH5_LSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH5_LSB[7 R
:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.64 MAX_CH5_MSB Register (Address = 0x6B) [Reset = 0x0]
MAX_CH5_MSB is shown in Figure 8-81 and described in Table 8-76.
Return to the Table 8-11.
Figure 8-81. MAX_CH5_MSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH5_MSB[7:0]
R-0b
Table 8-76. MAX_CH5_MSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH5_MSB[ R
7:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.65 MAX_CH6_LSB Register (Address = 0x6C) [Reset = 0x0]
MAX_CH6_LSB is shown in Figure 8-82 and described in Table 8-77.
Return to the Table 8-11.
Figure 8-82. MAX_CH6_LSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH6_LSB[7:0]
R-0b
Table 8-77. MAX_CH6_LSB Register Field Descriptions
Bit
Field
Type
7-0
MAX_VALUE_CH6_LSB[7 R
:0]
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.66 MAX_CH6_MSB Register (Address = 0x6D) [Reset = 0x0]
MAX_CH6_MSB is shown in Figure 8-83 and described in Table 8-78.
Return to the Table 8-11.
Figure 8-83. MAX_CH6_MSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH6_MSB[7:0]
R-0b
58
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Table 8-78. MAX_CH6_MSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH6_MSB[ R
7:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.67 MAX_CH7_LSB Register (Address = 0x6E) [Reset = 0x0]
MAX_CH7_LSB is shown in Figure 8-84 and described in Table 8-79.
Return to the Table 8-11.
Figure 8-84. MAX_CH7_LSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH7_LSB[7:0]
R-0b
Table 8-79. MAX_CH7_LSB Register Field Descriptions
Bit
Field
7-0
MAX_VALUE_CH7_LSB[7 R
:0]
Type
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.68 MAX_CH7_MSB Register (Address = 0x6F) [Reset = 0x0]
MAX_CH7_MSB is shown in Figure 8-85 and described in Table 8-80.
Return to the Table 8-11.
Figure 8-85. MAX_CH7_MSB Register
7
6
5
4
3
2
1
0
MAX_VALUE_CH7_MSB[7:0]
R-0b
Table 8-80. MAX_CH7_MSB Register Field Descriptions
Bit
Field
Type
7-0
MAX_VALUE_CH7_MSB[ R
7:0]
Reset
Description
0b
Maximum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0.
8.5.69 MIN_CH0_LSB Register (Address = 0x80) [Reset = 0xFF]
MIN_CH0_LSB is shown in Figure 8-86 and described in Table 8-81.
Return to the Table 8-11.
Figure 8-86. MIN_CH0_LSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH0_LSB[7:0]
R-11111111b
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Table 8-81. MIN_CH0_LSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH0_LSB[7: R
0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.70 MIN_CH0_MSB Register (Address = 0x81) [Reset = 0xFF]
MIN_CH0_MSB is shown in Figure 8-87 and described in Table 8-82.
Return to the Table 8-11.
Figure 8-87. MIN_CH0_MSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH0_MSB[7:0]
R-11111111b
Table 8-82. MIN_CH0_MSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH0_MSB[7 R
:0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.71 MIN_CH1_LSB Register (Address = 0x82) [Reset = 0xFF]
MIN_CH1_LSB is shown in Figure 8-88 and described in Table 8-83.
Return to the Table 8-11.
Figure 8-88. MIN_CH1_LSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH1_LSB[7:0]
R-11111111b
Table 8-83. MIN_CH1_LSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH1_LSB[7: R
0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.72 MIN_CH1_MSB Register (Address = 0x83) [Reset = 0xFF]
MIN_CH1_MSB is shown in Figure 8-89 and described in Table 8-84.
Return to the Table 8-11.
Figure 8-89. MIN_CH1_MSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH1_MSB[7:0]
R-11111111b
60
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Table 8-84. MIN_CH1_MSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH1_MSB[7 R
:0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.73 MIN_CH2_LSB Register (Address = 0x84) [Reset = 0xFF]
MIN_CH2_LSB is shown in Figure 8-90 and described in Table 8-85.
Return to the Table 8-11.
Figure 8-90. MIN_CH2_LSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH2_LSB[7:0]
R-11111111b
Table 8-85. MIN_CH2_LSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH2_LSB[7: R
0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.74 MIN_CH2_MSB Register (Address = 0x85) [Reset = 0xFF]
MIN_CH2_MSB is shown in Figure 8-91 and described in Table 8-86.
Return to the Table 8-11.
Figure 8-91. MIN_CH2_MSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH2_MSB[7:0]
R-11111111b
Table 8-86. MIN_CH2_MSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH2_MSB[7 R
:0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.75 MIN_CH3_LSB Register (Address = 0x86) [Reset = 0xFF]
MIN_CH3_LSB is shown in Figure 8-92 and described in Table 8-87.
Return to the Table 8-11.
Figure 8-92. MIN_CH3_LSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH3_LSB[7:0]
R-11111111b
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Table 8-87. MIN_CH3_LSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH3_LSB[7: R
0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.76 MIN_CH3_MSB Register (Address = 0x87) [Reset = 0xFF]
MIN_CH3_MSB is shown in Figure 8-93 and described in Table 8-88.
Return to the Table 8-11.
Figure 8-93. MIN_CH3_MSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH3_MSB[7:0]
R-11111111b
Table 8-88. MIN_CH3_MSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH3_MSB[7 R
:0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.77 MIN_CH4_LSB Register (Address = 0x88) [Reset = 0xFF]
MIN_CH4_LSB is shown in Figure 8-94 and described in Table 8-89.
Return to the Table 8-11.
Figure 8-94. MIN_CH4_LSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH4_LSB[7:0]
R-11111111b
Table 8-89. MIN_CH4_LSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH4_LSB[7: R
0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.78 MIN_CH4_MSB Register (Address = 0x89) [Reset = 0xFF]
MIN_CH4_MSB is shown in Figure 8-95 and described in Table 8-90.
Return to the Table 8-11.
Figure 8-95. MIN_CH4_MSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH4_MSB[7:0]
R-11111111b
62
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Table 8-90. MIN_CH4_MSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH4_MSB[7 R
:0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.79 MIN_CH5_LSB Register (Address = 0x8A) [Reset = 0xFF]
MIN_CH5_LSB is shown in Figure 8-96 and described in Table 8-91.
Return to the Table 8-11.
Figure 8-96. MIN_CH5_LSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH5_LSB[7:0]
R-11111111b
Table 8-91. MIN_CH5_LSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH5_LSB[7: R
0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.80 MIN_CH5_MSB Register (Address = 0x8B) [Reset = 0xFF]
MIN_CH5_MSB is shown in Figure 8-97 and described in Table 8-92.
Return to the Table 8-11.
Figure 8-97. MIN_CH5_MSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH5_MSB[7:0]
R-11111111b
Table 8-92. MIN_CH5_MSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH5_MSB[7 R
:0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.81 MIN_CH6_LSB Register (Address = 0x8C) [Reset = 0xFF]
MIN_CH6_LSB is shown in Figure 8-98 and described in Table 8-93.
Return to the Table 8-11.
Figure 8-98. MIN_CH6_LSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH6_LSB[7:0]
R-11111111b
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Table 8-93. MIN_CH6_LSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH6_LSB[7: R
0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.82 MIN_CH6_MSB Register (Address = 0x8D) [Reset = 0xFF]
MIN_CH6_MSB is shown in Figure 8-99 and described in Table 8-94.
Return to the Table 8-11.
Figure 8-99. MIN_CH6_MSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH6_MSB[7:0]
R-11111111b
Table 8-94. MIN_CH6_MSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH6_MSB[7 R
:0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.83 MIN_CH7_LSB Register (Address = 0x8E) [Reset = 0xFF]
MIN_CH7_LSB is shown in Figure 8-100 and described in Table 8-95.
Return to the Table 8-11.
Figure 8-100. MIN_CH7_LSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH7_LSB[7:0]
R-11111111b
Table 8-95. MIN_CH7_LSB Register Field Descriptions
Bit
Field
Type
7-0
MIN_VALUE_CH7_LSB[7: R
0]
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.84 MIN_CH7_MSB Register (Address = 0x8F) [Reset = 0xFF]
MIN_CH7_MSB is shown in Figure 8-101 and described in Table 8-96.
Return to the Table 8-11.
Figure 8-101. MIN_CH7_MSB Register
7
6
5
4
3
2
1
0
MIN_VALUE_CH7_MSB[7:0]
R-11111111b
64
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Table 8-96. MIN_CH7_MSB Register Field Descriptions
Bit
Field
7-0
MIN_VALUE_CH7_MSB[7 R
:0]
Type
Reset
Description
11111111b
Minimum code recorded on the analog input channel from the last
time this register was read. Reading the register will reset the value
to 0xFF.
8.5.85 RECENT_CH0_LSB Register (Address = 0xA0) [Reset = 0x0]
RECENT_CH0_LSB is shown in Figure 8-102 and described in Table 8-97.
Return to the Table 8-11.
Figure 8-102. RECENT_CH0_LSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH0_LSB[7:0]
R-0b
Table 8-97. RECENT_CH0_LSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH0_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.86 RECENT_CH0_MSB Register (Address = 0xA1) [Reset = 0x0]
RECENT_CH0_MSB is shown in Figure 8-103 and described in Table 8-98.
Return to the Table 8-11.
Figure 8-103. RECENT_CH0_MSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH0_MSB[7:0]
R-0b
Table 8-98. RECENT_CH0_MSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH0_MSB[ R
7:0]
Type
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.87 RECENT_CH1_LSB Register (Address = 0xA2) [Reset = 0x0]
RECENT_CH1_LSB is shown in Figure 8-104 and described in Table 8-99.
Return to the Table 8-11.
Figure 8-104. RECENT_CH1_LSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH1_LSB[7:0]
R-0b
Table 8-99. RECENT_CH1_LSB Register Field Descriptions
Bit
Field
Type
7-0
LAST_VALUE_CH1_LSB[ R
7:0]
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
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8.5.88 RECENT_CH1_MSB Register (Address = 0xA3) [Reset = 0x0]
RECENT_CH1_MSB is shown in Figure 8-105 and described in Table 8-100.
Return to the Table 8-11.
Figure 8-105. RECENT_CH1_MSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH1_MSB[7:0]
R-0b
Table 8-100. RECENT_CH1_MSB Register Field Descriptions
Bit
Field
Type
7-0
LAST_VALUE_CH1_MSB[ R
7:0]
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.89 RECENT_CH2_LSB Register (Address = 0xA4) [Reset = 0x0]
RECENT_CH2_LSB is shown in Figure 8-106 and described in Table 8-101.
Return to the Table 8-11.
Figure 8-106. RECENT_CH2_LSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH2_LSB[7:0]
R-0b
Table 8-101. RECENT_CH2_LSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH2_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.90 RECENT_CH2_MSB Register (Address = 0xA5) [Reset = 0x0]
RECENT_CH2_MSB is shown in Figure 8-107 and described in Table 8-102.
Return to the Table 8-11.
Figure 8-107. RECENT_CH2_MSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH2_MSB[7:0]
R-0b
Table 8-102. RECENT_CH2_MSB Register Field Descriptions
Bit
Field
Type
7-0
LAST_VALUE_CH2_MSB[ R
7:0]
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.91 RECENT_CH3_LSB Register (Address = 0xA6) [Reset = 0x0]
RECENT_CH3_LSB is shown in Figure 8-108 and described in Table 8-103.
Return to the Table 8-11.
Figure 8-108. RECENT_CH3_LSB Register
7
66
6
5
4
3
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Figure 8-108. RECENT_CH3_LSB Register (continued)
LAST_VALUE_CH3_LSB[7:0]
R-0b
Table 8-103. RECENT_CH3_LSB Register Field Descriptions
Bit
Field
Type
7-0
LAST_VALUE_CH3_LSB[ R
7:0]
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.92 RECENT_CH3_MSB Register (Address = 0xA7) [Reset = 0x0]
RECENT_CH3_MSB is shown in Figure 8-109 and described in Table 8-104.
Return to the Table 8-11.
Figure 8-109. RECENT_CH3_MSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH3_MSB[7:0]
R-0b
Table 8-104. RECENT_CH3_MSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH3_MSB[ R
7:0]
Type
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.93 RECENT_CH4_LSB Register (Address = 0xA8) [Reset = 0x0]
RECENT_CH4_LSB is shown in Figure 8-110 and described in Table 8-105.
Return to the Table 8-11.
Figure 8-110. RECENT_CH4_LSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH4_LSB[7:0]
R-0b
Table 8-105. RECENT_CH4_LSB Register Field Descriptions
Bit
Field
Type
7-0
LAST_VALUE_CH4_LSB[ R
7:0]
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.94 RECENT_CH4_MSB Register (Address = 0xA9) [Reset = 0x0]
RECENT_CH4_MSB is shown in Figure 8-111 and described in Table 8-106.
Return to the Table 8-11.
Figure 8-111. RECENT_CH4_MSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH4_MSB[7:0]
R-0b
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Table 8-106. RECENT_CH4_MSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH4_MSB[ R
7:0]
Type
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.95 RECENT_CH5_LSB Register (Address = 0xAA) [Reset = 0x0]
RECENT_CH5_LSB is shown in Figure 8-112 and described in Table 8-107.
Return to the Table 8-11.
Figure 8-112. RECENT_CH5_LSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH5_LSB[7:0]
R-0b
Table 8-107. RECENT_CH5_LSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH5_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.96 RECENT_CH5_MSB Register (Address = 0xAB) [Reset = 0x0]
RECENT_CH5_MSB is shown in Figure 8-113 and described in Table 8-108.
Return to the Table 8-11.
Figure 8-113. RECENT_CH5_MSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH5_MSB[7:0]
R-0b
Table 8-108. RECENT_CH5_MSB Register Field Descriptions
Bit
Field
Type
7-0
LAST_VALUE_CH5_MSB[ R
7:0]
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.97 RECENT_CH6_LSB Register (Address = 0xAC) [Reset = 0x0]
RECENT_CH6_LSB is shown in Figure 8-114 and described in Table 8-109.
Return to the Table 8-11.
Figure 8-114. RECENT_CH6_LSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH6_LSB[7:0]
R-0b
Table 8-109. RECENT_CH6_LSB Register Field Descriptions
68
Bit
Field
7-0
LAST_VALUE_CH6_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
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8.5.98 RECENT_CH6_MSB Register (Address = 0xAD) [Reset = 0x0]
RECENT_CH6_MSB is shown in Figure 8-115 and described in Table 8-110.
Return to the Table 8-11.
Figure 8-115. RECENT_CH6_MSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH6_MSB[7:0]
R-0b
Table 8-110. RECENT_CH6_MSB Register Field Descriptions
Bit
Field
Type
7-0
LAST_VALUE_CH6_MSB[ R
7:0]
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.99 RECENT_CH7_LSB Register (Address = 0xAE) [Reset = 0x0]
RECENT_CH7_LSB is shown in Figure 8-116 and described in Table 8-111.
Return to the Table 8-11.
Figure 8-116. RECENT_CH7_LSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH7_LSB[7:0]
R-0b
Table 8-111. RECENT_CH7_LSB Register Field Descriptions
Bit
Field
7-0
LAST_VALUE_CH7_LSB[ R
7:0]
Type
Reset
Description
0b
Next 8 bits of the last result for this analog input channel.
8.5.100 RECENT_CH7_MSB Register (Address = 0xAF) [Reset = 0x0]
RECENT_CH7_MSB is shown in Figure 8-117 and described in Table 8-112.
Return to the Table 8-11.
Figure 8-117. RECENT_CH7_MSB Register
7
6
5
4
3
2
1
0
LAST_VALUE_CH7_MSB[7:0]
R-0b
Table 8-112. RECENT_CH7_MSB Register Field Descriptions
Bit
Field
Type
7-0
LAST_VALUE_CH7_MSB[ R
7:0]
Reset
Description
0b
MSB aligned first 8 bits of the last result for this analog input
channel.
8.5.101 GPO0_EVENT_CFG Register (Address = 0xC3) [Reset = 0x0]
GPO0_EVENT_CFG is shown in Figure 8-118 and described in Table 8-113.
Return to the Table 8-11.
Figure 8-118. GPO0_EVENT_CFG Register
7
6
5
4
3
2
1
0
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Figure 8-118. GPO0_EVENT_CFG Register (continued)
GPO0_EVENT_CFG[7:0]
R/W-0b
Table 8-113. GPO0_EVENT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO0_EVENT_CFG[7:0]
R/W
0b
Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger
an event based update on GPO0.
0b = Event flags for the AIN/GPIO corresponding to this bit do not
trigger GPO0 output.
1b = Event flags for the AIN/GPIO corresponding to this bit trigger
GPO0 output.
8.5.102 GPO1_EVENT_CFG Register (Address = 0xC5) [Reset = 0x0]
GPO1_EVENT_CFG is shown in Figure 8-119 and described in Table 8-114.
Return to the Table 8-11.
Figure 8-119. GPO1_EVENT_CFG Register
7
6
5
4
3
2
1
0
GPO1_EVENT_CFG[7:0]
R/W-0b
Table 8-114. GPO1_EVENT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO1_EVENT_CFG[7:0]
R/W
0b
Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger
an event based update on GPO1.
0b = Event flags for the AIN/GPIO corresponding to this bit do not
trigger GPO1 output.
1b = Event flags for the AIN/GPIO corresponding to this bit trigger
GPO1 output.
8.5.103 GPO2_EVENT_CFG Register (Address = 0xC7) [Reset = 0x0]
GPO2_EVENT_CFG is shown in Figure 8-120 and described in Table 8-115.
Return to the Table 8-11.
Figure 8-120. GPO2_EVENT_CFG Register
7
6
5
4
3
2
1
0
GPO2_EVENT_CFG[7:0]
R/W-0b
Table 8-115. GPO2_EVENT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO2_EVENT_CFG[7:0]
R/W
0b
Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger
an event based update on GPO2.
0b = Event flags for the AIN/GPIO corresponding to this bit do not
trigger GPO2 output.
1b = Event flags for the AIN/GPIO corresponding to this bit trigger
GPO2 output.
8.5.104 GPO3_EVENT_CFG Register (Address = 0xC9) [Reset = 0x0]
GPO3_EVENT_CFG is shown in Figure 8-121 and described in Table 8-116.
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Return to the Table 8-11.
Figure 8-121. GPO3_EVENT_CFG Register
7
6
5
4
3
2
1
0
GPO3_EVENT_CFG[7:0]
R/W-0b
Table 8-116. GPO3_EVENT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO3_EVENT_CFG[7:0]
R/W
0b
Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger
an event based update on GPO3.
0b = Event flags for the AIN/GPIO corresponding to this bit do not
trigger GPO3 output.
1b = Event flags for the AIN/GPIO corresponding to this bit trigger
GPO3 output.
8.5.105 GPO4_EVENT_CFG Register (Address = 0xCB) [Reset = 0x0]
GPO4_EVENT_CFG is shown in Figure 8-122 and described in Table 8-117.
Return to the Table 8-11.
Figure 8-122. GPO4_EVENT_CFG Register
7
6
5
4
3
2
1
0
GPO4_EVENT_CFG[7:0]
R/W-0b
Table 8-117. GPO4_EVENT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO4_EVENT_CFG[7:0]
R/W
0b
Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger
an event based update on GPO4.
0b = Event flags for the AIN/GPIO corresponding to this bit do not
trigger GPO4 output.
1b = Event flags for the AIN/GPIO corresponding to this bit trigger
GPO4 output.
8.5.106 GPO5_EVENT_CFG Register (Address = 0xCD) [Reset = 0x0]
GPO5_EVENT_CFG is shown in Figure 8-123 and described in Table 8-118.
Return to the Table 8-11.
Figure 8-123. GPO5_EVENT_CFG Register
7
6
5
4
3
2
1
0
GPO5_EVENT_CFG[7:0]
R/W-0b
Table 8-118. GPO5_EVENT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO5_EVENT_CFG[7:0]
R/W
0b
Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger
an event based update on GPO5.
0b = Event flags for the AIN/GPIO corresponding to this bit do not
trigger GPO5 output.
1b = Event flags for the AIN/GPIO corresponding to this bit trigger
GPO5 output.
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8.5.107 GPO6_EVENT_CFG Register (Address = 0xCF) [Reset = 0x0]
GPO6_EVENT_CFG is shown in Figure 8-124 and described in Table 8-119.
Return to the Table 8-11.
Figure 8-124. GPO6_EVENT_CFG Register
7
6
5
4
3
2
1
0
GPO6_EVENT_CFG[7:0]
R/W-0b
Table 8-119. GPO6_EVENT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO6_EVENT_CFG[7:0]
R/W
0b
Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger
an event based update on GPO6.
0b = Event flags for the AIN/GPIO corresponding to this bit do not
trigger GPO6 output.
1b = Event flags for the AIN/GPIO corresponding to this bit trigger
GPO6 output.
8.5.108 GPO7_EVENT_CFG Register (Address = 0xD1) [Reset = 0x0]
GPO7_EVENT_CFG is shown in Figure 8-125 and described in Table 8-120.
Return to the Table 8-11.
Figure 8-125. GPO7_EVENT_CFG Register
7
6
5
4
3
2
1
0
GPO7_EVENT_CFG[7:0]
R/W-0b
Table 8-120. GPO7_EVENT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO7_EVENT_CFG[7:0]
R/W
0b
Select the inputs AIN/GPIO[7:0], analog or digital, which can trigger
an event based update on GPO7.
0b = Event flags for the AIN/GPIO corresponding to this bit do not
trigger GPO7 output.
1b = Event flags for the AIN/GPIO corresponding to this bit trigger
GPO7 output.
8.5.109 GPO_UPDATE_ON_EVENT Register (Address = 0xE9) [Reset = 0x0]
GPO_UPDATE_ON_EVENT is shown in Figure 8-126 and described in Table 8-121.
Return to the Table 8-11.
Figure 8-126. GPO_UPDATE_ON_EVENT Register
7
6
5
4
3
2
1
0
GPO_UPDATE_ON_EVENT[7:0]
R/W-0b
72
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Table 8-121. GPO_UPDATE_ON_EVENT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO_UPDATE_ON_EVE
NT[7:0]
R/W
0b
Update digital outputs GPO[7:0] when the corresponding trigger is
set.
0b = Digital output is not updated in response to the alert flags.
1b = Digital output is updated when the corresponding alert flags are
set. Configure GPOx_TRIG_EVENT_SEL register to select which
alert flags can trigger an update on the desired GPO.
8.5.110 GPO_VALUE_ON_EVENT Register (Address = 0xEB) [Reset = 0x0]
GPO_VALUE_ON_EVENT is shown in Figure 8-127 and described in Table 8-122.
Return to the Table 8-11.
Figure 8-127. GPO_VALUE_ON_EVENT Register
7
6
5
4
3
2
1
0
GPO_VALUE_ON_EVENT[7:0]
R/W-0b
Table 8-122. GPO_VALUE_ON_EVENT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPO_VALUE_ON_EVEN
T[7:0]
R/W
0b
Value to be set on digital outputs GPO[7:0] when the corresponding
trigger occurs. GPO update on alert flags must be enabled in the
corresponding bit in the GPO_TRIGGER_CFG register.
0b = Digital output is set to logic 0.
1b = Digital output is set to logic 1.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register analog-to-digital converter (SAR ADC) are the input driver and the reference driver circuits. This section
details some general principles for designing the input driver circuit, reference driver circuit, and provides some
application circuits designed for the ADS7038-Q1.
9.2 Typical Applications
9.2.1 Mixed-Channel Configuration
Digital Output (open-drain)
Digital Output (push-pull)
Analog Input
Analog Input
Analog Input
Analog Input
AVDD (VREF)
SPI
Device
Controller
Digital Input
Digital Input
Figure 9-1. DAQ Circuit: Single-Supply DAQ
9.2.1.1 Design Requirements
The goal of this application is to configure some channels of the ADS7038-Q1 as digital inputs, open-drain digital
outputs, and push-pull digital outputs.
9.2.1.2 Detailed Design Procedure
The ADS7038-Q1 can support GPIO functionality at each input pin. Any analog input pin can be independently
configured as a digital input, a digital open-drain output, or a digital push-pull output though the PIN_CFG and
GPIO_CFG registers; see Table 8-4.
9.2.1.2.1 Digital Input
The digital input functionality can be used to monitor a signal within the system. Figure 9-2 illustrates that the
state of the digital input can be read from the GPI_VALUE register.
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ADC
From input device
AVDD
GPIx
SW
GPIx
Figure 9-2. Digital Input
9.2.1.2.2 Digital Open-Drain Output
The channels of the ADS7038-Q1 can be configured as digital open-drain outputs supporting an output voltage
up to 5.5 V. An open-drain output, as shown in Figure 9-3, consists of an internal FET (Q) connected to ground.
The output is idle when not driven by the device, which means Q is off and the pullup resistor, R PULL_UP,
connects the GPOx node to the desired output voltage. The output voltage can range anywhere up to 5.5 V,
depending on the external voltage that the GPIOx is pulled up to. When the device is driving the output, Q turns
on, thus connecting the pullup resistor to ground and bringing the node voltage at GPOx low.
VPULL_UP
Receiving Device
ADC
RPULL_UP
GPOx
ILOAD
Q
Figure 9-3. Digital Open-Drain Output
The minimum value of the pullup resistor, as calculated in Equation 3, is given by the ratio of V PULL_UP and the
maximum current supported by the device digital output (5 mA).
RMIN = (VPULL_UP / 5 mA)
(3)
The maximum value of the pullup resistor, as calculated in Equation 4, depends on the minimum input current
requirement, ILOAD, of the receiving device driven by this GPIO.
RMAX = (VPULL_UP / ILOAD)
(4)
Select RPULL_UP such that RMIN < RPULL_UP < RMAX.
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9.2.1.3 Application Curve
45000
39581
30000
Frequency
25955
15000
0
2048
2049
Output Code
C001
Standard deviation = 0.49 LSB
Figure 9-4. DC Input Histogram
9.2.2 Digital Push-Pull Output Configuration
The channels of the ADS7038-Q1 can be configured as digital push-pull outputs supporting an output voltage up
to AVDD. As shown in Figure 9-5, a push-pull output consists of two mirrored opposite bipolar transistors, Q1
and Q2. The device can both source and sink current because only one transistor is on at a time (either Q2 is on
and pulls the output low, or Q1 is on and sets the output high). A push-pull configuration always drives the line
opposed to an open-drain output where the line is left floating.
ADC
AVDD
Q1
GPOx
Digital
output
Q2
Figure 9-5. Digital Push-Pull Output
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10 Power Supply Recommendations
10.1 AVDD and DVDD Supply Recommendations
The ADS7038-Q1 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. For supplies greater than 2.35 V, AVDD and DVDD can be shorted externally if
single-supply operation is desired. The AVDD supply also defines the full-scale input range of the device.
Decouple the AVDD and DVDD pins individually, as shown in Figure 10-1, with 1-µF ceramic decoupling
capacitors. The minimum capacitor value required for AVDD and DVDD is 200 nF and 20 nF, respectively. If both
supplies are powered from the same source, a minimum capacitor value of 220 nF is required for decoupling.
Connect 1-µF ceramic decoupling capacitors between the DECAP and GND pins.
AVDD
AVDD
1 PF
DECAP
1 PF
GND
GND
1 PF
DVDD
DVDD
Figure 10-1. Power-Supply Decoupling
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11 Layout
11.1 Layout Guidelines
Figure 11-1 shows a board layout example for the ADS7038-Q1. Avoid crossing digital lines with the analog
signal path and keep the analog input signals and the AVDD supply away from noise sources.
Use 1-µF ceramic bypass capacitors in close proximity to the analog (AVDD) and digital (DVDD) power-supply
pins. Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors. Connect the GND pin to
the ground plane using short, low-impedance paths. The AVDD supply voltage also functions as the reference
voltage for the ADS7038-Q1. Place the decoupling capacitor for AVDD close to the device AVDD and GND pins
and connect the decoupling capacitor to the device pins with thick copper tracks.
GND
DVDD
CS
SDO
11.2 Layout Example
SCLK
DECAP
SDI
AVDD
AIN/GPIO
Figure 11-1. Example Layout
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS7038QRTERQ1
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7038Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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