®
ADS
ADS7824
782
4
ADS
782
4
www.burr-brown.com/databook/ADS7824.html
4 Channel, 12-Bit Sampling CMOS A/D Converter
FEATURES
DESCRIPTION
● 25µs max SAMPLING AND CONVERSION
● SINGLE +5V SUPPLY OPERATION
The ADS7824 can acquire and convert 12 bits to
within ±0.5 LSB in 25µs max while consuming only
50mW max. Laser-trimmed scaling resistors provide
the standard industrial ±10V input range and channelto-channel matching of ±0.1%. The ADS7824 is a
low-power 12-bit sampling A/D with a four channel
input multiplexer, S/H, clock, reference, and a
parallel/serial microprocessor interface. It can be configured in a continuous conversion mode to sequentially digitize all four channels. The 28-pin ADS7824
is available in a plastic 0.3" DIP and in a SOIC, both
fully specified for operation over the industrial –40°C
to +85°C range.
● PIN-COMPATIBLE WITH 16-BIT ADS7825
● PARALLEL AND SERIAL DATA OUTPUT
● 28-PIN 0.3" PLASTIC DIP AND SOIC
● ±0.5 LSB max INL AND DNL
● 50mW max POWER DISSIPATION
● 50µW POWER DOWN MODE
● ±10V INPUT RANGE, FOUR CHANNEL
MULTIPLEXER
● CONTINUOUS CONVERSION MODE
Channel
Continuous Conversion
CONTC
A0
A1
40kΩ
AIN0
R/C
CS
Successive Approximation Register
Clock
and Control Logic
20kΩ
PWRD
8kΩ
40kΩ
CDAC
AIN1
BUSY
20kΩ
8kΩ
Serial
40kΩ
AIN2
Comparator
DATACLK
Data
Out
20kΩ
Parallel
40kΩ
Data
AIN3
Out
20kΩ
SDATA
or
8kΩ
8kΩ
Buffer
CAP
Internal
+2.5V Ref
8
D7-D0
BYTE
6kΩ
REF
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
©
SBAS044
1996 Burr-Brown Corporation
PDS-1303B
1
Printed in U.S.A. October, 1997
ADS7824
SPECIFICATIONS
ELECTRICAL
At TA = –40°C to +85°C, f S = 40kHz, VS1 = VS2 = VS = +5V ±5%, using external reference, CONTC = 0V, unless otherwise specified.
ADS7824P, U
PARAMETER
CONDITIONS
MIN
TYP
RESOLUTION
ADS7824PB, UB
MAX
MIN
TYP
12
ANALOG INPUT
Voltage Range
Impedance
Capacitance
Channel On or Off
THROUGHPUT SPEED
Conversion Time
Acquisition Time
Multiplexer Settling Time
Complete Cycle (Acquire and Convert)
Complete Cycle (Acquire and Convert)
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise(3)
Full Scale Error(4)
Full Scale Error Drift
Full Scale Error(4)
Full Scale Error Drift
Bipolar Zero Error
Bipolar Zero Error Drift
Channel-to-Channel Mismatch
Power Supply Sensitivity
AC ACCURACY
Spurious-Free Dynamic Range(5)
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
Channel Separation(6)
–3dB Bandwidth
Useable Bandwidth(7)
SAMPLING DYNAMICS
Aperture Delay
Transient Response(8)
Overvoltage Recovery(9)
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
(Must use external buffer)
External Reference Voltage Range
for Specified Linearity
External Reference Current Drain
Includes Acquisition
20
5
5
✻
✻
✻
µs
µs
µs
µs
µs
kHz
✻
✻
✻
±0.15
±0.15
Guaranteed
0.1
±7
±2
±2
+4.75 < VS < +5.25
80
70
70
90
90
–90
73
73
100
2
90
±1
±1
✻
✻
✻
✻
±0.5
±5
±0.5
±0.5
±0.5
±0.25
±0.25
✻
±10
✻
✻
±0.1
±0.5
±0.1
✻
✻
–80
72
72
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
40
5
1
FS Step
LSB (2)
LSB
LSB
%
ppm/°C
%
ppm/°C
mV
ppm/°C
%
LSB
dB
dB
dB
dB
dB
MHz
kHz
ns
µs
µs
2.48
2.5
1
2.52
✻
✻
✻
✻
V
µA
2.3
2.5
2.7
✻
✻
✻
V
✻
µA
✻
✻
✻
✻
V
V
µA
µA
✻
V
V
µA
pF
VREF = +2.5V
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
100
–0.3
+2.4
DIGITAL OUTPUTS
Data Format
Data Coding
VOL
VOH
Leakage Current
Output Capacitance
V
kΩ
pF
25
40
1kHz
1kHz
1kHz
1kHz
1kHz
Bits
✻
✻
✻
40
fIN =
fIN =
fIN =
fIN =
fIN =
UNITS
✻(1)
±10V
45.7
35
CONTC = +5V
Internal Reference
Internal Reference
MAX
+0.8
VS +0.3V
±10
±10
Parallel in two bytes; Serial
Binary Two's Complement
+0.4
+4
±5
15
ISINK = 1.6mA
ISOURCE = 500µA
High-Z State, VOUT = 0V to VS
High-Z State
✻
✻
✻
✻
✻
✻
✻
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
ADS7824
2
SPECIFICATIONS (CONT)
ELECTRICAL
At TA = –40°C to +85°C, fS = 40kHz, VS1 = VS2 = V S = +5V ±5%, using external reference, CONTC = 0V, unless otherwise specified.
ADS7824P, U
PARAMETER
CONDITIONS
DIGITAL TIMING
Bus Access Time
Bus Relinquish Time
Data Clock
Internal Clock (Output only when
transmitting data)
External Clock
POWER SUPPLIES
VS1 = VS2 = VS
Power Dissipation
MIN
TYP
ADS7824PB, UB
MAX
MIN
TYP
MAX
UNITS
✻
✻
ns
ns
PAR/SER = +5V
PAR/SER = +5V
PAR/SER = 0V
EXT/INT LOW
83
83
0.5
1.5
✻
✻
MHz
EXT/INT HIGH
0.1
10
✻
✻
MHz
+5.25
50
✻
✻
✻
V
mW
µW
✻
✻
°C
°C
+4.75
+5
fS = 40kHz
PWRD HIGH
✻
✻
50
TEMPERATURE RANGE
Specified Performance
Storage
Thermal Resistance (θJA)
Plastic DIP
SOIC
–40
–65
✻
✻
+85
+150
°C/W
°C/W
✻
✻
75
75
NOTES: (1) An asterik (✻) specifies same value as grade to the left. (2) LSB means Least Significant Bit. For the 12-bit, ±10V input ADS7824, one LSB is 4.88mV. (3)
Typical rms noise at worst case transitions and temperatures. (4) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and
last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) All specifications in dB are referred
to a full-scale ±10V input. (6) A full scale sinewave input on one channel will be attenuated by this amount on the other channels. (7) Useable Bandwidth defined as
Full-Scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy. (8) The ADS7824 will accurately acquire any input step if given
a full acquisition period after the step. (9) Recovers to specified performance after 2 x FS input overvoltage, and normal acquisitions can begin.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
ADS7824P
ADS7824PB
ADS7824U
ADS7824UB
Plastic Dip
Plastic Dip
SOIC
SOIC
246
246
217
217
TEMPERATURE
RANGE
MAXIMUM INTEGRAL
LINEARITY ERROR (LSB)
MINIMUM SIGNALTO-(NOISE + DISTORTION)
RATIO (dB)
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±1
±0.5
±1
±0.5
70
72
70
72
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Analog Inputs: AIN0, AIN1, AIN2, AIN3 .............................................. ±15V
REF ................................... (AGND2 –0.3V) to (VS + 0.3V)
CAP ........................................ Indefinite Short to AGND2,
Momentary Short to VS
VS1 and VS2 to AGND2 ........................................................................... 7V
VS1 to VS2 .......................................................................................... ±0.3V
Difference between AGND1, AGND2 and DGND ............................. ±0.3V
Digital Inputs and Outputs .......................................... –0.3V to (VS + 0.3V)
Maximum Junction Temperature ..................................................... 150°C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ................................................ +300°C
Maximum Input Current to Any Pin ................................................. 100mA
Top View
ELECTROSTATIC
DISCHARGE SENSITIVITY
DIP/SOIC
AGND1
1
28 VS1
AIN0
2
27 VS2
AIN1
3
26 PWRD
AIN2
4
25 CONTC
AIN3
5
24 BUSY
CAP
6
23 CS
REF
7
AGND2
8
21 BYTE
9
20 PAR/SER
ADS7824
22 R/C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
TRI-STATE
D7
TRI-STATE
D6 10
19 A0
TRI-STATE
D5 11
18 A1
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
EXT/INT
D4 12
17 D0
TAG
SYNC
D3 13
16 D1
SDATA
DGND 14
15 D2
DATACLK
®
3
ADS7824
PIN ASSIGNMENTS
PIN #
NAME
1
AGND1
I/O
DESCRIPTION
2
AIN0
Analog Input Channel 0. Full-scale input range is ±10V.
3
AIN 1
Analog Input Channel 1. Full-scale input range is ±10V.
4
AIN 2
Analog Input Channel 2. Full-scale input range is ±10V.
5
AIN 3
Analog Input Channel 3. Full-scale input range is ±10V.
6
CAP
Internal Reference Output Buffer. 2.2µF Tantalum to ground.
7
REF
Reference Input/Output. Outputs +2.5V nominal. If used externally, must be buffered to maintain ADS7825 accuracy.
Can also be driven by external system reference. In both cases, bypass to ground with a 2.2µF Tantalum capacitor.
8
AGND2
9
D7
O
Parallel Data Bit 7 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I.
10
D6
O
Parallel Data Bit 6 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I.
11
D5
O
Parallel Data Bit 5 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I.
12
D4
I/O
Parallel Data Bit 4 if PAR/SER HIGH; if PAR/SER LOW, a LOW level input here will transmit serial data on SDATA from
the previous conversion using the internal serial clock; a HIGH input here will transmit serial data using an external serial
clock input on DATACLK (D2). See Table I.
13
D3
O
Parallel Data Bit 3 if PAR/SER HIGH; SYNC output if PAR/SER LOW. See Table I.
14
DGND
15
D2
I/O
Parallel Data Bit 2 if PAR/SER HIGH; if PAR/SER LOW, this will output the internal serial clock if EXT/INT (D4) is LOW;
will be an input for an external serial clock if EXT/INT (D4) is HIGH. See Table I.
16
D1
O
Parallel Data Bit 1 if PAR/SER HIGH; SDATA serial data output if PAR/SER LOW. See Table I.
17
D0
I/O
Parallel Data Bit 0 if PAR/SER HIGH; TAG data input if PAR/SER LOW. See Table I.
18
A1
I/O
Channel Address. Input if CONTC LOW, output if CONTC HIGH. See Table I.
19
A0
I/O
20
PAR/SER
I
Select Parallel or Serial Output. If HIGH, parallel data will be output on D0 thru D7. If LOW, serial data will be output on
SDATA. See Table I and Figure 1.
21
BYTE
I
Byte Select. Only used with parallel data, when PAR/SER HIGH. Determines which byte is available on D0 thru D7.
Changing BYTE with CS LOW and R/C HIGH will cause the data bus to change accordingly. LOW selects the 8 MSBs;
HIGH selects the 4 LSBs, see Figures 2 and 3.
22
R/C
I
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a
conversion. With CS LOW, a rising edge on R/C enables the output data bits if PAR/SER HIGH, or starts transmission
of serial data if PAR/SER LOW and EXT/INT HIGH.
23
CS
I
Chip Select. Internally OR'd with R/C. With CONTC LOW and R/C LOW, a falling edge on CS will initiate a conversion.
With R/C HIGH, a falling edge on CS will enable the output data bits if PAR/SER HIGH, or starts transmission of serial
data if PAR/SER LOW and EXT/INT HIGH.
24
BUSY
O
Busy Output. Falls when conversion is started; remains LOW until the conversion is completed and the data is latched
into the output register. In parallel output mode, output data will be valid when BUSY rises, so that the rising edge can
be used to latch the data.
25
CONTC
I
Continuous Conversion Input. If LOW, conversions will occur normally when initiated using CS and R/C; if HIGH,
acquisition and conversions will take place continually, cycling through all four input channels, as long as CS, R/C and
PWRD are LOW. See Table I. For serial mode only.
26
PWRD
I
Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the
previous conversion are maintained in the output register. In the continuous conversion mode, the multiplexer address
channel is reset to channel 0
27
VS2
Supply Input. Nominally +5V. Connect directly to pin 28. Decouple to ground with 0.1µF ceramic and 10µF Tantalum
capacitors.
28
VS1
Supply Input. Nominally +5V. Connect directly to pin 27.
Analog Ground. Used internally as ground reference point.
Analog Ground.
Digital Ground.
Channel Address. Input if CONTC LOW, output if CONTC HIGH. See Table I.
®
ADS7824
4
TYPICAL PERFORMANCE CURVES
At TA = +25°C, fS = 40kHz, VS1 = VS2 = +5V, using internal reference, unless otherwise noted.
ADJACENT CHANNEL CROSSTALK, WORST PAIR
(8192 Point FFT; AIN3 = 1.02kHz, –0.1dB; AIN2 = AGND)
0
0
–10.0
–10.0
–20.0
–20.0
–30.0
–30.0
Amplitude (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(8192 Point FFT; fIN = 1.02kHz, –0.5dB)
–40.0
–50.0
–60.0
–70.0
–40.0
–50.0
–60.0
–70.0
–80.0
–80.0
–90.0
–90.0
–100.0
–100.0
–110.0
–110.0
0
5
10
Frequency (kHz)
15
20
0
5
10
Frequency (kHz)
15
20
ADJACENT CHANNEL CROSSTALK, WORST PAIR
(8192 Point FFT; AIN3 = 10.1kHz, –0.1dB; AIN2 = AGND)
0
12-Bit LSBs
–10.0
–30.0
–40.0
–50.0
All Codes INL
0
512
1024
1536
–60.0
2048
2560
3072
3584
4095
3072
3584
4095
Decimal Code
–70.0
12-Bit LSBs
–80.0
–90.0
–100.0
–110.0
0
5
10
Frequency (kHz)
15
20
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
All Codes DNL
0
512
1024
1536
2048
2560
Decimal Code
ENDPOINT ERRORS
2
mV From Ideal
POWER SUPPLY RIPPLE SENSITIVITY
INL/DNL DEGRADATION PER LSB OF P-P RIPPLE
1
10–1
BPZ Error
1
0
–1
–2
0.2
Percent
From Ideal
10–2
INL
10–3
+FS Error
0
–0.2
10–4
0.2
–FS Error
DNL
Percent
From Ideal
Linearity Degradation (LSB/LSB)
Amplitude (dB)
–20.0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
10–5
101
102
103
104
105
106
107
0
Power Supply Ripple Frequency (Hz)
–0.2
–50
–25
0
25
50
75
100
Temperature (°C)
®
5
ADS7824
TYPICAL PERFORMANCE CURVES
(CONT)
At TA = +25°C, fS = 40kHz, VS1 = VS2 = +5V, using internal reference, unless otherwise noted.
CONVERSION TIME vs TEMPERATURE
2.520
15.7
2.515
15.6
2.510
Conversion Time (µs)
Internal Reference (V)
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE
2.505
2.500
2.495
2.490
2.485
15.5
15.4
15.3
15.2
15.1
15.0
14.9
2.480
–50
–25
0
25
50
75
14.8
–50
100
Temperature (°C)
0
25
50
Temperature (°C)
®
ADS7824
–25
6
75
100
BASIC OPERATION
PARALLEL OUTPUT
Figure 1a shows a basic circuit to operate the ADS7824 with
parallel output (Channel 0 selected). Taking R/C (pin 22)
LOW for 40ns (12µs max) will initiate a conversion. BUSY
(pin 24) will go LOW and stay LOW until the conversion is
completed and the output register is updated. If BYTE (pin
21) is LOW, the 8 most significant bits will be valid when
pin 24 rises; if BYTE is HIGH, the 4 least significant bits
will be valid when BUSY rises. Data will be output in
Binary Two’s Complement format. BUSY going HIGH can
be used to latch the data. After the first byte has been read,
BYTE can be toggled allowing the remaining byte to be
read. All convert commands will be ignored while BUSY is
LOW.
SERIAL OUTPUT
Figure 1b shows a basic circuit to operate the ADS7824 with
serial output (Channel 0 selected). Taking R/C (pin 22)
LOW for 40ns (12µs max) will initiate a conversion and
output valid data from the previous conversion on SDATA
(pin 16) synchronized to 12 clock pulses output on
DATACLK (pin 15). BUSY (pin 24) will go LOW and stay
LOW until the conversion is completed and the serial data
has been transmitted. Data will be output in Binary Two’s
Complement format, MSB first, and will be valid on both the
rising and falling edges of the data clock. BUSY going
HIGH can be used to latch the data. All convert commands
will be ignored while BUSY is LOW.
The ADS7824 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal.
The ADS7824 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal.
Parallel Output
±10V
1
28
2
27
3
26
4
25
5
24
6
23
7
22
0.1µF 10µF
+
+
+5V
BUSY
+
Convert Pulse
R/C
2.2µF
+
ADS7824
2.2µF
BYTE
8
21
9
20
10
19
11
18
12
17
13
16
14
15
40ns min
+5V(1)
Serial Output
Pin 21
LOW
D11 D10
D9
D8
D7
D6
Pin 21
HIGH
D3
D1
D0
LOW
LOW LOW LOW
D2
D5
D4
±10V
1
28
2
27
3
26
4
25
5
24
6
23
NOTE: (1) PAR/SER = 5V
+
0.1µF 10µF
+
+
+5V
BUSY
Convert Pulse
2.2µF
7
+
R/C
22
ADS7824
2.2µF
8
21
9
20
NC(2) 10
19
NC(2) 11
18
EXT/INT
12
17
SYNC
13
16
SDATA
14
15
DATACLK(1)
NC(2)
40ns min
(3)
NOTES: (1) DATACLK (pin 15) is an output when EXT/INT (pin 12) is LOW
and an input when EXT/INT is HIGH. (2) NC = no connection. (3) PAR/SER = 0V.
FIGURE 1. Basic Connection Diagram, (a) Parallel Output, (b) Serial Output.
®
7
ADS7824
STARTING A CONVERSION
initiating a conversion. If, however, it is critical that CS or
R/C initiates conversion ‘n’, be sure the less critical input is
LOW at least 10ns prior to the initiating input. If EXT/INT
(pin 12) is LOW when initiating conversion ‘n’, serial data
from conversion ‘n – 1’ will be output on SDATA (pin 16)
following the start of conversion ‘n’. See Internal Data
Clock in the Reading Data section.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. This will
have no effect when using the internal data clock in the serial
output mode. However, the parallel output and the serial
output (only when using an external data clock) will be
affected whenever R/C goes HIGH. Refer to the Reading
Data section and Figures 2, 3, 5, and 6.
The combination of CS (pin 23) and R/C (pin 22) LOW for
a minimum of 40ns places the sample/hold of the ADS7824
in the hold state and starts conversion ‘n’. BUSY (pin 24)
will go LOW and stay LOW until conversion ‘n’ is completed and the internal output register has been updated. All
new convert commands during BUSY LOW will be ignored.
CS and/or R/C must go HIGH before BUSY goes HIGH or
a new conversion will be initiated without sufficient time to
acquire a new signal.
The ADS7824 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal. Refer to
Tables Ia and Ib for a summary of CS, R/C, and BUSY states
and Figures 2 through 6 and Table II for timing information.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
INPUTS
OUTPUTS
CS
R/C
BYTE
CONTC
PWRD
BUSY
D7
D6
D5
D4
D3
D2
D1
D0
1
X
0
X
0
1
X
X
0
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
D10
Hi-Z
Hi-Z
D9
Hi-Z
Hi-Z
D8
Hi-Z
Hi-Z
D7
Hi-Z
Hi-Z
D6
Hi-Z
Hi-Z
D5
Hi-Z
Hi-Z
D4
0
1
1
X
X
X
Hi-Z
Hi-Z
D11
(MSB)
D3
D2
D1
LOW
LOW
LOW
LOW
0
1
X
X
X
↑
↑↓
↑↓
↑↓
D0
(LSB)
↑↓
↑↓
↑↓
↑↓
↑↓
COMMENTS
Results from last
completed conversion.
Results from last
completed conversion.
Data will change at the
end of a conversion.
TABLE Ia. Read Control for Parallel Data (PAR/SER = 5V.)
D3
SYNC
D2
DATACLK
D1
SDATA
D0
TAG
Input
LOW
LOW
LOW
Output
LOW
LOW
LOW
I/O
Output
Output
Output
Output
Hi-Z
Hi-Z
Output
Input
X
X
X
Hi-Z
LOW
LOW
Output
Output
X
X
Hi-Z
HIGH
LOW
Input
Output
Input
X
↑
Hi-Z
HIGH
LOW
Input
Output
Input
0
X
1
Hi-Z
HIGH
LOW
Input
Output
X
1
0
X
1
Hi-Z
HIGH
LOW
Input
Output
X
0
0
1
0
↓
Hi-Z
LOW
LOW
Output
Output
X
↓
1
X
X
X
Hi-Z
HIGH
Output
Input
Output
X
0
↑
X
X
X
Hi-Z
HIGH
Output
Input
Output
X
↓
0
1
X
X
Hi-Z
LOW
LOW
Output
Output
X
0
↓
1
X
X
Hi-Z
LOW
LOW
Output
Output
X
CONTC PWRD
BUSY
D7, D6, D5
D4
LOW
EXT/INT
CS
R/C
Input
1
X
0
Input
X
0
↓
Input
X
X
0
Input
X
X
X
Output
1
1
1
Output
Hi-Z
Hi-Z
Hi-Z
↓
0
0
X
1
0
1
0
X
0
1
0
0
↑
↓
TABLE Ib. Read Control for Serial Data (PAR/SER = 0V.)
®
ADS7824
8
COMMENTS
Starts transmission of data from previous
conversion on SDATA synchronized to 12
pulses output on DATACLK.
Starts transmission of data from previous
conversion on SDATA synchronized to 12
pulses output on DATACLK.
The level output on SDATA will be the level
input on TAG 12 DATACLK input cycles
earlier.
At the end of the conversion, when BUSY
rises, data from the conversion will be shifted
into the output registers. If DATACLK is HIGH,
valid data will be lost.
Initiates transmission of a HIGH pulse on
SYNC followed by data from last completed
conversion on SDATA synchronized to the
input on DATACLK.
Initiates transmission of a HIGH pulse on
SYNC followed by data from last completed
conversion on SDATA synchronized to the
input on DATACLK.
Starts transmission of data from previous
conversion on SDATA synchronized to 12
pulses output on DATACLK
SDATA becomes active. Inputs on DATACLK
shift out data.
SDATA becomes active. Inputs on DATACLK
shift out data.
Restarts continuous conversion mode (n – 1 data
transmitted when BUSY is LOW).
Restarts continuous conversion mode (n – 1 data
transmitted when BUSY is LOW).
t1
t1
R/C
t3
t3
t4
BUSY
t5
t6
t6
t7
Convert
Acquire
MODE
t8
t12
Acquire
Convert
t12
t11
t10
Parallel
Data Bus
Previous
High Byte Valid
Previous High
Byte Valid
Hi-Z
Previous Low
Byte Valid
Low Byte
Valid
High Byte
Valid
Not Valid
High Byte
Valid
t9
t2
t12
t12
t9
Hi-Z
t12
t12
BYTE
FIGURE 2. Conversion Timing with Parallel Output (CS LOW).
t21
t21
t21
t21
t21
t21
t21
t21
t21
t21
R/C
t1
CS
t3
t4
BUSY
BYTE
DATA
BUS
Hi-Z State
High Byte
Hi-Z State
t9
t12
Low Byte
t12
Hi-Z State
t9
FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.
t7 + t8
CS or R/C(1)
t14
1
t13
DATACLK
2
3
11
12
Bit 9 Valid
Bit 1 Valid
LSB Valid
1
2
MSB Valid
Bit 10 Valid
t16
t15
SDATA
MSB Valid
Hi-Z
t25
Bit 10 Valid
Hi-Z
(Results from previous conversion.)
BUSY
t26
NOTE: (1) If controlling with CS, tie R/C LOW. If controlling with R/C, tie CS LOW.
FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG LOW).
®
9
ADS7824
®
ADS7824
10
t21
t3
t1
t27
t21
t17
t19
t23
t20
1
t17
Tag 0
t24
2
Tag 1
Bit 11 (MSB)
3
Tag 2
Bit 10
4
FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT HIGH). Read After Conversion.
TAG
SDATA
SYNC
BUSY
R/C
CS
EXTERNAL
DATACLK
0
t18
Tag 11
Bit 1
13
Tag 12
Bit 0 (LSB)
14
Tag 13
Tag 0
t22
t28
11
ADS7824
®
t21
t3
t17
t1
t19
t20
t27
t23
Tag 0
t17
t24
Tag 1
Bit 11 (MSB)
t11
Tag 12
Bit 0 (LSB)
Tag 13
Tag 0
t22
t28
FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT HIGH). Read During Conversion (Previous Conversion Results).
TAG
SDATA
SYNC
BUSY
R/C
CS
EXTERNAL
DATACLK
t18
READING DATA
after the start of conversion ‘n’. Do not attempt to read data
beyond 12µs after the start of conversion ‘n’ until BUSY
(pin 24) goes HIGH; this may result in reading invalid data.
Refer to Table II and Figures 2 and 3 for timing constraints.
PARALLEL OUTPUT
To use the parallel output, tie PAR/SER (pin 20) HIGH. The
parallel output will be active when R/C (pin 22) is HIGH and
CS (pin 23) is LOW. Any other combination of CS and R/C
will tri-state the parallel output. Valid conversion data can be
read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When
BYTE (pin 21) is LOW, the 8 most significant bits will be
valid with the MSB on D7. When BYTE is HIGH, the 4 least
significant bits will be valid with the LSB on D4. BYTE can
be toggled to read both bytes within one conversion cycle.
SERIAL OUTPUT
When PAR/SER (pin 20) is LOW, data can be clocked out
serially with the internal data clock or an external data clock.
When EXT/INT (pin 12) is LOW, DATACLK (pin 15) is an
output and is always active regardless of the state of CS (pin
23) and R/C (pin 22). The SDATA output is active when
BUSY (pin 24) is LOW. Otherwise, it is in a tri-state
condition. When EXT/INT is HIGH, DATACLK is an input.
The SDATA output is active when CS is LOW and R/C is
HIGH. Otherwise, it is in a tri-state condition. Regardless of
the state of EXT/INT, SYNC (pin 13) is an output and always
active, while TAG (pin 17) is always an input.
Upon initial power up, the parallel output will contain
indeterminate data.
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13
and 15-17). BUSY going HIGH can be used to latch the
data. Refer to Table II and Figures 2 and 3 for timing
constraints.
INTERNAL DATA CLOCK (During A Conversion)
To use the internal data clock, tie EXT/INT (pin 12) LOW.
The combination of R/C (pin 22) and CS (pin 23) LOW will
initiate conversion ‘n’ and activate the internal data clock
(typically 900kHz clock rate). The ADS7824 will output 12
bits of valid data, MSB first, from conversion ‘n – 1’ on
SDATA (pin 16), synchronized to 12 clock pulses output on
DATACLK (pin 15). The data will be valid on both the
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n – 1’ can be read and will be valid up to 12µs
SYMBOL
DESCRIPTION
MIN
t1
Convert Pulse Width
0.04
TYP
t2
Start of Conversion to New Data Valid
t3
Start of Conversion to BUSY LOW
t4
BUSY LOW
15
t5
End of Conversion to BUSY HIGH
90
t6
Aperture Delay
40
t7
Conversion Time
15
t8
Acquisition Time
3
t7 + t8
Throughput Time
15
t9
Bus Relinquish Time
10
t10
Data Valid to BUSY HIGH
20
60
12
15
MAX
UNITS
12
µs
21
µs
85
ns
21
µs
ns
ns
21
µs
5
µs
25
µs
83
ns
ns
µs
t11
Start of Conversion to Previous Data Not Valid
t12
Bus Access Time and BYTE Delay
t13
Start of Conversion to DATACLK Delay
t14
DATACLK Period
t15
Data Valid to DATACLK HIGH
20
t16
DATACLK LOW to Data Not Valid
400
600
t17
External DATACLK Period
100
ns
t18
External DATACLK HIGH
50
ns
t19
External DATACLK LOW
40
ns
t20
CS LOW and R/C HIGH to External DATACLK HIGH (Enable Clock)
25
ns
t21
R/C to CS Setup Time
10
ns
t22
CS HIGH or R/C LOW to External DATACLK HIGH (Disable Clock)
25
ns
t23
DATACLK HIGH to SYNC HIGH
15
35
ns
t24
DATACLK HIGH to Valid Data
25
55
ns
t25
Start of Conversion to SDATA Active
83
ns
t26
End of Conversion to SDATA Tri-State
83
ns
t27
CS LOW and R/C HIGH to SDATA Active
83
ns
t28
CS HIGH or R/C LOW to SDATA Tri-State
83
ns
t29
BUSY HIGH to Address Valid
20
ns
t30
Address Valid to BUSY LOW
83
500
TABLE II. Conversion, Data, and Address Timing. TA = –40°C to +85°C.
®
ADS7824
12
ns
1.4
µs
1.1
µs
75
ns
ns
ns
rising and falling edges of the internal data clock. The rising
edge of BUSY (pin 24) can be used to latch the data. After
the 12th clock pulse, DATACLK will remain LOW until the
next conversion is initiated, while SDATA will go to whatever logic level was input on TAG (pin 17) during the first
clock pulse. The SDATA output will tri-state when BUSY
returns HIGH. Refer to Table II and Figure 4 for timing
information.
14th falling edge and the 15th rising edge of DATACLK; the
second input bit will be valid on the 15th falling edge and the
16th rising edge, etc. With a continuous data clock, TAG
data will be output on DATA until the internal output
registers are updated with the results from the next conversion. Refer to Table II and Figure 5 for timing information.
EXTERNAL DATA CLOCK (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n – 1’ can be read and will be valid up to 12µs
after the start of conversion ‘n’. Do not attempt to clock out
data from 12µs after the start of conversion ‘n’ until BUSY
(pin 24) rises; this will result in data loss.
EXTERNAL DATA CLOCK
To use an external clock, tie EXT/INT (pin 12) HIGH. The
external clock is not a conversion clock; it can only be used
as a data clock. To enable the output mode of the ADS7824,
CS (pin 23) must be LOW and R/C (pin 22) must be HIGH.
DATACLK must be HIGH for 20% to 70% of the total data
clock period; the clock rate can be between DC and 10MHz.
Serial data from conversion ‘n’ can be output on SDATA
(pin 16) after conversion ‘n’ is completed or during conversion ‘n + 1’.
NOTE: For the best possible performance when using an
external data clock, data should not be clocked out during a
conversion. The switching noise of the asynchronous data
clock can cause digital feedthrough degrading the converter’s
performance. Refer to Table II and Figure 6 for timing
information.
An obvious way to simplify control of the converter is to tie
CS LOW while using R/C to initiate conversions. While this
is perfectly acceptable, there is a possible problem when
using an external data clock. At an indeterminate point from
12µs after the start of conversion ‘n’ until BUSY rises, the
internal logic will shift the results of conversion ‘n’ into the
output register. If CS is LOW, R/C is HIGH and the external
clock is HIGH at this point, data will be lost. So, with CS
LOW, either R/C and/or DATACLK must be LOW during
this period to avoid losing valid data.
TAG FEATURE
TAG (pin 17) inputs serial data synchronized to the external
or internal data clock.
When using an external data clock, the serial bit stream input
on TAG will follow the LSB output on SDATA (pin 16)
until the internal output register is updated with new conversion results. See Table II and Figures 5 and 6.
The logic level input on TAG for the first rising edge of the
internal data clock will be valid on SDATA after all 12 bits
of valid data have been output.
EXTERNAL DATA CLOCK (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. With CS
LOW (pin 23) and R/C HIGH (pin 22), valid data from
conversion ‘n’ will be output on SDATA (pin 16) synchronized to the external data clock input on DATACLK (pin
15). Between 15 and 35ns following the rising edge of the
first external data clock, the SYNC output pin will go HIGH
for one full data clock period (100ns minimum). The MSB
will be valid between 25 and 55ns after the rising edge of the
second data clock. The LSB will be valid on the 13th falling
edge and the 14th rising edge of the data clock. TAG (pin
17) will input a bit of data for every external clock pulse.
The first bit input on TAG will be valid on SDATA on the
CONTC
CS
R/C
BUSY
PWRD
0
X
X
X
X
Inputs
0
0
0
0
X
0
↓
X
X
↓
0
X
0
1
1
X
0
0
0
1
Inputs
Inputs
Inputs
Inputs
1
X
X
X
X
Outputs
1
1
1
1
X
0
↓
X
X
↓
0
X
0
1
1
X
0
0
0
1
Outputs
Outputs
Outputs
Outputs
MULTIPLEXER TIMING
The four channel input multiplexer may be addressed manually or placed in a continuous conversion mode where all
four channels are sequentially addressed.
CONTINUOUS CONVERSION MODE (CONTC= 5V)
To place the ADS7824 in the continuous conversion mode,
CONTC (pin 25) must be tied HIGH. In this mode, acquisition and conversions will take place continually, cycling
through all four channels as long as CS, R/C and PWRD are
LOW (See Table III). Whichever address was last loaded
A0 and A1 OPERATION
Initiating conversion n latches in the levels input on A0 and A1 to select the channel for
conversion 'n + 1'.
Conversion in process. New convert commands ignored.
Initiates conversion on channel selected at start of previous conversion.
Initiates conversion on channel selected at start of previous conversion.
All analog functions powered down. Conversions in process or initiated will yield
meaningless data.
The end of conversion n (when BUSY rises) increments the internal channel latches and
outputs the channel address for conversion 'n + 1' on A0 and A1.
Conversion in process.
Restarts continuous conversion process on next input channel.
Restarts continuous conversion process on next input channel.
All analog functions powered down. Conversions in process or initiated will yield
meaningless data. Resets selected input channel for next conversion to AIN0.
TABLE III. Conversion Control.
®
13
ADS7824
into the A0 and A1 registers (pins 19 and 18, respectively)
prior to CONTC being raised HIGH, becomes the first
address in the sequential continuous conversion mode (e.g.,
if Channel 1 was the last address selected then Channel 2 will
follow, then Channel 3, and so on). The A0 and A1 address
inputs become outputs when the device is in this mode.
When BUSY rises at the end of a conversion, A0 and A1 will
output the address of the channel that will be converted when
BUSY goes LOW at the beginning of the next conversion.
Data will be valid for the previous channel after BUSY rises.
The address lines are updated when BUSY rises. See Table
IVa and Figure 7 for channel selection timing in continuous
conversion mode.
PWRD (pin 26) can be used to reset the multiplexer address
to zero. With the ADS7824 configured for no conversion,
PWRD can be taken HIGH for a minimum of 200ns. When
PWRD returns LOW, the multiplexer address will be reset to
zero. When the continuous conversion mode is enabled, the
first conversion will be done on Channel 0. Subsequent
conversions will proceed through each higher channel,
cycling back to zero after Channel 3.
If PWRD is held HIGH for a significant period of time, the
REF (pin 7) bypass capacitor may discharge (if the internal
reference is being utilized) and the CAP (pin 6) bypass
capacitor will discharge (for both internal and external
references). The continuous conversion mode should not be
enabled until the bypass capacitor(s) have recharged and
stabilized (1ms for 2.2µF capacitors recommended). In
addition, the continuous conversion mode should not be
enabled even with a short pulse on PWRD until the minimum acquisition time has been met.
MANUAL CHANNEL SELECTION (CONTC= 0V)
The channels of the ADS7824 can be selected manually by
using the A0 and A1 address pins (pins 19 and 18, respectively). See Table IVb for the multiplexer truth table and
Figure 8 for channel selection timing.
ADS7824 TIMING AND CONTROL
A1
A0
DATA AVAILABLE
FROM CHANNEL
CHANNEL TO BE
OR BEING CONVERTED
0
0
1
1
0
1
0
1
AIN3
AIN0
AIN1
AIN2
AIN0
AIN1
AIN2
AIN3
DESCRIPTION OF OPERATION
Channel being acquired or converted is output on these
address lines. Data is valid for the previous channel. These
lines are updated when BUSY rises.
TABLE IVa. A0 and A1 Outputs (CONTC HIGH).
A1
A0
CHANNEL SELECTED
WHEN BUSY GOES HIGH
0
0
1
1
0
1
0
1
AIN0
AIN1
AIN2
AIN3
DESCRIPTION OF OPERATION
Channel to be converted during conversion 'n + 1' is latched
when conversion 'n' is initiated (BUSY goes LOW). The selected
input starts being acquired as soon as conversion 'n' is done
(BUSY goes HIGH).
TABLE IVb. A0 and A1 Inputs (CONTC LOW).
Conversion Currently in Progress:
BUSY
n–2
n–1
n
n+1
n+2
n+3
n+4
Channel Address for Conversion:
A0, A1
(Output)
n–2
n–1
n
n+1
n+2
n+3
n+4
n+5
t29
Results from Conversion:
D7-D0
n–3
n–2
n–1
n
n+1
n+2
n+3
n+4
FIGURE 7. Channel Addressing in Continuous Conversion Mode (CONTC HIGH, CS and R/C LOW).
R/C
Conversion Currently in Progress:
BUSY
n–2
n–1
n
n+1
n+2
n+3
n+4
Channel Address for Conversion:
A0, A1
(Input)
n–1
n
n+1
n+2
n+3
n+4
n+5
t30
Results from Conversion:
D7-D0
n–3
n–2
n–1
n
n+1
n+2
FIGURE 8. Channel Addressing in Normal Conversion Mode (CONTC and CS LOW).
®
ADS7824
14
n+3
n+4
CALIBRATION
CDAC. Capacitor values larger than 2.2(F will have little
affect on improving performance.
The ADS7824 has no internal provision for correcting the
individual bipolar zero error or full-scale error for each
individual channel. Instead, the bipolar zero error of each
channel is guaranteed to be below a level which is quite
small for a converter with a ±10V input range (slightly more
than ±2 LSBs). In addition, the channel errors should match
each other to within 1 LSB.
For the full-scale error, the circuit of Figure 9 can be used.
This will allow the reference to be adjusted such that the
full-scale error for any single channel can be set to zero.
Again, the close matching of the channels will ensure that
the full-scale errors on the other channels will be small.
The output of the buffer is capable of driving up to 1mA of
current to a DC load. Using an external buffer will allow the
internal reference to be used for larger DC loads and AC
loads. Do not attempt to directly drive an AC load with the
output voltage on CAP. This will cause performance degradation of the converter.
PWRD
PWRD (pin 26) HIGH will power down all of the analog
circuitry including the reference. Data from the previous
conversion will be maintained in the internal registers and
can still be read. With PWRD HIGH, a convert command
yields meaningless data. When PWRD is returned LOW,
adequate time must be provided in order for the capacitors
on REF (pin 7) and CAP (pin 6) to recharge. For 2.2µF
capacitors, a minimum recharge/settling time of 1ms is
recommended before the conversion results should be considered valid.
AIN2
AIN3
+5V
CAP
R1
1MΩ
+
P1
50kΩ
2.2µF
LAYOUT
REF
2.2µF
+
POWER
The ADS7824 uses 90% of its power for the analog circuitry, and the converter should be considered an analog
component. For optimum performance, tie both power pins
to the same +5V power supply and tie the analog and digital
grounds together.
The +5V power for the converter should be separate from
the +5V used for the system’s digital logic. Connecting VS1
and VS2 (pins 28 and 27) directly to a digital supply can
reduce converter performance due to switching noise from
the digital logic. For best performance, the +5V supply can
be produced from whatever analog supply is used for the rest
of the analog signal conditioning. If +12V or +15V supplies
are present, a simple +5V regulator can be used. Although it
is not suggested, if the digital supply must be used to power
the converter, be sure to properly filter the supply. Either
using a filtered digital supply or a regulated analog supply,
both VS1 and VS2 should be tied to the same +5V source.
AGND2
FIGURE 9. Full Scale Trim.
REFERENCE
The ADS7824 can operate with its internal 2.5V reference or
an external reference. By applying an external reference to
pin 7, the internal reference can be bypassed.
REF
REF (pin 7) is an input for an external reference or the output
for the internal 2.5V reference. A 2.2µF capacitor should be
connected as close to the REF pin as possible. This capacitor
and the output resistance of REF create a low pass filter to
bandlimit noise on the reference. Using a smaller value
capacitor will introduce more noise to the reference degrading the SNR and SINAD. The REF pin should not be used
to drive external AC or DC loads.
The range for the external reference is 2.3V to 2.7V and
determines the actual LSB size. Increasing the reference
voltage will increase the full scale range and the LSB size of
the converter which can improve the SNR.
GROUNDING
Three ground pins are present on the ADS7824. DGND is
the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground which all analog signals
internal to the A/D are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path
of least resistance back to the power supply.
All the ground pins of the A/D should be tied to an analog
ground plane, separated from the system’s digital logic
ground, to achieve optimum performance. Both analog and
digital ground planes should be tied to the ‘system’ ground
as near to the power supplies as possible. This helps to
prevent dynamic digital ground currents from modulating
the analog ground through a common impedance to power
ground.
CAP
CAP (pin 6) is the output of the internal reference buffer. A
2.2µF capacitor should be placed as close to the CAP pin as
possible to provide optimum switching currents for the
CDAC throughout the conversion cycle. This capacitor also
provides compensation for the output of the buffer. Using a
capacitor any smaller than 1µF can cause the output buffer
to oscillate and may not have sufficient charge for the
®
15
ADS7824
CROSSTALK
With a full-scale 1kHz input signal, worst case crosstalk on
the ADS7824 is better than –95dB. This should be adequate
for even the most demanding applications. However, if
crosstalk is a concern, the following items should be kept in
mind:
The worst case crosstalk is generally from Channel 3 to 2. In
addition, crosstalk from Channel 3 to any other channel is
worse than from those channels to Channel 3. The reason for
this is that channel three is nearer to the reference on the
ADS7824. This allows two coupling modes: channel-tochannel and Channel 3 to the reference. In general, when
crosstalk is a concern, avoid placing signals with higher
frequency components on Channel 3.
If a particular channel should be as immune as possible from
crosstalk, Channel 0 would be the best channel for the signal
and Channel 1 should have the signal with the lowest
frequency content. If two signals are to have as little crosstalk
as possible, they should be placed on Channel 0 and Channel
2 with lower frequency, less-sensitive inputs on the other
channels.
minimal requirement for the drive capability on the signal
conditioning preceding the A/D. Any op amp sufficient for
the signal in an application will be sufficient to drive the
ADS7824.
The resistive front end of the ADS7824 also provides a
guaranteed ±15V overvoltage protection. In most cases, this
eliminates the need for external over voltage protection
circuitry.
INTERMEDIATE LATCHES
The ADS7824 does have tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversions, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7824 has an internal LSB size of 610µV.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance. The effect of this phenomenon will
be more obvious when using the pin-compatible ADS7825
or any of the other 16-bit converters in the ADS Family. This
is due to the smaller LSB size of 38µV.
For an ADS7824 with proper layout, grounding, and bypassing; the effect should only be a few tenths of an LSB at the
most. In those cases where this is not true, it is possible for
the conversion results to exhibit random errors of many
LSBs. Poor grounding, poor bypassing, and high-speed
digital signals will increase the magnitude of the errors.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS
A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The
amount of charge injection due to the sampling FET switch
on the ADS7824 is approximately 5-10% of the amount on
similar ADCs with the charge redistribution DAC (CDAC)
architecture. There is also a resistive front end which attenuates any charge which is released. The end result is a
®
ADS7824
16
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ADS7824U
ACTIVE
SOIC
DW
28
20
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
ADS7824U
Samples
ADS7824U/1K
ACTIVE
SOIC
DW
28
1000
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
ADS7824U
Samples
ADS7824UB
ACTIVE
SOIC
DW
28
20
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
ADS7824U
B
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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