ADS7831U

® FPO ADS 783 1 ADS7831 ADS 783 1 12-Bit 600kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER FEATURES q 600kHz THROUGHPUT RATE q STANDARD ±2.5V INPUT RANGE q 69dB min SINAD WITH 250kHz INPUT q COMPLETE WITH S/H, REF, CLOCK, ETC. q PARALLEL DATA w/LATCHES q FULLY SPECIFIED –40°C TO +85°C q 15MHz –3dB BANDWIDTH q 28-PIN 0.3" PDIP AND SOIC DESCRIPTION The ADS7831 is a complete 12-bit sampling A/D using state-of-the-art CMOS structures. It contains a complete 12-bit capacitor-based SAR A/D with inherent S/H, reference, clock, interface for microprocessor use, and three-state output drivers. The ADS7831 is specified at a 600kHz sampling rate, and guaranteed over the full temperature range. A ±2.5V input range and excellent Nyquist performance provide an optimum solution in ±5V supply systems. The 28-pin ADS7831 is available in a plastic 0.3" DIP and in an SOIC, both fully specified for operation over the industrial –40°C to +85°C range. FREQUENCY SPECTRUM (16384 Point FFT; fIN = 250kHz, –0.5dB) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 THD SNR SFDR 2nd Harmonic 3rd Harmonic : : : : : –91dB 72dB 94dB –98dB –94dB Amplitude (dB) 3 2 SFDR: 94dBc 75 150 Frequency (kHz) 225 300 International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1994 Burr-Brown Corporation PDS-1275 1 ADS7831 Printed in U.S.A. March, 1995 SPECIFICATIONS At TA = –40°C to +85°C, fS = 600kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistor shown in Figure 4b, unless otherwise specified. ADS7831P, U PARAMETER RESOLUTION ANALOG INPUT Voltage Range Impedance Capacitance THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Total Unadjusted Error(2, 3) (Includes Bipolar Zero Error and Full Scale Error) Power Supply Sensitivity (+VDIG = +VANA = VD) AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Usable Bandwidth(5) Full-Power Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Overvoltage Recovery(6) REFERENCE Reference Voltage Reference DC Source Current (External load should be static) DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current Output Capacitance DIGITAL TIMING Bus Access Time Bus Relinquish Time POWER SUPPLIES Specified Performance +VDIG = +VANA –VANA +IDIG +IANA –IANA Power Dissipation TEMPERATURE RANGE Specified Performance Storage Thermal Resistance (θJA) Plastic DIP SOIC ±2.5 3.1 5 1.3 Acquire & Convert 600 ±1 ±1 Guaranteed ±10 LSB 1.66 CONDITIONS MIN TYP MAX 12 UNITS Bits V kΩ pF µs µs kHz LSB(1) LSB +4.75V < VD < +5.25V –5.25V < –VANA < –4.75V fIN = fIN = fIN = fIN = 250kHz 250kHz 250kHz 250kHz 77 69 69 87 –85 71 72 1.6 15 20 10 200 250 2.45 2.5 100 ±5 LSB –77 dB(4) dB dB dB MHz MHz ns ps ns ns FS Step 2.55 V µA –0.3 +2.4 VIL = 0V VIH = 5V Parallel 12-bits Binary Two's Complement ISINK = 1.6mA ISOURCE = 500µA High-Z State, VOUT = 0V to VDIG High-Z State +0.8 VD + 0.3 ±10 ±10 V V µA µA +0.4 +2.8 ±5 15 62 83 V V µA pF ns ns +4.75 –5.25 fS = 600kHz –40 –65 +5 –5 +16 +16 –12 220 +5.25 –4.75 275 +85 +150 V V mA mA mA mW °C °C °C/W °C/W 75 75 NOTES: (1) LSB means Least Significant Bit. For the 12-bit, ±2.5V input ADS7831, one LSB is 1.22mV. (2) Measured with 50Ω in series with analog input. Adjustable to zero with external potentiometers. (3) Total unadjusted error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. (4) All specifications in dB are referred to a full-scale ±2.5V input. (5) Usable Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy. 6) Recovers to specified performance after 2 x FS input over voltage. ® ADS7831 2 BLOCK DIAGRAM Clock Successive Approximation Register and Control Logic CDAC 575Ω ±2.5V Input 2.5kΩ Comparator Cap Output Latches and Three State Drivers BUSY Three State Parallel Data Bus 18kΩ Buffer 4.8kΩ 8.6kΩ 2.5V Ref Out Internal Ref ABSOLUTE MAXIMUM RATINGS Analog Inputs: VIN .............................................................................. ±25V REF ..................................... +VANA +0.3V to AGND2 –0.3V CAP ........................................... Indefinite Short to AGND2 Momentary Short to +VANA Ground Voltage Differences: DGND, AGND1, AGND2 ................... ±0.3V +VANA .................................................................................................... +7V +VDIG to +VANA ................................................................................... +0.3V +VDIG ...................................................................................................... 7V –VANA .................................................................................................... –7V Digital Inputs ............................................................. –0.3V to +VDIG +0.3V Maximum Junction Temperature ................................................... +165°C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ................................................ +300°C PACKAGE AND ORDERING INFORMATION(1) MODEL ADS7831P ADS7831U PACKAGE 28-Pin Plastic DIP 28-Pin SOIC PACKAGE DRAWING NUMBER 246 217 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADS7831 PIN ASSIGNMENTS PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 NAME VIN AGND1 REF CAP AGND2 D11 (MSB) D10 D9 D8 D7 D6 D5 D4 DGND D3 D2 D1 D0 (LSB) DIGITAL I/O DESCRIPTION Analog Input. Connect via 50Ω to analog input. Full-scale input range is ±2.5V. Analog Ground. Used internally as ground reference point. Minimal current flow. Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system reference. In both cases, decouple to ground with a 0.1µF ceramic capacitor. Reference Buffer Output. 10µF tantalum capacitor to ground. Nominally +2V. Analog Ground. Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. Digital Ground. Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. Not internally connected. Analog Positive Supply Input. Nominally +5V. Connect directly to pins 21, 27 and 28. Digital Supply Input. Nominally +5V. Connect directly to pins 20, 27 and 28. Digital ground. Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion. With CS LOW and no conversion in progress, a rising edge on R/C enables the output data bits. Chip Select. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH and no conversion in progress, a falling edge on CS will enable the output data bits. Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the output register. With CS LOW and R/C HIGH, output data will be valid when BUSY rises, so that the rising edge can be used to latch the data. Analog Negative Supply Input. Nominally –5V. Decouple to ground with 0.1µF ceramic and 10µF tantalum capacitors. Digital Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 28. Analog Positive Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 27, and decouple to ground with 0.1µF ceramic and 10µF tantalum capacitors. O O O O O O O O O O O O +VANA +VDIG DGND R/C I 24 25 CS BUSY I O 26 27 28 –VANA +VDIG +VANA PIN CONFIGURATION Top View DIP/SOIC VIN AGND1 REF CAP AGND2 D11 (MSB) D10 D9 D8 D7 D6 D5 D4 DGND 1 2 3 4 5 6 7 ADS7831 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +VANA +VDIG –VANA BUSY CS R/C DGND +VDIG +VANA NC(1) D0 (LSB) D1 D2 D3 NOTE: (1) Not Internally Connected. ® ADS7831 4 TYPICAL PERFORMANCE CURVES T = +25°C, fS =600kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistor shown in Figure 4b, unless otherwise specified. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 252kHz, –0.5dB) 0 –20 Amplitude (dB) Amplitude (dB) 0 –20 –40 –60 –80 –100 –120 FREQUENCY SPECTRUM (4096 Point FFT; fIN = 502kHz, –0.5dB) –40 –60 –80 –100 –120 0 75 150 Frequency (kHz) 225 300 0 75 150 Frequency (kHz) 225 300 FREQUENCY SPECTRUM (4096 Point FFT; fIN = 1.002MHz, –0.5dB) 0 –20 FREQUENCY SPECTRUM (4096 Point FFT; f1IN = 232kHz, –6.5dB; f2IN = 272kHz, –6.5dB) 0 –20 Amplitude (dB) Amplitude (dB) –40 –60 –80 –100 –120 0 75 150 Frequency (kHz) 225 300 –40 –60 –80 –100 –120 0 75 150 Frequency (kHz) 225 300 SIGNAL-TO-(NOISE + DISTORTION) vs INPUT FREQUENCY (fIN = –0.5dB) 90 SFDR, SNR, and SINAD (dB) A.C. PARAMETERS vs TEMPERATURE (fIN = 250kHz, –0.5dB) 100 95 90 THD (dB) 80 70 SFDR SINAD (dB) 60 50 40 30 20 10 1k 10k 100k 1M 10M Input Signal Frequency (Hz) 85 80 75 70 SINAD 65 60 –75 –50 –25 0 25 50 75 100 125 150 Temperature (°C) THD SNR ® 5 ADS7831 TYPICAL PERFORMANCE CURVES (CONT) T = +25°C, fS =600kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistor shown in Figure 4b, unless otherwise specified. CODE TRANSITION NOISE 0.5 0 –0.5 All Codes INL –1 0 512 1024 1536 2048 2560 3072 3584 4095 Decimal Code 1 Conversions Yielding Expected Code (%) 1 12 Bit LSBs 100 75 50 25 12 Bit LSBs 0.5 0 –0.5 All Codes DNL –1 0 512 1024 1536 2048 2560 3072 3584 4095 Decimal Code D.C. PARAMETERS vs. TEMPERATURE 2 1 0 –1 –2 0.2 0.1 0 –0.1 –0.2 0 0 0.25 0.5 0.75 1 Analog Input Voltage – Expected Code Center (LSBs) INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 2.520 LSBs From Ideal Offset Error 2.515 Internal Reference (V) 2.510 2.505 2.500 2.495 2.490 2.485 2.480 –75 –50 –25 0 25 50 75 100 125 150 Percent From Ideal +FS Error 0.2 –FS Error 0.1 0 –0.1 –0.2 –75 –50 –25 Percent From Ideal 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) 1500 1450 Conversion Time (ns) CONVERSION TIME (t7) vs TEMPERATURE 1400 1350 1300 1250 1200 1150 1100 1050 –75 –50 –25 0 25 50 75 100 125 150 Temperature (°C) ® ADS7831 6 BASIC OPERATION Figure 1 shows a basic circuit to operate the ADS7831. Taking R/C (pin 23) LOW for 40ns will initiate a conversion. BUSY (pin 25) will go LOW and stay LOW until the conversion is completed and the output registers are updated. Data will be output in Binary Two’s Complement with the MSB on D11 (pin 6). BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW. The ADS7831 will begin tracking the input signal at the end of the conversion. Allowing 1.66µs between convert commands assures accurate acquisition of a new signal. no conversion is in progress. See the Reading Data section and refer to Table I for control line functions for ‘read’ and ‘convert’ modes. CS 1 ↓ 0 0 ↓ ↓ 0 0 R/C X 0 ↓ 1 1 1 ↑ 0 BUSY X 1 1 ↑ 1 0 0 ↑ OPERATION None. Databus in Hi-Z state. Initiates conversion. Databus remains in Hi-Z state. Initiates conversion. Databus enters Hi-Z state. Conversion completed. Valid data from the most recent conversion on the databus. Enables databus with valid data from the most recent conversion. Conversion in progress. Databus in Hi-Z state, enabled when the conversion is completed. Conversion in progress. Databus in Hi-Z state, enabled when the conversion is completed. Conversion completed. Valid data from the most recent conversion in the output register, but the output pins D11-D0 remain tri-stated. New convert commands ignored. Conversion in progress. STARTING A CONVERSION The combination of CS (pin 24) and R/C (pin 23) LOW for a minimum of 40ns immediately puts the sample/hold of the ADS7831 in the hold state and starts a conversion. BUSY (pin 25) will go LOW and stay LOW until the conversion is completed and the internal output register has been updated. All new convert commands during BUSY LOW will be ignored. The ADS7831 will begin tracking the input signal at the end of the conversion. Allowing 1.66µs between convert commands assures accurate acquisition of a new signal. Refer to Table I for a summary of CS, R/C, and BUSY states and Figures 2 and 3 for timing parameters. CS and R/C are internally OR’d and level triggered. There is not a requirement which input goes LOW first when initiating a conversion. If it is critical that CS or R/C initiate the conversion, be sure the less critical input is LOW at least 10ns prior to the initiating input. To reduce the number of control pins, CS can be tied LOW using R/C to control the read and convert modes. Note that the parallel output will be active whenever R/C is HIGH and X X 0 Table I. Control Line Functions for ‘read’ and ‘convert’. DESCRIPTION Full Scale Range Least Significant Bit (LSB) +Full Scale (2.5V – 1LSB) Midscale One LSB below Midscale –Full Scale 0V –1.22mV –2.5V 0000 0000 0000 1111 1111 1111 1000 0000 0000 000 FFF 800 ANALOG INPUT ±2.5V 1.22mV BINARY CODE 2.499V 0111 1111 1111 HEX CODE 7FF DIGITAL INPUT BINARY TWO'S COMPLEMENT TABLE II. Ideal Input Voltages and Output Codes. 50Ω ±2.5V 1 2 3 0.1µF 0.1µF 10µF + 28 27 26 25 24 23 22 ADS7831 21 20 19 18 17 16 15 NC 0.1µF 10µF + +5V –5V 10µF D11 (MSB) D10 D9 D8 D7 D6 D5 D4 + 4 5 6 7 8 9 10 11 12 13 14 BUSY Convert Pulse 40ns min D0 (LSB) D1 D2 D3 FIGURE 1. Basic Operation ® 7 ADS7831 t1 R/C t12 t2 t3 BUSY t4 t5 t6 MODE Acquire Convert t7 Acquire t8 Convert DATA BUS Data Valid t9 Hi-Z State Data Valid t10 HI Z State FIGURE 2. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low). READING DATA The ADS7831 outputs full parallel data in Binary Two’s Complement data output format. The parallel output will be active when R/C (pin 23) is HIGH, CS (pin 24) is LOW, and no conversion is in progress. Any other combination will tristate the parallel output. Valid conversion data can be read in a full parallel, 12-bit word on D11-D0 (pins 6-13 and 15-18). Refer to Table II for ideal output codes. After the conversion is completed and the output registers have been updated, BUSY (pin 25) will go HIGH. Valid data from the most recent conversion will be available on D11-D0 (pins 6-13 and 15-18). BUSY going HIGH can be used to latch the data. Refer to Table III and Figures 2 and 3. Note: For best performance, the external data bus connected to D11-D0 should not be active during a conversion. The switching noise of the external asynchronous data signals can cause digital feed through degrading the converter’s performance. The number of control lines can be reduced by tieing CS LOW while using R/C to initiate conversions and activate the output mode of the converter. See Figure 2. The nominal input impedance of 3.125kΩ results from the combination of the internal resistor network shown on page 3 of this data sheet and the external 50Ω resistor. The input resistor divider network provides inherent over-voltage protection guaranteed to at least ±25V. The 50Ω, 1% resistor does not compromise the accuracy or drift of the converter. It has little influence relative to the internal resistors, and tighter tolerances are not required. Note: The values shown for the internal resistors are for reference only. The exact values can vary by ±30%. This is true of all resistors internal to the ADS7831. Each resistive divider is trimmed so that the proper division is achieved. NOTE: (1) Full scale error includes offset and gain errors measured at both +FS and –FS. SYMBOL t1 t2 t3 t4 DESCRIPTION Convert Pulse Width Data Valid Delay After Start of Conversion BUSY Delay From Start of Conversion BUSY LOW BUSY Delay After End of Conversion Aperture Delay Conversion Time Acquisition Time Throughput Time Bus Relinquish Time BUSY Delay After Data Valid R/C to CS Setup Time Time Between Conversions Bus Access Time MIN 40 TYP MAX UNITS ns 1310 75 1300 90 20 1285 200 1485 10 20 10 1660 10 30 55 65 1460 125 1440 ns ns ns ns ns ANALOG INPUT The ADS7831 has a ±2.5V input range. Figures 4a and 4b show the necessary circuit connections for the ADS7831 with and without external trim. Offset and full scale error(1) specifications are tested and guaranteed with the 50Ω resistor shown in Figure 4b. This external resistor makes it possible to trim the offset ±12mV using R1 and P1 as shown in Figure 4a. This resistor may be left out if the offset and gain errors will be corrected in software or if they are negligible in regards to the particular application. See the Calibration section of the data sheet for details. t5 t6 t7 t8 t7 & t8 t9 t10 t11 t12 t13 1400 250 1650 83 100 ns ns ns ns ns ns ns 62 ns TABLE III. Timing Specifications (TMIN to TMAX). ® ADS7831 8 CALIBRATION The ADS7831 can be trimmed in hardware or software. The offset should be trimmed before the gain since the offset directly affects the gain. Hardware Calibration To calibrate the offset and gain of the ADS7831, install the proper resistors and potentiometers as shown in Figure 4a. The calibration range is ±12mV for the offset and ±30mV for full scale. Potentiometer P1 and resistor R1 form the offset adjust circuit and P2 and R2 the gain adjust circuit. The exact values are not critical. R1 and R2 should not be made any larger than the value shown. They can easily be made smaller to provide increased adjustment range. Reducing these below 15% of the indicated values could begin to adversely affect the operation of the converter. P1 and P2 can also be made larger to reduce power dissipation. However, larger resistances will push the useful adjustment range to the edges of the potentiometer. P1 should probably not exceed 20kΩ and P2 100kΩ in order to maintain reasonable sensitivity. Software Calibration or No Calibration The ADS7831 does not require external resistors for its basic operation. However, the component is designed to be used with an external 50Ω resistor on the input, and the specifications apply to this condition. If this resistor is not used, the only specification that will be affected is total unadjusted error. With the 50Ω resistor, the nominal input voltage range is ±2.5V and the total unadjusted error is ±10LSBs guaranteed. Without the 50Ω resistor, the nominal input voltage range will be ±2.46V and the total unadjusted error is not guaranteed. While it will typically be much less, the total unadjusted error could be as high as ±20LSBs. t11 R/C t1 CS t11 t11 t11 t3 BUSY t4 t5 t6 MODE Acquire Convert t7 t2 DATA BUS Hi-Z State t13 Data Valid t9 HI Z State Acquire FIGURE 3. Using CS to Control Conversion and Read Timing. 50Ω VIN +5V P1 5kΩ –5V P2 5kΩ 0.1µF 10µF + AGND2 10µF + AGND2 NOTE: Use 1% metal film resistors. Trim offset at 0V first, then trim gain at 2.5V. VIN R1 20kΩ +5V R2 604kΩ REF VIN AGND1 50Ω VIN AGND1 REF CAP 0.1µF CAP FIGURE 4a. Circuit Diagram With External Hardware Trim. 9 FIGURE 4b. Circuit Diagram Without External Hardware Trim. ® ADS7831 REFERENCE REF REF (pin 3) is the output for the internal 2.5V reference. A 0.1µF capacitor should be connected as close to the REF pin as possible. The capacitor and the output resistance of REF create a low pass filter to band limit noise on the reference. Using a smaller value capacitor will introduce more noise to the reference degrading the SNR and SINAD. The REF pin should not be used to drive external AC or DC loads. CAP CAP (pin 4) is the output of the internal reference buffer. A 10µF capacitor should be placed as close to the CAP as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and compensation for the output of the buffer. Using a capacitor any smaller than 2.2µF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 10µF will have little effect on improving performance. The voltage on the CAP pin is approximately 2V when using the internal reference, or 80% of an externally supplied reference. GROUNDING Three ground pins are present on the ADS7831. DGND (pin 22) is the digital supply ground. AGND2 (pin 5) is the analog supply ground. AGND1 (pin 2) is the ground which all analog signals internal to the A/D are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. All the ground pins of the ADS should be tied to the analog ground plane, separated from the system’s digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the “system” ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. SIGNAL CONDITIONING The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The FET switch on the ADS7831, compared to FET switches on other CMOS A/D converters, releases 5%—10% of the charge. There is also a resistive front end which attenuates any charge which is released. The end result is a minimal requirement for the op amp on the front end. Any op amp sufficient for the signal in an application will be sufficient to the drive the ADS7831. The resistive front end of the ADS7831 also provides a guaranteed ±25V over voltage protection. In most cases, this eliminates the need for external input protection circuitry. INTERMEDIATE LATCHES The ADS7831 does have tri-state outputs for the parallel port, but intermediate latches should be used if the bus will be active during conversions. If the bus is not active during conversions, the tri-state outputs can be used to isolate the A/D from other peripherals on the same bus. Intermediate latches are beneficial on any monolithic A/D converter. The ADS7831 has an internal LSB size of 610µV. Transients from fast switching signals on the parallel port, even when the A/D is tri-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. LAYOUT POWER The ADS7831 uses the majority of its power for analog and static circuitry and it should be considered as an analog component. For optimum performance, tie the analog and digital +5V power pins to the same +5V power supply and tie the analog and digital grounds together. For best performance, the ±5V supplies can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If ±12V or ±15V supplies are present, simple regulators can be used. The +5V power for the A/D should be separate from the +5V used for the system’s digital logic. Connecting VDIG (pin 27) directly to a digital supply can reduce converter performance due to switching noise from the digital logic. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied to the same +5V source. ® ADS7831 10