Not Recommended for New Designs
ADS8254
www.ti.com
SLAS643A – MARCH 2009 – REVISED JANUARY 2014
16-BIT, 1-MSPS, PSEUDO-BIPOLAR DIFFERENTIAL SAR ADC WITH ON-CHIP ADC
DRIVER (OPA) AND 4-CHANNEL DIFFERENTIAL MULTIPLEXER
Check for Samples: ADS8254
FEATURES
APPLICATIONS
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
1.0-MHz Sample Rate, Zero Latency at Full
Speed
16-Bit Resolution
Supports Pseudo-Bipolar Differential Input
Range: -4 V to +4 V with 2-V Common-Mode
Built-In Four Channel, Differential Ended
Multiplexer; with Channel Count Selection and
Auto/Manual Mode
On-Board Differential ADC Driver (OPA)
Buffered Reference Output to Level Shift
Bipolar ±4-V Input with External Resistance
Divider
Reference/2 Output to Set Common-Mode for
External Signal Conditioner
16-/8-Bit Parallel Interface
SNR: 95.4dB Typ at 2-kHz I/P
THD: –118dB Typ at 2-kHz I/P
Power Dissipation: 331.25 mW at 1 MSPS
Internal Reference
Internal Reference Buffer
64-Pin QFN Package
Medical Imaging/CT Scanners
Automated Test Equipment
High-Speed Data Acquisition Systems
High-Speed Closed-Loop Systems
DESCRIPTION
The ADS8254 is a high-performance analog systemon-chip (SoC) device with an 16-bit, 1-MSPS A/D
converter, 4-V internal reference, an on-chip ADC
driver (OPA), and a 4-channel differential multiplexer.
The channel count of the multiplexer and auto/manual
scan modes of the device are user selectable.
The ADC driver is designed to leverage the very high
noise performance of the differential ADC at optimum
power usage levels.
The ADS8254 outputs a buffered reference signal for
level shifting of a ±4-V bipolar signal with an external
resistance divider. A Vref/2 output signal is available
to set the common-mode of a signal conditioning
circuit. The device also includes an 16-/8-bit parallel
interface.
The ADS8254 is available in a 9 mm x 9 mm, 64-pin
QFN package and is characterized from -40°C to
85°C.
HIGH-SPEED SAR CONVERTER FAMILY
TYPE/SPEED
500 kHz
~600 kHz
ADS8383
ADS8381
750 kHz
1 MHz
1.25 MHz
2 MHz
3 MHz
4MHz
ADS8481
18-Bit Pseudo-Diff
ADS8380 (s)
ADS8382 (s)
ADS8284
ADS8484
18-Bit Pseudo-Bipolar, Fully Diff
ADS8482
ADS8327
16-Bit Pseudo-Diff
ADS8370 (s)
ADS8371
ADS8471
ADS8328
ADS8401
ADS8411
ADS8405
ADS8410 (s)
ADS8319
ADS8318
ADS8372 (s)
ADS8472
ADS8402
ADS8412
ADS8254
ADS8406
ADS8413 (s)
ADS8422
16-Bit Pseudo-Bipolar, Fully Diff
14-Bit Pseudo-Diff
12-Bit Pseudo-Diff
ADS7890 (s)
ADS7886
ADS7891
ADS7883
ADS7881
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2014, Texas Instruments Incorporated
Not Recommended for New Designs
ADS8254
SLAS643A – MARCH 2009 – REVISED JANUARY 2014
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AUTO, C1, C2, C3,
MXCLK
VCC
CH0P
VOLTAGE
CLAMP
-
CH1P
CH2P
VCC
VEE
+VA
AGND
+VA
OPA-1
CH3P
10Ω
+
+VBD
BGND
+VA
VEE
+VA
VCC
CH0M
CH1M
16 bit 1 MSPS
ADC
-
CH2M
DB0-DB15
LOGIC
I/O
BUFFER
OPA-2
CH3M
10Ω
+
BYTE
RD
CS
CONVST
VEE
BUSY
ADC REF
INP
INM
+VA
VCC
VCM-O
VREF/2
VCC
REFIN
BUF-REF
REFM
+VA
INTERNAL - REF
PD-RBUF
2
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REFOUT
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links :ADS8254
Not Recommended for New Designs
ADS8254
www.ti.com
SLAS643A – MARCH 2009 – REVISED JANUARY 2014
ORDERING INFORMATION (1)
MODEL
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
CODES AT
RESOLUTION
(BIT)
ADS8254lB
±0.75
±0.5
16
PACKAGE
TYPE
64-pin QFN
ADS8254l
(1)
±1.5
±0.5
PACKAGE
DESIGNATOR
RGC
16
TRANSPORT
MEDIA
QUANTITY
TEMPERATURE
RANGE
ORDERING
INFORMATION
ADS8254IBRGCT
250
–40°C to
85°C
ADS8254IBRGCR
2000
ADS8254IRGCT
250
ADS8254IRGCR
2000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, refer to the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VEE–0.3 to VCC + 0.3
V
VCC to VEE
-0.3 to 18
V
+VA to AGND
–0.3 to 7
V
+VBD to BDGND
–0.3 to 7
V
ADC control digital input voltage to GND
–0.3 to (+VBD + 0.3)
V
ADC control digital output to GND
–0.3 to (+VBD + 0.3)
V
–0.3 to (+VA + 0.3)
V
CH(i) to AGND (both P and M inputs)
Multiplexer control digital input voltage to GND
Power control digital input voltage to GND
–0.3 to (+VCC + 0.3)
V
Operating temperature range
–40 to 85
°C
Storage temperature range
–65 to 150
°C
150
°C
Junction temperature (TJmax)
QFN package
Lead temperature, soldering
(1)
(TJ Max–TA)/ θJA
Power dissipation
θJA Thermal impedance
86
°C/W
Vapor phase (60 sec)
215
°C
Infrared (15 sec)
220
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SPECIFICATIONS
TA = –40°C to 85°C, VCC = 5 V, VEE =–5 V, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 4 V, fSAMPLE = 1 MSPS (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage at multiplexer input (1)
CH(i)P–CH(i)M
–Vref
Vref
V
Absolute input range at multiplexer input
CH (i)
–0.2
Vref + 0.2
V
(Vref)/2
+ 0.2
V
[CH(i)P + CH(i)M] /2
Input common-mode voltage
(Vref)/2
– 0.2
(Vref)/2
SYSTEM PERFORMANCE
Resolution
16
No missing codes
Integral linearity
(2)
Differential linearity
Offset error (4)
Gain error (4)
ADS8254IB
16
ADS8254I
16
ADS8254IB
Bits
Bits
–0.75
±0.4
0.75
–1.5
±0.4
1.5
–0.5
±0.32
0.5
–0.5
±0.32
0.5
ADS8254IB
–0.5
±0.05
0.5
ADS8254I
–0.5
±0.05
0.5
–0.1
±0.025
0.1
–0.1
±0.025
0.1
ADS8254I
ADS8254IB
ADS8254I
ADS8254IB
ADS8254I
DC Power supply rejection ratio
At 18-bit level
External reference
At 3FFF0H output code. For +VA or VCC, VEE
variation of 0.5V individually
80
LSB
(3)
LSB (3)
mV
%FS
dB
SAMPLING DYNAMICS
Conversion time
Acquisition time
+VBD = 5 V
625
650
ns
+VDB = 3 V
625
650
ns
+VBD = 5 V
320
350
+VDB = 3 V
320
350
Maximum throughput rate
ns
1.0
MHz
Aperture delay
4
ns
Aperture jitter
5
ps
For ADC only
150
ns
For OPA (OP1, OP2)+ Mux
700
For ADC only
150
Settling time to 0.5 LSB
Over voltage recovery
ns
DYNAMIC CHARACTERISTICS
ADS8254I
ADS8254IB
Total harmonic distortion
(THD) (4)
ADS8254I
ADS8254IB
ADS8254I
ADS8254IB
ADS8254I
ADS8254IB
Signal to noise ratio (SNR)
ADS8254I
ADS8254IB
ADS8254I
ADS8254IB
(1)
(2)
(3)
(4)
4
–118
VIN = 4 Vpp at 2 kHz
–118
–105
VIN = 4 Vpp at 10 kHz
–105
–100
VIN = 4 Vpp at 100 kHz,
LoPWR = 0
VIN = 4 Vpp at 2 kHz
VIN = 4 Vpp at 10 kHz
VIN = 4 Vpp at 100 kHz,
LoPWR = 0
–100
95.4
94
95.4
95
95
93
94.5
dB
dB
dB
dB
dB
dB
Ideal input span, does not include gain or offset error.
Measured relative to acutal measured referenceThis is endpoint INL, not best fit.
LSB means least significant bit
Calculated on the first nine harmonics of the input frequency.
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SLAS643A – MARCH 2009 – REVISED JANUARY 2014
SPECIFICATIONS (continued)
TA = –40°C to 85°C, VCC = 5 V, VEE =–5 V, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 4 V, fSAMPLE = 1 MSPS (unless otherwise
noted)
PARAMETER
ADS8254I
ADS8254IB
Signal to noise + distortion
(SINAD)
ADS8254I
ADS8254IB
ADS8254I
ADS8254IB
ADS8254I
ADS8254IB
ADS8254I
Spurious free dynamic
range (SFDR)
ADS8254IB
ADS8254I
ADS8254IB
TEST CONDITIONS
MIN
TYP
MAX
UNIT
95.2
VIN = 4 Vpp at 2 kHz
dB
95.2
94.5
VIN = 4 Vpp at 10 kHz
dB
94.5
92.2
VIN = 4 Vpp at 100 kHz,
LoPWR = 0
dB
93.4
120
VIN = 4 Vpp at 2 kHz
dB
120
106
VIN = 4 Vpp at 10 kHz
dB
106
101
VIN = 4 Vpp at 100 kHz,
LoPWR = 0
dB
101
–3dB Small signal bandwidth
8
MHz
VOLTAGE REFERENCE INPUT (REFIN)
Reference voltage at REFIN, Vref
Reference input current
3.0
(5)
4.096
+VA – 0.8
V
1
1
μA
120
ms
4.096
4.111
V
10
μA
INTERNAL REFERENCE OUTPUT (REFOUT)
Internal reference start-up time
From 95% (+VA), with 1-μF storage capacitor
Reference voltage range, Vref
4.081
Source current
Static load
Line regulation
+VA = 4.75 V ~ 5.25 V
60
μV
Drift
IO = 0
±6
PPM/°C
REFIN = 4V, at 85°C
70
mA
BUFFERED REFERENCE OUTPUT (BUF-REF)
Output current
REFERENCE/2 OUTPUT (VCMO)
Reference/2 Voltage Range
At No Load on VCMO
Output current
REFIN = 4V, at +85°C
1.938
2.048
2.158
V
μA
50
ANALOG MULTIPLEXER
Number of channels
8
Channel to channel crosstalk
100 kHz i/p
Channel selection
Auto sequencer with selection of channel count OR
Manual selection through control lines
–95
dB
DIGITAL INPUT-OUTPUT
ADC CONTROL PINS
Logic Family-CMOS
Logic level
VIH
IIH = 5 μA
VIL
IIL = 5 μA
VOH
IOH = 2 TTL loads
VOL
IOL = 2 TTL loads
+V BD–1
+VBD + 0.3
V
0.3
0.8
V
+VBD–6
+VBD
V
0
0.4
V
MULTIPLEXER CONTROL PINS
Logic Family - CMOS
Logic Level
IIH
IIH = 5 μA
2.3
+VA +0.3
V
IIL
IIL = 5 μA
–0.3
0.8
V
VIH
IIH = 5 μA
2.3
+VA +0.3
V
VIL
IIL = 5 μA
–0.3
0.8
V
POWER CONTROL PINS
Logic Family - CMOS
Logic Level
(5)
Can vary ±20%
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SPECIFICATIONS (continued)
TA = –40°C to 85°C, VCC = 5 V, VEE =–5 V, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 4 V, fSAMPLE = 1 MSPS (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY REQUIREMENTS
+VBD
Power supply voltage
2.7
3.3
5.25
V
+VA
4.75
5
5.25
V
VCC
4.75
5
7.5
V
VEE
–7.5
–5
–3
V
ADC driver positive supply (VCC) current (for OP1 and
OP2 together)
VCC = +5, VEE = -5V, CH0 - CH3 p and m inputs
shorted to each other and connected to 2V
ADC driver negative supply (VEE) current (for OP1 and
OP2 together)
VCC = +5, CH0 - CH3 p and m inputs shorted to
each other and connected to 2V
11.65
9.6
+VA Supply Current, 1MHz Sample Rate
Reference buffer (BUF-REF) supply current (VCC to
GND)
mA
45
VCC= +5, PD-RBUF = 0, Quiescent current
VCC = 5, PD-RBUF = 1 (6)
mA
50
mA
8
mA
10
μA
TEMPERATURE RANGE
Operating free air
(6)
6
–40
85
°C
PD-RBUF=1 powers down the Reference buffer (BUF-REF), note that it does not 3-state the BUF-REF output.
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ADS8254
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SLAS643A – MARCH 2009 – REVISED JANUARY 2014
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA =+VBD = 5 V
(1) (2) (3)
PARAMETER
MIN
TYP
MAX
UNIT
650
ns
t(CONV)
Conversion time
t(ACQ)
Acquisition time
t(HOLD)
Sample capacitor hold time
25
ns
tpd1
CONVST low to BUSY high
40
ns
tpd2
Propagation delay time, end of conversion to BUSY low
15
ns
tpd3
Propagation delay time, start of convert state to rising edge of BUSY
15
ns
tw1
Pulse duration, CONVST low
40
ns
tsu1
Setup time, CS low to CONVST low
20
ns
tw2
Pulse duration, CONVST high
20
320
CONVST falling edge jitter
ns
ns
10
t(ACQ)min
ps
tw3
Pulse duration, BUSY signal low
tw4
Pulse duration, BUSY signal high
th1
Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or
BUS18/16 input changes) after CONVST low
td1
tsu2
tw5
Pulse duration, RD low
ten
Enable time, RD low (or CS low for read cycle) to data valid
td2
Delay time, data hold from RD high
td3
Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid
10
tw6
Pulse duration, RD high
20
ns
tw7
Pulse duration, CS high
20
ns
th2
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge
50
ns
tpd4
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
edge
0
ns
td4
Delay time, BYTE edge to BUS18/16 edge skew
0
ns
tsu3
Setup time, BYTE or BUS18/16 transition to RD falling edge
10
ns
th3
Hold time, BYTE or BUS18/16 transition to RD falling edge
10
tdis
Disable time, RD high (CS high for read cycle) to 3-stated data bus
td5
Delay time, BUSY low to MSB data valid delay
td6
Delay time, CS rising edge to BUSY falling edge
50
ns
td7
Delay time, BUSY falling edge to CS rising edge
50
ns
tsu5
BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16
transition setup time, from BUS18/16 to next BUS18/16.
50
ns
ns
40
ns
Delay time, CS low to RD low
0
ns
Setup time, RD high to CS high
0
ns
50
ns
20
5
tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the
next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the
next falling edge of CS (when CS is used to abort).
(1)
(2)
(3)
ns
650
60
ns
ns
20
ns
ns
20
ns
0
ns
550
ns
All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
See timing diagrams.
All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins.
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TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = 5 V +VBD = 3 V
(1) (2) (3)
PARAMETER
MIN
TYP
MAX
UNIT
650
ns
t(CONV)
Conversion time
t(ACQ)
Acquisition time
t(HOLD)
Sample capacitor hold time
25
ns
tpd1
CONVST low to BUSY high
40
ns
tpd2
Propagation delay time, end of conversion to BUSY low
25
ns
tpd3
Propagation delay time, start of convert state to rising edge of BUSY
25
ns
tw1
Pulse duration, CONVST low
40
ns
tsu1
Setup time, CS low to CONVST low
20
ns
tw2
Pulse duration, CONVST high
20
310
ns
ns
CONVST falling edge jitter
10
t(ACQ)min
ps
tw3
Pulse duration, BUSY signal low
tw4
Pulse duration, BUSY signal high
th1
Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or
BUS18/16 input changes) after CONVST low
td1
tsu2
tw5
Pulse duration, RD low
ten
Enable time, RD low (or CS low for read cycle) to data valid
td2
Delay time, data hold from RD high
td3
Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid
10
tw6
Pulse duration, RD high
20
ns
tw7
Pulse duration, CS high
20
ns
th2
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge
50
ns
tpd4
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
edge
0
ns
td4
Delay time, BYTE edge to BUS18/16 edge skew
0
ns
tsu3
Setup time, BYTE or BUS18/16 transition to RD falling edge
10
ns
th3
Hold time, BYTE or BUS18/16 transition to RD falling edge
10
tdis
Disable time, RD high (CS high for read cycle) to 3-stated data bus
td5
Delay time, BUSY low to MSB data valid delay
td6
Delay time, CS rising edge to BUSY falling edge
50
ns
td7
Delay time, BUSY falling edge to CS rising edge
50
ns
tsu5
BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16
transition setup time, from BUS18/16 to next BUS18/16.
50
ns
ns
40
ns
Delay time, CS low to RD low
0
ns
Setup time, RD high to CS high
0
ns
50
ns
30
5
tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the
next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the
next falling edge of CS (when CS is used to abort).
(1)
(2)
(3)
ns
650
ns
ns
30
ns
ns
70
30
ns
0
ns
550
ns
MAX
UNIT
600
ns
All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
See timing diagrams.
All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins.
MULTIPLEXER TIMING REQUIREMENTS
VCC = 4.75 V to 7.5 V, VEE = -3 V to -7.5 V
MIN
tsu6
Setup time C1, C2 or C3 to MXCLK rising edge
td8
Multiplexer and driver settle time ( from MXCLK rising edge to CONVST falling edge)
8
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600
TYP
ns
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SLAS643A – MARCH 2009 – REVISED JANUARY 2014
PIN ASSIGNMENTS
NC
BUF-REF
VCMO
+VA
AGND
REFOUT
REFIN
REFM
REFM
+VA
AGND
+VA
CS
RD
CONVST
BYTE
QFN PACKAGE
(TOP VIEW)
16 15 14 13 12 11 10 9 8
17
7 6
5 4 3
2
1
64
18
63
19
62
20
61
21
60
22
59
NC
+VBD
BUSY
NC
NC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
BGND
+VBD
DB8
58
23
ADS8254
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
AUTO
C3
C2
C1
MXCLK
+VA
AGND
+VA
AGND
DB15
DB14
DB13
DB12
DB11
DB10
DB9
CH0P
CH0M
CH1P
CH1M
PD-RBUF
VEE
VCC
VCC
INP
AGND
INM
NC
CH2P
CH2M
CH3P
CH3M
PIN FUNCTIONS
PIN
NO
NAME
I/O
DESCRIPTION
MULTIPLEXER INPUT PINS
17
CH0P
I
Non-inverting analog input for differential multiplexer channel number 0. Device performance is optimized for 50 ohm source
impedance at this input.
18
CH0M
I
Inverting analog input for differential multiplexer channel number 0. Device performance is optimized for 50 ohm source
impedance at this input.
19
CH1P
I
Non-inverting analog input for differential multiplexer channel number 1. Device performance is optimized for 50 ohm source
impedance at this input.
20
CH1M
I
Inverting analog input for differential multiplexer channel number 1. Device performance is optimized for 50 ohm source
impedance at this input.
29
CH2P
I
Non-inverting analog input for differential multiplexer channel number 2. Device performance is optimized for 50 ohm source
impedance at this input.
30
CH2M
I
Inverting analog input for differential multiplexer channel number 2. Device performance is optimized for 50 ohm source
impedance at this input.
31
CH3P
I
Non-inverting analog input for differential multiplexer channel number 3. Device performance is optimized for 50 ohm source
impedance at this input.
32
CH3M
I
Inverting analog input for differential multiplexer channel number 3. Device performance is optimized for 50 ohm source
impedance at this input.
ADC INPUT PINS
25
INP
I
ADC Non inverting input., connect 1nF cap across INP and INM
27
INM
I
ADC Inverting input, connect 1nF cap across INP and INM
REFERENCE INPUT/ OUTPUT PINS
8, 9
REFM
I
Reference ground.
10
REFIN
I
Reference Input. Add 0.1-μF decoupling capacitor between REFIN and REFM.
11
REFOUT
O
Reference Output. Add 1-μF capacitor between the REFOUT pin and REFM pin when internal reference is used.
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PIN FUNCTIONS (continued)
PIN
I/O
DESCRIPTION
NO
NAME
14
VCMO
O
This pin outputs Refin/2 and can be used to set common-mode voltage of differential analog inputs.
15
BUFREF
O
Buffered reference output. Useful to level shift bipolar signals using external resistors.
I
High on this pin powers down the reference buffer (BUF-REF).
POWER CONTROL PINS
PDRBUF
21
MULTIPLEXER CONTROL PINS
33
AUTO
I
High level on this pin selects ‘Auto’ mode for multiplexer scanning. Low level selects manual mode of multiplexer scanning
34
C3
I
In auto mode (AUTO=1) multiplexer channel selection is reset to CH0 on rising edge of MXCLK while C3=1. The pin is 'do
not care' in manual mode.
35
C2
I
Acts as multiplexer address bit when AUTO=0 (Manual mode). In auto mode (AUTO=1) C2 and C1 select the last
multiplexer channel (channel count) in the auto scan sequence.
36
C1
I
Acts as multiplexer address LSB when AUTO=0 (Manual mode). In auto mode (AUTO=1) C2 and C1 select the last
multiplexer channel (channel count) in the auto scan sequence.
37
MXCLK
I
Multiplexer channel is selected on rising edge of MXCLK irrespective of whether it is auto or manual mode. Device BUSY
output can be connected to MXCLK so that device selects next channel at the end of every sample.
ADC DATA BUS
8-BIT BUS
16-BIT BUS
42-49, 52-59
Data Bus
42
DB15
O
D15 (MSB)
D7
D15(MSB)
43
DB14
O
D14
D6
D14
44
DB13
O
D13
D5
D13
45
DB12
O
D12
D4
D12
46
DB11
O
D11
D3
D11
47
DB10
O
D10
D2
D10
48
DB9
O
D9
D1
D9
49
DB8
O
D8
D0
D8
52
DB7
O
D7
All ones
D7
53
DB6
O
D6
All ones
D6
54
DB5
O
D5
All ones
D5
55
DB4
O
D4
All ones
D4
56
DB3
O
D3
All ones
D3
57
DB2
O
D2
All ones
D2
58
DB1
O
D1
All ones
D1
59
DB0
O
D0 (LSB)
All ones
D0 (LSB)
BYTE = 0
BYTE = 1
BYTE = 0
ADC CONTROL PINS
62
BUSY
O
Status output. This pin is held high when device is converting.
1
BYTE
I
Byte Select Input. Used for 8-bit bus reading. Refer to the ADC DATA BUS description above.
2
CONVST
I
Convert start. This input is active low and can act independent of the CS\ input.
3
RD
I
Synchronization pulse for the parallel output.
4
CS
I
Chip Select.
DEVICE POWER SUPPLIES
22
VEE
Negative supply for OPA (OP1, OP2)
23, 24
VCC
Positive supply for OPA (OP1, OP2, BUF-REF)
5, 7, 13, 38,
40
+VA
Analog power supply.
6, 12, 26, 39,
41
AGND
Analog ground.
50, 63
+VBD
Digital Power Supply For ADC Bus.
51
BGND
Digital ground for ADC bus interface digital supply.
NOT CONNECTED PINS
16, 28, 60,
61, 64
10
NC
No connection.
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DEVICE OPERATION AND TIMING DIAGRAMS
The ADS8254 is analog system-on-chip (SoC) device. The device includes a multiplexer, a single-ended
input/differential output ADC driver and differential input high-performance ADC, an additional internal reference,
a buffered reference output, and a REF/2 output.
Figure 1 shows the basic operation of the device (including all elements). Subsequent sections describe the
detailed timings of the individual blocks of the device (primarily the multiplexer and ADC).
m-1
m
m+1
m+2
CONVST
BUSY
SELECTED
CHANNEL
Ch (n-1)
Ch (n)
Ch (n+1)
Ch (n+2)
Ch (n+3)
INP
Vref V
ADC differential
input assuming
alternate channels
have+Vref & -Vref
differential input
SAMPLE,
(Vinp- Vinm)
0V
INM
S(m-1)
-Vref
DB15 - DB0
Parallel o/ p bus
Ch (n-2)
S(m)
+Vref
Ch (n-1)
S(m+1)
-Vref
Ch (n)
S(m+2)
+Vref
Ch (n+1)
Figure 1. Device Operation
As shown in the diagram, the device can be controlled with only one (CONVST) digital input. On the falling edge
of CONVST, the BUSY output of the device goes high. A high level on BUSY indicates the device has sampled
the signal and it is converting the sample into its digital equivalent. After the conversion is complete, the BUSY
output falls to a logic low level and the device output data corresponding to the recently converted sample is
available for reading.
It is recommended (not mandatory) to short the BUSY output of the device to the MXCLK input. The device
selects a new channel at every rising edge of MXCLK. The multiplexer is differential. The multiplexer and ADC
driver are designed to settle to the 18-bit level before sampling; even at the maximum conversion speed.
ADC Control and Timing: The timing diagrams in the this section describe ADC operation; multiplexer operation
is described in a the following sections.
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tw2
tw1
CONVST
tpd1
tpd2
tw4
tw3
BUSY
tsu1
tw7
CS
tpd3
CONVERT†
t(HOLD)
t(CONV)
t(CONV)
SAMPLING†
(When CS Toggle)
t(ACQ)
BYTE
tsu(ABORT)
tsu(ABORT)
tsu5
th1
tsu5
tsu5
tsu5
tsu2
tpd4
th2
td1
RD
tdis
ten
DB[15:8]
Hi−Z
Hi−Z
D[15:8]
DB[7:0]
D[7:0]
Hi−Z
Hi−Z
D[7:0]
†Signal
internal to device
Figure 2. Timing for Conversion and Acquisition Cycles With CS and RD Toggling
12
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tw1
tw2
CONVST
tpd1
tw4
tpd2
tw3
BUSY
tw7
tsu6
CS
tpd3
CONVERT†
t(CONV)
t(CONV)
t(HOLD)
SAMPLING†
(When CS Toggle)
t(ACQ)
tsu(ABORT)
tsu(ABORT)
tsu5
BYTE
tsu5
th1
tsu5
tsu5
tdis
tsu2
tpd4
th2
ten
RD = 0
ten
ten
DB[15:8]
Hi−Z
Previous
D [15:8]
tdis
Hi−Z
D[15:8]
DB[7:0]
Hi−Z
Previous
D [7:0]
Hi−Z
Hi−Z
Previous
D [15:8]
Hi−Z
Previous
D [7:0]
D[7:0]
D[7:0]
†Signal
internal to device
Figure 3. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND
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tw1
tw2
CONVST
tpd1
tpd2
tw4
tw3
BUSY
CS = 0
tpd3
CONVERT†
t(CONV)
t(CONV)
t(HOLD)
t(ACQ)
SAMPLING†
(When CS = 0)
tsu(ABORT)
tsu(ABORT)
tsu5
BYTE
tsu5
th1
tpd4
th2
RD
tdis
ten
DB[15:8]
Hi−Z
Hi−Z
D[15:8]
DB[7:0]
Hi−Z
D[7:0]
Hi−Z
D[7:0]
†Signal
internal to device
Figure 4. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
14
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tw2
tw1
CONVST
tpd1
tw4
tpd2
tw3
BUSY
CS = 0
CONVERT†
t(CONV)
t(CONV)
tpd3
tpd3
t(HOLD)
t(HOLD)
t(ACQ)
SAMPLING†
(When CS = 0)
tsu(ABORT)
tsu(ABORT)
BYTE
tsu5
tsu5
th1
th1
tdis
tsu5
tsu5
RD = 0
td5
DB[15:8]
D[7:0]
Previous D[7:0]
Next D[15:8]
D[15:8]
DB[7:0]
Next D[7:0]
D[7:0]
†Signal
internal to device
Figure 5. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND - Auto Read
CS
RD
tsu4
BYTE
ten
tdis
tdis
ten
DB[15:0]
td3
Hi−Z
Hi−Z
Valid
Valid
Valid
Hi−Z
Figure 6. Detailed Timing for Read Cycles
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Multiplexer: The multiplexer has two modes of sequencing namely auto sequencing and manual sequencing.
Multiplexer mode selection and operation is controlled with the AUTO, C1, C2, C3, and MXCLK pins.
Auto Sequencing: A logic one level on the AUTO pin selects auto sequencing mode. It is possible to select the
number of channels to be scanned (always starting from channel zero) in auto sequencing mode. Pins C1 and
C2 select the channel count (last channel in the auto sequence).
On every rising edge of MXCLK while C3 is at the logic zero level, the next higher channel (in ascending order)
is selected. Channel selection rolls over to channel zero on the rising edge of MXCLK after channel selection
reaches the channel count (last channel in the auto sequence selected by pins C1and C2).
Any time during the sequence the channel sequence can be reset to channel zero. A rising edge on MXCLK
while C3 is at the logic one level resets channel selection to channel zero.
Table 1. Channel Selection in Auto Mode
CHANNEL COUNT PINS
CLOCK PIN
LAST CHANNEL IN SEQUENCE
CHANNEL SEQUENCE
C3
C2
C1
MXCLK
0
0
0
↑
0
0,0,0,0..
0
0
1
↑
1
0,1,0,1,..
0
1
0
↑
2
0,1,2,0,1,2,0…
0
1
1
↑
3
0,1,2,3,0,1,2,3,0…
1
X
X
↑
X
n → 0 (channel reset to zero)
MXCLK
C3
tsu6
C2
C1
Selected
Channel
Ch 0
Ch 1
Ch 0
Ch 1
Ch 0
Ch 0
Ch 1
Ch 2
AUTO = 1, device operation in auto mode
Figure 7. Multiplexer Auto Mode Timing Diagram
Manual Sequencing: A logic zero level on the AUTO pin selects manual sequencing mode. Pins C1and C2 set
the channel address. On the rising edge of MXCLK, the addressed channel is connected to the ADC driver input.
Table 2. Channel Selection in Manual Mode
MODE
16
CHANNEL ADDRESS PINS
CLOCK PIN
CHANNEL
AUTO
C3
C2
C1
MXCLK
0
X
0
0
↑
0
0
X
0
1
↑
1
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Table 2. Channel Selection in Manual Mode (continued)
MODE
CHANNEL ADDRESS PINS
CLOCK PIN
CHANNEL
AUTO
C3
C2
C1
MXCLK
0
X
1
0
↑
2
0
X
1
1
↑
3
MXCLK
C2
C1
Selected
Channel
tsu6
Ch 0
Ch 3
Ch 1
Ch 2
Ch 0
Ch 1
Ch 3
Ch 2
AUTO = 0, device operation in manual mode
Figure 8. Multiplexer Manual Mode Timing Diagram
TYPICAL CHARACTERISTICS
DC HISTOGRAM
(without switching)
INTERNAL REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
DC HISTOGRAM
(CH0 with mux switching CH0-1-0)
10000
70000
61431
4.098
9368
+VA = 5 V,
+VBD = 5 V
9000
60000
4.0975
Vref = 4.096 V,
VCC = 6 V,
VEE = -6 V,
+VA = 5 V,
TA = 25°C,
40000
30000
Throughput =
1 MSPS
20000
7000
4000
Vref = 4.096 V,
VCC = 6 V,
VEE = -6 V,
+VA = 5 V,
TA = 25°C,
3000
Throughput =
1 MSPS
6000
5000
2000
1000
360
0
32760
32761
32762
0
4.097
4.0965
4.096
4.0955
10000
3745
Reference Voltage - V
8000
50000
576
56
32757
32758
32759
4.095
-40
-25 -10
5
20
35
50
65
80
TA - Free-Air Temperature - °C
Figure 9.
Figure 10.
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
ANALOG VOLTAGE (+VA) SUPPLY
CURRENT (IA)
vs
FREE-AIR TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs
SUPPLY VOLTAGE
44
44
4.0972
+VA = 5 V,
Throughput = 1 MSPS
43.75
4.09718
43.5
4.09717
4.09716
4.09715
43.25
43
42.75
4.09714
42.5
4.09713
4.75
4.85
4.95
5.05
5.15
Supply Voltage - V
5.25
43
42.75
42.5
-40
-20
0
20 40
60 80
TA - Free-Air Temperature - °C
42
4.7
100
4.8
4.9
5
5.1
5.2
+VA - Analog Voltage - V
5.3
5.4
Figure 13.
Figure 14.
ANALOG SUPPLY CURRENT
vs
SAMPLE RATE
OPA POSITIVE SUPPLY CURRENT
(ICC)
vs
FREE-AIR TEMPERATURE
OPA POSITIVE SUPPLY CURRENT
(ICC)
vs
OPA POSITIVE SUPPLY VOLTAGE
(+VCC)
14
+VA = 5 V,
+VBD = 5 V,
TA = 25°C,
12
VCC = 6 V,
11.9
13.5 VEE = -6 V
11.8
ICC - Supply Current - mA
ICC - supply Current - mA
13
Vref = 4.096 V
44
12.5
43
42
41
12
11.5
11
10.5
10
750
500
Sample Rate - KSPS
9
-60 -40
1000
11.7
11.6
11.5
11.4
11.3
VEE = -6 V,
TA = 25°C
11.2
11.1
9.5
39
250
-20
0
20
40
60
80
11
4
100
5
6
7
VCC - Supply Voltage - V
TA - Free-Air Temperature - °C
8
Figure 15.
Figure 16.
Figure 17.
OPA -VE SUPPLY CURRENT (IEE)
vs
FREE-AIR TEMPERATURE
OPA NEGATIVE SUPPLY CURRENT
(IEE)
vs
OPA NEGATIVE SUPPLY (-VEE)
DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
9.65
11
VCC = 6 V,
VEE = -6 V
0.65
DNL - Differential Nonlinearity - LSB
VCC = 6 V,
TA = 25°C
10.5
9.6
IEE - Supply Current - mA
IEE - Supply Current - mA
43.25
Figure 12.
40
10
9.5
9
8.5
8
-60 -40
-20
0
20
40
60
80
100
TA - Free-Air Temperature - °C
Figure 18.
18
43.5
42.25
42.25
-60
46
45
TA = 25°C,
Throughput = 1 MSPS
43.75
IA - Supply Current - mA
4.09719
Supply Current - mA
Reference Voltage - V
TA = 25°C
Supply Current - mA
SUPPLY CURRENT (IA)
vs
ANALOG VOLTAGE (+VA)
9.55
9.5
9.45
9.4
-8
0.45
0.25
0.05
-0.15
-0.35
-0.55
Channel 0 = 0 V, Vref = 4.096 V,
VCC = 6 V, VEE = -6 V,
+VA = 5 V, Throughput = 1 MSPS
-0.75
-7
-6
-5
-4
-3
VEE - Supply Voltage - V
Figure 19.
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-60 -40
-20
0
20
40
60
80
100
TA - Free-Air Temperature - °C
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL NONLINEARITY
vs
ANALOG SUPPLY VOLTAGE (+VA)
DIFFERENTIAL NONLINEARITY
vs
REFERENCE VOLTAGE
0.65
0.45
0.25
0.05
-0.15
-0.35
Channel 0 = 0 V, Vref = 4.096 V,
-0.55
VCC = 6 V, TA = 25°C,
Throughput = 1 MSPS
-0.75
4.6
0.45
0.25
0.05
-0.15
-0.35
Channel 0 = 0 V, +VA = 5 V,
VCC = 6 V, TA = 25°C,
-0.55
Throughput = 1 MSPS
-0.75
4.7 4.8 4.9
5
5.1 5.2 5.3
+VA - Analog Supply Voltage - V
3
5.4
3.4
3.6
3.8
4
4.2
VREF - Voltage Reference - V
-0.35
-0.55
4
4.5
5
5.5
6
6.5
7
VCC - Supply Voltage - V
7.5
8
INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
INTEGRAL NONLINEARITY
vs
ANALOG SUPPLY VOLTAGE (+VA)
0.65
Vref = 4.096 V, VCC = 6 V, +VA = 5 V,
VEE = -6V, TA = 25°C,
0.45
0.25
0.05
-0.15
-0.35
Channel 0, Vref = 4.096 V, VCC = 6 V,
-0.55
+VA = 5 V, VEE = -6 V,
Throughput = 1 MSPS
Throughput = 1 MSPS
0
1
2
INL - Integral Nonlinearity - LSB
INL - Integral Nonlinearity - LSB
-0.15
-0.75
3
0.45
0.25
0.05
-0.15
-0.35
-0.55
-0.75
4.7
Channel 0, Vref = 4.096 V, VCC = 6 V,
VEE = -6V, TA = 25°C,
Throughput = 1 MSPS
TA - Free-Air Temperature - °C
4.8
4.9
5
5.1 5.2
5.3
+VA - Analog Voltage Supply - V
Figure 24.
Figure 25.
Figure 26.
INTEGRAL NONLINEARITY
vs
REFERENCE VOLTAGE
INTEGRAL NONLINEARITY
vs
OPA SUPPLY VOLTAGE (+VCC)
INTEGRAL NONLINEARITY
vs
MULTIPLEXER CHANNELS
-60 -40
Channnels
0.65
-20
0
20
40
60
80
100
0.45
0.25
Channel 0, VCC = 6 V, VEE = -6V,
TA = 25°C, +VA = 5 V,
Throughput = 1 MSPS
-0.35
-0.55
0.45
0.25
Channel 0, Vref = 4.096 V,
0.05
-0.15
5.4
0.65
INL - Integral Nonlinearity - LSB
INL - Integral Nonlinearity - LSB
0.65
-0.15
Throughput = 1 MSPS,
VCC = -VEE except
VCC = 4.7 V where VEE = -2.5 V
-0.15
DIFFERENTIAL NONLINEARITY
vs
MULTIPLEXER CHANNELS
0.05
0.05
+VA = 5 V, TA = 25°C,
Figure 23.
0.25
-0.55
Channel 0 = 0 V, Vref = 4.096 V,
0.05
-0.75
4.4
0.65
-0.35
0.25
Figure 22.
0.45
-0.75
3.2
0.45
Figure 21.
0.65
DNL - Differential Nonlinearity - LSB
0.65
DNL - Differential Nonlinearity - LSB
DNL - Differential Nonlinearity - LSB
DNL - Differential Nonlinearity - LSB
0.65
INL - Integral Nonlinearity - LSB
DIFFERENTIAL NONLINEARITY
vs
OPA SUPPLY VOLTAGE (VCC)
+VA = 5V, TA = 25°C,
Throughput = 1 MSPS,
VCC = -VEE except
VCC = 4.7 V where VEE = -2.5 V
-0.35
-0.55
0.45
0.25
0.05
-0.15
-0.35
Vref = 4.096 V, VCC = 6 V,
-0.55
VEE = -6V, +VA = 5 V, TA = 25°C,
Throughput = 1 MSPS
-0.75
3
3.2
3.4
3.6
3.8
4
4.2
VREF - Voltage Reference - V
4.4
Figure 27.
-0.75
4
4.5
5
5.5
6
6.5
7
VCC - Supply Voltage - V
7.5
Figure 28.
8
-0.75
0
1
2
Multiplexer Channels
Figure 29.
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TYPICAL CHARACTERISTICS (continued)
FULL CHIP OFFSET
vs
FREE-AIR TEMPERATURE
FULL CHIP OFFSET
vs
OPA SUPPLY VOLTAGE (VCC)
150
FULL CHIP OFFSET
vs
ANALOG SUPPLY VOLTAGE (+VA)
0
0
-25
-25
VEE = -6V, +VA = 5 V,
Throughput = 1 MSPS
Full Chip Offset - mV
Full Chip Offset - mV
100
50
0
-50
-50
-75
-150
-60 -40
Channel 0, Vref = 4.096 V,
-20
0
20
40
60
80
-150
4
100
TA - Free-Air Temperature - °C
-50
-75
-100
-100
Channel 0, Vref = 4.096 V, VCC = 6 V,
+VA = 5 V, TA = 25°C,
VCC = -VEE
Throughput = 1 MSPS
-125
-100
Full Chip Offset - mV
Channel 0, Vref = 4.096 V, VCC = 6 V,
4.5
5
5.5
6
6.5
7
VCC - Supply Voltage - V
VEE = -6 V, TA = 25°C,
-125
Throughput = 1 MSPS
7.5
-150
4.6
8
4.7 4.8 4.9 5.0 5.1 5.2 5.3
+VA - Analog Supply Voltage - V
Figure 30.
Figure 31.
Figure 32.
FULL CHIP OFFSET
vs
REFERENCE VOLTAGE
FULL CHIP OFFSET
vs
CHANNEL
FULL CHIP GAIN ERROR
vs
FREE-AIR TEMPERATURE
0
5.4
0
0
-15
-75
-150
3
-45
-60
-75
-90
-105
Channel 0, +VA = 5 V, VCC = 6 V,
VEE = -6V, TA = 25°C,
-120
Throughput = 1 MSPS
-135
3.2
3.4
3.6
3.8
4
4.2
VREF - Voltage Reference - V
-150
4.4
TA = 25°C,
VCC = 6 V,
VEE = -6 V,
Vref = 4.096 V,
+VA = 5 V,
Throughput = 1 MSPS
0
-0.015
-0.02
Channel 0, Vref = 4.096 V, VCC = 6 V,
VEE = -6V, +VA = 5 V,
Throughput = 1 MSPS
-0.03
3
-60 -40
-20
0
20
40
60
80
Figure 34.
Figure 35.
FULL CHIP GAIN ERROR
vs
OPA SUPPLY VOLTAGE (VCC)
FULL CHIP GAIN ERROR
vs
ANALOG SUPPLY VOLTAGE (+VA)
FULL CHIP GAIN ERROR
vs
REFERENCE VOLTAGE
-0.01
-0.01
Full Chip Gain Error - %FS
0
-0.02
-0.03
Channel 0, Vref = 4.096 V,
-0.04
-0.03
Throughput = 1 MSPS
5
5.5
6
6.5
7
VCC - Supply Voltage - V
Channel 0, Vref = 4.096 V, VCC = 6 V,
VEE = -6 V, TA = 25°C,
7.5
Figure 36.
8
-0.05
4.7
4.8
4.9
5.0 5.1
5.2
5.3
+VA - Analog Voltage Supply - V
Figure 37.
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0.04
Channel 0, VCC = 6 V,
VEE = -6 V, TA = 25°C,
0.03
Throughput = 1 MSPS
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
Throughput = 1 MSPS
-0.05
4.5
0.05
-0.02
-0.04
100
TA - Free-Air Temperature - °C
Figure 33.
+VA = 5 V, TA = 25°C,
20
2
Channels
0
4
1
-0.01
-0.025
Full Chip Gain Error - %FS
-125
Full Chip Gain Error - %FS
-50
-100
Full Chip Gain Error - %FS
-0.005
-30
Full Chip Offset - mV
Full Chip Offset - mV
-25
5.4
-0.05
2.9
3.1
3.3
3.5
3.7
3.9
4.1
VREF - Voltage Reference - V
4.3
Figure 38.
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links :ADS8254
Not Recommended for New Designs
ADS8254
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SLAS643A – MARCH 2009 – REVISED JANUARY 2014
TYPICAL CHARACTERISTICS (continued)
FULL CHIP GAIN ERROR
vs
MULTIPLEXER CHANNELS
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
SNR - Signal-To-Noise Ratio - dB
+VA = 5 V, TA = 25°C,
-0.01
Throughput = 1 MSPS
-0.02
-0.03
-0.04
-0.05
1
2
Multiplexer Channels
3
95.45
-111
95.35
95.25
95.15
95.05
94.95
94.85
Channel 0, Vref = 4.096 V, VCC = 6 V,
VEE = -6 V, +VA = 5 V, TA = 25°C,
fi = 1.9 kHz, Throughput = 1 MSPS
Channel 0, Vref = 4.096 V,
VCC = 6 V, VEE = -6 V,
+VA = 5 V, fi = 1.9 kHz,
-112
Throughput = 1 MSPS
-113
-114
-115
-116
-117
-118
-119
-60 -40
-20
0
20
40
60
80
100
-60 -40
-20
0
20
40
60
80
100
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
Figure 39.
Figure 40.
Figure 41.
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs
ANALOG SUPPLY VOLTAGE (+VA)
125
16
124
123
122
121
Channel 0, Vref = 4.096 V,
120
VCC = 6 V, VEE = -6 V,
+VA = 5 V, TA = 25°C,
119
fi = 1.9 kHz,
Throughput = 1 MSPS
118
-60 -40
-20
0
20
40
60
80
95.1
Channel 0, Vref = 4.096 V, VCC = 6 V,
SNR - Signal-To-Noise Ratio - dB
ENOB - Effective Number of Bits - bits
SFDR - Spurious Free Dynamic Range - dB
-110
94.75
0
VEE = -6 V, +VA = 5 V, fi = 1.9 kHz,
15.9
Throughput = 1 MSPS
15.8
15.7
15.6
15.5
100
95.05
95
94.95
94.9
94.85
Channel 0, Vref = 4.096 V, VCC = 6 V,
94.8
VEE = -6 V, TA = 25°C, fi = 1.9 kHz
Throughput = 1 MSPS
15.4
94.75
4.7
TA - Free-Air Temperature - °C
4.8
4.9
5
5.1 5.2
5.3
+VA - Analog Voltage Supply - V
Figure 42.
Figure 43.
Figure 44.
TOTAL HARMONIC DISTORTION
vs
ANALOG SUPPLY VOLTAGE (+VA)
SPURIOUS FREE DYNAMIC RANGE
vs
ANALOG SUPPLY VOLTAGE (+VA)
EFFECTIVE NUMBERR OF BITS
vs
ANALOG SUPPLY VOLTAGE (+VA)
-60 -40
TA - Free-Air Temperature - °C
SFDR - Spurious Free Dynamic Range - dB
-110
THD - Total Harmonic Distortion - dB
95.55
Channel 0, Vref = 4.096 V, VCC = 6 V,
-112
VEE = -6 V, TA = 25°C, fi = 1.9 kHz,
Throughput = 1 MSPS
-114
-116
-118
-120
-122
4.6
4.7
4.8 4.9
5
5.1 5.2 5.3
+VA - Analog Voltage Supply - V
5.4
Figure 45.
-20
0
20
40
60
80
100
125
5.4
16
ENOB - Effective Number of Bits - bits
Full Chip Gain Error - %FS
Vref = 4.096 V, VCC = 6 V, VEE = -6 V,
THD - Total Harmonic Distortion - dB
0
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
124
123
122
121
120
119
Channel 0, Vref = 4.096 V, VCC = 6 V,
VEE = -6V, TA = 25°C, fi = 1.9 kHz,
118
Throughput = 1 MSPS
117
4.6
Channel 0, Vref = 4.096 V, VCC = 6 V,
15.9
VEE = -6 V, TA = 25°C, fi = 1.9 kHz,
Throughput = 1 MSPS
15.8
15.7
15.6
15.5
15.4
4.7 4.8 4.9 5.0 5.1 5.2 5.3
+VA - Analog Voltage Supply - V
Figure 46.
5.4
4.7
4.8
4.9
5
5.1 5.2
5.3
+VA - Analog Voltage Supply - V
Figure 47.
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TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE RATIO
vs
REFERENCE VOLTAGE
TOTAL HARMONIC DISTORTION
vs
REFERENCE VOLTAGE
95 fi = 1.9 kHz,
Throughput = 1 MSPS
94.8
94.6
94.4
94.2
94
93.8
3
3.5
4
VREF - Voltage Reference - V
4.5
-118
-120
-122
-124
3
3.5
4
VREF - Voltage Reference - V
4.5
124
123
122
Channel 0, VCC = 6 V,
VEE = -6 V, +VA = 5 V,
TA = 25°C, fi = 1.9 kHz,
121
Throughput = 1 MSPS
120
2.5
3
3.5
4
VREF - Voltage Reference - V
Figure 50.
EFFECTIVE NUMBER OF BITS
vs
REFERENCE VOLTAGE
SIGNAL-TO-NOISE RATIO
vs
OPA SUPPLY VOLTAGE VCC
TOTAL HARMONIC DISTORTION
vs
OPA SUPPLY VOLTAGE (VCC)
-110
95.1
Channel 0, VCC = 6 V, VEE = -6 V,
+VA = 5 V, fi = 1.9 kHz, TA = 25°C,
Throughput = 1 MSPS
15.45
15.4
15.35
15.3
95.05
95
94.95
Channel 0, Vref = 4.096 V,
94.9
94.85
+VA = 5 V, fi = 1.9 kHz, TA = 25°C,
Throughput = 1 MSPS,
VCC = -VEE except VCC = 4.7 V
where VEE = -2.5 V
94.8
94.75
4
Channel 0, Vref = 4.096 V,
+VA = 5 V, fi = 1.9 kHz, TA = 25°C,
Throughput = 1 MSPS,
VCC = -VEE except VCC = 4.7 V
where VEE = -2.5 V
-112
-114
-116
-118
-120
4.5
5
5.5
6
6.5
7
VCC - Supply Voltage - V
7.5
4
8
5
6
7
VCC - Supply Voltage - V
Figure 51.
Figure 52.
Figure 53.
SPURIOUS FREE DYNAMIC RANGE
vs
OPA SUPPLY VOLTAGE (VCC)
EFFECTIVE NUMBER OF BITS
vs
OPA SUPPLY VOLTAGE (VCC)
SIGNAL-TO-NOISE RATIO
vs
SOURCE RESISTANCE (RIN)
124
Channel 0,
Vref = 4.096 V,
+VA = 5 V,
fi = 1.9 kHz,
TA = 25°C,
Throughput
= 1 MSPS
122
15.9
+VA = 5 V, fi = 1.9 kHz, TA = 25°C,
Throughput = 1 MSPS,
VCC = -VEE except VCC = 4.7 V
where VEE = -2.5 V
15.8
15.7
15.6
15.5
4
5
6
7
VCC - Supply Voltage - V
Figure 54.
8
TA = 25°C, Throughput = 1 MSPS
95.4
95.35
95.3
95.25
95.2
95.15
95.1
95.05
95
15.4
121.5
Channel 0, VCC = 6 V, VEE = -6 V,
Vref = 4.096 V, +VA = 5 V, fi = 1.9 kHz,
95.45
Channel 0, Vref = 4.096 V,
SNR - Signal-To-Noise Ratio - dB
ENOB - Effective Number of Bits - bits
123
8
95.5
16
VCC = -VEE
except VCC =
4.7 V where
123.5 VEE = -2.5 V
122.5
4.4
Figure 49.
SNR - Signal-To-Noise Ratio - dB
ENOB - Effective Number of Bits - bits
SFDR - Spurious Free Dynamic Range - dB
-116
125
Figure 48.
15.25
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
VREF - Voltage Reference - V
22
fi = 1.9 kHz, Throughput = 1 MSPS
-126
2.5
15.55
15.5
-114
THD - Total Harmonic Distortion - dB
93.6
2.5
-112
Channel 0, VCC = 6 V,
VEE = -6 V, +VA = 5 V, TA = 25°C,
SFDR - Spurious Free Dynamic Range - dB
-110
Channel 0,
95.2 VCC = 6 V, VEE = -6V,
+VA = 5 V, TA = 25°C,
THD - Total Harmonic Distortion - dB
SNR - Signal-To-Noise Ratio - dB
95.4
SPURIOUS FREE DYNAMIC RANGE
vs
REFERENCE VOLTAGE
4
4.5
5
5.5
6
6.5
7
VCC - Supply Voltage - V
7.5
Figure 55.
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8
0
200
400
600
800
1000
RI - Input Resistance - W
1200
Figure 56.
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links :ADS8254
Not Recommended for New Designs
ADS8254
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SLAS643A – MARCH 2009 – REVISED JANUARY 2014
TYPICAL CHARACTERISTICS (continued)
SFDR - Spurious Free Dynamic Range - dB
-118.5
-119
-119.5
-120
Channel 0, VCC = 6 V, VEE = -6 V,
Vref = 4.096 V, +VA = 5 V,
-120.5
0
200
400
600
800
1000
RI - Input Resistance - W
1200
124
123.5
123
122.5
122
121.5
121
VEE = -6 V, +VA = 5 V, fi = 1.9 kHz,
TA = 25°C, Throughput = 1 MSPS
15.8
15.7
15.6
15.5
15.4
120.5
0
200
400
600
800
1000
RI - Input Resistance - W
1200
0
200
400
600
800
RI - Input Resistance - W
1000
Figure 59.
SIGNAL-TO-NOISE RATIO
vs
MULTIPLEXER CHANNELS
TOTAL HARMONIC DISTORTION
vs
MULTIPLEXER CHANNELS
SPURIOUS FREE DYNAMIC RANGE
vs
MULTIPLEXER CHANNELS
-110
THD - Total Harmonic Distortion - dB
SNR - Signal-to-Noise Ratio - dB
Channel 0, Vref = 4.096 V, VCC = 6 V,
15.9
Figure 58.
95.00
94.95
94.90
94.85
Vref = 4.096 V, VCC = 6 V, VEE = -6 V,
94.80
+VA = 5 V, fi = 1.9 kHz, TA = 25°C,
Ri = 50 W, Throughput = 1 MSPS
1
2
Multiplexer Channel
Vref = 4.096 V, VCC = 6 V, VEE = -6 V,
-112
+VA = 5 V, fi = 1.9 kHz, TA = 25°C,
Ri = 50 W, Throughput = 1 MSPS
-114
-116
-118
-120
-122
0
3
1
2
Multiplexer Channel
3
125
Vref = 4.096 V, VCC = 6 V, VEE = -6 V,
+VA = 5 V, fi = 1.9 kHz, TA = 25°C,
Ri = 50 W, Throughput = 1 MSPS
124
123
122
121
120
0
1
2
Multiplexer Channel
3
Figure 60.
Figure 61.
Figure 62.
EFFECTIVE NUMBER OF BITS
vs
MULTIPLEXER CHANNELS
VCM_O VOLTAGE
vs
OPA SUPPLY VOLTAGE (VCC)
BUFFER REFERENCE OUTPUT
VOLTAGE
vs
OPA SUPPLY VOLTAGE (VCC)
16
4.0871
2.04145
Vref = 4.096 V, VCC = 6 V, VEE = -6 V,
2.0414
+VA = 5 V, fi = 1.9 kHz, TA = 25°C,
2.04135
Throughput = 1 MSPS
VCM_O - Voltage - V
ENOB - Effective Number of Bits - Bits
VEE = -6 V, +VA = 5 V, fi = 1.9 kHz,
TA = 25°C, Throughput = 1 MSPS
Figure 57.
95.05
15.9
Channel 0, Vref = 4.096 V, VCC = 6 V,
124.5
95.10
94.75
0
16
125
SFDR - Spurious Free Dynamic Range - dB
-121
fi = 1.9 kHz, TA = 25°C,
Throughput = 1 MSPS
EFFECTIVE NUMBER OF BITS
vs
SOURCE RESISTANCE (RIN)
15.8
15.7
15.6
2.0413
2.04125
VCC = -VEE except
VCC = 4.7 V where
VEE = -2.5 V,
Vref = 4.096 V,
VCC = -VEE except
VCC = 4.7 V where
VEE = -2.5 V,
Vref = 4.096 V,
4.087
BUF_REF - Output - V
THD - Total Harmonic Distortion - dB
-118
SPURIOUS FREE DYNAMIC RANGE
vs
SOURCE RESISTANCE (RIN)
ENOB - Effective Number Of Bite - Bits
TOTAL HARMONIC DISTORTION
vs
SOURCE RESISTANCE (RIN)
+VA = 5 V,
TA = 25°C,
2.0412
2.04115
2.0411
4.0869
+VA = 5 V,
TA = 25°C
4.0868
4.0867
4.0866
2.04105
15.5
4.0865
2.041
15.4
0
1
2
Multiplexer Channel
3
Figure 63.
2.04095
4
4.0864
4.5
5
5.5
6
6.5
7
VCC - Supply Voltage - V
Figure 64.
7.5
8
4
4.5
5
5.5
6
6.5
7
VCC - Supply Voltage - V
Product Folder Links :ADS8254
8
Figure 65.
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ADS8254
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TYPICAL CHARACTERISTICS (continued)
TYPICAL DNL
0.4
+VA = 5 V, +VBD = 5 V, TA = 25C, Fs = 1 MSPS, Vref = 4.096 V
0.3
DNL - LSB
0.2
0.1
0
-0.1
-0.2
-0.3
0
10000
20000
30000
40000
Codes
Figure 66.
50000
60000
70000
TYPICAL INL
0.4
0.3
INL - LSBs
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
+VA = 5 V, +VBD = 5 V, TA = 25C, Fs = 1 MSPS, Vref = 4.096 V
-0.5
0
10000
20000
40000
30000
50000
60000
70000
Codes
Figure 67.
TYPICAL FFT
0
Input Frequency = 19 kHz, Fs = 1 MSPS, SNR 95.2 dB,
THD = 113 dB, SFDR = 115 dB, SINAD = 94.8 dB
-20
Power - dB
-40
-60
-80
-100
-120
-140
-160
-180
-200
0
24
100000
200000
300000
f - Frequency - Hz
Figure 68.
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400000
500000
Copyright © 2009–2014, Texas Instruments Incorporated
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Not Recommended for New Designs
ADS8254
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SLAS643A – MARCH 2009 – REVISED JANUARY 2014
APPLICATION INFORMATION
As discussed before, the ADS8254 is 16-bit analog SoC that includes various blocks like a multiplexer, ADC
driver, internal reference, internal reference buffer, buffered reference output, and Ref/2 output on-board. The
following diagram shows the recommended analog and digital interfacing of the ADS8254.
APPLICATION DIAGRAM
From Host
AUTO,
C1, C2,
C3
MXCLK
VOLTAGE
CLAMP
-
CH1P
+/-4 V,
diffSignals
with 2 V
common
mode,
Source
res
< = 50 W
+VA
VCC
CH0P
CH2P
OPA-1
10 Ω
+
CH3P
BUSY
+VA
DB0 - DB15
VEE
+VA
VCC
CH0M
16 Bit 1 MSPS
ADC
-
CH1M
CH2M
LOGIC
I/O
BUFFER
To Host
BYTE
RD
CS
OPA-2
10 Ω
+
CH3M
CONVST
VEE
ADC REF
INP
1nF
INM
VCM-O:
Ref/2 for common
mode of diffamplifier in signal
path
+VA
VCC
VREF/2
REFIN
VCC
BUF-REF:
For use on
application board
+VA
INTERNAL - REF
REFOUT
0.1
mF
PD-RBUF : Connect this
pin to VCC to power
down ‘Ref-Buffer’ when not in use
1 mF
REFM
Figure 69. Analog and Digital Interface Diagram
As shown in Figure 69, the ADS8254 accepts unipolar differential analog inputs in the range of ±Vref with a
common-mode voltage of Vref/2 . An application may require the interfacing of bipolar input signals. The following
diagram shows the conversion of bipolar input signals to unipolar differential signals.
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From BUF-REF o/p of ADC
(Use external buffer if current drawn by
resistor network exceeds current output
specification of reference buffer)
R
R
CHnP
CHnM
C
R
C
R
±2* Ref True Bipolar,
Diff Signals
Note: Value of R depends on signal BW Use R = 1.2 kW for signal BW
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