ADS8328IPWR

ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE Check for Samples: ADS8327, ADS8328 FEATURES APPLICATIONS • • • • • • • • 1 • • • • • • • • • • • • • • 2.7-V to 5.5-V Analog Supply, Low Power: – 10.6 mW (500 kHz, +VA = 2.7 V, +VBD = 1.8 V) 500-kHz Sampling Rate Excellent DC Performance – ±1.5 LSB Typ, ±2 LSB Max INL – ±0.6 LSB Typ, ±1 LSB Max DNL – 16-Bit NMC Over Temperature – ±0.5 mV Max Offset Error at 2.7 V – ±1 mV Max Offset Error at 5 V Excellent AC Performance at fI = 10 kHz with 91 dB SNR, 100 dB SFDR, –96 dB THD Built-In Conversion Clock (CCLK) 1.65 V to 1.5×(+VA) I/O Supply – SPI/DSP Compatible Serial – SCLK up to 50 MHz Comprehensive Power-Down Modes: – Deep Power-Down – Nap Power-Down – Auto Nap Power-Down Unipolar Input Range: 0 V to VREF Software Reset Global CONVST (Independent of CS) Programmable Status/Polarity EOC/INT 16-Pin 4×4 QFN or 16-Pin TSSOP Packages Multi-Chip Daisy Chain Mode Programmable TAG Bit Output Auto/Manual Channel Select Mode ADS8328 ADS8327 +IN1 NC +IN0 COM +IN −IN REF+ REF− Communications Transducer Interface Medical Instruments Magnetometers Industrial Process Control Data Acquisition Systems Automatic Test Equipment DESCRIPTION The ADS8327 is a low power, 16-bit, 500-kSPS analog-to-digital converter with a unipolar input. The device includes a 16-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8328 is based on the same core and includes a 2-to-1 input MUX with programmable option of TAG bit output. Both the ADS8327 and ADS8328 offer a high-speed, wide voltage serial interface and are capable of chain mode operation when multiple converters are used. These converters are available in a 16-lead TSSOP or 4x4 QFN packages and are fully specified for operation over the industrial –40°C to +85°C temperature range. Table 1. Low Power, High-Speed SAR Converter Family Type/Speed 16 Bit Pseudo-Diff 1 MHz ADS8327 ADS8329 Dual ADS8328 ADS8330 OUTPUT LATCH and 3−STATE DRIVER SAR + _ 500 kHz Single SDO CDAC COMPARATOR OSC CONVERSION and CONTROL LOGIC FS/CS SCLK SDI CONVST EOC/INT/CDI 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. © 2006–2011, Texas Instruments Incorporated ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) MODEL ADS8327I MAXIMUM INTEGRAL LINEARITY (LSB) ±3 MAXIMUM DIFFERENTIAL LINEARITY (LSB) –1/+2 MAXIMUM OFFSET ERROR (mV) PACKAGE TYPE PACKAGE DESIGNATOR TSSOP-16 PW ±1.25 TSSOP-16 ±2 ±1 ±3 –1/+2 ±1 2 ADS8327IRSAT Small tape and reel 250 ADS8327IRSAR Tape and reel 3000 ADS8327IBPW Tube 90 ADS8327IBPWR Tape and reel 2000 ADS8327IBRSAT Small tape and reel 250 ADS8327IBRSAR Tape and reel 3000 RSA ADS8328IPW Tube 90 ADS8328IPWR Tape and reel 2000 ADS8328IRSAT Small tape and reel 250 ADS8328IRSAR Tape and reel 3000 PW RSA ADS8328IBPW Tube 90 ADS8328IBPWR Tape and reel 2000 ADS8328IBRSAT Small tape and reel 250 ADS8328IBRSAR Tape and reel 3000 PW ±1 –40°C to +85°C 4×4 QFN-16 (1) ADS8327IPWR –40°C to +85°C TSSOP-16 ±2 Tube 90 Tape and reel 2000 PW ±1.25 4×4 QFN-16 ADS8328IB ADS8327IPW –40°C to +85°C TSSOP-16 TRANSPORT MEDIA QUANTITY RSA ±1 4×4 QFN-16 ADS8328I ORDERING INFORMATION –40°C to +85°C 4×4 QFN-16 ADS8327IB TEMPERATURE RANGE RSA For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range, unless otherwise noted. (1) UNIT Voltage +IN to AGND –0.3 V to +VA + 0.3 V –IN to AGND –0.3 V to +VA + 0.3 V –0.3 V to 7 V +VA to AGND Voltage range +REF to AGND –0.3 V to +VA + 0.3 V –REF to AGND –0.3 V to +0.3 V +VBD to BDGND –0.3 V to 7 V AGND to BDGND –0.3 V to 0.3 V Digital input voltage to BDGND –0.3 V to +VBD + 0.3 V Digital output voltage to BDGND –0.3 V to +VBD + 0.3 V TA Operating free-air temperature range –40°C to +85°C Tstg Storage temperature range –65°C to +150°C Junction temperature (TJ max) (1) TSSOP-16 Package Power dissipation 4×4 QFN-16 Package Power dissipation +150°C (TJMax - TA)/qJA qJA thermal impedance 86°C/W (TJMax – TA)/qJA qJA thermal impedance 47°C/W Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 3 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com SPECIFICATIONS TA = –40°C to 85°C, +VA = 2.7 V to 3.6 V, +VBD = 1.65 V to 1.5 × (+VA), VREF = 2.5 V, and fSAMPLE = 500 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V ANALOG INPUT Full-scale input voltage (1) +IN – (–IN) or (+INx – COM) Absolute input voltage 0 +VREF +IN, +IN0, +IN1 AGND – 0.2 +VA + 0.2 –IN or COM AGND – 0.2 AGND + 0.2 Input capacitance 40 No ongoing conversion, DC Input Input leakage current Input channel isolation, ADS8328 only –1 At dc 108 VI = ±1.25 VPP at 50 kHz 101 V 45 pF 1 nA dB SYSTEM PERFORMANCE Resolution 16 No missing codes INL Integral linearity Differential linearity DNL Offset error (3) EO –2 ±1.2 2 ADS8327I, ADS8328I –3 ±2 3 ADS8327IB, ADS8328IB –1 ±0.6 1 ADS8327I, ADS8328I –1 ±1 2 ADS8327IB, ADS8328IB –0.5 ±0.1 0.5 ADS8327I, ADS8328I –0.8 ±0.1 0.8 –0.25 –0.07 0.2 Gain error Gain error drift CMRR Common-mode rejection ratio At dc 70 VI = 0.4 VPP at 1 MHz 50 Power-supply rejection ratio At FFFFh output code (3) LSB (2) LSB (2) mV ppm/°C 0.25 0.3 Noise PSRR Bits ADS8327IB, ADS8328IB Offset error drift EG Bits 16 %FSR ppm/°C dB 33 mV RMS 78 dB 18 CCLK SAMPLING DYNAMICS tCONV tSAMPLE1 tSAMPLE2 Conversion time Acquisition time Manual trigger Auto trigger 3 Throughput rate (1) (2) (3) 4 CCLK 3 500 kHz Aperture delay 5 ns Aperture jitter 10 ps Step response 100 ns Overvoltage recovery 100 ns Ideal input span, does not include gain or offset error. LSB means least significant bit. Measured relative to an ideal full-scale input [+IN – (–IN)] of 2.5 V when +VA = 2.7 V. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com SPECIFICATIONS (continued) TA = –40°C to 85°C, +VA = 2.7 V to 3.6 V, +VBD = 1.65 V to 1.5 × (+VA), VREF = 2.5 V, and fSAMPLE = 500 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS (4) THD Total harmonic distortion SNR Signal-to-noise ratio SINAD Signal-to-noise + distortion SFDR Spurious-free dynamic range –98 VIN = 2.5 VPP at 10 kHz VIN = 2.5 VPP at 100 kHz –83.5 VIN = 2.5 VPP at 10 kHz 88.5 VIN = 2.5 VPP at 100 kHz dB dB 85 VIN = 2.5 VPP at 10 kHz 88.5 VIN = 2.5 VPP at 100 kHz 81 VIN = 2.5 VPP at 10 kHz 101 VIN = 2.5 VPP at 100 kHz 84 –3dB small-signal bandwidth dB dB 30 MHz CLOCK Internal conversion clock frequency SCLK External serial clock 10.5 11 Used as I/O clock only 12.2 33 As I/O clock and conversion clock 1 21 0.3 2.525 –0.1 0.1 MHz MHz EXTERNAL VOLTAGE REFERENCE INPUT VREF Input reference range Resistance VREF(REF+ – REF–) 3.6 V ≥ +VA ≥ 2.7 V (REF–) – AGND (5) Reference input 80 V kΩ DIGITAL INPUT/OUTPUT Logic family—CMOS VIH High-level input voltage (+VA × 1.5) V ≥ +VBD ≥ 1.65 V 0.65 × (+VBD) +VBD + 0.3 VIL Low-level input voltage (+VA × 1.5) V ≥ +VBD ≥ 1.65 V –0.3 0.35 × (+VBD) V II Input current VI = +VBD or BDGND –50 50 nA CI Input capacitance 5 VOH High-level output voltage (+VA × 1.5) V ≥ +VBD ≥ 1.65 V, IO = 100 mA VOL Low-level output voltage (+VA × 1.5) V ≥ +VBD ≥ 1.65 V, IO = 100 mA CO Output capacitance CL Load capacitance V pF +VBD – 0.6 +VBD V 0 0.4 V 5 pF 30 pF 1.5 × (+VA) V 3.6 V Data format—straight binary POWER-SUPPLY REQUIREMENTS Power-supply voltage +VBD 1.65 +VA Supply current +VA 2.7 500-kHz Sample rate 3.8 5 NAP/Auto-NAP mode 0.2 0.4 2 50 nA 14 mW +85 °C Deep power-down mode Buffer I/O supply current 500 kSPS Power dissipation +VA = 2.7 V, +VBD = 1.8 V 0.2 10.6 mA mA TEMPERATURE RANGE TA (4) (5) –40 Operating free-air temperature Calculated on the first nine harmonics of the input frequency. Can vary ±30%. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 5 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com SPECIFICATIONS TA = –40°C to 85°C, +VA = 4.5 V to 5.5 V, +VBD = 1.65 V to 5.5 V, VREF = 4.096 V, and fSAMPLE = 500 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V ANALOG INPUT Full-scale input voltage (1) Absolute input voltage +IN – (–IN) or (+INx – COM) 0 +VREF +IN, +IN0, +IN1 AGND – 0.2 +VA + 0.2 –IN or COM AGND – 0.2 AGND + 0.2 Input capacitance 40 Input leakage current Input channel isolation, ADS8328 only No ongoing conversion, DC Input –1 At dc 109 VI = ±1.25 VPP at 50 kHz 101 V 45 pF 1 nA dB SYSTEM PERFORMANCE Resolution 16 No missing codes ADS8327IB, Integral linearity ADS8328IB ADS8327I, ADS8328I INL Differential linearity DNL Offset error (3) EO ±1.5 2 –3 ±2 3 ADS8327IB, ADS8328IB –1 ±0.7 1 ADS8327I, ADS8328I –1 ±1 2 ADS8327IB, ADS8328IB –1 ±0.4 1 –1.25 ±0.4 1.25 –0.25 –0.07 Offset error drift 0.5 Gain error Gain error drift CMRR Common-mode rejection ratio At dc 70 VI = 1 VPP at 1 MHz 50 Power-supply rejection ratio At FFFFh output code (3) LSB (2) LSB (2) mV ppm/°C 0.25 0.3 Noise PSRR Bits –2 ADS8327I, ADS8328I EG Bits 16 %FSR ppm/°C dB 33 mV RMS 78 dB 18 CCLK SAMPLING DYNAMICS tCONV Conversion time tSAMPLE 1 tSAMPLE Manual trigger 3 Acquisition time CCLK Auto trigger 3 2 Throughput rate (1) (2) (3) 6 500 kHz Aperture delay 5 ns Aperture jitter 10 ps Step response 100 ns Overvoltage recovery 100 ns Ideal input span, does not include gain or offset error. LSB means least significant bit. Measured relative to an ideal full-scale input [+IN – (–IN)] of 4.096 V when +VA = 5 V. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com SPECIFICATIONS (continued) TA = –40°C to 85°C, +VA = 4.5 V to 5.5 V, +VBD = 1.65 V to 5.5 V, VREF = 4.096 V, and fSAMPLE = 500 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS VIN = 4.096 VPP at 10 kHz THD Total harmonic distortion (4) SNR Signal-to-noise ratio SINAD Signal-to-noise + distortion SFDR Spurious-free dynamic range -96 VIN = 4.096 VPP at 100 kHz, ADS8327/28IB –95.7 VIN = 4.096 VPP at 100 kHz, ADS8327/28I –95.7 VIN = 4.096 VPP at 10 kHz 91 VIN = 4.096 VPP at 100 kHz 89 VIN = 4.096 VPP at 10 kHz 91 VIN = 4.096 VPP at 100 kHz 88 VIN = 4.096 VPP at 10 kHz dB dB dB 100 VIN = 4.096 VPP at 100 kHz, ADS8327/28IB 98.8 VIN = 4.096 VPP at 100 kHz, ADS8327/28I 98.8 –3dB Small-signal bandwidth dB 30 MHz CLOCK Internal conversion clock frequency SCLK External serial clock 10.9 12 Used as I/O clock only 12.6 50 As I/O clock and conversion clock 1 21 MHz MHz EXTERNAL VOLTAGE REFERENCE INPUT VREF Input reference range Resistance VREF (REF+ – REF–) 5.5 V ≥ +VA ≥ 4.5 V 0.3 (REF–) – AGND (5) 4.096 –0.1 Reference input 4.2 0.1 80 V kΩ DIGITAL INPUT/OUTPUT Logic family—CMOS VIH High-level input voltage 5.5 V ≥ +VBD ≥ 4.5 V 0.65 × (+VBD) +VBD + 0.3 VIL Low-level input voltage 5.5 V ≥ +VBD ≥ 4.5 V –0.3 0.35 × (+VBD) V II Input current VI = +VBD or BDGND -50 50 nA CI Input capacitance 5 VOH High-level output voltage 5.5 V ≥ +VBD ≥ 4.5 V, IO = 100 mA VOL Low-level output voltage 5.5 V ≥ +VBD ≥ 4.5 V, IO = 100 mA CO Output capacitance CL Load capacitance V pF +VBD – 0.6 +VBD V 0 0.4 V 5 pF 30 pF Data format—straight binary POWER-SUPPLY REQUIREMENTS Power supply voltage +VBD 1.65 3.3 5.5 V 4.5 5 5.5 V 500-kHz Sample rate 5 6.2 NAP/Auto-NAP mode 0.3 0.5 Deep power-down mode 6 50 500 kSPS 1 +VA Supply current Buffer I/O supply current Power dissipation +VA = 5 V, +VBD = 5 V +VA = 5 V, +VBD = 1.8 V mA nA mA 30 38.5 25.4 32 mW TEMPERATURE RANGE TA (4) (5) –40 Operating free-air temperature +85 °C Calculated on the first nine harmonics of the input frequency. Can vary ±30% Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 7 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = 2.7 v, +VBD = 1.8 V (1) (2) PARAMETER fCCLK Frequency, conversion clock, CCLK MIN External, fCCLK = 1/2 fSCLK 0.5 Internal fCCLK = 1/2 fSCLK 10.5 TYP MAX UNIT 10.5 MHz 11 12.2 tsu(CSF-EOC) Setup time, falling edge of CS to EOC 1 CCLK th(CSF-EOC) Hold time, falling edge of CS to EOC 0 ns twL(CONVST) Pulse duration, CONVST low 40 ns tsu(CSF-EOS) Setup time, falling edge of CS to EOS 20 ns th(CSF-EOS) Hold time, falling edge of CS to EOS 20 ns tsu(CSR-EOS) Setup time, rising edge of CS to EOS 20 ns th(CSR-EOS) Hold time, rising edge of CS to EOS 20 ns tsu(CSF-SCLK1F) Setup time, falling edge of CS to first falling SCLK 5 ns twL(SCLK) Pulse duration, SCLK low 8 tc(SCLK) – 8 ns twH(SCLK) Pulse duration, SCLK high 8 tc(SCLK) – 8 ns I/O Clock only I/O and conversion clock tc(SCLK) Cycle time, SCLK I/O Clock, chain mode I/O and conversion clock, chain mode 30 47.6 2000 ns 30 47.6 2000 td(SCLKF-SDOINVALID) Delay time, falling edge of SCLK to SDO invalid 10-pF Load td(SCLKF-SDOVALID) Delay time, falling edge of SCLK to SDO valid 10-pF Load 16 ns td(CSF-SDOVALID) Delay time, falling edge of CS to SDO valid, SDO MSB output 10-pF Load 13 ns tsu(SDI-SCLKF) Setup time, SDI to falling edge of SCLK 8 ns th(SDI-SCLKF) Hold time, SDI to falling edge of SCLK 4 ns td(CSR-SDOZ) Delay time, rising edge of CS/FS to SDO 3-state tsu(16th SCLKF-CSR) Setup time, 16th falling edge of SCLK before rising edge of CS/FS td(SDO-CDI) Delay time, CDI high to SDO high in daisy chain mode (1) (2) 8 7.5 ns 8 10 10-pF Load, chain mode ns ns 25 ns All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V (1) (2) PARAMETER fCCLK Frequency, conversion clock, CCLK MIN External, fCCLK = 1/2 fSCLK 0.5 Internal fCCLK = 1/2 fSCLK 10.9 TYP MAX UNIT 10.5 MHz 12 12.6 tsu(CSF-EOC) Setup time, falling edge of CS to EOC 1 CCLK th(CSF-EOC) Hold time, falling edge of CS to EOC 0 ns twL(CONVST) Pulse duration, CONVST low 40 ns tsu(CSF-EOS) Setup time, falling edge of CS to EOS 20 ns th(CSF-EOS) Hold time, falling edge of CS to EOS 20 ns tsu(CSR-EOS) Setup time, rising edge of CS to EOS 20 ns th(CSR-EOS) Hold time, rising edge of CS to EOS 20 ns tsu(CSF-SCLK1F) Setup time, falling edge of CS to first falling SCLK 5 ns twL(SCLK) Pulse duration, SCLK low 8 tc(SCLK) – 8 ns twH(SCLK) Pulse duration, SCLK high 8 tc(SCLK) – 8 ns I/O Clock only I/O and conversion clock tc(SCLK) Cycle time, SCLK I/O Clock, chain mode I/O and conversion clock, chain mode 20 47.6 2000 ns 20 47.6 2000 td(SCLKF-SDOINVALID) Delay time, falling edge of SCLK to SDO invalid 10-pF Load td(SCLKF-SDOVALID) Delay time, falling edge of SCLK to SDO valid 10-pF Load 10 ns td(CSF-SDOVALID) Delay time, falling edge of CS to SDO valid, SDO MSB output 10-pF Load 8.5 ns tsu(SDI-SCLKF) Setup time, SDI to falling edge of SCLK 8 ns th(SDI-SCLKF) Hold time, SDI to falling edge of SCLK 4 ns td(CSR-SDOZ) Delay time, rising edge of CS/FS to SDO 3-state tsu(16th SCLKF-CSR) Setup time, 16th falling edge of SCLK before rising edge of CS/FS td(SDO-CDI) Delay time, CDI high to SDO high in daisy-chain mode (1) (2) 2 ns 5 10 10-pF Load, chain mode ns ns 16 ns All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 9 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com PIN ASSIGNMENTS ADS8327 ADS8328 PW PACKAGE (TOP VIEW) PW PACKAGE (TOP VIEW) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 +VA RESERVED +IN −IN AGND REF− REF+ (REFIN) NC +VBD SCLK BDGND SDO SDI FS/CS EOC/INT CONVST 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 +VA +IN1 +IN0 COM AGND REF− REF+ (REFIN) NC +VBD SCLK BDGND SDO SDI FS/CS EOC/INT CONVST NC − No internal connection REF− AGND COM +IN0 13 16 15 14 13 11 +VA CONVST 3 10 EOC/INT/CDI 4 9 6 7 8 1 12 +IN1 NC 2 11 +VA +VBD CONVST 3 10 +VBD SCLK EOC/INT/CDI 4 9 SCLK 5 6 7 8 BDGND 2 5 REF+(REFIN) SDO NC BDGND RESERVED SDO 12 SDI 1 FS/CS REF+(REFIN) SDI 14 FS/CS 15 +IN 16 −IN AGND ADS8328 RSA PACKAGE (TOP VIEW) REF− ADS8327 RSA PACKAGE (TOP VIEW) NC − No internal connection CAUTION: The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. 10 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com ADS8327 Terminal Functions NAME NO. I/O DESCRIPTION TSSOP QFN AGND 5 15 – Analog ground BDGND 14 8 – Interface ground CONVST 9 3 I Freezes sample and hold, starts conversion with next rising edge of internal clock O Status output. If programmed as EOC, this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed duration after the end of conversion and valid data are to be output. The polarity of EOC or INT is programmable. This pin can also be used as a chain data input when the device is operated in chain mode. EOC/ INT/ CDI 10 4 FS/CS 11 5 +IN 3 –IN 4 NC 8 2 REF+ 7 1 I External reference input. REF– 6 16 I Connect to AGND through individual via. RESERVED 2 12 – Reserved, connect to AGND or +VA SCLK 15 9 I Clock for serial interface SDI 12 6 I Serial data in SDO 13 7 O Serial data out +VA 1 11 Analog supply, +2.7 V to +5.5 VDC. +VBD 16 10 Interface supply I Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface slave select (SS–). 13 I Noninverting input 14 I Inverting input, usually connected to ground No connection ADS8328 Terminal Functions NAME NO. I/O DESCRIPTION TSSOP QFN AGND 5 15 – Analog ground BDGND 14 8 – Interface ground COM 4 14 I Common inverting input, usually connected to ground CONVST 9 3 I Freezes sample and hold, starts conversion with next rising edge of internal clock EOC/ INT/ CDI 10 4 O Status output. If programmed as EOC, this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed duration after the end of conversion and valid data are to be output. The polarity of EOC or INT is programmable. This pin can also be used as a chain data input when the device is operated in chain mode. FS/CS 11 5 I Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface +IN1 2 12 I Second noninverting input. +IN0 3 13 I First noninverting input NC 8 2 – No connection. REF+ 7 1 I External reference input. REF– 6 16 I Connect to AGND through individual via. SCLK 15 9 I Clock for serial interface SDI 12 6 I Serial data in (conversion start and reset possible) SDO 13 7 O Serial data out +VA 1 11 Analog supply, +2.7 V to +5.5 VDC. +VBD 16 10 Interface supply Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 11 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com MANUAL TRIGGER / READ While Sampling (use internal CCLK, EOC and INT polarity programmed as active low) Nth Nth tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs min INT (active low) tSAMPLE1 = 3 CCLKs min th(CSR-EOS) th(CSF-EOC) th(CSF-EOS) EOS twL(CONVST) EOC EOC (active low) EOS EOC CONVST th(CSF-EOC) tsu(CSF-EOC) tsu(CSF-EOS) CS/FS 1 SCLK 1 . . . . . . . . . . . . . . . . . . . . 16 SDO td(CSR-EOS) = 20 ns min Nth Nth−1st SDI 1101b 1101b READ Result READ Result Figure 1. Timing for Conversion and Acquisition Cycles for Manual Trigger (Read While Sampling) AUTO TRIGGER / READ While Sampling (use internal CCLK, EOC and INT polarity programmed as active low) tCONV = 18 CCLKs tSAMPLE2 = 3 CCLKs Nth tSAMPLE2 = 3 CCLKs tCONV = 18 CCLKs INT (active low) EOS EOC (active low) EOC EOS EOS EOC CONVST = 1 th(CSF-EOS) th(CSF-EOC) tsu(CSF-EOS) tsu(CSF-EOS) CS/FS SCLK SDO SDI 1 . . . . . . . . . . . . . . . . . . .16 1 . . . . . . . . . . . . . . . . . . .16 N − 2nd N − 1st 1110b. . . . . . . . . . . . . . CONFIGURE 1101b READ Result th(CSF-EOC) 1 Nth 1101b READ Result Figure 2. Timing for Conversion and Acquisition Cycles for Autotrigger (Read While Sampling) 12 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com MANUAL TRIGGER / READ While Converting (use internal CCLK, EOC and INT polarity programmed as active low) N + 1st Nth Nth EOC (active low) EOS EOC twL(CONVST) EOS CONVST tCONV = 18 CCLKs N + 1st tSAMPLE1 = 3 CCLKs min INT (active low) th(CSF-EOS) tsu(CSR-EOS) tsu(CSF-EOS) CS/FS tsu(CSF-EOC) th(CSF-EOC) SCLK 1 1 . . . . . . . . . . . . . . . . . . . .16 SDO N th N − 1st 1101b SDI 1101b READ Result READ Result Figure 3. Timing for Conversion and Acquisition Cycles for Manual Trigger (Read While Converting) AUTO TRIGGER / READ While Converting (use internal CCLK, EOC and INT polarity programmed as active low) th(CSF-EOS) tsu(CSF-EOS) tSAMPLE2 = 3 CCLKs min tSAMPLE2 = 3 CCLKs min Nth EOS tCONV = 18 CCLKs tCONV = 18 CCLKs INT (active low) N + 1st EOC EOC (active low) EOS EOS EOC CONVST = 1 th(CSR-EOS) tsu(CSR-EOS) th(CSF-EOS) CS/FS 1 . . . . . . . . . . . . . . . . . . 16 SCLK SDO SDI 1 . . . . . . . . . . . . . . . . . . .16 N − 2nd 1 . . . . . . . . . . . . . . . . . . 16 ?? 1110b . . . . . . . . . . . . . . . CONFIGURE tsu(CSR-EOS) Nth N − 1st 1101b READ Result 1101b READ Result Figure 4. Timing for Conversion and Acquisition Cycles for Autotrigger (Read While Converting) Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 13 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 1 2 www.ti.com 3 4 5 6 14 7 15 16 SCLK tsu(CSF−SCLK1F) tc(SCLK) twH(SCLK) twL(SCLK) CS/FS tsu(16thSCLK−CSR) td(SCLKF−SDOINVALID) td(CSR−SDOZ) td(SCLKF−SDOVALID) td(CSF−SDOVALID) SDO Hi−Z MSB−1 MSB−2 MSB−3 MSB−4 MSB MSB−5 MSB−6 LSB+2 LSB+1 LSB th(SDI−SCLKF) MSB SDI MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 LSB+2 LSB+1 LSB tsu(SDI−SCLKF) Figure 5. Detailed SPI Transfer Timing MANUAL TRIGGER / READ While Sampling (use internal CCLK active high, EOC and INT active low, TAG enabled, auto channel select) Nth CH1 Nth CH0 CONVST twL(CONVST) EOS EOC (active low) EOC twL(CONVST) Nth CH0 Nth CH1 tCONV = 18 CCLKs tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs min INT (active low) tsu(CSF-EOS) th(CSF-EOC) CS/FS SCLK 1 . . . . . . . . . . . . . . . . . . . . . . . 16 17 1 . . . . . . . . . . . . . . . . . . . . . . . 16 17 td(CSR-EOS) = 20 ns MIN SDO Hi−Z Nth CH0 N−1th CH1 TAG = 0 TAG = 1 SDI 1101b Hi−Z 1101b READ Result READ Result Figure 6. Simplified Dual Channel Timing 14 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS At –40°C to 85°C, VREF (REF+ – REF–) = 4.096 V when +VA = +VBD = 5 V or VREF (REF+ – REF–) = 2.5 V when +VA = +VBD = 2.7 V, fSCLK = 21 MHz, fI = DC for DC curves, and fI = 100 kHz for AC curves, unless otherwise noted. CROSSTALK vs FREQUENCY DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.9 110 1.8 105 1.7 +VA = 5 V +VA = 5 V INL - LSB 95 DNL - LSB Crosstalk - dB 0.8 100 0.7 1.6 +VA = 5 V +VA = 2.7 90 1.5 0.6 85 +VA = 2.7 V +VA = 2.7 80 0 50 100 150 F -Frequency - kHz 0.5 -40 -25 -10 200 5 20 35 50 65 1.4 5 20 35 50 65 -40 -25 -10 TA - Free-Air Temperature - °C 80 TA - Free-Air Temperature - °C 80 Figure 7. Figure 8. Figure 9. DIFFERENTIAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY INTEGRAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY DIFFERENTIAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY 2 2 2 +VA = 5 V +VA = 5 V +VA = 2.7 V 1.5 1.5 1.5 Max MAX 1 1 1 0.5 0.5 0 MIN DNL - LSB INL - LSB DNL - LSB Max 0.5 0 -0.5 -0.5 -1 -1 -1.5 -1.5 0 Min -0.5 -1 Min -1.5 -2 -2 0 -2 External Clock Frequency - MHz 5 10 15 External Clock Frequency - MHz Figure 10. Figure 11. 5 10 15 20 0 20 0 10 15 5 External Clock Frequency - MHz Figure 12. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 20 15 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) INTEGRAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY OFFSET VOLTAGE vs FREE-AIR TEMPERATURE 2 OFFSET VOLTAGE vs SUPPLY VOLTAGE 1 1 0.8 0.8 +VA = 2.7 V 1.5 Max 0.5 0 -0.5 -1 0.6 +VA = 5 V 0.4 0.2 5 10 15 20 External Clock Frequency - MHz 25 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 5.2 Figure 14. Figure 15. GAIN ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs SUPPLY VOLTAGE POWER-SUPPLY REJECTION RATIO vs SUPPLY RIPPLE FREQUENCY +VA = 5 V -0.070 +VA = 2.7 -0.075 -40 -25 -10 5 20 35 50 65 -0.068 -0.070 -0.073 -0.075 2.7 80 PSRR - Power Supply Rejection Ratio - dB Offset Voltage Change - mV -0.065 -0.068 TA - Free-Air Temperature - °C 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V -80 -78 -76 +VA = 5 V +VA = 2.7 V -74 -72 -70 5.2 0 20 40 60 80 Supply Ripple Frequency - kHz 100 Figure 17. Figure 18. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY +VA = 5 V 90 88 +VA = 2.7 V 86 20 40 60 80 fi - Input Frequency - kHz 100 Figure 19. SINAD - Signal-To-Noise and Distortion - dB Figure 16. 92 84 0 0 2.7 80 Figure 13. -0.065 -0.073 -10 5 20 35 50 65 TA - Free-Air Temperature - °C -150 92 THD - Total Harmonic Distortion - dB 0 Gain Error - % FSR 0.4 0.2 +VA = 2.7 0 -40 -25 -2 SNR - Signal-To-Noise Ratio - dB 0.6 Min -1.5 16 Offset Voltage - mV Offset Voltage - mV INL - LSB 1 +VA = 5 V 90 88 +VA = 2.7 V 86 84 82 80 0 20 40 60 80 fi - Input Frequency - kHz 100 Figure 20. Submit Documentation Feedback -100 +VA = 5 V -95 -90 +VA = 2.7 V -85 -80 0 20 40 60 80 fi - Input Frequency - kHz 100 Figure 21. © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY SNR - Signal-To-Noise Ratio - dB 100 +VA = 5 V 95 +VA = 2.7 V 90 85 5V 84 80 76 72 0 60 80 20 40 fi - Input Frequency - kHz 0 100 1 2 3 Full Scale Range - V 4 2.7 V 5V 84 80 76 72 5 0 1 2 3 Full Scale Range - V 4 5 Figure 22. Figure 23. Figure 24. TOTAL HARMONIC DISTORTION vs FULL-SCALE RANGE SPURIOUS-FREE DYNAMIC RANGE vs FULL-SCALE RANGE TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE SFDR - Spurious Free Dynamic Range - dB -100 10 kHz Input 2.7 V -96 5V -92 -88 0 1 2 3 Full Scale Range - V 4 102 -100 10 KHz 100 2.7 V 98 5V 96 94 92 +VA = 2.7 V, 10 kHz Input -98 +VA = 5 V, 100 kHz Input -96 90 5 0 1 2 3 4 Full Scale Range - V -94 20 35 50 65 -40 -25 -10 5 TA - Free-Air Temperature - °C 5 Figure 25. Figure 26. Figure 27. SPURIOUS-FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE 92 102 +VA = 5 V, 100 kHz Input SNR - Signal-To-Noise Ratio - dB THD - Total Harmonic Distortion -dB 2.7 V 10 kHz Input 88 THD - Total Harmonic Distortion - dB 80 88 SINAD - Signal-To-Noise and Distortion - dB SFDR - Spurious Free Dynamic Range - dB 10 kHz Input 105 92 SINAD - Signal-To-Noise and Distortion - dB 92 110 SFDR - Spurious Free Dynamic Range - dB SIGNAL-TO-NOISE AND DISTORTION vs FULL-SCALE RANGE SIGNAL-TO-NOISE RATIO vs FULL-SCALE RANGE +VA = 2.7 V, 10 kHz Input 100 +VA = 5 V, 100 kHz Input 98 96 94 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C Figure 28. 80 91 90 89 +VA = 2.7 V, 10 kHz Input 88 87 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 29. 92 91 +VA =5 V, 100 kHz Input 90 89 +VA = 2.7 V, 10 kHz Input 88 87 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C Product Folder Link(s): ADS8327 ADS8328 80 Figure 30. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated 80 17 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE INTERNAL CLOCK FREQUENCY vs SUPPLY VOLTAGE INTERNAL CLOCK FREQUENCY vs FREE-AIR TEMPERATURE 14.7 +VA = 5 V, 100 kHz Input 14.5 12 Internal Clock Frequency - MHz 14.9 Internal Clock Frequency - MHz 11.8 11.6 11.4 11.2 11.0 2.7 14.3 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 3.2 11.2 3.7 4.2 4.7 5.2 +VA - Supply Voltage - V 11 -40 5.7 80 ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE 12 NAP Mode 4.6 4.1 PD Mode 300 Analog Supply Current - nA 5.1 280 260 240 220 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 200 2.7 5.2 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 10 8 6 4 2 0 2.7 5.2 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 5.2 Figure 34. Figure 35. Figure 36. ANALOG SUPPLY CURRENT vs SAMPLE RATE ANALOG SUPPLY CURRENT vs SAMPLE RATE ANALOG SUPPLY CURRENT vs FREE-AIR TEMPERATURE 6 5.5 400 Analog Supply Current - mA 5 4 +VA = 5 V 3 +VA = 2.7 V 2 1 300 +VA = 5 V 200 +VA = 2.7 V 100 200 300 400 Sample Rate - kSPS 500 600 Figure 37. 5 +VA = 5 V 4.5 4 +VA = 2.7 V 3.5 3 0 0 100 500 kSPS Sample Rate PD Mode Autonap Mode 0 -10 5 20 35 50 65 TA - Free-Air Temperature - °C ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE 320 3.6 2.7 -25 Figure 33. Analog Supply Current - mA Analog Supply Current - mA +VA = 2.7 V 11.4 Figure 32. 500 kSPS Analog Supply Current - mA 11.6 Figure 31. 5.6 18 +VA = 5 V 11.8 +VA = 2.7 V, 10 kHz Input Analog Supply Current - mA ENOB - Effective Number of Bits - bits 12 0 5 10 15 Sample Rate - kSPS 20 25 Figure 38. Submit Documentation Feedback -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 39. © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) ANALOG SUPPLY CURRENT vs FREE-AIR TEMPERATURE 0.4 Analog Supply Current - mA NAP Mode +VA = 5 V 0.3 +VA = 2.7 0.2 0.1 0 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 40. INL DNL 2 3 fi = 500 kSPS, +VA = 5 V, Vref = 4.096 V 2.5 2 fi = 500 kSPS, +VA = 5 V, Vref = 4.096 V 1.5 1.5 1 1 DNL - Bits INL - Bits 0.5 0.5 0 -0.5 0 -0.5 -1 -1 -1.5 -2 -1.5 -2.5 -3 -2 0 10000 20000 30000 40000 Code 50000 60000 70000 0 10000 20000 30000 40000 50000 60000 70000 Code Figure 41. Figure 42. INL DNL 2 3 fi = 500 kSPS, +VA = 2.7 V, Vref = 2.5 V 2.5 2 fi = 500 kSPS, +VA = 2.7 V, Vref = 2.5 V 1.5 1.5 1 1 DNL - Bits INL - Bits 0.5 0.5 0 0 -0.5 -0.5 -1 -1.5 -1 -2 -1.5 -2.5 3 -2 0 10000 20000 30000 40000 50000 60000 70000 0 10000 Code Figure 43. 20000 30000 40000 Code 50000 60000 70000 Figure 44. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 19 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) FFT FFT 0 0 1 kHz Input,+VA = 2.7 V, Vref = 2.5 V, fs = 500 kSPS -20 -40 -40 Amplitude - dB Amplitude - dB 10 kHz Input,+VA = 2.7 V, Vref = 2.5 V, fs = 500 kSPS -20 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 50 100 150 f - Frequency - kHz 200 250 0 50 Figure 45. 100 150 f - Frequency - kHz FFT 200 250 FFT 0 100 kHz Input, +VA = 2.7 V, Vref = 2.5 V, fs = 500 kSPS -20 1 kHz Input,+VA = 5 V, Vref = 4.096 V, fs = 500 kSPS -20 -40 Amplitude - dB -40 Amplitude - dB 250 Figure 46. 0 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 50 100 150 200 250 0 50 100 150 f - Frequency - kHz f - Frequency - kHz Figure 47. 20 200 Figure 48. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) FFT FFT 0 0 10 kHz Input,+VA = 5 V, Vref = 4.096 V, fs = 500 kSPS 100 kHz Input,+VA = 5 V, Vref = 4.096 V, fs = 500 kSPS -20 -40 -40 -60 -60 Amplitude - dB Amplitude - dB -20 -80 -100 -80 -100 -120 -120 -140 -140 -160 -160 0 50 100 150 f - Frequency - kHz 200 250 0 50 Figure 49. 100 150 f - Frequency - kHz 200 250 Figure 50. THEORY OF OPERATION The ADS8327/28 is a high-speed, low power, successive approximation register (SAR) analog-to-digital converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently includes a sample/hold function. The ADS8327/28 has an internal clock that is used to run the conversion but can also be programmed to run the conversion based on the external serial clock, SCLK. The ADS8327 has one analog input. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both +IN and –IN inputs are disconnected from any internal function. The ADS8328 has two inputs. Both inputs share the same common pin—COM. The negative input is the same as the –IN pin for the ADS8327. The ADS8328 can be programmed to select a channel manually or can be programmed into the auto channel select mode to sweep between channel 0 and 1 automatically. ANALOG INPUT When the converter enters hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The voltage on the –IN input is limited between AGND – 0.2 V and AGND + 0.2 V, allowing the input to reject small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to VREF + 0.2 V. The input span (+IN – (–IN)) is limited to 0 V to VREF. The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the ADS8327/28 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (45 pF) to a 16-bit settling level within the minimum acquisition time (238 ns). When the converter goes into hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN and –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may result in an offset error, gain error, and linearity error which change with temperature and input voltage. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 21 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Device in Hold Mode 40 pF 150 W +IN 4 pF +VA AGND 4 pF 40 pF 150 W −IN AGND Figure 51. Input Equivalent Circuit Driver Amplifier Choice The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031 or OPA365 . An RC filter is recommended at the input pins to low-pass filter the noise from the source. Two resistors of 20Ω and a capacitor of 470 pF is recommended. The input to the converter is a unipolar input voltage in the range 0 V to VREF. The minimum -3dB bandwidth of the driving operational amplifier can be calculated to: f3db = (ln(2) ×(n+1))/(2p × tACQ) where n is equal to 16, the resolution of the ADC (in the case of the ADS8327/28). When tACQ = 238 ns (minimum acquisition time), the minimum bandwidth of the driving amplifier is 7.9 MHz. The bandwidth can be relaxed if the acquisition time is increased by the application. The OPA365, OPA827, or THS4031 from Texas Instruments are recommended. The THS4031 used in the source follower configuration to drive the converter is shown in the typical input drive configuration, Figure 52. For the ADS8330, a series resistor of 0Ω should be used on the COM input (or no resistor at all). Bipolar to Unipolar Driver In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional DC bias applied to its + input so as to keep the input to the ADS8327/28 within its rated operating voltage range. This configuration is also recommended when the ADS8327/28 is used in signal processing applications where good SNR and THD performance is required. The DC bias can be derived from the REF3225 or the REF3240 reference voltage ICs. The input configuration shown in Figure 53 is capable of delivering better than 91-dB SNR and –96-dB THD at an input frequency of 10 kHz. In case bandpass filters are used to filter the input, care should be taken to ensure that the signal swing at the input of the bandpass filter is small so as to keep the distortion introduced by the filter minimal. In such cases, the gain of the circuit shown in Figure 53 can be increased to keep the input to the ADS8327/28 large to keep the SNR of the system high. Note that the gain of the system from the + input to the output of the THS4031 in such a configuration is a function of the gain of the AC signal. A resistor divider can be used to scale the output of the REF3225 or REF3240 to reduce the voltage at the DC input to THS4031 to keep the voltage at the input of the converter within its rated operating range. 5V ADS8327 +VA Input Signal (0 V to 4 V) 20 W THS4031 +IN 470 pF -IN 50 W 20 W Figure 52. Unipolar Input Drive Configuration 22 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com 5V ADS8327 +VA 1 VDC 20 W THS4031 Input Signal (-2V to 2 V) +IN 600 W 470 pF -IN 600 W 20 W Figure 53. Bipolar Input Drive Configuration REFERENCE The ADS8327/28 can operate with an external reference with a range from 0.3 V to 4.2 V. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF3240 can be used to drive this pin. A 10-mF ceramic decoupling capacitor is required between the REF+ and REF– pins of the converter. These capacitors should be placed as close as possible to the pins of the device. REF– should be connected to its own via to the analog ground plane with the shortest possible distance. CONVERTER OPERATION The ADS8327/28 has an oscillator that is used as an internal clock which controls the conversion rate. The frequency of this clock is 10.5 MHz minimum. The oscillator is always on unless the device is in the deep power-down state or the device is programmed for using SCLK as the conversion clock (CCLK). The minimum acquisition (sampling) time takes 3 CCLKs (this is equivalent to 238 ns at 12.6 MHz) and the conversion time takes 18 conversion clocks (CCLK) (~1500 ns) to complete one conversion. The conversion can also be programmed to run based on the external serial clock, SCLK, if is so desired. This allows a system designer to achieve system synchronization. The serial clock SCLK, is first reduced to 1/2 of its frequency before it is used as the conversion clock (CCLK). For example, with a 21-MHz SCLK this provides a 10.5-MHz clock for conversions. If it is desired to start a conversion at a specific rising edge of the SCLK when the external SCLK is programmed as the source of the conversion clock (CCLK) (and manual start of conversion is selected), the setup time between CONVST and that rising SCLK edge should be observed. This ensures the conversion is complete in 18 CCLKs (or 36 SCLKs). The minimum setup time is 20 ns to ensure synchronization between CONVST and SCLK. In many cases the conversion can start one SCLK period (or CCLK) later which results in a 19 CCLK (or 37 SCLK) conversion. The 20 ns setup time is not required once synchronization is relaxed. The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirements of 8 ns. Since the ADS8327/28 is designed for high-speed applications, a higher serial clock (SCLK) must be supplied to be able to sustain the high throughput with the serial interface and so the clock period of SCLK must be at most 1 ms (when used as conversion clock (CCLK). The minimum clock frequency is also governed by the parasitic leakage of the capacitive digital-to-analog (CDAC) capacitors internal to the ADS8327/28. CFR_D10 Conversion Clock (CCLK) =1 OSC =0 Divider 1/2 SPI Serial Clock (SCLK) Figure 54. Converter Clock Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 23 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Manual Channel Select Mode The conversion cycle starts with selecting an acquisition channel by writing a channel number to the command register (CMR). This cycle time can be as short as 4 serial clocks (SCLK). Auto Channel Select Mode Channel selection can also be done automatically if auto channel select mode is enabled. This is the default channel select mode. The dual channel converter, ADS8328, has a built-in 2-to-1 MUX. If the device is programmed for auto channel select mode then signals from channel 0 and channel 1 are acquired with a fixed order. Channel 0 is accessed first in the next cycle after the command cycle that configured CFR_D11 to 1 for auto channel select mode. This automatic access stops the cycle after the command cycle that sets CFR_D11 to '0'. Start of a Conversion The end of acquisition or sampling instance (EOS) is the same as the start of a conversion. This is initiated by bringing the CONVST pin low for a minimum of 40 ns. After the minimum requirement has been met, the CONVST pin can be brought high. CONVST acts independent of FS/CS so it is possible to use one common CONVST for applications requiring simultaneous sample/hold with multiple converters. The ADS8327/28 switches from sample to hold mode on the falling edge of the CONVST signal. The ADS8327/28 requires 18 conversion clock (CCLK) edges to complete a conversion. The conversion time is equivalent to 1500 ns with a 12-MHz internal clock. The minimum time between two consecutive CONVST signals is 21 CCLKs. A conversion can also be initiated without using CONVST if it is so programmed (CFR_D9 = 0). When the converter is configured as auto trigger, the next conversion is automatically started three conversion clocks (CCLK) after the end of a conversion. These three conversion clocks (CCLK) are used as the acquisition time. In this case the time to complete one acquisition and conversion cycle is 21 CCLKs. Table 2. Different Types of Conversion MODE SELECT CHANNEL Auto Channel Select (1) Automatic No need to write channel number to the CMR. Use internal sequencer for the ADS8328. Manual (1) Manual Channel Select Write the channel number to the CMR. START CONVERSION Auto Trigger Start a conversion based on the conversion clock CCLK. Manual Trigger Start a conversion with CONVST. Auto channel select should be used with auto trigger and also with the TAG bit enabled. Status Output EOC/INT When the status pin is programmed as EOC and the polarity is set as active low, the pin works in the following manner: The EOC output goes LOW immediately following CONVST going LOW when manual trigger is programmed. EOC stays LOW throughout the conversion process and returns to HIGH when the conversion has ended. The EOC output goes low for three conversion clocks (CCLK) after the previous rising edge of EOC, if auto trigger is programmed. This status pin is programmable. It can be used as an EOC output (CFR.D[7:6] = 1, 1) where the low time is equal to the conversion time. This status pin can be used as INT. (CFR.D[7:6] = 1, 0) which is set LOW at the end of a conversion is brought to HIGH (cleared) by the next read cycle. The polarity of this pin, used as either function (EOC or INT), is programmable through CFR_D7. 24 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Power-Down Modes The ADS8327/28 has a comprehensive built-in power-down feature. There are three power-down modes: Deep power-down mode, Nap power-down mode, and auto nap power-down mode. All three power-down modes are enabled by setting the related CFR bits. The first two power-down modes are activated when enabled. A wakeup command, 1011b, can resume device operation from a power-down mode. Auto nap power-down mode works slightly different. When the converter is enabled in auto nap power-down mode, an end of conversion instance (EOC) puts the device into auto nap power-down. The beginning of sampling resumes operation of the converter. The contents of the configuration register is not affected by any of the power-down modes. Any ongoing conversion when nap or deep power-down is activated is aborted. +VA − Supply Current − mA 100 10 1 0.1 20 10020 20020 30020 40020 Settling Time − ns Figure 55. Typical Analog Supply Current Drop versus Time After Power-Down Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 25 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Deep Power-Down Mode Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in deep power-down mode, all blocks except the interface are in power-down. The external SCLK is blocked to the analog block. The analog blocks no longer have bias currents and the internal oscillator is turned off. In this mode, supply current falls from 5 mA to 6 nA in 100 ns. The wake-up time after a power-down is 1 ms. When bit D2 in the configuration register is set to 0, the device is in deep power-down. Setting this bit to '1' or sending a wake-up command can resume the converter from the deep power-down state. Nap Mode In nap mode the ADS8327/28 turns off biasing of the comparator and the mid-volt buffer. In this mode supply current falls from 5 mA in normal mode to about 0.3 mA in 200 ns after the configuration cycle. The wake-up (resume) time from nap power-down mode is 3 CCLKs (238 ns with a 12.6-MHz conversion clock). As soon as the CFR_D3 bit in the control register is set to '0', the device goes into nap power-down mode, regardless of the conversion state. Setting this bit to '1' or sending a wake-up command can resume the converter from the nap power-down state. Auto Nap Mode Auto nap mode is almost identical to nap mode. The only difference is the time when the device is actually powered down and the method to wake up the device. Configuration register bit D4 is only used to enable/disable auto nap mode. If auto nap mode is enabled, the device turns off biasing after the conversion has finished, which means the end of conversion activates auto nap power-down mode. The supply current falls from 5 mA in normal mode to about 0.3 mA in 200 ns. A CONVST resumes the device and turns biasing on again in 3 CCLKs (238 ns with a 12.6-MHz conversion clock). The device can also be woken up by disabling auto nap mode when bit D4 of the configuration register is set to '1'. Any channel select command 0XXXb, wake-up command, or the set default mode command 1111b can also wake up the device from auto nap power-down. NOTE 1. This wake-up command is the word 1011b in the command word. This command sets bits D2 and D3 to 1 in the configuration register but not D4. But a wake-up command does remove the device from either one of these power-down states, deep/nap/auto nap power-down. 2. Wake-up time is defined as the time between when the host processor tries to wake up the converter and when a convert start can occur. Table 3. Power-Down Mode Comparisons TYPE OF POWER-DOWN POWER CONSUMPTION Normal operation 5 mA/3.8 mA Deep power-down 6 nA/2 nA Nap power-down Auto nap power-down 26 0.3 mA/0.2 mA ACTIVATED BY Setting CFR Setting CFR EOC (end of conversion) ACTIVATION TIME RESUME POWER BY RESUME TIME ENABLE 100 ns Woken up by command 1011b 1 ms Set CFR 200 ns Woken up by command 1011b to achieve 6.6 mA since (1.3 + 12)/2 = 6.6 3 CCLKs Set CFR 200 ns Woken up by CONVST, any channel select command, default command 1111b, or wake up command 1011b. 3 CCLKs Set CFR Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com EOS EOC EOS Converter State N+1 Converter State EOC N CONVST N+1 −th Sampling N −th Conversion N+1 −th Conversion Read While Converting 20 ns MIN 1 CCLK MIN CS (For Read Result) Read N−1 −th Result Read While Sampling 0 ns MIN 20 ns MIN CS (For Read Result) Read N −th Result Figure 56. Read While Converting versus Read While Sampling (Manual trigger) Manual Trigger Converter State Resume N −th Sampling >=3CCLK N −th Conversion Activation Resume =18 CCLK N+1 −th Sampling >=3CCLK EOC EOC EOS N+1 EOS N CONVST N+1 −th Conversion Activation =18 CCLK 20 ns MIN 20 ns MIN 1 CCLK MIN Read While Converting Read N−1 −th CS Read N −th Result Result 20 ns MIN 20 ns MIN Read While Sampling Read N−1 −th CS 20 ns MIN 0 ns MIN 20 ns MIN Read N −th Result Result 20 ns MIN 20 ns MIN Figure 57. Read While Converting versus Read While Sampling with Deep or Nap Power-Down Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 27 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com 40 ns MIN Manual Trigger Case 1 N N+1 Converter State Resume N −th Sampling EOS POWERDOWN N −th Conversion >=3CCLK Resume =18 CCLK EOC EOS EOC (programmed Active Low) EOC CONVST N+1 −th Sampling N+1 −th Conversion >=3CCLK =18 CCLK 6 CCLKs POWERDOWN 6 CCLKs Read While Converting 20 ns MIN 20 ns MIN Read N −th Result Read N−1 −th Result CS 20 ns MIN 20 ns MIN 1 CCLK MIN Read While Sampling 1 CCLK MIN 0 ns MIN Read N −th Result Read N−1 −th Result CS 20 ns MIN 20 ns MIN 40 ns MIN Manual Trigger Case 2 (wake up by CONVST) N+1 Converter State N −th Sampling >=3CCLK N −th Conversion POWER DOWN Resume N+1 −th Sampling >=3CCLK =18 CCLK EOC EOS Resume EOS N EOC (programmed Active Low) EOC CONVST N+1 −th Conversion POWER DOWN =18 CCLK Read While Converting 20 ns MIN CS 20 ns MIN Read While Sampling 20 ns MIN 20 ns MIN CS 20 ns MIN Read N −th Result Read N−1 −th Result 0 ns MIN 20 ns MIN Read N −th Result Read N−1 −th Result 20 ns MIN 20 ns MIN Figure 58. Read While Converting versus Read While Sampling with Auto Nap Power-Down 28 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Total Acquisition + Conversion Cycle Time: Automatic: = 21 CCLKs Manual: ≥ 21 CCLKs Manual + deep power-down: ≥ 4SCLK + 100 ms + 3 CCLK + 18 CCLK +16 SCLK + 1 ms Manual + nap power-down: ≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK Manual + auto nap power-down: ≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use wakeup to resume) Manual + auto nap power-down: ≥ 1 CCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use CONVST to resume) DIGITAL INTERFACE The serial clock is designed to accommodate the latest high-speed processors with an SCLK frequency up to 50 MHz. Each cycle is started with the falling edge of FS/CS. The internal data register content which is made available to the output register at the EOC is presented on the SDO output pin at the falling edge of FS/CS. This is the MSB. Output data are valid at the falling edge of SCLK with td(SCLKF–SDOVALID) delay so that the host processor can read it at the falling edge. Serial data input is also read with the falling edge of SCLK. The complete serial I/O cycle starts with the first falling edge of SCLK after the falling edge of FS/CS and ends 16 (see NOTE) falling edges of SCLK later. The serial interface is very flexible. It works with CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0. This means the falling edge of FS/CS may fall while SCLK is high. The same relaxation applies to the rising edge of FS/CS where SCLK may be high or low as long as the last SCLK falling edge happens before the rising edge of FS/CS. NOTE There are cases where a cycle is four SCLKs or up to 24 SCLKs depending on the read mode combination. See Table 4 for details. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 29 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Internal Register The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration data register (CFR). Table 4. Command Set Defined by Command Register (CMR) (1) D[15:12] HEX COMMAND D[11:0] (2) WAKE UP FROM AUTO NAP MINIMUM SCLKs REQUIRED R/W 0000b 0h Select analog input channel 0 Don't care Y 4 W 0001b 1h Select analog input channel 1 (2) Don't care Y 4 W 0010b 2h Reserved Reserved – – – 0011b 3h Reserved Reserved – – – 0100b 4h Reserved Reserved – – – 0101b 5h Reserved Reserved – – – 0110b 6h Reserved Reserved – – – 0111b 7h Reserved Reserved – – – 1000b 8h Reserved Reserved – – – 1001b 9h Reserved Reserved – – – 1010b Ah Reserved Reserved – – – 1011b Bh Wake up Don't care Y 4 W 1100b Ch Read CFR Don't care – 16 R 1101b Dh Read data Don't care – 16 R 1110 Eh Write CFR CFR Value – 16 W 1111b Fh Default mode (load CFR with default value) Don't care Y 4 W (1) (2) When SDO is not in 3-state (FS/CS low and SCLK running), the bits from SDO are always part (depending on how many SCLKs are supplied) of the previous conversion result. These two commands apply to the ADS8328 only. WRITING TO THE CONVERTER There are two different types of writes to the register, a 4-bit write to the CMR and a full 16-bit write to the CMR plus CFR. The command set is listed in Table 4. A simple command requires only 4 SCLKs and the write takes effect at the 4th falling edge of SCLK. A 16-bit write or read takes at least 16 SCLKs (see Table 7 for exceptions that require more than 16 SCLKs). Configuring the Converter and Default Mode The converter can be configuring with command 1110b (write to the CFR) or command 1111b (default mode). A write to the CFR requires a 4-bit command followed by 12-bits of data. A 4-bit command takes effect at the fourth falling edge of SCLK. A CFR write takes effect at the 16th falling edge of SCLK. A default mode command can be achieved by simply tying SDI to +VBD. As soon as the chip is selected at least four 1s are clocked in by SCLK. The default value of the CFR is loaded into the CFR at the 4th falling edge of SCLK. CFR default values are all 1s (except for CFR_D1, this bit is ignored by the ADS8327 and is always read as a 0). The same default values apply for the CFR after a power-on reset (POR) and SW reset. 30 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com READING THE CONFIGURATION REGISTER The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is similar to reading a conversion result except CONVST is not used and there is no activity on the EOC/INT pin. The CFR value read back contains the first four MSBs of conversion data plus valid 12-bit CFR contents. Table 5. Configuration Register (CFR) Map SDI BIT DEFINITION CFR – D[11 – 0] Channel select mode D11 Default = 1 D10 Default = 1 D9 Default = 1 D8 Default = 0 D7 Default = 1 D6 Default = 1 D5 Default = 1 D4 Default = 1 D3 Default = 1 D2 Default = 1 D1 Default = 0: ADS8327 1: ADS8328 D0 Default = 1 0: Manual channel select enabled. Use channel select commands to access a different channel. 1: Auto channel select enabled. All channels are sampled and converted sequentially until the cycle after this bit is set to 0. Conversion clock (CCLK) source select 0: Conversion clock (CCLK) = SCLK/2 1: Conversion clock (CCLK) = Internal OSC Trigger (conversion start) select: start conversion at the end of sampling (EOS). If D9 = 0, the D4 setting is ignored. 0: Auto trigger automatically starts (4 internal clocks after EOC inactive) 1: Manual trigger manually started by falling edge of CONVST Don't care Don't care Pin 10 polarity select when used as an output (EOC/INT) 0: EOC Active high/INT active high 1: EOC Active low/INT active low Pin 10 function select when used as an output (EOC/INT) 0: Pin used as INT 1: Pin used as EOC Pin 10 I/O select for chain mode operation 0: Pin 10 is used as CDI input (chain mode enabled) 1: Pin 10 is used as EOC/INT output Auto nap power-down enable/disable (mid voltage and comparator shut down between cycles). This bit setting is ignored if D9 = 0. 0: Auto nap power-down enabled (not activated) 1: Auto nap power-down disabled Nap power-down (mid voltage and comparator shut down between cycles). This bit is set to 1 automatically by wake-up command. 0: Enable/activate device in nap power-down 1: Remove device from nap power-down (resume) Deep power-down. This bit is set to 1 automatically by wake-up command. 0: Enable/activate device in deep power-down 1: Remove device from deep power-down (resume) TAG bit enable. This bit is ignored by the ADS8327 and is always read 0. 0: TAG bit disabled. 1: TAG bit output enabled. TAG bit appears at the 17th SCLK. Reset 0: System reset 1: Normal operation READING CONVERSION RESULT The conversion result is available to the input of the output data register (ODR) at EOC and presented to the output of the output register at the next falling edge of CS or FS. The host processor can then shift the data out via the SDO pin any time except during the quiet zone. This is 20 ns before and 20 ns after the end of sampling (EOS) period. End of sampling (EOS) is defined as the falling edge of CONVST when manual trigger is used or the end of the 3rd conversion clock (CCLK) after EOC if auto trigger is used. The falling edge of FS/CS should not be placed at the precise moment (minimum of at least one conversion clock (CCLK) delay) at the end of a conversion (by default when EOC goes high), otherwise the data are corrupt. If FS/CS is placed before the end of a conversion, the previous conversion result is read. If FS/CS is placed after the end of a conversion, the current conversion result is read. The conversion result is 16-bit data in straight binary format as shown in Table 5. Generally 16 SCLKs are necessary, but there are exceptions where more than 16 SCLKS are required (see Table 7). Data output from the serial output (SDO) is left adjusted MSB first. The trailing bits are filled with the TAG bit first (if enabled) plus all zeros. SDO remains low until FS/CS is brought high again. SDO is active when FS/CS is low. The rising edge of FS/CS 3-states the SDO output. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 31 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com NOTE Whenever SDO is not in 3-state (when FS/CS is low and SCLK is running), a portion of the conversion result is output at the SDO pin. The number of bits depends on how many SCLKs are supplied. For example, a manual select channel command cycle requires 4 SCLKs, therefore 4 MSBs of the conversion result are output at SDO. The exception is SDO outputs all 1s during the cycle immediately after any reset (POR or software reset). If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out all 16 SDO bits during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case it is better to read the conversion result during the conversion time (36 SCLKs or 48 SCLKs in auto nap mode). Table 6. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full scale range VREF STRAIGHT BINARY Least significant bit (LSB) VREF/65536 Full scale +VREF – 1 LSB 1111 1111 1111 1111 FFFF Midscale VREF/2 1000 0000 0000 0000 8000 Midscale – 1 LSB VREF/2– 1 LSB 0111 1111 1111 1111 7FFF Zero 0V 0000 0000 0000 0000 0000 BINARY CODE HEX CODE TAG Mode The ADS8328 includes a feature, TAG, that can be used as a tag to indicate which channel sourced the converted result. An address bit is added after the LSB read out from SDO indicating which channel the result came from if TAG mode is enabled. This address bit is 0 for channel 0 and 1 for channel 1. The converter requires more than the 16 SCLKs that are required for a 4 bit command plus 12 bit CFR or 16 data bits because of the additional TAG bit. Chain Mode The ADS8327/28 can operate as a single converter or in a system with multiple converters. System designers can take advantage of the simple high-speed SPI compatible serial interface by cascading them in a single chain when multiple converters are used. A bit in the CFR is used to reconfigure the EOC/INT status pin as a secondary serial data input, chain data input (CDI), for the conversion result from an upstream converter. This is chain mode operation. A typical connection of three converters is shown in Figure 59. Micro Controller INT GPIO1 GPIO2 SDI SCLK CONVST CS ADS8327 #1 SDO EOC/INT Program Device #1 CFR_D5 = 1 GPIO3 SDI SCLK CONVST CS ADS8327 #2 SDO CDI SDOSCLK SDI SDI SCLK CONVST CS ADS8327 #3 CDI SDO Program Devices #2 and #3 CFR_D5 = 0 Figure 59. Multiple Converters Connected Using Chain Mode 32 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com When multiple converters are used in chain mode, the first converter is configured in regular mode while the rest of the converters downstream are configured in chain mode. When a converter is configured in chain mode, the CDI input data goes straight to the output register, therefore the serial input data passes through the converter with a 16 SCLK (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active. See Figure 60 for detailed timing. In this timing the conversion in each converters are done simultaneously. INT #3 (active low) Nth EOS EOC #1 (active low) EOC CONVST #1, CONVST #2, CONVST #3 EOS Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC active low, and INT active low) CS held low during the N times 16 bits transfer cycle. tSAMPLE1 = 3 CCLKs min tCONV = 18 CCLKs td(CSR-EOS) = 20 ns min CS/FS #1 SCLK #1, SCLK #2, SCLK #3 SDO #1, CDI #2 1 . . . . . . . . . . . . . . . . . . 16 1 . . . . . . . . . . . . . . . . . . 16 Hi-Z Nth from #1 td(CSR-EOS) = 20 ns min CS/FS #2, CS/FS #3 SDO #2, CDI #3 SDO #3 1 . . . . . . . . . . . . . . . . . . 16 Hi-Z Hi-Z td(SDO-CDI) Hi-Z Nth from #2 Hi-Z Nth from #1 Hi-Z Nth from #3 SDI #1, SDI #2, SDI #3 Nth from #1 td(SDO-CDI) 1110............ CONFIGURE Nth from #2 1101b READ Result Nth from #1 1101b READ Result Figure 60. Simplified Cascade Mode Timing with Shared CONVST and Continuous CS Care must be given to handle the multiple CS signals when the converters are operating in chain mode. The different chip select signals must be low for the entire data transfer (in this example 48 bits for three converters). The first 16-bit word after the falling chip select is always the data from the chip that received the chip select signal. Case 1: If chip select is not toggled (CS stays low), the next 16 bits are data from the upstream converter, and so on. This is shown in Figure 60. If there is no upstream converter in the chain, as converter #1 in the example, the same data from the converter is going to be shown repeatedly. Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in Figure 61, the same data from the converter is read out again and again in all three discrete 16-bit cycles. This is not a desired result. Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 33 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com INT #1 (active low) Nth EOS EOC #1 (active low) EOC CONVST #1, CONVST #2, CONVST #3 EOS Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC, and INT polarity programmed as active low) CS held low during the N times 16 bits transfer cycle. tSAMPLE1 = 3 CCLKs min td(EOS-CSF) = 20 ns min tCONV = 18 CCLKs td(CSR-EOS) = 20 ns min CS/FS #1 SCLK #1, SCLK #2, SCLK #3 16 1 SDO #1, CDI #2 1 16 Nth from #1 CS/FS #2 SCLK #2, SDO #2, CDI #3 Nth from #2 CS/FS #3 1 16 Nth from #1 Nth from #1 td(EOS-CSF) = td(CSR-EOS) = 20 ns min 20 ns min Nth from #1 td(EOS-CSF) = 20 ns min Nth from #1 td(CSR-EOS) = 20 ns min SDO #3 SDI #1, SDI #2, SDI #3 Nth from #2 Nth from #3 1110............ CONFIGURE 1101b READ Result Nth from #1 1101b READ Result Figure 61. Simplified Cascade Mode Timing with Shared CONVST and Discrete CS Figure 62 shows a slightly different scenario where CONVST is not shared by the second converter. Converters #1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data downstream. 34 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC active low and INT active low) CS held low during the N times 16 bits transfer cycle. Note : old data shown. INT #1 (active low) Nth EOS EOC #1 (active low) EOC CONVST #2 = 1 EOS CONVST #1, CONVST #3 tSAMPLE1 = 3 CCLKs min tCONV = 18 CCLKs td(CSR-EOS) = 20 ns min CS/FS #1 SCLK #1, SCLK #2, SCLK #3 1 . . . . . . . . . . . . . . . . . .16 1 . . . . . . . . . . . . . . . . . .16 1 . . . . . . . . . . . . . . . . . .16 Hi-Z SDO #1, CDI #2 Hi-Z Nth from #1 td(CSR-EOS) = 20 ns min CS/FS #2, CS/FS #3 td(SDO-CDI) SDO #2, CDI #3 Hi-Z SDO #3 Hi-Z Hi-Z Nth from #1 N − 1th from #2 SDI #1, SDI #2, SDI #3 td(SDO-CDI) Hi-Z N − 1th from #2 Nth from #3 1110............ CONFIGURE Nth from #1 1101b 1101b READ Result READ Result Figure 62. Simplified Cascade Timing (Separate CONVST) The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG bit, chain mode, and the way a channel is selected, i.e., auto channel select. This is listed in Table 7. Table 7. Required SCLKs For Different Read Out Mode Combinations CHAIN MODE AUTO CHANNEL ENABLED CFR.D5 SELECT CFR.D11 TAG ENABLED CFR.D1 NUMBER OF SCLK PER SPI READ TRAILING BITS 0 0 0 16 None 0 0 1 ≥17 MSB is TAG bit plus zero(s) 0 1 0 16 None 0 1 1 ≥17 TAG bit plus 7 zeros 1 0 0 16 None 1 0 1 24 TAG bit plus 7 zeros 1 1 0 16 None 1 1 1 24 TAG bit plus 7 zeros Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 35 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com SCLK skew between converters and data path delay through the converters configured in chain mode can affect the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be necessary to slow down the SCLK when the devices are configured in chain mode. ADS 8327 # 3 CDI SDO Logic D Delay < = 8 .3 ns Logic Delay Plus PAD 2.7 ns Serial data output Logic Delay Plus PAD 8.3 ns Q CLK ADS 8327 # 2 SDO CDI Logic D Delay < = 8 .3 ns Logic Delay Plus PAD 2.7 ns Logic Delay Plus PAD 8.3 ns Q CLK ADS 8327 # 1 CDI Serial data input SDO Logic D Delay < = 8 .3 ns Logic Delay Plus PAD 2.7 ns Logic Delay Plus PAD 8.3 ns Q CLK SCLK input Figure 63. Typical Delay Through Converters Configured in Chain Mode RESET The converter has two reset mechanisms, a power-on reset (POR) and a software reset using CFR_D0. These two mechanisms are NOR-ed internally. When a reset (software or POR) is issued, all register data are set to the default values (all 1s) and the SDO output (during the cycle immediately after reset) is set to all 1s. The state machine is reset to the power-on state. SW RESET CDI POR SET SAR Shift Register Intermediate Latch Output Register Conversion Clock Latched by End Of Conversion SDO SCLK Latched by Falling Edge of CS CS EOC EOC Figure 64. Digital Output Under Reset Condition 36 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com When the device is powered up, the POR sets the device in default mode when AVDD reaches 1.5 V. When the device is powered down, the POR circuit requires AVDD to remain below 125 mV for a duration of at least 350 ms to ensure proper discharging of internal capacitors and to correct the behavior of the device when powered up again. If AVDD drops below 400 mV but remains above 125 mV, the internal POR capacitor does not discharge fully and the device requires a software reset to perform correctly after the recovery of AVDD (this is shown as the undefined zone in Figure 65). AVDD (V) 5.500 5.000 Specified Supply Voltage Range 4.000 3.000 2.700 2.000 POR Trigger Level 1.500 1.000 0.400 0.125 Undefined Zone 0 0.350 t (s) Figure 65. Relevant Voltage Levels for POR Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 37 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com APPLICATION INFORMATION TYPICAL CONNECTION Analog +5 V 4.7 mF AGND Ext Ref Input 10 mF Analog Input AGND +VA REF+ REF− AGND IN+ IN− Host Processor FS/CS SDO SDI SCLK Interface Supply +1.8 V ADS8327 BDGND CONVST 4.7 mF EOC/INT +VBD Figure 66. Typical Circuit Configuration Part Change Notification # 20071101000 The ADS8327 and ADS8328 devices underwent a silicon change under Texas Instruments Part Change Notification (PCN) number 20071101000. Details on this part change can be obtained from the Product Information Center at Texas Instruments or by contacting your local sales/distribution office. Devices with a date code of 82xx and higher are covered by this PCN. 38 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (June 2009) to Revision E Page • Updated Figure 60 .............................................................................................................................................................. 33 • Updated Figure 61 .............................................................................................................................................................. 34 Changes from Revision C (March 2008) to Revision D Page • Added +REF to AGND and –REF to AGND specifications to Absolute Maximum Ratings table ........................................ 3 • Revised conditions of 2.7 V to 3.6 V Specifications table to +VA = 2.7 V to 3.6 V and +VDB = 1.65 V to 1.5 × (+VA) ...... 4 • Revised conditions of 2.7 V to 3.6 V Specifications table to +VA = 2.7 V to 3.6 V and +VDB = 1.65 V to 1.5 × (+VA) ...... 5 • Changed test condition of Supply current, Nap mode row to NAP/Auto-NAP mode in 2.7 V to 3.6 V Specifications table ...................................................................................................................................................................................... 5 • Changed test condition of Supply current, PD Mode row to Deep power-down mode in Specifications table .................... 5 • Revised conditions of 4.5 V to 5.5 V Specifications table to read +VA = 4.5 V to 5.5 V and +VDB = 1.65 V to 5.5 V ........ 6 • Revised conditions of 4.5 V to 5.5 V Specifications table to read +VA = 4.5 V to 5.5 V and +VDB = 1.65 V to 5.5 V ........ 7 • Changed test condition of Supply current, Nap mode row to NAP/Auto-NAP mode in 4.5 V to 5.5 V Specifications table ...................................................................................................................................................................................... 7 • Changed test condition of Supply current, PD Mode row to Deep power-down mode in 4.5 V to 5.5 V Specifications table ...................................................................................................................................................................................... 7 • Corrected typo in Figure 1 .................................................................................................................................................. 12 • Updated SDO trace in Figure 2 .......................................................................................................................................... 12 • Changed N – 1th to N + 1st in CONVST trace of Figure 3 ................................................................................................ 13 • Corrected EOC and SDO traces in Figure 4 ...................................................................................................................... 13 • Added last sentence to Driver Amplifier Choice section ..................................................................................................... 22 • Updated Figure 52 .............................................................................................................................................................. 22 • Updated Figure 53 .............................................................................................................................................................. 23 • Changed fifth sentence of the Deep Power-Down Mode section ....................................................................................... 26 • Changed second sentence of Nap Mode section ............................................................................................................... 26 • Changed fifth sentence of Auto Nap Mode section ............................................................................................................ 26 • Changed ms to ns in Activation Time column of Table 3 .................................................................................................... 26 • Added Figure 65 and corresponding paragraph to the RESET section ............................................................................. 37 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8327 ADS8328 39 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ADS8327IBPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 8327I A B ADS8327IBPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 8327I A B ADS8327IBRSAR ACTIVE QFN RSA 16 3000 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS 8327I A Samples ADS8327IBRSAT ACTIVE QFN RSA 16 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS 8327I A Samples ADS8327IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 8327I A Samples ADS8327IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 8327I A Samples ADS8328IBPW ACTIVE TSSOP PW 16 90 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS 8328I A B ADS8328IBPWG4 ACTIVE TSSOP PW 16 90 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS 8328I A B ADS8328IBRSAT ACTIVE QFN RSA 16 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS 8328I A Samples ADS8328IPW ACTIVE TSSOP PW 16 90 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS 8328I A Samples ADS8328IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS 8328I A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of