ADS
ADS8361
836
1
AD
S83
61
SBAS230E – AUGUST 2002 – REVISED AUGUST 2007
Dual, 500kSPS, 16-Bit, 2 + 2 Channel,
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 2 SIMULTANEOUS 16-BIT DACs
● 4 FULLY DIFFERENTIAL INPUT CHANNELS
● 2μs THROUGHPUT PER CHANNEL
● 4μs TOTAL THROUGHPUT FOR FOUR CHANNELS
● LOW POWER: 150mW
● INTERNAL REFERENCE
● FLEXIBLE SERIAL INTERFACE
● 16-BIT UPGRADE TO THE 12-BIT ADS7861
● PIN COMPATIBLE WITH THE ADS7861
● OPERATING TEMPERATURE RANGE:
–40°C to +125°C
The ADS8361 is a dual, 16-bit, 500kSPS, Analog-to-Digital
(A/D) converter with four fully differential input channels grouped
into two pairs for high-speed, simultaneous signal acquisition.
Inputs to the sample-and-hold amplifiers are fully differential
and are maintained differentially to the input of the A/D converter. This provides excellent common-mode rejection of
80dB at 50kHz, which is important in high-noise environments.
The ADS8361 offers a high-speed, dual serial interface and
control inputs to minimize software overhead. The output data
for each channel is available as a 16-bit word. The ADS8361
is offered in SSOP-24 and QFN-32 (5x5) packages and is fully
specified over the –40°C to +125°C operating range.
APPLICATIONS
● MOTOR CONTROL
● MULTI-AXIS POSITIONING SYSTEMS
● 3-PHASE POWER CONTROL
CH A0+
SAR
CH A0–
COMP
SHA
SERIAL DATA A
CDAC
CH A1+
SERIAL DATA B
CH A1–
M0
M1
REFIN
Serial
Interface
Internal
2.5V
Reference
REFOUT
A0
CLOCK
CS
CH B0+
CH B0–
RD
SHA
COMP
CDAC
BUSY
CONVST
CH B1+
CH B1–
SAR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2002-2007, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted)(1).
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Supply Voltage, AGND to AVDD ............................................. –0.3V to 7V
Supply Voltage, BGND to BVDD ............................................. –0.3V to 7V
Analog Input Voltage ................................. AGND – 0.3V to AVDD + 0.3V
Reference Input Voltage ........................... AGND – 0.3V to AVDD + 0.3V
Digital Input Voltage .................................. BGND – 0.3V to BVDD + 0.3V
Ground Voltage Differences, AGND to BGND ................................ ±0.3V
Voltage Differences, BVDD to AGND ..................................... –0.3V to 7V
Input Current to Any Pin Except Supply ......................... –20mA to 20mA
Power Dissipation ....................................... See Dissipation Rating Table
Operating Virtual Junction Temperature Range, TJ ...... –40°C to +150°C
Operating Free-Air Temperature Range, TA .................. –40°C to +125°C
Storage Temperature Range, TSTG ................................ –65°C to +150°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those
indicated under Recommended Operating Conditions is not implied. Exposure
to absolute-maximum-rated conditions of extended periods may affect device
reliability.
PACKAGE/ORDERING INFORMATION(1)
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
NO MISSING
CODES
ERROR (LSB)
ADS8361
±8
ADS8361
±8
PRODUCT
"
"
"
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
14
SSOP-24
DBQ
14
QFN-32
RHB
"
"
"
"
"
"
"
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
–40°C to +125°C
ADS8361IDBQ
ADS8361IDBQR
Rails, 56
Tape and Reel, 2500
–40°C to +125°C
ADS8361IRHBT
ADS8361IRHBR
Tape and Reel, 250
Tape and Reel, 3000
"
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at
www.ti.com.
RECOMMENDED OPERATING CONDITIONS
CONDITIONS
Supply Voltage, AGND to AVDD
Supply Voltage, BGND to BVDD
Low-Voltage Levels
5V Logic Levels
Reference Input Voltage
Operating Common-Mode Signal
Analog Inputs
Operating Junction Temperature Range
–IN
+IN – (–IN)
TJ
MIN
NOM
MAX
UNITS
4.75
2.7
4.5
1.2
2.2
0
–40
5
5.25
3.6
5.5
2.6
2.8
±VREF
+105
V
V
V
V
V
V
°C
5
2.5
2.5
PACKAGE DISSIPATION RATING
PACKAGE
RθJC
RθJA
DERATING FACTOR
ABOVE TA = +25°C
TA ≤ +25°C
POWER RATING
TA ≤ +70°C
POWER RATING
TA = +85°C
POWER RATING
SSOP-24
QFN-32 (5x5)
28.5°C/W
1.007°C/W
88°C/W
36.7°C/W
11.364mW/°C
27.25mW/°C
1420mW
2725mW
909mW
1499mW
738mW
1090mW
EQUIVALENT INPUT CIRCUIT
AVDD
BVDD
RON = 20Ω
AIN
C(SAMPLE) = 25pF
DIN
AGND
BGND
Diode Turn on Voltage: 0.35V
Equivalent Analog Input Circuit
2
Equivalent Digital Input Circuit
ADS8361
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SBAS230E
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at TA = –40°C to +125°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500kSPS,
unless otherwise noted.
ADS8361
PARAMETER
CONDITIONS
ANALOG INPUT
(FSR)
Full-Scale Range(2)
Operating Common-Mode Signal
Input Switch Resistance
Input Capacitance
Input Leakage Current
Differential Input Switch Resistance
Differential Input Capacitance
Common-Mode Rejection Ratio
(CMRR)
DC ACCURACY
Resolution
No Missing Code
Integral Linearity Error
Integral Linearity Match
Differential Nonlinearity
Bipolar Offset Error
Bipolar Offset Error Match
Bipolar Offset Error Drift
Gain Error(6)
Gain Error Match
Gain Error Drift
Noise
Power-Supply Rejection Ratio
MIN
–IN = VREF
–IN = VREF
–IN = VREF
At DC
VIN = ±1.25VPP at 50kHz
TA = –40°C to +85°C
TA = –40°C to +125°C
Channel 0/1, Same A/D
(TCGERR)
(PSRR)
4.75V < AVDD < 5.25V, with
External Reference, at DC
(tCONV)
(tAQ)
100kHz ≤ fCLK ≤ 10MHz
fCLK = 10MHz
VOLTAGE REFERENCE INPUT
Reference Voltage Input
Reference Input Resistance
Reference Input Capacitance
Reference Input Current
20
25
±1
40
15
84
80
V
V
Ω
pF
nA
Ω
pF
dB
dB
±3
4
+1.5(4)
±0.5
±0.5
0.5
0.4
±0.05
0.05
20
60
–70
Bits
Bits
LSB(3)
LSB
LSB
mV
mV
mV
ppm/°C
%
%
ppm/°C
μVrms
dB
1.6
400
±8
±2
±2.5
1
±0.5
0.15
160
500
5
100
50
0.1
(THD)
(SFDR)
(SNR)
(SINAD)
VOLTAGE REFERENCE OUTPUT
Reference Voltage Ouput
(VOUT)
Initial Accuracy
Output Voltage Temperature Drift (dVOUT/dT)
Output Voltage Noise
Power-Supply Rejection Ratio
Output Current
Short-Circuit Current
Turn On Settling Time
±VREF
2.8
16
14
(TCVOS)
(GERR)
AC ACCURACY
Total Harmonic Distortion
Spurious-Free Dynamic Range
Signal-to-Noise Ratio
Signal-to-Noise + Distortion
Channel-to-Channel Isolation
UNITS
2.2
Channel 0/1, Same A/D
SAMPLING DYNAMICS
Conversion Time per A/D
Acquisition Time
Throughout Rate
Aperture Delay
Aperture Delay Matching
Aperture Jitter
Clock Frequency
MAX
+IN – (–IN)
(NMC)
(INL)
(DNL)
(VOS)
TYP(1)
(PSRR)
(IOUT)
(ISC)
VIN
VIN
VIN
VIN
VIN
=
=
=
=
=
±2.5VPP
±2.5VPP
±2.5VPP
±2.5VPP
±2.5VPP
at
at
at
at
at
10kHz
10kHz
10kHz
10kHz
10kHz
–94
94
83
83
96
2.475
2.5
dB
dB
dB
dB
dB
2.525
±1
V
%
ppm/°C
μVPP
μVrms
dB
μA
mA
μs
2.6
V
MΩ
pF
μA
±20
10
12
60
10
0.5
100
f = 0.1Hz to 10Hz, CL = 10μF
f = 10Hz to 10kHz, CL = 10μF
to 0.1% at CL = 0
(VIN)
10
1.2
100
2.5
μs
ns
kSPS
ns
ps
ps
MHz
5
1
NOTES: (1) All values are at TA = +25°C.
(2) Ideal input span; does not include gain or offset error.
(3) LSB means Least Significant Bit, with VREF equal to +2.5V; 1LSB = 76μV.
(4) Specified for 14-bit no missing code.
(5) Specified for 15-bit no missing code.
(6) Measured relative to an ideal, full-scale input (+IN – (–IN)) of 4.9999V. Thus, gain error does not include the error of the internal voltage reference.
ADS8361
SBAS230E
www.ti.com
3
ELECTRICAL CHARACTERISTICS (Cont.)
Over recommended operating free-air temperature range at TA = –40°C to +125°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500kSPS,
unless otherwise noted.
ADS8361
PARAMETER
DIGITAL INPUTS(2)
Logic Family
High-Level Input Voltage
Low-Level Input Voltage
Input Current
Input Capacitance
CONDITIONS
TYP(1)
MAX
UNITS
VDD + 0.3
0.3 • VDD
±50
V
V
nA
pF
CMOS
(VIH)
(VIL)
(IIN)
(CI)
DIGITAL OUTPUTS(2)
Logic Family
High-Level Output Voltage
(VOH)
Low-Level Output Voltage
(VOL)
High-Impedance-State Output Current (IOZ)
Output Capacitance
(CO)
Load Capacitance
(CL)
Data Format
DIGITAL INPUTS(3)
Logic Family
High-Level Input Voltage
Low-Level Input Voltage
Input Current
Input Capacitance
MIN
0.7 • VDD
–0.3
VI = BVDD or BGND
5
CMOS
BVDD = 4.5V, IOH = –100μA
BVDD = 4.5V, IOH = –100μA
CS = BVDD, VI = BVDD or BGND
4.44
0.5
±50
5
30
Binary Two’s Complement
V
V
nA
pF
pF
pF
LVCMOS
(VIH)
(VIL)
(IIN)
(CI)
DIGITAL OUTPUTS(3)
Logic Family
High-Level Output Voltage
(VOH)
Low-Level Output Voltage
(VOL)
High-Impedance-State Output Current (IOZ)
Output Capacitance
(CO)
Load Capacitance
(CL)
Data Format
BVDD = 3.6V
BVDD = 2.7V
VI = BVDD or BGND
2
–0.3
BVDD = 2.7V, IOH = –100μA
BVDD = 2.7V, IOH = –100μA
CS = BVDD, VI = BVDD or BGND
VDD – 0.2
VDD + 0.3
0.8
±50
5
V
V
nA
pF
LVCMOS
0.2
±50
5
30
Binary Two’s Complement
V
V
nA
pF
pF
pF
POWER SUPPLY
Analog Supply Voltage
Digital Supply Voltage
Analog Operating Supply Current
Digital Operating Supply Current
Power Dissipation
(AVDD)
(BVDD)
(AIDD)
(BIDD)
Low-Voltage Levels
5V Logic Levels
BVDD
BVDD
BVDD
BVDD
=
=
=
=
3V
5V
3V
5V
4.75
2.7
4.5
150
150
5.25
3.6
5.5
35
1(4)
1(4)
200
200
V
V
V
mA
μA
μA
mW
mW
NOTES: (1) All values are at TA = +25°C.
(2) Applies for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V.
(3) Applies for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V.
(4) No clock active (static).
4
ADS8361
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SBAS230E
BASIC CIRCUIT CONFIGURATION
+
ADS8361
+
0.1μF
10μF
10μF
0.1μF
+2.7V to +5.5V Digital Supply
1
BGND
BVDD 24
2
CH B1+
SERIAL DATA A 23
3
CH B1–
SERIAL DATA B 22
4
CH B0+
BUSY 21
5
CH B0–
CLOCK 20
Clock Input
6
CH A1+
CS 19
Chip Select
7
CH A1–
RD 18
Read Input
8
CH A0+
CONVST 17
9
CH A0–
A0 16
A0 Address Select
10 REFIN
M0 15
M0 Address Select
11 REFOUT
M1 14
M1 Address Select
12 AGND
AVDD 13
BUSY Output
Conversion Start
+
+5V Analog Supply
10μF
0.1μF
TRUTH TABLE
M0
M1
A0
TWO-CHANNEL/FOUR-CHANNEL OPERATION
DATA ON SERIAL OUTPUTS
CHANNELS CONVERTED
0
0
0
Two-Channel
A and B
A0 and B0
0
0
1
Two-Channel
A and B
A1 and B1
0
1
0
Two-Channel
A Only
A0 and B0
0
1
1
Two-Channel
A Only
A1 and B1
1
0
X
Four-Channel
A and B
Sequential
1
1
X
Four-Channel
A Only
Sequential
NOTE: X = Don’t Care.
ADS8361
SBAS230E
www.ti.com
5
PIN CONFIGURATION
NC(2)
NC(2)
NC(2)
BGND
BVDD
NC(2)
SERIAL DATA A
30
29
28
27
26
25
QFN
NC(2)
Top View
31
SSOP
32
Top View
ADS8361
1
BGND
2
CH B1+
SERIAL DATA A 23
3
CH B1–
SERIAL DATA B 22
CH B1+
1
24
SERIAL DATA B
4
CH B0+
BUSY 21
CH B1−
2
23
BUSY
5
CH B0–
CLOCK 20
CH B0+
3
22
CLOCK
CH B0−
4
21
CS
CH A1+
5
20
RD
CH A1−
6
19
CONVST
CH A0+
7
18
A0
CH A0−
8
17
M0
12 AGND
16
M1
M1 14
15
11 REFOUT
NC(2)
M0 15
14
10 REFIN
NC(2)
A0 16
CH A0–
13
CONVST 17
AVDD
9
CH A0+
12
8
AGND
RD 18
11
CH A1–
NC(2)
7
ADS8361
9
CS 19
10
CH A1+
REFIN
6
(1)
REFOUT
BVDD 24
AVDD 13
NOTE: (1) The thermal pad is internally connected to the substrate.
This pad can be connected to the analog ground or left floating.
Keep the thermal pad separate from the digital ground, if possible.
(2) NC = Not Connected.
PIN DESCRIPTIONS
SSOP QFN
PIN
PIN
6
NAME
DESCRIPTION
Digital I/O Ground. Connect directly to analog ground (pin 12).
1
28
BGND
2
1
CH B1+
3
2
CH B1–
Inverting Input Channel B1
4
3
CH B0+
Noninverting Input Channel B0
5
4
CH B0–
Inverting Input Channel B0
6
5
CH A1+
Noninverting Input Channel A1
7
6
CH A1–
Inverting Input Channel A1
8
7
CH A0+
Noninverting Input Channel A0
Inverting Input Channel A0
Noninverting Input Channel B1
9
8
CH A0–
10
9
REFIN
11
10
REFOUT
12
12
AGND
13
13
AVDD
14
16
M1
Selects between the Serial Outputs. When M1 is LOW, both Serial Output A and Serial Output B are selected for data transfer. When M1
is HIGH, Serial output A is configured for both Channel A data and Channel B data; Serial Output B goes into tri-state (i.e., high impedance).
15
17
M0
Selects between two-channel and four-channel operation. When M0 is LOW, two-channel operation is selected and operates in
conjunction with A0. When A0 is HIGH, Channel A1 and Channel B1 are being converted. When A0 is LOW, Channel A0 and Channel
B0 are being converted. When M0 is HIGH, four-channel operation is selected. In this mode, all four channels are converted in sequence
starting with Channels A0 and B0, followed by Channels A1 and B1.
16
18
A0
A0 operates in conjunction with M0. With M0 LOW and A0 HIGH, Channel A1 and Channel B1 are converted. With M0 LOW and A0 LOW,
Channel A0 and Channel B0 are converted.
17
19
CONVST
Convert Start. When CONVST switches from LOW to HIGH, the device switches from the sample to hold mode, independent of the status
of the external clock.
18
20
RD
19
21
CS
20
22
CLOCK
An external CMOS-compatible clock can be applied to the CLOCK input to synchronize the conversion process to an external source.
The CLOCK pin controls the sampling rate by the equation: fSAMPLE (max) = CLOCK/20.
21
23
BUSY
BUSY goes HIGH during a conversion and returns LOW after the third LSB has been transmitted on either the Serial A or Serial B output
pin.
22
24
SERIAL
DATA B
The Serial Output data word is comprised of channel information and 16 bits of data. In operation, data is valid on the falling edge of
DCLOCK for 20 edges after the rising edge of RD.
23
25
SERIAL
DATA A
The Serial Output data word is comprised of channel information and 16 bits of data. In operation, data is valid on the falling edge of
DCLOCK for 20 edges after the rising edge of RD. When M1 is HIGH, both Channel A data and Channel B data are available.
24
27
BVDD
Reference Input
2.5V Reference Output
Analog Ground. Connect directly to digital ground (pin 1).
Analog Power Supply, +5VDC. Decouple to analog ground with a 0.1μF ceramic capacitor and a 10μF tantalum capacitor.
Synchronization Pulse for the Serial Output.
Chip Select. When LOW, the Serial Output A and Serial Output B outputs are active; when HIGH, the serial outputs are tri-stated.
Digital I/O Power Supply, 2.7V to 5.5V
ADS8361
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SBAS230E
TIMING CHARACTERISTICS
tCKH
CLOCK
1
0
2
3
4
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
tCKL
t6
t1
CONVST
t11
t2
t3
A0
t4
t5
t7
RD
t8
CS
t9
t8
t10
Serial
Data A
CH
0/1
CH
A/B
D15
D14
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
D15
D14
D13
D12
Serial
Data B
CH
0/1
0
D15
D14
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
D15
D14
D13
D12
BUSY
tCONV
tACQ
tCONV
TIMING CHARACTERISTICS
Timing Characteristics over recommended operating free-air temperature range TMIN to TMAX, AVDD = 5V, REFIN = REFOUT internal reference +2.5V,
fCLK = 10MHz, fSAMPLE = 500kSPS, and BVDD = 2.7 ÷ 5.5V (unless otherwise noted).
SYMBOL
tCONV
tACQ
tCKP
tCKL
tCKH
tF
tR
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
DESCRIPTION
MIN
Conversion Time
Acquisition Time
Clock Period
Clock LOW
Clock HIGH
DOUT Fall Time
DOUT Rise Time
CONVST HIGH
Address Setup Time
Address Hold Time
RD Setup Time
RD to CS Hold Time
CONVST LOW
RD LOW
CS Setup Time
CLOCK to Data Valid Delay
Data Valid After CLOCK(3)
CS Setup Time
1.6
0.4
100
40
40
MAX
10,000
25
30
15
15
15
15
15
20
20
15
30
1
0
UNITS
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
COMMENTS
When TCKP = 100ns
When TCKP = 100ns
Address latched on falling edge of CLK cycle ‘2’.
Before falling edge of CLOCK.
After falling edge of CLOCK.
Before falling edge of CLOCK (for RD).
Maximum delay following rising edge of CLOCK.
Time data is valid after second rising edge of CLOCK.
Before CONVST
NOTES: (1) All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagram above.
(3) ‘n – 1’ data will remain valid 1ns after rising edge of next CLOCK cycle.
ADS8361
SBAS230E
www.ti.com
7
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500kSPS, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR vs CODE
INTEGRAL LINEARITY ERROR vs CODE
5
3
Typical curve for all four channels.
4
3
2
DNL (LSB)
INL (LSB)
2
1
0
–1
1
0
–2
–3
–4
8000H
0000H
4000H
7FFFH
8000H
4
2
2
1
0
–1
1
0
–1
–2
–2
–3
–3
C000H
0000H
4000H
–4
8000H
FFFFH
C000H
0000H
4000H
FFFFH
Output Code
Output Code
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
INTEGRAL LINEARITY ERROR MATCH
vs TEMPERATURE
4
4
3
3.5
Max
2
3
2.5
LSB
LSB
7FFFH
INTEGRAL LINEARITY MATCH OF
CHANNELS A0 AND A1 (or B0 and B1) vs CODE
4.5
2
1.5
1
0
–1
1
–2
0.5
0
25
–3
–40
85
Temperature (°C)
8
4000H
INTEGRAL LINEARITY MATCH OF
CHANNELS A0 AND B0 vs CODE
3
0
–40
0000H
Output Code
3
–4
8000H
C000H
Output Code
INL Match (LSB)
INL Match (LSB)
4
–1
C000H
Min
0
25
85
Temperature (°C)
ADS8361
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SBAS230E
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500kSPS, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 point FFT, fIN = 5kHz, –0.2dB)
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
0
–60
–80
–100
–60
–80
–100
–120
–120
–140
–140
–160
–160
0
50
100
150
200
250
0
50
100
150
200
Frequency (kHz)
Frequency (kHz)
CHANGE IN BIPOLAR OFFSET vs TEMPERATURE
BIPOLAR OFFSET MATCH vs TEMPERATURE
Channel A0/Channel B0
500
600
400
500
300
250
400
200
μV
μV
FREQUENCY SPECTRUM
(4096 point FFT, fIN = 10kHz, –0.2dB)
300
100
200
0
100
–100
–200
–40
0
25
0
–40
85
0
Temperature (°C)
REFERENCE VOLTAGE vs TEMPERATURE
2.502
31
Supply Current (mA)
32
VREF (V)
2.5
2.498
2.496
2.494
30
29
28
27
26
0
25
25
–40
85
Temperature (°C)
0
25
85
Temperature (°C)
ADS8361
SBAS230E
85
SUPPLY CURRENT vs TEMPERATURE
2.504
2.492
–40
25
Temperature (°C)
www.ti.com
9
INTRODUCTION
REFERENCE
The ADS8361 is a high-speed, low-power, dual, 16-bit A/D
converter that operates from +3V/+5V supply. The input
channels are fully differential with a typical common-mode
rejection of 80dB. The part contains dual, 4μs successive
approximation A/D converter, two differential sample-andhold amplifiers, an internal +2.5V reference with REFIN and
REFOUT pins, and a high-speed serial interface. The ADS8361
requires an external clock. In order to achieve the maximum
throughput rate of 500kSPS, the master clock must be set at
10MHz. A minimum of 20 clock cycles are required for each
16-bit conversion.
There are four analog inputs that are grouped into two channels (A and B). Channel selection is controlled by the M0 (pin
14), M1 (pin 15), and A0 (pin 16) pins. Each channel has two
inputs (A0, A1 and B0, B1) that are sampled and converted
simultaneously, thus preserving the relative phase information
of the signals on both analog inputs. The part accepts an
analog input voltage in the range of –VREF to +VREF, centered
around the internal +2.5V reference. The part will also accept
bipolar input ranges when a level shift circuit is used at the front
end (see Figure 7).
All conversions are initiated on the ADS8361 by bringing the
CONVST pin HIGH for a minimum of 15ns. CONVST HIGH
places both sample-and-hold amplifiers in the hold state
simultaneously and the conversion process is started on both
channels. The RD pin (pin 18) can be connected to CONVST
to simplify operation. Depending on the status of the M0, M1,
and A0 pins, the ADS8361 will (a) operate in either twochannel or four-channel mode and (b) output data on both
the Serial A and Serial B output or both channels can be
transmitted on the A output only.
NOTE: See the Timing and Control section of this data sheet
for more information.
SAMPLE-AND-HOLD SECTION
Under normal operation, the REFOUT pin (pin 2) should be
directly connected to the REFIN pin (pin 1) to provide an
internal +2.5V reference to the ADS8361. The ADS8361 can
operate, however, with an external reference in the range of
1.2V to 2.6V for a corresponding full-scale range of 2.4V to
5.2V.
The internal reference of the ADS8361 is buffered. If the
internal reference is used to drive an external load, a buffer
is provided between the reference and the load applied to pin 2
(the internal reference can typically source 10μA of current—
load capacitance should be 0.1μF and 10μF). If an external
reference is used, the second buffer provides isolation between the external reference and the Capacitve Digital-toAnalog Converter (CDAC). This buffer is also used to recharge all of the capacitors of both CDACs during conversion.
ANALOG INPUT
The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS8361: single-ended or differential (see Figures 1 and 2).
When the input is single-ended, the –IN input is held at the
common-mode voltage. The +IN input swings around the
same common voltage and the peak-to-peak amplitude is
the (common-mode + VREF) and the (common-mode – VREF).
The value of VREF determines the range over which the
common-mode voltage may vary (see Figure 3).
When the input is differential, the amplitude of the input is the
difference between the +IN and –IN input, or (+IN) – (–IN). The
peak-to-peak amplitude of each input is ±1/2 VREF around this
common voltage. However, since the inputs are 180° out-ofphase, the peak-to-peak amplitude of the differential voltage is
+VREF to –VREF. The value of VREF also determines the range
of the voltage that may be common to both inputs (see
Figure 4).
The sample-and-hold amplifiers on the ADS8361 allow the
A/D converter to accurately convert an input sine wave of fullscale amplitude to 16-bit accuracy. The input bandwidth of
the sample-and-hold is greater than the Nyquist rate (Nyquist
equals one-half of the sampling rate) of the A/D converter
even when the A/D converter is operated at its maximum
throughput rate of 500kSPS.
–VREF to +VREF
peak-to-peak
ADS8361
Common
Voltage
Single-Ended Input
Typical aperture delay time, or the time it takes for the
ADS8361 to switch from the sample to the hold mode
following the CONVST pulse, is 3.5ns. The average delta of
repeated aperture delay values is typically 50ps (also known
as aperture jitter). These specifications reflect the ability of
the ADS8361 to capture AC input signals accurately at the
exact same moment in time.
VREF
peak-to-peak
Common
Voltage
VREF
peak-to-peak
ADS8361
Differential Input
FIGURE 1. Methods of Driving the ADS8361 Single-Ended or
Differential.
10
ADS8361
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SBAS230E
+IN
CM + VREF
+VREF
CM Voltage
–IN = CM Voltage
–VREF
t
CM – VREF
CM + 1/2 VREF
Single-Ended Inputs
+IN
+VREF
CM Voltage
CM – 1/2 VREF
–VREF
–IN
t
Differential Inputs
NOTES: Common-Mode Voltage (Differential Mode) =
(+IN) + (–IN)
, Common-Mode Voltage (Single-Ended Mode) = IN–.
2
The maximum differential voltage between +IN and –IN of the ADS8361 is VREF. See Figures 3 and 4 for a further
explanation of the common voltage range for single-ended and differential inputs.
FIGURE 2. Using the ADS8361 in the Single-Ended and Differential Input Modes.
5
4.1
3
2.7
Single-Ended Input
2.3
2
1
0.9
AVDD = 5V
4.0
3
Differential Input
2
1.0
1
0
0
0.3
–1
–1
1.0
4.7
4
Common Voltage Range (V)
4
Common Voltage Range (V)
5
AVDD = 5V
1.2
2.0
2.5
2.6
1.0
3.0
1.2
2.0
2.5
2.6
3.0
VREF (V)
VREF (V)
FIGURE 3. Single-Ended Input: Common-Mode Voltage
Range vs VREF.
FIGURE 4. Differential Input: Common-Mode Voltage
Range vs VREF.
In each case, care should be taken to ensure that the output
impedance of the sources driving the +IN and –IN inputs are
matched. Otherwise, this may result in offset error, gain error,
and linearity error which will change with both temperature
and input voltage.
capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able
to charge the input capacitance (25pF) to a 16-bit settling
level within 4 clock cycles. When the converter goes into the
hold mode, the input impedance is greater than 1GΩ.
The input current on the analog inputs depend on a number
of factors: sample rate, input voltage, and source impedance.
Essentially, the current into the ADS8361 charges the internal capacitor array during the sampling period. After this
Care must be taken regarding the absolute analog input
voltage. The +IN and –IN inputs should always remain within
the range of AGND – 0.3V to AVDD + 0.3V.
ADS8361
SBAS230E
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11
TRANSITION NOISE
BIPOLAR INPUTS
The transition noise of the ADS8361 itself is low,
as shown in Figure 5. These histograms were generated by
applying a low-noise DC input and initiating 8000 conversions.
The digital output of the A/D converter will vary in output code
due to the internal noise of the ADS8361. This is true for all 16bit, Successive Approximation Register (SAR-type) A/D converters. Using a histogram to plot the output codes, the
distribution should appear bell-shaped with the peak of the bell
curve representing the nominal code for the input value. The
±1σ, ±2σ, and ±3σ distributions will represent the 68.3%,
95.5%, and 99.7%, respectively, of all codes. The transition
noise can be calculated by dividing the number of codes
measured by 6 and this will yield the ±3σ distribution, or
99.7%, of all codes. Statistically, up to three codes could fall
outside the distribution when executing 1000 conversions.
Remember, to achieve this low-noise performance, the peakto-peak noise of the input signal and reference must be
< 50μV.
The differential inputs of the ADS8361 were designed to
accept bipolar inputs (–VREF and +VREF) around the internal
reference voltage (2.5V), which corresponds to a 0V to 5V
input range with a 2.5V reference. By using a simple op amp
circuit featuring a single amplifier and four external resistors,
the ADS8361 can be configured to except bipolar inputs. The
conventional ±2.5V, ±5V, and ±10V input ranges can be
interfaced to the ADS8361 using the resistor values shown in
Figure 7.
R1
4kΩ
600Ω
+IN
OPA227
20kΩ
Bipolar Input
600Ω
–IN
R2
ADS8361
OPA227
Number of Conversions
5000
4500
BIPOLAR INPUT
R1
R2
4000
±10V
±5V
±2.5V
1kΩ
2kΩ
4kΩ
5kΩ
10kΩ
20kΩ
3500
REFOUT (pin 11)
2.5V
3000
2500
2000
FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.
1500
1000
500
TIMING AND CONTROL
0
32761
32762
32763
32764
32765
The operation of the ADS8361 can be configured in four
different modes by using the address pins M0 (pin 14), M1
(pin 15), and A0 (pin 16).
32766
Code (decimal)
FIGURE 5. Histogram of 8000 Conversions of a DC Input.
1.4V
3kΩ
DATA
Test Point
The M0 pin selects between two- and four-channel operation
(in two-channel operation, the A0 pin selects between Channels 0 and 1; in four-channel operation the A0 pin is ignored
and the channels are switched automatically after each
conversion). The M1 pin selects between having serial data
transmitted simultaneously on both the Serial A data output
(pin 23) and the Serial B data output (pin 22) or having both
channels output data through the Serial A port. The A0 pin
selects either Channel 0 or Channel 1 (see Pin Descriptions
and Serial Output Truth Table for more information).
The next four sections will explain the four different modes of
operation.
100pF
CLOAD
Mode I (M0 = 0, M1 = 0)
VOH
DATA
VOL
tR
tF
Voltage Waveforms for DATA Rise-and-Fall Times tR, and tF.
FIGURE 6. Test Circuits for Timing Specifications.
12
With the M0 and M1 pins both set to ‘0’, the ADS8361 will
operate in two-channel operation (the A0 pin must be used
to switch between Channels A and B). A conversion is
initiated by bringing CONVST HIGH for a minimum of 15ns.
It is very important that CONVST be brought HIGH a minimum of 10ns prior to a falling edge of the external clock or
5ns after the falling edge. If CONVST is brought HIGH within
this window, it is then uncertain as to when the ADS8361 will
initiate conversion (see Figure 9 for a more detailed descrip-
ADS8361
www.ti.com
SBAS230E
0111 1111 1111 1111
65535
0111 1111 1111 1110
65534
0111 1111 1111 1101
65533
0000 0000 0000 0001
32769
0000 0000 0000 0000
32768
1111 1111 1111 1111
32767
1000 0000 0000 0010
Step
Digital Output Code
Binary Two’s Complement
BTC
2
1000 0000 0000 0001
1
1000 0000 0000 0000
0
2.499962V
VNFS = VCM – VREF = 0V
0.000038V
2.500038V
VPFS = VCM + VREF = 5V
VPFS – 1LSB = 4.999924V
VBPZ = 2.5V
0.000076V
4.999848V
Unipolar Analog Input Voltage
0.000152V
1LSB = 76μV
16-BIT
Bipolar Input, Binary Two’s Complement Output: (BTC)
Negative Full-Scale Code = VNFS = 8000H, Vcode = VCM – VREF
Bipolar Zero Code
= VBPZ = 0000H, Vcode = VCM
Positive Full-Scale Code
= VPFS = 7FFFH, Vcode = (VCM + VREF) – 1LSB
VCM = 2.5V
VREF = 2.5V
FIGURE 8. Ideal Conversion Characteristics (Condition: Single Ended, VCM = chXX– = 2.5V, VREF = 2.5V)
tion). Twenty clock cycles are required to perform a single
conversion. Immediately following CONVST switching to
HIGH, the ADS8361 will switch from the sample mode to the
hold mode asynchronous to the external clock. The BUSY
output pin will then go HIGH and remain HIGH for the
duration of the conversion cycle. On the falling edge of the
first cycle of the external clock, the ADS8361 will latch in the
address for the next conversion cycle depending on the
status of the A0 pin (HIGH = Channel 1, LOW = Channel 0).
The address must be selected 15ns prior to the falling edge of
cycle one of the external clock and must remain ‘held’ for 15ns
following the clock edge. For maximum throughput time, the
CONVST and RD pins should be tied together. CS must be
brought LOW to enable the CONVST and RD inputs. Data will
be valid on the falling edge of all 20 clock cycles per conversion. The first bit of data will be a status flag for either Channel
0 or 1, the second bit will be a second status flag for either
Channel A or B. First and second bit will be 0 in Mode I. See
Table II below. The subsequent data will be MSB-first through
the LSB, followed by two zeros (see Table III and Figures 9
and 10).
MODE
M0
BIT 1
M1
BIT 2
CH0/1
CHA/B
CHANNEL SELECTION
DATA OUTPUT
1
2
3
4
0
0
1
1
0
1
0
1
0
0
0/1
0/1
0
0 = A/1 = B
0
0 = A/1 = B
Ch0/1 Selected by A0
Ch0/1 Selected by A0
Ch0/1 Alternating
Ch0/1 Alternating
On Data A and B
Sequentially on Data A
On Data A and B
Sequentially on Data A
TABLE II. Mode Selection.
CLOCK CYCLE
SERIAL DATA
1
2
3
4
5
6
CH0 OR CH1 CHA OR CHB DB15 DB14 DB13 DB12
7
8
9
10
DB11 DB10 DB9 DB8
11
12
13
14
15
16
17
18
19
20
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
TABLE III. Serial Data Output Format.
ADS8361
SBAS230E
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13
Mode II (M0 = 0, M1 = 1)
With M1 set to ‘1’, the ADS8361 will output data on the
Serial Data A pin only. All other pins function in the same
manner as Mode I except that the Serial Data B output will
tri-state (i.e., high impedance) after a conversion following
M1 going HIGH. Another difference in this mode involves
the CONVST pin. Since it takes 40 clock cycles to output
the results from both A/D converters (rather than 20 when
M1 = 0), the ADS8361 will take 4μs to complete a conversion on both A/D converters (See Figure 11).
Mode III (M0 = 1, M1 = 0)
With M0 set to ‘1’, the ADS8361 will cycle through Channels
0 and 1 sequentially (the A0 pin is ignored). At the same time,
setting M1 to ‘0’ places both Serial Outputs, A and B, in the
active mode (See Figure 12).
Mode IV (M0 = 1, M1 = 1)
Similar to Mode II, Mode IV uses the Serial A output line to
transmit data exclusively. Following the first conversion after
M1 goes HIGH, the serial B output will go into tri-state. See
Figure 13. As in Mode II, the second CONVST command is
always ignored when M1 = 1.
READING DATA
In all four timing diagrams, the CONVST pin and the RD pins
are tied together. If so desired, the two lines can be separated. Data on the Serial Output pins (A and B) will become
valid following the third rising SCLK edge following RD rising
edge. Refer to Table III for data output format.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8361 circuitry. This is particularly
true if the CLOCK input is approaching the maximum throughput rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, driving any single
conversion for an n-bit SAR converter, there are n “windows”
in which large external transient voltages can affect the
conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on
the reference voltage, layout, and the exact timing of the
external event. Their error can change if the external event
changes in time with respect to the CLOCK input.
With this in mind, power to the ADS8361 should be clean and
well bypassed. A 0.1μF ceramic bypass capacitor should be
placed as close to the device as possible. In addition, a 1μF
to 10μF capacitor is recommended. If needed, an even larger
capacitor and a 5Ω or 10Ω series resistor may be used to
low-pass filter a noisy supply. On average, the ADS8361
draws very little current from an external reference as the
reference voltage is internally buffered. However, glitches
from the conversion process appear at the VREF input and the
reference source must be able to handle this. Whether the
reference is internal or external, the VREF pin should be
bypassed with a 0.1μF capacitor. An additional larger capacitor may also be used, if desired. If the reference voltage is
external and originates from an op amp, make sure that it can
drive the bypass capacitor or capacitors without oscillation.
No bypass capacitor is necessary when using the internal
reference (tie pin 10 directly to pin 11).
The GND pin should be connected to a clean ground point.
In many cases, this will be the ‘analog’ ground. Avoid
connections which are too near the grounding point of a
microcontroller or Digital Signal Processor (DSP). If required,
run a ground trace directly from the converter to the powersupply entry point. The ideal layout will include an analog
ground plane dedicated to the converter and associated
analog circuitry.
APPLICATION INFORMATION
In Figures 14 through 17, different connection diagrams to
DSPs or microcontrollers are shown.
tCKP
100ns
CLOCK
Cycle 1
Cycle 2
10ns
10ns
5ns
CONVST
A
B
5ns
C
NOTE: All CONVST commands which occur more than 10ns before the falling edge before cycle ‘1’ of the external clock (Region ‘A’) will initiate a conversion on the rising
edge of cycle ‘1’. All CONVST commands which occur 5ns after the falling edge before cycle ‘1’ or 10ns before the falling edge before cycle 2 (Region ‘B’) will initiate a
conversion on the rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the falling edge of cycle ‘2’ (Region ‘C’) will initiate a conversion on the rising
edge of the next clock period. The CONVST pin should never be switched from LOW to HIGH in the region 10ns prior to the falling edge of the CLOCK and 5ns after the
falling edge (gray areas). If CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or the following edge.
FIGURE 9. Conversion Mode.
14
ADS8361
www.ti.com
SBAS230E
1
20
CLOCK
Conversion of Ch0
Conversion of Ch1
CONVST
A0 LOW, Next Conversion: Ch0
A0 HIGH, Next Conversion: Ch1
A0
RD Connected to CONVST
RD
CS
CS HIGH, Outputs in Tri-State
Serial
Data A
16-Bit Data of Chx
16-Bit Data of ChA1
Serial
Data B
16-Bit Data of Chx
16-Bit Data of ChB1
Conversion of Chx
BUSY
TIME 0
Conversion of Ch0
Conversion of Ch1
1μ
2μ
3μ
4μ
5μ
6μ
Time (seconds)
FIGURE 10. Mode I, Timing Diagram for M0 = 0 and M1 = 0.
1
20
CLOCK
CONVST
A0
Conversion of Chx
M1 = 1 and 1st CONVST
Conversion
A0 HIGH
Next Conversion Ch1
M1 = 1 and 2nd CONVST
No Conversion
A0 LOW
Next Conversion Ch0
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
A0 LOW
Next Conversion Ch0
M1
M1 HIGH
Only Serial Data A Used as Output Starting with 1st Conversion
RD
RD Connected with CONVST
CS LOW Output Active
CS
Serial
Data A
Serial
Data B
BUSY
16-Bit Data of ChAx
C
h
A
M1 = 1 and 1st CONVST
Data of ChA
C
h M1 = 1 and 2nd CONVST
B
Data of ChB
C
h M1 = 1 and 2nd CONVST
B
Data of ChB
M1 = 1 Serial Data B in Tri-state
16-Bit Data of ChBx
Conversion of Chx
C
h M1 = 1 and 1st CONVST
A
Data of ChA
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
TIME 0
5μ
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
10μ
Time (seconds)
FIGURE 11. Mode II, Timing Diagram for M0 = 0 and M1 = 1.
ADS8361
SBAS230E
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15
1
20
CLOCK
4-Ch Operation and 1st Conversion Ch0
CONVST
M0 = 1 A0 Ignored
A0
M0
RD
4-Ch Operation and 2nd Conversion Ch1
M0 = 1, 4-Ch Operation Starts with Next Conversion
RD Connected with CONVST
CS
CS LOW, Output is Active
Serial
Data A
16-Bit Data of ChAx
C
h
0
16-Bit Data of ChA0
C
h
1
16-Bit Data of ChA1
Serial
Data B
16-Bit Data of ChBx
C
h
0
16-Bit Data of ChB0
C
h
1
16-Bit Data of ChB1
BUSY
TIME 0
1μ
2μ
3μ
4μ
5μ
6μ
Time (seconds)
FIGURE 12. Mode III, Timing Diagram for M0 = 1 and M1 = 0.
16
ADS8361
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SBAS230E
1
20
CLOCK
M1 = 1 and 1st CONVST
Conversion
Conversion of Chx
CONVST
M1 = 1 and 2nd CONVST
No Conversion
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
M0 HIGH
4-Ch Operation Starts, A0 Ignored
A0
M0
M0 HIGH
4-Ch Operation Starts
M1
M1 HIGH
Only Serial Data A Used as Output Starting with 1st Conversion
RD
M0 = 1 and 1st Active CONVST
Ch0
M0 = 1 and 2nd Active CONVST
Ch1
RD Connected with CONVST
CS LOW Output Active
CS
Serial
Data A
Serial
Data B
BUSY
CC
hh
0A
16-Bit Data of ChAx
M1 = 1 and 1st CONVST
Data of ChA0
CC
h h M1 = 1 and 2nd CONVST
0 B
Data of ChB0
C C
h h M1 = 1 and 1st CONVST
1 A
Data of ChA1
CC
h h M1 = 1 and 2nd CONVST
1B
Data of ChB1
M1 = 1 Serial Data B in Tri-state
16-Bit Data of ChBx
Conversion of Chx
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
TIME 0
M1 = 1 and 1st CONVST
Conversion
5μ
M1 = 1 and 2nd CONVST
No Conversion
10μ
Time (seconds)
FIGURE 13. Mode IV, Timing Diagram for M0 = 1 and M1 = 1.
MSP430x1xx/4xx
ADS8361
SERIAL DATA A
MISO
CLOCK
SCLK
CONVST
P3.5
RD
BVDD
BUSY
M1
A0
M0
CS
P2.1(INT)
P3.6
FIGURE 14. 2x2 Channel Using A Output.
ADS8361
SBAS230E
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17
TMS320F28xx/
C54xx/C67xx
ADS8361
DR
SERIAL DATA A
CONVST
FSX
RD
FSR
CLOCK
CLKX
CLKR
BVDD
EXT_INT
BUSY
M1
A0
M0
CS
DX
FIGURE 15. 2x2 Channel Using A Output.
TMS320C54xx/
C67xx
ADS8361
SERIAL DATA A
DRA
SERIAL DATA B
DRB
CONVST
FSXA
RD
FSRA
FSRB
CLOCK
BVDD
M1
CLKXA
CLKRA
CLKRB
M0
CS
FIGURE 16. 4-Channel Sequential Mode Using A and B Outputs.
TMS320F28xx/
C54xx/C67xx
ADS8361
SERIAL DATA A
DRX
CONVST
FSX
RD
FSR
CLOCK
BVDD
M0
CLKX
CLKR
M1
CS
FIGURE 17. 4-Channel Sequential Mode Using A Output.
18
ADS8361
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SBAS230E
Revision History
DATE REVISION PAGE
SECTION
E
Pin Configuration
Added Note (1) to QFN package.
Entire Document
Changed Throughput Rate from 500kHz to 500kSPS throughout document.
8/07
6
1
Features
Description
2
8/06
Absolute Maximum Ratings
Package/Ordering Table
D
DESCRIPTION
Added Operating Temperature Range: –40°C to +125°C.
Changed Operating Temperature Range upper limit from +85°C to +125°C.
Changed Operating Temperature Range upper limit from +85°C to +125°C.
Deleted Lead Temperture.
Changed Specified Temperature Range upper limit from +85°C to +125°C.
Changed temperature range from –40°C to +85°C to TA = –40°C to +125°C in
top-of-page header condition.
3
Electrical Characteristics
Added TA = –40°C to +85°C to Bipolar Offset Error condition.
Added new row under Bipolar Offset Error for TA = –40°C to +125°C condition.
4
Electrical Characteristics
Added (Cont.) to Title.
Added BVDD = 3V to top-of-page header condition.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
ADS8361
SBAS230E
www.ti.com
19
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS8361IDBQ
ACTIVE
SSOP
DBQ
24
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ADS8361I
ADS8361IDBQG4
ACTIVE
SSOP
DBQ
24
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ADS8361I
ADS8361IDBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ADS8361I
ADS8361IDBQRG4
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ADS8361I
ADS8361IRHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ADS
8361I
ADS8361IRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ADS
8361I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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