ADS8422IBPFBT

Burr Brown Products from Texas Instruments ADS8422 SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE FEATURES • • • • • • • • • • • • Fully Differential Input with Pseudo-Bipolar Input Range -4 V to +4 V 16-Bit NMC at 4 MSPS 1 LSB INL Typ 92dB SNR, -102dB THD Typ with 100-kHz Input Internal 4.096-V Reference and Reference Buffer REFIN/2 Available for Setting Analog Input Common-Mode Voltage Zero Latency High-Speed Parallel Interface Single Supply Operation Capability Low Power: 155 mW at 4 MHz Typ, Flexible Power-Down Scheme Pin-Out Similar to ADS8412/8402 48-Pin 9×9 TQFP Package APPLICATIONS • • • • • • • DWDM Instrumentation High-Speed, High-Resolution, Zero Latency Data Acquisition Systems Transducer Interface Medical Instruments Spectrum Analysis ATE DESCRIPTION The ADS8422 is a 16-bit, 4-MHz A/D converter with an internal 4.096-V reference. The device includes a 16-bit capacitor-based multi-bit SAR A/D converter with inherent sample and hold. This converter includes a full 16-bit interface and an 8-bit option where data is read using two 8-bit read cycles if necessary. The ADS8422 has a fully differential, pseudo-bipolar input. It is available in a 48-lead TQFP package and is characterized over the industrial -40°C to +85°C temperature range. HIGH-SPEED SAR CONVERTER FAMILY (1) TYPE/SPEED 18-Bit Pseudo-Diff ADS8380 (s) 18-Bit Pseudo-Bipolar, Fully Diff 16-Bit Pseudo-Diff ADS8327/28 (s) 16-Bit Pseudo-Bipolar, Fully Diff ADS8406 14-Bit Pseudo-Diff 12-Bit Pseudo-Diff ADS7886 ADS7890 (s) ADS7883 ADS8413 (s) ADS7891 ADS7881 ADS8372 (s) ADS8329/30 (s) ADS8472 ADS8405 ADS8402 ADS8410 (s) ADS8412 ADS8422 ADS8382 (s) ADS8370 (s) ADS8371 ADS8482 ADS8471 ADS8401 ADS8411 500 kHz ADS8383 ~600 kHz ADS8381 750 kHz 1 MHz ADS8481 1.25 MHz 2 MHz 3 MHz 4MHz (1) S: Serial TEMPOUT +IN −IN COMMOUT REFIN REFOUT ½ Temp Sensor SAR CDAC Comparator Clock 4.096-V Internal Reference Output Latches and 3-State Drivers BYTE 16-/8-Bit Parallel Data Output Bus Conversion and Control Logic PD2 RESET/PD1 CONVST BUSY CS RD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNATOR TEMPERATURE RANGE ORDERING INFORMATION TRANSPORT MEDIA QTY. Small tape and reel 250 Tape and reel 1000 Small tape and reel 250 Tape and reel 1000 ADS8422I ±6 ±2 15 9×9 48-Pin TQFP ADS8422IPFBT PFB –40°C to 85°C ADS8422IPFBR ADS8422IBPFBT PFB –40°C to 85°C ADS8422IBPFBR ADS8422IB ±2 +1.5/-1 16 9×9 48-Pin TQFP (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE +IN to AGND Voltage –IN to AGND +VA to AGND +VBD to BDGND Digital input voltage to BDGND Digital output voltage to BDGND TA Tstg Operating free-air temperature range Storage temperature range Junction temperature (TJ max) TQFP 48-pin package Lead temperature, soldering (1) Power dissipation θJA thermal impedance Vapor phase (60 sec) Infrared (15 sec) –0.4 to +VA + 0.1 –0.4 to +VA + 0.1 –0.3 to 7 –0.3 to 7 –0.3 to +VBD + 0.3 –0.3 to +VBD + 0.3 –40 to 85 –65 to 150 150 (TJMax – TA)/θJA 86 215 220 °C/W °C °C UNIT V V V V V V °C °C °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 Submit Documentation Feedback ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VAREG = 5 V to 3 V, +VBD = 5 V to 2.7 V, fSAMPLE = 4 MSPS, Vref = 4.096 V (measured with internal reference buffer) (unless otherwise noted) PARAMETER ANALOG INPUT Full-scale input voltage (1) Absolute input voltage Common-mode input range Input capacitance Input leakage current SYSTEM PERFORMANCE Resolution No missing codes (2) (3) TEST CONDITIONS MIN TYP MAX UNIT +IN – (–IN) +IN –IN –Vref –0.2 –0.2 (Vref)/2 – 0.2 (Vref)/2 30 Vref Vref + 0.2 Vref + 0.2 (Vref)/2 + 0.2 1 V V V pF nA 16 ADS8422I ADS8422IB ADS8422I ADS8422IB ADS8422I ADS8422IB 15 16 –6 –2 –2 –1 –0.5 ±2 ±1 ±0.7 ±0.7 ±0.25 ±0.2 Vref = 4.096 V Vref = 4.096 V At dc At code 0000h with [+IN + (–IN)]/2 = 512 mVpp at 500 kHz, At 0000h output code At 8000h output code –0.1 ±0.05 ±2 81 78 40 78 0.1 6 2 2 1.5 0.5 Bits Bits LSB (16 bit) (2) LSB (16 bit) mV ppm/°C %FS ppm/°C dB µV RMS dB µs µs 4 MHz ns ps RMS ns ns Integral linearity Differential linearity Offset error Offset error drift Gain error (4) (5) Gain error drift Common-mode rejection ratio Noise Power supply rejection ratio SAMPLING DYNAMICS Conversion time Acquisition time Throughput rate Aperture delay Aperture jitter Step response Overvoltage recovery 0.180 0.070 3 7 70 140 (1) (2) (3) (4) (5) Ideal input span, does not include gain or offset error. LSB means least significant bit and is equal to 2VREF/65536. This is endpoint INL, not best fit. Measured relative to an ideal full-scale input [+IN – (–IN)] of 8.192 V. This specification does not include the internal reference voltage error and drift. Submit Documentation Feedback 3 ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 SPECIFICATIONS (Continued) TA = –40°C to 85°C, +VA = 5 V, +VAREG = 5.25 V to 3 V, +VBD = 5 V to 2.7 V, fSAMPLE = 4 MSPS, Vref = 4.096 V (measured with internal reference buffer) (unless otherwise noted) PARAMETER DYNAMIC CHARACTERISTICS 10 kHz Total harmonic distortion (THD) (1) VIN = 8 Vpp 100 kHz 500 kHz 10 kHz Signal to noise ratio (SNR) VIN = 8 Vpp 100 kHz 500 kHz 10 kHz Signal to noise + distortion (SINAD) VIN = 8 Vpp 100 kHz 500 kHz 10 kHz Spurious free dynamic range (SFDR) VIN = 8 Vpp 100 kHz 500 kHz –3dB Small signal bandwidth Maximum input frequency, fi(max) (2) VOLTAGE REFERENCE INPUT Reference voltage at REFIN, Vref Reference resistance INTERNAL REFERENCE OUTPUT Internal reference start-up time Reference voltage range, Vref Source current Line regulation Drift ANALOG COMMON-MODE, PIN 3 Output voltage range Source current IO = 0 Static load VREF/2 - 0.016 VREF/2 200 VREF/2 + 0.016 V µA From 95% (+VA), with 1-µF capacitor on REFOUT IO = 0, TA = 25°C Static load +VA = 4.75 V to 5.25 V IO = 0 ±1 ±6 4.088 4.096 25 4.104 10 ms V µA mV PPM/°C 3.9 4.096 1000 4.15 V MΩ VIN = 8 Vpp 2 –114 –102 –100 93 92 90 92.5 91.5 89.5 116 109 106 30 MHz MHz dB dB dB dB TEST CONDITIONS MIN TYP MAX UNIT (1) (2) Calculated on the first nine harmonics of the input frequency. ADC Sampling circuit is optimized to accept inputs until Nyquist frequency. Dynamic performance may degrade rapidly above fi(max). 4 Submit Documentation Feedback ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 SPECIFICATIONS (Continued) TA = –40°C to 85°C, +VA = 5 V, +VAREG = 5 V to 3 V, +VBD = 5 V to 2.7 V, fSAMPLE = 4 MSPS, Vref = 4.096 V (measured with internal reference buffer) (unless otherwise noted) PARAMETER DIGITAL INPUT/OUTPUT Logic family – CMOS VIH Logic level VIL VOH VOL Data format – Twos complement POWER SUPPLY REQUIREMENTS +VA Power supply voltage +VAREG +VBD +VA +VAREG +VBD (1) POWER DOWN (2) Supply current Power Power-up time Supply current Power Power-up time TEMPERATURE RANGE Operating free-air –40 85 °C (PD1, PD2) : (0,0) → (1,1) , 1-µF Storage capacitor from REFOUT to AGND +VA +VAREG (PD1, PD2) : (0,1) → (1,1) PD1 = 0, PD2 = 0 5 5 40 25 +VA +VAREG PD1 = 0, PD2 = 1, +VA = 5 V 2.5 5 17 5 3.4 mA µA mW µs µA µW ms +VA = 5 V, PD1 = 1, PD2 = 1 +VAREG = 5 V, PD1 = 1, PD2 = 1 +VAREG = 3 V, PD1 = 1, PD2 = 1 +VBD = 3 V, 10 pF/pin +VBD = 5 V, 20 pF/pin 4.75 2.85 2.7 5 3.0 3.0 24 12 12 0.55 1.8 5.25 5.25 5.25 27 14 14 mA mA V IIH = 5 µA IIL = 5 µA IOH = 2 TTL loads IOL = 2 TTL loads 0.75×(+VBD) –0.3 +VBD – 0.6 0.4 +VBD + 0.3 0.8 V TEST CONDITIONS MIN TYP MAX UNIT Supply current mA (1) (2) This includes the current required for charging the external load capacitance on the digital outputs and is measured with four digital outputs toggling at the same time. (PD1 , PD2 ) = (1,0) is reserved. Do not use this power-down pins combination. Submit Documentation Feedback 5 ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 TIMING CHARACTERISTICS FROM DIGITAL INPUTS All specifications typical at –40°C to 85°C, +VBD = 2.7 V to 5.25 V PARAMETER CONVERSION AND ACQUISITION t(ACQ) tw1 tw2 tp1 tq1 tq2 Acquisition time, internal to device, not externally visible Pulse duration, CONVST low Pulse duration, CONVST high Period, CONVST Quiet time, last toggle of interface input signals during acquisition before CONVST falling Quiet time, CONVST falling to first toggle of interface input signals PD1 low for only ADC reset (no powerdown) tw3 Pulse duration PD1 low for ADC reset and also ADC powerdown PD2 low pulse duration for REFOUT and COMMOUT buffers powerdown Pulse duration, all others unspecified (1) (2) (3) (3) (3) (1) (2) MIN 70 20 100 250 30 10 20 1500 1500 10 TYP MAX UNIT ns ns ns ns ns ns POWER DOWN 500 ns ns All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from after 90% of transition. All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching 90% of transition. Quiet time zones are for meeting performance and not functionality. TIMING CHARACTERISTICS OF DIGITAL OUTPUTS All specifications typical at –40°C to 85°C, +VBD = 2.7 V to 5.25 V PARAMETER CONVERSION AND ACQUISITION t(CONV) td1 td2 td3 td4 td5 td6 td7 td8 Conversion time, internal to device, not externally visible Delay time, CONVST fall to conversion start (aperture delay) Delay time, CONVST low to data valid if CS = RD = 0 Delay time, data valid to BUSY low if CS = RD = 0 Delay time, RD (or CS) low to data valid Delay time, BYTE toggle to data valid Delay time, data three-state after RD (or CS) high Delay time, PD1 low to BUSY rising Delay time, PD1 high to device operational (with PD2 held high) Delay time, PD2 high to REFOUT/COMMOUT valid Delay time, power up (after AVDD = 4.75 V) td9 (1) (2) Delay time, data three-state after PD1 low 5 17 20 12 20 5 25 25 1.5 3 225 180 ns ns ns ns ns ns ns ns µs ms ms µs (1) (2) MIN TYP MAX UNIT DATA READ OPERATION POWER DOWN All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from after 90% of transition. All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching 90% of transition. 6 Submit Documentation Feedback ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 PIN ASSIGNMENTS PFB Package (Top View) REFM REFM +VA AGND AGND +VA CS RD CONVST BYTE RESET/PD1 PD2 48 47 46 45 44 43 42 41 40 39 38 37 REFIN REFOUT COMMOUT +VA AGND +IN −IN AGND CAP1 +VAREG NC AGND 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 BUSY BDGND +VBD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 BDGND CAP2 AGND AGND DB15 DB14 DB13 DB12 DB11 DB10 DB9 A. B. C. D. E. NC - No connection +VAREG can be connected to a 3-V to 5-V supply. Pin 3 outputs REFIN/2 Pins 9 and 13 are internally regulated 3-V outputs and are externally to be connected to decoupling capacitors only. Pin 38 can be used for ADC powerdown and pin 37 for analog output powerdown. TERMINAL FUNCTIONS NAME AGND BDGND BUSY BYTE NO 5, 8, 12, 14, 15, 44, 45 25, 35 36 39 I/O – – O I Analog ground Digital ground for bus interface digital supply Status output. High when a conversion is in progress. Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[15:8]. This pin outputs REFIN/2 and can be used to set the common-mode voltage of the differential analog input, (+IN + –IN)/2. Convert start. This input is low true and can act independent of the CS input. Chip select. Decoupling of internally generated 3-V supply. Add 1-µF capacitor from these pins to AGND. 8-BIT BUS BYTE = 0 16 17 18 19 20 21 O O O O O O D15 (MSB) D14 D13 D12 D11 D10 D7 D6 D5 D4 D3 D2 BYTE = 1 D15 (MSB) D14 D13 D12 D11 D10 16-BIT BUS BYTE = 0 DESCRIPTION COMMOUT CONVST CS CAP1, CAP2 Data Bus DB15 DB14 DB13 DB12 DB11 DB10 3 40 42 9, 13 O I I O DB8 +VBD Submit Documentation Feedback 7 ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 TERMINAL FUNCTIONS (continued) NAME DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 –IN +IN NC PD2 REFIN REFOUT REFM RESET/PD1 RD +VA +VAREG +VBD NO 22 23 26 27 28 29 30 31 32 33 7 6 11 37 1 2 47, 48 38 41 4, 46 10 24, 34 I/O O O O O O O O O O O I I – I I O I I I – – – D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) Inverting input channel Noninverting input channel No connection Low true signal. A logic low longer than 1.5 µs applied to this pin powers down only the analog outputs that include REFOUT and COMMOUT. (NOTE: The combination PD1 = 1, PD2 = 0 is reserved. Do not use this combination.) Reference input. Add 0.1-µF decoupling capacitor between REFIN and REFM. Reference output. Add 1-µF capacitor between the REFOUT pin and REFM pin when internal reference is used. Reference ground Low true signal. A low pulse applied to this pin resets the ADC; the ongoing conversion is aborted. A low pulse shorter than 0.5 µs only resets, and one longer than 1.5 µs resets and also powers down the ADC. Note that analog outputs REFOUT and COMMOUT can be powered down by PD2, if necessary. Synchronization pulse for the parallel output. Analog power supplies, 4.75 V to 5.25 VDC Regulator supply, 2.85 V to 5.25 VDC Digital power supply for bus D1 D0 (LSB) All ones All ones All ones All ones All ones All ones All ones All ones DESCRIPTION D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) TYPICAL CHARACTERISTICS INTERNAL REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE (Three Devices Shown) 4.098 HISTOGRAM OF 262144 CONVERSIONS OF DC INPUT AT CENTER CODE (Internal Reference) 250000 234937 +VA = 5 V, +VAREG = 3 V, 200000 +VBD = 3 V, Int REFIN = 4.096 V, 262144 Points, Sigma = 0.325, 150000 HISTOGRAM OF 262144 CONVERSIONS OF DC INPUT AT CENTER CODE (External Reference) REFOUT - Internal Reference Voltage - V 250000 235679 +VA = 5 V, +VAREG = 3 V, 200000 +VBD = 3 V, Ext REFIN = 4.096 V, 262144 Points, Sigma = 0.319, 150000 D3 4.097 D2 +VA = 5 V, +VAREG = 3 V, +VBD = 3 V COUNTS COUNTS D1 4.096 100000 100000 50000 68 0 FFFD FFFE FFFF 0000 Code - Hex 0001 14024 13025 93 50000 78 0 FFFD FFFE FFFF 0000 Code - Hex 0001 13793 12575 19 4.095 4.094 -40 -25 -10 5 20 35 50 65 80 TA - Free-Air Temperature - ºC Figure 1. Figure 2. Figure 3. 8 Submit Documentation Feedback ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) OFFSET VOLTAGE vs FREE-AIR TEMPERATURE 0.200 0.040 GAIN ERROR vs FREE-AIR TEMPERATURE 94 +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY SNR - Signal-to-Noise Ratio - dB +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V 0.150 0.030 92 Offset Voltage - mV Gain Error - %FS 90 0.100 0.020 88 0.050 0.010 86 +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V 84 1 10 100 1000 0 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - ºC 80 0 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - ºC 80 fi - Input Frequency - kHz Figure 4. SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 94 16 Figure 5. EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 94 Figure 6. SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V, fi = 18 kHz 93 SINAD - Signal-to-Noise + Distortion - dB 92 Effective Number of Bits - ENOB 15.5 90 15 SNR - Signal-to-Noise Ratio - dB 92 88 14.5 91 86 +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V 84 1 10 100 fi - Input Frequency - kHz 1000 14 +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V 13.5 1 100 10 fi - Input Frequency - kHz 1000 90 -40 -25 5 20 35 50 65 80 -10 TA - Free-Air Temperature - ºC Figure 7. TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SFDR - Spurious Free Dynamic Range - dB -85 Figure 8. SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY 125 120 115 110 105 100 95 90 85 1 100 10 fi - Input Frequency - kHz 1000 +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V Figure 9. TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE -100 THD - Total Harmonic Distortion - dB -90 -95 -100 -105 -110 -115 -120 -125 1 THD - Total Harmonic Distortion - dB +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V, fi = 18 kHz -105 -110 -115 10 100 fi - Input Frequency - kHz 1000 -120 -40 -25 -10 5 20 35 50 65 80 TA - Free-Air Temperature - ºC Figure 10. Figure 11. Figure 12. Submit Documentation Feedback 9 ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) POWER DISSIPATION vs THROUGHPUT 180 170 160 12 +VAREG CURRENT vs THROUGHPUT 25 24.5 24 11 +VA CURRENT vs THROUGHPUT +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V, Device not powered down between conversions PD - Power Dissipation - mW +VAREG Current - mA +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V, Device not powered down between conversions 11.5 +VA Current - mA +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V, Device not powered down between conversions 0 1000 2000 3000 Throughput - KSPS 4000 23.5 23 22.5 22 21.5 21 0 150 10.5 140 10 9.5 130 120 0 9 1000 2000 3000 Throughput - KSPS 4000 1000 2000 3000 Throughput - KSPS 4000 Figure 13. DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 1.50 2 Figure 14. INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V Max 1 Figure 15. COMMON-MODE REJECTION RATIO vs FREQUENCY CMRR - Common-Mode Rejection Ratio - dB 85 80 75 70 65 60 55 50 1 10 100 1000 f - Frequency - kHz 10000 +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V 1 Max DNL - LSBs INL - LSBs 0.50 0 0 Min -0.50 Min -1 +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V -1 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - ºC 80 -2 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - ºC 80 Figure 16. 1.5 Figure 17. DNL Figure 18. +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V 1 DNL - LSBs 0.5 0 -0.5 -1 0 16384 32768 Code Figure 19. 49152 65536 10 Submit Documentation Feedback ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) INL 2 1.5 1 +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V INL - LSBs 0.5 0 -0.5 -1 -1.5 -2 0 16384 32768 Code Figure 20. 49152 65536 FFT (10 kHz) 0 Amplitude - dB of Full-Scale -40 -80 -120 -160 -200 0 +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V, fi = 10 kHz, SNR = 93 dB, THD = 114 dB 200 400 600 800 1000 1200 f - Frequency - kHz Figure 21. 1400 1600 1800 2000 FFT (100 kHz) Amplitude - dB of Full-Scale 0 -40 -80 -120 -160 -200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 f - Frequency - kHz Figure 22. +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V, fi = 100 kHz, SNR = 92 dB, THD = 102 dB Submit Documentation Feedback 11 ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) FFT (500 kHz) 0 Amplitude - dB of Full-Scale -40 -80 -120 -160 -200 +VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V, fi = 500 kHz, SNR = 90 dB, THD = 100 dB 0 200 400 600 800 1000 1200 1400 1600 1800 2000 f - Frequency - kHz Figure 23. TIMING DIAGRAMS tw1 tq1 tq2 CONVST tp1 tw2 td1 ACQUISITION Sample(N) t(acq) Sample(N+1) t(CONV) CONVERT Conversion(N) td2 DB (Internal) DB(N-1) DB(N) td3 BUSY Note: The DB shown here is internal to the device and output on the pins only if and when CS and RD are both low (after td4 ns). This is shown in Figure 25. Figure 24. Conversion Control Timing 12 Submit Documentation Feedback ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 CS RD BYTE td4 Hi-Z DB Valid Data td6 Hi-Z td4 Valid Data td5 Valid Data td6 Hi-Z Note: Data is output on the pins only if CS and RD are both low, td4 ns after this condition is satisfied. Figure 25. Data Read Timing td8 CONVST tw2 tw3 > 1500 ns PD1 td7 BUSY Conversion(1) td2 DB Hi-Z td9 Undefined Data DB(1) DB(2) Conversion(2) ICC Note: Data is valid from the first conversion initiated 5 µs after PD1 is pulled high. Figure 26. ADC Power-Down Timing Submit Documentation Feedback 13 ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 PD1 = 0 tw3 > 1500 ns PD2 td8 COMMOUT Valid Analog Outputs REFOUT Note: Analog outputs are valid 25 ms after PD2 is pulled high. Figure 27. Analog Output Power-Down Timing RESET TIMING CONVST tw2 tw3 < 500 ns PD1 td7 BUSY Conversion(1) td2 DB Undefined Data DB(1) DB(2) Conversion(2) Note: Data valid from first conversion initiated 100 ns after PD1 is pulled high. Figure 28. ADC Reset 14 Submit Documentation Feedback ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 PRINCIPLES OF OPERATION The ADS8422 is a member of a family of high-speed multi-bit successive approximation register (SAR) analog-to-digital converters (ADC). The architecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 34 for the application circuit for the ADS8422. The conversion clock is generated internally. The conversion time is a maximum of 180 ns that is capable of sustaining a 4-MHz throughput. The analog input is provided to two input pins: +IN and -IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. REFERENCE The ADS8422 has a built-in 4.096-V reference but can operate with an external 4.096-V reference. When internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with a 0.1-µF decoupling capacitor and a 1-µF storage capacitor between pin 2 (REFOUT) and pins 47 and 48 (REFM). The internal reference of the converter is double buffered. If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected (floating) if an external reference is used. ANALOG INPUT The ADS8422 has a pseudo-bipolar, fully differential input. When the input is differential, the amplitude of the input equals the difference between +IN and –IN. The peak-to-peak amplitude of each input is VREF. However since the two inputs are 180° out of phase, the peak-to-peak amplitude of the difference voltage [+IN – (–IN)] is equal to 2VREF. The common-mode input range is from VREF/2 – 0.2 V to VREF/2 + 0.2 V. In order to avoid additional external circuitry on the board, the ADS8422 outputs reference input on REFIN divided by 2 on pin 3 (COMMOUT). This voltage can be used to set the common-mode of the output from the input driver. Figure 29, Figure 30, Figure 31, Figure 32, and Figure 33 show the recommended circuits to interface an analog input signal to the ADS8422. Submit Documentation Feedback 15 ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 PRINCIPLES OF OPERATION (continued) 390 W +VIN= Vincm + 4Vpp +VCC 390 W 0.1 mF THS4131 3 12 W 6 +VIN Vincm -VIN 4Vpp 4Vpp 8 2 Vocm 1 mF 1 time 5 220 pF C0G 4 0.1 mF 12 W +IN ADS8422 6 7 -IN COMMOUT 3 -VIN= Vincm + 4Vpp 390 W -VCC 390 W A. Input common-mode voltage (Vincm) range is restricted by the amplifier. Refer to the amplifier data sheet for more information. Output common mode of the THS4131 is set by the voltage at pin 2. The COMMOUT pin of the ADS8422 is designed to source pin 2 of the THS4131. However to use this feature both the positive supply and negative supply rails must equal (|-VCC| = |+VCC|), absolutely. Figure 29. Fully Differential Input Driver Circuit for Unipolar or Bipolar Signals 16 Submit Documentation Feedback ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 PRINCIPLES OF OPERATION (continued) 390 W +Vin=Vincm +8Vpp 390 W +VCC 0.1 mF THS4131 +VIN Vincm -VIN 8Vpp 8 2 Vocm 3 5 220 pF C0G 6 390 W 12 W 6 +IN 1 mF time -Vin=Vincm ADS8422 1 4 0.1 mF 12 W 7 -IN COMMOUT 3 -VCC 390 W A. Input common-mode voltage (Vincm) range is restricted by the amplifier. Refer to the amplifier data sheet for more information. Output common mode of the THS4131 is set by the voltage at pin 2. The COMMOUT pin of the ADS8422 is designed to source pin 2 of the THS4131. However to use this feature both the positive supply and negative supply rails must equal (|-VCC| = |+VCC|), absolutely. Figure 30. Single-Ended Input Driving Circuit for When Input is Unipolar or Bipolar Submit Documentation Feedback 17 ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 PRINCIPLES OF OPERATION (continued) 50 W -VCC 4 Vin = 0 to +4V with Vincm=2.048V 50 W VIN 2.048 4Vpp 2 0.1 mF 6 0.1 mF 12 W 6 +IN THS4031 3 7 +VCC 1000 W 220 pF C0G ADS8422 time 1000 W 12 W -VCC 7 -IN COMMOUT 4 2 THS4031 3 1 mF 7 6 0.1 mF 0.1 mF 3 +VCC Figure 31. Single-Ended Driving Circuit for When Input is Single-Ended Unipolar and has Common-Mode of 2.048 V 50 W -VCC 0.1 mF 6 THS4032 7 0.1 mF 220 pF C0G ADS8422 4 2 12 W 50 W +Vin 0V to +4V with Vcm=2.048V 3 OpAmp A 6 +IN +VIN 2.048V -VIN 4 Vpp +VCC 50 W 4Vpp -VCC time 0.1 mF 4 2 50 W - Vin 0V to +4V with Vcm=2.048V OpAmp B 3 7 6 12 W THS4032 7 -IN 0.1 mF +VCC A. This circuit is used to specify ADS8422 performance parameters listed in the data sheet. Figure 32. Driver Circuit for When Input is Fully Differential Riding on Common-Mode of 2.048 V 18 Submit Documentation Feedback ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 PRINCIPLES OF OPERATION (continued) 49.9 W -VCC 1000 W +4.096V 2 +VIN = 8Vpp with Vincm=0V +4 V +VIN 0.1 mF 4 THS4031 7 6 0.1 mF 12 W 6 +IN 1000 W 3 +VCC 49.9 W 0V -VIN 8Vpp 8Vpp 220 pF C0G ADS8422 -VCC -4V time 0.1 mF 4 1000 W +4.096V 2 3 THS4031 7 6 0.1 mF 12 W 7 -IN -VIN = 8Vpp with Vincm=0V 1000 W +VCC Figure 33. Driver Circuit for Bipolar Fully Differential Input Signals with 0-V Common-Mode The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8422 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (30 pF) to a 16-bit settling level within the 70 ns acquisition time of the device. When the converter goes into hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, both -IN and +IN inputs should be within the limits specified. Outside of these ranges, the converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low pass filters should be used. Care should be taken to ensure that the output impedances of the sources driving the +IN and –IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may result in offset error, gain error, and linearity error which change with temperature and input voltage. When the converter enters hold mode, the voltage difference between the +IN and -IN inputs is captured on the internal capacitor array. DIGITAL INTERFACE Timing and Control See the timing diagrams for detailed information on timing signals and their requirements. The ADS8422 uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. No external clock input is required. Submit Documentation Feedback 19 ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 PRINCIPLES OF OPERATION (continued) Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum requirement has been met, the CONVST pin can be brought high). The converter switches from sample to hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important to the performance of the converter. The BUSY pin is brought high immediately following CONVST going low. BUSY stays high through the conversion process and returns low when the conversion has ended and data is available on the DB pins. Once the conversion is started, it cannot be stopped except with an asynchronous RESET (or a logical PD1). If CONVST is detected high at the end of conversion, the device immediately enters sampling mode and the analog input is connected to the CDAC. Otherwise, the CDAC is connected to the analog input only when CONVST goes high. The high duration of CONVST should be at least 100 ns. There is no maximum high pulse duration specification for CONVST. Reading Data The ADS8422 outputs full parallel data in 2’s complement format as shown in Table 1. The parallel output is active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 30 ns prior to the falling edge of CONVST and 10 ns after the falling edge. No data read should be attempted within this zone. Any other combination of CS and RD three-states the parallel output. BYTE is used for multi-word read operation. BYTE is used whenever lower bits on the bus are output on the higher byte of the bus. Refer to Table 1 for ideal output codes. Table 1. Ideal Input Voltages and Output Codes DESCRIPTION Full scale range Least significant bit (LSB) +Full scale Midscale Midscale – 1 LSB -Full scale ANALOG VALUE 2Vref 2Vref)/65536 (+Vref) – 0V 0V– –Vref+ DIGITAL OUTPUT 2'S COMPLIMENT BINARY CODE 0111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000 HEX CODE 7FFF 0000 FFFF 8000 The output data can be read as a full 16-bit word on pins DB15 – DB0 (MSB-LSB) if BYTE is low. The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15-DB8. In this case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB15-DB8, then bringing BYTE high. When BYTE is high, the low bits (D7-D0) appear on pins DB15-DB8. These multi-word read operations can be performed with a multiple active (toggling) RD signal or with the RD signal tied low for simplicity. Table 2. Conversion Data Read Out DATA READ OUT BYTE High Low PINS DB15–DB8 D7 - D0 D15 - D8 PINS DB7–DB0 All One's D7 - D0 RESET RESET/PD1 is an asynchronous active low input signal. Maximum RESET/PD1 low time is 0.5 µs to avoid ADC powerdown. Current conversion is aborted no later than 20 ns after the converter is in reset mode. The converter returns to normal operation mode no later than 20 ns after the RESET/PD1 input is brought high (see Figure 28). The converter provides two power saving options: ADC powerdown (using pin 38, PD1) and analog output powerdown (PD2). 20 Submit Documentation Feedback ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 ADC powerdown is activated by asserting PD1 to 0 for longer than 1.5 µs. If the signal PD1 is asserted 0 for less than 0.5 µs, the ADC is only reset and any ongoing conversion aborted. See Figure 26. ADC operation can be resumed from ADC powerdown by de-asserting the PD1 pin. In ADC power-down mode, the analog outputs from the ADC(COMMOUT, REFOUT) are not powered down thereby reducing the power-on time. Full chip power-down is activated by turning off the power supply or by asserting both, PD1 = 0 and PD2 = 0 for longer than 1.5 µs (see Figure 27). In this mode, even the analog outputs of the ADC (COMMOUT, REFOUT) are powered down thereby giving maximum power saving. Device operation can be resumed from full chip power-down by turning on the power supply or by deasserting both, PD1 = 1 and PD2 = 1. Table 3. Effects of RESET, PD1, and PD2 COMMAND RESET/PD1 = 0 PD1 = 0, PD2 = 1 PD1 = PD2 = 0 PD1 = 1, PD2 = 0 APPLICATION TIME 20 ns 1.5 µs 1.5 µs POWER WHEN APPLIED No change 17mW 40 µW Reserved – Do not use this combination RESUME TIME 20 ns 5 µs 25 ms LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8422 circuitry. As the ADS8422 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-clock SAR converter, there are n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The 50 ns period before BUSY falls should be kept free of supply glitches. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS8422 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor is recommended from pin 1 directly to REFM (pin 48). REFM and AGND should be shorted on the same ground plane underneath the device. The AGND, BDGND, and AGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA and +VAREG should be connected to their respective power supply planes or traces that are separate from the connection for digital logic, until they are connected at the power entry point. Power to the ADS8422 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 4 for capacitor placement. In addition, a 1-µF to 10-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors — all designed to essentially low-pass filter the +5-V supply, thus removing the high frequency noise. Table 4. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE SUPPLY PINS Pin pairs that require shortest path to decoupling capacitors CONVERTER ANALOG SIDE (4,5), (9,8), (10,12), (13,15), (43,44), (46,45) CONVERTER DIGITAL SIDE (24,25), (34,35) Submit Documentation Feedback 21 ADS8422 www.ti.com SLAS512B – JUNE 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION ADS8422 TO A HIGH PERFORMANCE DSP INTERFACE Figure 34 shows a parallel interface between the ADS8422 and a Texas instruments high performance DSP such as the TMS320C6713 using the full 16-bit bus. The ADS8422 is mapped onto the CE2 memory space of the TMS320C6713 DSP. The read and reset signals are generated by using a 3-to-8 decoder. A read operation from the address 0xA000C000 generates a pulse on the RD pin of the data converter, wheras a read operation form word address 0xA0014000 generates a pulse on the RESET/PD1 pin. The CE2 signal of the DSP acts as CS (chip select) for the converter. As the TMS320C6713 features a 32-bit external memory interface, the BYTE input of the converter can be tied permanently low, disabling the foldback of the data bus. The BUSY signal of the ADS8422 is appiled to the EXT_INT6 interrupt input of the DSP, enabling the EDMA controller to react on the falling edge of this signal and to collect the conversion result. The TOUT1 (timer out 1) pin of the TMS320C6713 is used to source the CONVST signal of the converter. +VAREG = 3 V 0W See Note A 0.1 mF AGND 10 mF 0.1 mF AGND 10 mF 1 mF Ext Ref Input Analog Input +VA = 5 V +VAREG +VA REFIN REFM AGND CE2 TMS320C6713 DSP Address Decoder EA[16:14] ARE TOUT1 EXT_INTG ED[15:0] CS +IN −IN PD1/RESET PD2 ADS8422 RD I/O Supply +VBD +2.7 V +VBD 0.1 mF CONVST BUSY DB[15:0] BDGND BYTE I/O Digital Ground BDGND A. This resistor (0 Ω) can be installed to use the same 5-V supply. Figure 34. ADS8422 Application Circuitry +VAREG = 3 V +VA = 5 V 0W 0.1 mF See Note A 0.1 mF AGND 10 mF 1 mF AGND 10 mF 0.1 mF AGND +VAREG REFOUT REFIN REFM +VA ADS8422 A. This resistor (0 Ω) can be installed to use the same 5-V supply. Figure 35. ADS8422 Using Internal Reference Submit Documentation Feedback 23 AGND PACKAGE OPTION ADDENDUM www.ti.com 18-Dec-2006 PACKAGING INFORMATION Orderable Device ADS8422IBPFBR ADS8422IBPFBT ADS8422IPFBR ADS8422IPFBT (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE Package Type TQFP TQFP TQFP TQFP Package Drawing PFB PFB PFB PFB Pins Package Eco Plan (2) Qty 48 48 48 48 1000 Green (RoHS & no Sb/Br) 250 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR 1000 Green (RoHS & no Sb/Br) 250 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,50 36 25 0,27 0,17 0,08 M 37 24 48 13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,05 MIN 1,05 0,95 Seating Plane 0,75 0,45 Gage Plane 0,25 0°– 7° 12 1,20 MAX 0,08 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. 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