AFE1104E/1KG4

Not Recommended for New Designs ® AFE AFE1104E 110 4 HDSL/MDSL ANALOG FRONT END FEATURES DESCRIPTION ● COMPLETE ANALOG INTERFACE Burr-Brown’s Analog Front End greatly reduces the size and cost of an HDSL or MDSL system by providing all of the active analog circuitry needed to connect PairGain Technologies SPAROW HDSL digital signal processor to an external compromise hybrid and a 1:2 HDSL line transformer. All internal filter responses as well as the pulse former output scale with clock frequency—allowing the AFE1104 to operate over a range of bit rates from 196kbps to 1.168Mbps. ● T1, E1, AND MDSL OPERATION ● CLOCK SCALEABLE SPEED ● SINGLE CHIP SOLUTION ● +5V ONLY (5V OR 3.3V DIGITAL) ● 250mW POWER DISSIPATION ● 48-PIN SSOP ● –40°C TO +85°C OPERATION Functionally, this unit is separated into a transmit and a receive section. The transmit section generates, filters, and buffers outgoing 2B1Q data. The receive section filters and digitizes the symbol data received on the telephone line and passes it to the SPAROW. The HDSL Analog Interface is a monolithic device fabricated on 0.6µCMOS. It operates on a single +5V supply. It is housed in a 48-pin SSOP package. Pulse Former Line Driver txLINEP txLINEN REFP PLLOUT PLLIN Voltage Reference Transmit Control txDAT VCM REFN txCLK rxSYNC rxCLK rxLOOP Receive Control rxLINEP 2 rxGAIN Delta-Sigma Modulator rxLINEN rxHYBP 14 rxD13 - rxD0 Decimation Filter rxHYBN Patents Pending International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1996 Burr-Brown Corporation SBWS002 1 PDS-1331A Printed in U.S.A. August, 1996 AFE1104 Not Recommended for New Designs SPECIFICATIONS Typical at 25°C, AVDD = +5V, DVDD = +3.3V, ftx = 584kHz (E1 rate), unless otherwise specified. AFE1104E PARAMETER RECEIVE CHANNEL Number of Inputs Input Voltage Range Common-Mode Voltage Input Impedance Input Capacitance Input Gain Matching Resolution Programmable Gain Settling Time for Gain Change Gain + Offset Error Output Data Coding Output Data Rate, rxSYNC(3) TRANSMIT CHANNEL Transmit Symbol Rate, ftx T1 Transmit –3dB Point T1 Rate Power Spectral Density(4) E1 Transmit –3dB Point E1 Rate Power Spectral Density(4) Transmit Power(4, 5) Pulse Output Common-Mode Voltage, VCM Output Resistance(6) TRANSCEIVER PERFORMANCE Uncanceled Echo(7) DIGITAL INTERFACE(6) Logic Levels VIH VIL VOH VOL Receive Channel Interface trx1 trx2 trx3 trx4 Transmit Channel Interface ttx1 ttx2 ttx3 POWER Analog Power Supply Voltage Analog Power Supply Voltage Digital Power Supply Voltage Digital Power Supply Voltage Power Dissipation(4, 5, 8) Power Dissipation(4, 5, 8) PSRR COMMENTS MIN Differential Balanced Differential(1) 1.5V CMV Recommended All Inputs 2 Line Input vs Hybrid Input Four Gains: 0dB, 3.25dB, 6dB, and 9dB TYP MAX ±3.0 +1.5 See Typical Performance Curves 10 ±2 14 0 9 6 Tested at Each Gain Range 5 Two’s Complement 98 584 98 Bellcore TA-NWT-3017 Compliant ETSI RTR/TM-03036 Compliant DC to 1MHz 584 196 See Typical Performance Curves 292 See Typical Performance Curves 13 14 See Typical Performance Curves AVDD/2 1 rxGAIN = 0dB, Loopback Enabled rxGAIN = 0dB, Loopback Disabled rxGAIN = 3.25dB, Loopback Disabled rxGAIN = 6dB, Loopback Disabled rxGAIN = 9dB, Loopback Disabled |IIH| < 10µA |IIL| < 10µA IOH = –20µA IOL = 20µA DVDD –1 –0.3 DVDD –0.5 rxCLK Period rxCLK Duty Cycle rxSYNC to rxCLK Setup Time rxCLK to rxSYNC Hold Time rxCLK to rxD13 - rxD0 Delay 35 45 10 10 txCLK Period txCLK Pulse Width Basic txDAT Pulse Unit 1.7 50 10.2 ttx1/96 kHz dBm V Ω ns % ns ns ns µs ns ns 5.25 V V V V mW mW dB +85 °C 5.25 3.3 250 300 60 –40 kHz kHz V V V V 5 TEMPERATURE RANGE Operating(6) kHz DVDD +0.3 +0.8 50 3.15 pF % Bits dB Symbol Periods %FSR(2) dB dB dB dB dB 215 55 4.75 V V –67 –67 –69 –71 –73 +0.4 Specification Operating Range Specification Operating Range DVDD = 3.3V DVDD = 5V UNITS NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the common mode voltage on each pin is ±1.5V to achieve a differential input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (27dBm output from txLINEP and txLINEN). (5) See the Discussion of Specifications section of this data sheet for more information. (6) Guaranteed by design and characterization. (7) Uncanceled Echo is a measure of the total analog errors in the transmitter and receiver sections including the effect of non-linearity and noise. See the Discussion of Specifications section of this data sheet for more information. (8) Power dissipation includes only the power dissipated within the component and does not include power dissipated in the external loads. See the Discussion of Specifications section for more information. ® AFE1104 2 Not Recommended for New Designs PIN DESCRIPTIONS PIN # TYPE NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Ground Power Input Ground Input Output Output Output Output Output Output Ground Power Output Output Output Output Output Output Output Output Input Input Input Input Input Power Input Input Input Input Ground Ground Output Output Output Power Ground Output Power Output Ground NC NC NC NC Output Input PGND PVDD txCLK DGND txDAT rxD0 rxD1 rxD2 rxD3 rxD4 rxD5 DGND DVDD rxD6 rxD7 rxD8 rxD9 rxD10 rxD11 rxD12 rxD13 rxCLK rxSYNC rxGAIN0 rxGAIN1 rxLOOP AVDD rxHYBN rxHYBP rxLINEN rxLINEP AGND AGND REFP VCM REFN AVDD AGND txLINEN AVDD txLINEP AGND NC NC NC NC PLLOUT PLLIN DESCRIPTION Analog Ground for PLL Analog Supply (+5V) for PLL Transmit Symbol Clock (392kHz for T1, 584kHz for E1) Digital Ground DAC+ Line from SPAROW ADC Output Bit-0 ADC Output Bit-1 ADC Output Bit-2 ADC Output Bit-3 ADC Output Bit-4 ADC Output Bit-5 Digital Ground Digital Supply (+3.3V to +5V) ADC Output Bit-6 ADC Output Bit-7 ADC Output Bit-8 ADC Output Bit-9 ADC Output Bit-10 ADC Output Bit-11 ADC Output Bit-12 ADC Output Bit-13 A/D Clock (18.816MHz for T1, 28.03MHz for E1) ADC Sync Signal (392kHz for T1, 584kHz for E1) Receive Gain Control Bit-0 Receive Gain Control Bit-1 Loopback Control Signal (loopback is enabled by positive signal) Analog Supply (+5V) Negative Input from Hybrid Network Positive Input from Hybrid Network Negative Line Input Positive Line Input Analog Ground Analog Ground Positive Reference Output, Nominally 3.5V Common-Mode Voltage (buffered), Nominally 2.5V Negative Reference Output, Nominally 1.5V Analog Supply (+5V) Analog Ground Transmit Line Output Negative Analog Supply (+5V) Transmit Line Output Positive Analog Ground Connection to Ground Recommended Connection to Ground Recommended Connection to Ground Recommended Connection to Ground Recommended PLL Filter Output PLL Filter Input The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 AFE1104 Not Recommended for New Designs PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Top View Analog Inputs: Current .............................................. ±100mA, Momentary ±10mA, Continuous Voltage .................................. AGND –0.3V to AVDD +0.3V Analog Outputs Short Circuit to Ground (+25°C) ..................... Continuous AVDD to AGND ........................................................................ –0.3V to 6V PVDD to PGND ........................................................................ –0.3V to 6V DVDD to DGND ........................................................................ –0.3V to 6V PLLIN or PLLOUT to PGND ......................................... –0.3V to PVDD +0.3V Digital Input Voltage to DGND .................................. –0.3V to DVDD +0.3V Digital Output Voltage to DGND ............................... –0.3V to DVDD +0.3V AGND, DGND, PGND Differential Voltage ......................................... 0.3V Junction Temperature (TJ) ............................................................ +150°C Storage Temperature Range .......................................... –40°C to +125°C Lead Temperature (soldering, 3s) ................................................. +260°C Power Dissipation ......................................................................... 700mW SSOP PGND 1 48 PLLIN PVDD 2 47 PLLOUT txCLK 3 46 NC DGND 4 45 NC txDAT 5 44 NC rxD0 6 43 NC rxD1 7 42 AGND rxD2 8 41 txLINEP rxD3 9 40 AVDD rxD4 10 39 txLINEN rxD5 11 38 AGND DGND 12 37 AVDD DVDD 13 36 REFN rxD6 14 35 VCM rxD7 15 34 REFP rxD8 16 33 AGND AFE1104E rxD9 17 32 AGND rxD10 18 31 rxLINEP rxD11 19 30 rxLINEN rxD12 20 29 rxHYBP rxD13 21 28 rxHYBN rxCLK 22 27 AVDD rxSYNC 23 26 rxLOOP rxGAIN0 24 25 rxGAIN1 PACKAGE/ORDERING INFORMATION PACKAGE AFE1104E 48-Pin Plastic SSOP 333 TEMPERATURE RANGE –40°C to +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® AFE1104 PRODUCT PACKAGE DRAWING NUMBER(1) 4 Not Recommended for New Designs TYPICAL PERFORMANCE CURVES At Output of Pulse Transformer Typical at 25°C, AVDD = +5V, DVDD = +3.3V, unless otherwise specified. POWER SPECTRAL DENSITY LIMIT Power Spectral Density (dBm/Hz) –20 –38dBm/Hz for T1 –40 –80dB/decade T1 –40dBm/Hz for E1 E1 –60 –118dBm/Hz –80 196kHz 292kHz –120dBm/Hz for E1 –100 –120 1K 10K 1M 100K 10M Frequency (Hz) CURVE 1. Upper Bound of Power Spectral Density Measured at the Transformer Output. 0.4T 0.4T B = 1.07 C = 1.00 D = 0.93 QUATERNARY SYMBOLS NORMALIZED LEVEL A B C D E F G H 0.01 1.07 1.00 0.93 0.03 –0.01 –0.16 –0.05 +3 +1 –1 –3 0.0264 2.8248 2.6400 2.4552 0.0792 –0.0264 –0.4224 –0.1320 0.0088 0.9416 0.8800 0.8184 0.0264 –0.0088 –0.1408 –0.0440 –0.0088 –0.9416 –0.8800 –0.8184 –0.0264 0.0088 0.1408 0.0440 –0.0264 –2.8248 –2.6400 –2.4552 –0.0792 0.0264 0.4224 0.1320 1.25T A = 0.01 E = 0.03 F = –0.01 –1.2T –0.6T A = 0.01 H = –0.05 14T G = –0.16 0.5T F = –0.01 50T CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at the Transformer Output. INPUT IMPEDANCE vs BIT RATE 200 Input Impedance (kΩ) T1 = 78kbps, 45kΩ E1 = 1168kbps, 30kΩ 150 100 T1 50 E1 0 100 300 700 500 900 1100 1300 Bit Rate (kbps) CURVE 3. Input Impedance of rxLINE and rxHYB. ® 5 AFE1104 Not Recommended for New Designs THEORY OF OPERATION AFE. The rxHYBP and rxHYBN inputs remain connected. Loopback is enabled by applying a positive signal (Logic 1) to rxLOOP. The transmit channel consists of a switched-capacitor pulse forming network followed by a differential line driver. The pulse forming network receives symbol data from SPAROW’S DAC+ line and generates a 2B1Q output waveform. The output meets the pulse mask and power spectral density requirements defined in European Telecommunications Standards Institute document RTR/TM-03036 for E1 mode and in sections 6.2.1 and 6.2.2.1 of Bellcore technical advisory TA-NWT-001210 for T1 mode. The differential line driver uses a composite output stage combining class B operation (for high efficiency driving large signals) with class AB operation (to minimize crossover distortion). The receive channel is designed around a fourth-order delta sigma A/D converter. It includes a difference amplifier that can be used with an external compromise hybrid for first order analog crosstalk reduction. A programmable gain amplifier with gains of 0dB to +9dB is also included. The delta sigma modulator operating at a 24X oversampling ratio produces 14 bits of resolution at output rates up to 584kHz. The basic functionality of the AFE1104 is illustrated in Figure 1 shown below. ECHO CANCELLATION IN THE AFE The rxHYB input is designed to be subtracted from the rxLINE input for first order echo cancellation. To accomplish this, note that the rxLINE input is connected to the same polarity signal at the transformer (positive to positive and negative to negative) while the rxHYB input is connected to opposite polarity through the compromise hybrid (negative to positive and positive to negative) as shown in Figure 2. RECEIVE DATA CODING The data from the receive channel A/D converter is in two’s complement code. ANALOG INPUT OUTPUT CODE (rxD13 - rxD0) Positive Full Scale Mid Scale Negative Full Scale The receive channel operates by summing the two differential inputs, one from the line (rxLINE) and the other from the compromise hybrid (rxHYB). The connection of these two inputs so that the hybrid signal is subtracted from the line signal is described in the paragraph titled “Echo Cancellation in the AFE”. The equivalent gain for each input in the difference amp is 1. The resulting signal then passes to a programmable gain amplifier which can be set for gains of 0dB through 9dB. The ADC converts the signal to a 14-bit digital word, rxD13 - rxD0. 01111111111111 00000000000000 10000000000000 RECEIVE CHANNEL PROGRAMMABLE GAIN AMPLIFIER The gain of the amplifier at the input of the Receive Channel is set by two gain control pins, rxGAIN1 and rxGAIN0. The resulting gain between 0dB and +9dB is shown below. rxGAIN1 rxLOOP INPUT rxLOOP is the loopback control signal. When enabled, the rxLINEP and rxLINEN inputs are disconnected from the rxGAIN0 GAIN 0 0 0dB 0 1 3.25dB 1 0 6dB 1 1 9dB txLINEP Pulse Former txDAT txLINEN Differential Line Driver rxHYBP rxHYBN 14 rxD13 - rxD0 ADC rxLINEP Programmable Gain Amp FIGURE 1. Functional Block Diagram of AFE1104. ® AFE1104 6 rxLINEN Difference Amplifier Not Recommended for New Designs 0.1µF PLLOUT REFP VCM 0.1µF 0.1µF REFN 1kΩ 0.01µF 200Ω SPAROW 1:2 Transformer Tip 13Ω txLINEP PLLIN 13Ω txLINEN 0.1µF DAC+ txDAT TX_SYM_CLK txCLK HOLD_ Ring Neg Neg 750Ω rxCLK rxHYBP rxLOOP Pos 0.1µF 2kΩ AFE1104 rxGAIN1 100pF 750Ω rxHYBN rxGAIN0 AD13 - AD0 0.01µF Compromise Hybrid rxSYNC MCLK19_2 Pos REFN 2kΩ 0.1µF rxD13 - rxD0 Input antialias filter fC ≅ 1MHz 14 rxLINEN AGND 750Ω PGND 100pF DGND AGND 0.1µF 2kΩ REFN 2kΩ rxLINEP AGND 0.1µF 750Ω AGND PVDD DVDD AVDD AVDD AVDD 5V to 3.3V Digital 5V Analog 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF + 1 - 10µF 5 - 10Ω resistor for isolation FIGURE 2. Basic Connection Diagram. rxHYB AND rxLINE INPUT ANTI-ALIASING FILTERS The –3dB frequency of the input anti-aliasing filter for the rxLINE and rxHYB differential inputs should be about 1MHz. Suggested values for the filter are 750Ω for each of the two input resistors and 100pF for the capacitor. Together the two 750Ω resistors and the 100pF capacitor result in a –3dB frequency of just over 1MHz. The 750Ω input resistors will result in a minimal voltage divider loss with the input impedance of the AFE1104. rxHYB AND rxLINE INPUT BIAS VOLTAGE The transmitter output on the txLINE pins is centered at midscale, 2.5V. But, the rxLINE input signal is centered at 1.5V in the circuit shown in Figure 2 above. Inside the AFE1104, the rxHYB and rxLINE signals are subtracted as described in the paragraph on echo cancellation above. This means that the rxHYB inputs need to be centered at 1.5V just as the rxLINE signal is centered at 1.5V. REFN (Pin 36) is a 1.5V voltage source. The external compromise hybrid must be designed so that the signal into the rxHYB inputs is centered at 1.5V. This circuit applies at both T1 and E1 rates. For slower rates, the antialiasing filters will give best performance with their –3dB frequency approximately equal to the bit rate. For example, a –3dB frequency of 500kHz should be used for a single pair bit rate of 500kbps. ® 7 AFE1104 Not Recommended for New Designs TIMING DIAGRAMS ttx2 txCLK txCLK48 (Internal) txDAT (+3 Symbol) txDAT (+1 Symbol) txDAT (–1 Symbol) txDAT (–3 Symbol) txDAT (0 Symbol) txDAT (0 Symbol) ttx3 3ttx3 5ttx3 7ttx3 9ttx3 NOTES: (1) ttx1 is the txCLK period which is 1/(Symbol Rate). (2) txCLK48 is an internal 48X oversample clock generated by an on-chip phase-locked loop from the txCLK signal. (3) txDAT is sampled on the first four rising edges of txCLK48 during each symbol period. (4) All transitions are specified relative to the falling edge of txCLK. (5) Maximum allowable error for any edge is ± ttx1/96 (±17.8ns at E1 rate; ±26.6ns at T1 rate). FIGURE 3. Transmit Channel Timing. trx1 rxCLK trx3 trx2 rxSYNC trx4 rxD13 - rxD0 trx4 Data 1a Data 1 Data 2 ttx1/2 NOTES: (1) rxCLK is an externally supplied clock with a frequency of 48 times the symbol rate. It is divided by 2 in the AFE1104 and used as the 24X oversampling clock of the delta-sigma A/D converter. (2) rxSYNC controls the availability of the 14-bit output of the A/D converter. FIGURE 4. Receive Channel Timing. ® AFE1104 8 Not Recommended for New Designs RECEIVE TIMING both to the AFE and to the input of an adaptive filter. The output of the adaptive filter is subtracted from the AFE output to form the uncanceled echo signal. Once the filter taps have converged, the RMS value of the uncancelled echo is calculated. Since there is no far-end signal source or additive line noise, the uncanceled echo contains only noise and linearity errors generated in the transmitter and receiver. The rxSYNC signal controls portions of the A/D converter’s decimation filter and the data output timing of the A/D converter. It is generated at the symbol rate by the user and must be synchronized with rxCLK. The bandwidth of the A/D converter decimation filter is equal to one half of the symbol rate. The A/D converter data output rate is 2X the symbol rate. The specifications of the AFE1104 assume that one A/D converter output is used per symbol period and the other interpolated output is ignored. The Receive Timing Diagram suggests using the rxSYNC pulse to read the first data output in a symbol period. Either data output may be used. Both data outputs may be used for more flexible postprocessing. The data sheet value for uncancelled echo is the ratio of the RMS uncanceled echo (referred to the receiver input through the receiver gain) to the nominal transmitted signal (13.5dBm into 135Ω, or 1.74Vrms). This echo value is measured under a variety of conditions: with loopback enabled (line input disconnected); with loopback disabled under all receiver gain ranges; and with the line shorted (S1 closed in Figure 5). DISCUSSION OF SPECIFICATIONS POWER DISSIPATION Approximately 75% of the power dissipation in the AFE1104 is in the analog circuitry, and this component does not change with clock frequency. However, the power dissipation in the digital circuitry does decrease with lower clock frequency. In addition, the power dissipation in the digital section is decreased when operating from a smaller supply voltage, such as 3.3V. (The analog supply, AVDD, must remain in the range 4.75V to 5.25V). UNCANCELED ECHO The key measure of transceiver performance is uncanceled echo. This measurement is made as shown in the diagram of Figure 5 and the measurement is made as follows. The AFE is connected to an output circuit including a typical 1:2 line transformer. The line is simulated by a 135Ω resistor. Symbol sequences are generated by the tester and applied 13Ω Transmit Data txDATP 1:2 5.6Ω txLINEP 13Ω 5.6Ω 135Ω S1 txLINEN 576Ω 0.047µF rxHYBP 1.54kΩ 2kΩ 150Ω 2kΩ 100pF Adaptive Filter AFE1104 0.01µF rxHYBN 576Ω 0.047µF 0.1µF 750Ω rxLINEP 2kΩ 100pF 2kΩ rxLINEN 750Ω Uncancelled Echo rxD13 - rxD0 0.1µF REFN FIGURE 5. Uncanceled Echo Test Diagram. ® 9 AFE1104 Not Recommended for New Designs The power dissipation listed in the specifications section applies under these normal operating conditions: 5V Analog Power Supply; 3.3V Digital Power Supply; standard 13.5dBm delivered to the line; and a pseudo-random equiprobable sequence of HDSL output pulses. The power dissipation specifications includes all power dissipated in the AFE1104, it does not include power dissipated in the external load. The external power is 16.5dBm, 13.5dBm to the line and 13.5dBm to the impedance matching resistors. The external load power of 16.5dBm is 45mW. The typical power dissipation in the AFE1104 under various conditions is shown in Table I. BIT RATE PER AFE1104 (Symbols/sec) DVDD (V) TYPICAL POWER DISSIPATION IN THE AFE1104 (mW) 584 (E1) 584 (E1) 392 (T1) 392 (T1) 146 (E1/4) 146 (E1/4) 3.3 5 3.3 5 3.3 5 250 300 240 270 230 245 pins of the AFE11104 (pins 3 through 26). However, DVDD may be supplied by a wide printed circuit board (PCB) trace. A digital ground plane underneath all digital pins is strongly recommended. The phase-locked loop is powered from PVDD (pin 2) and its ground is referenced to PGND (pin 1). Note that PVDD must be in the 4.75V to 5.25V range. This portion of the AFE1104 should be decoupled with both a 10µF Tantalum capacitor and a 0.1µF ceramic capacitor. The ceramic capacitor should be placed as close to the AFE1104 as possible. The placement of the Tantalum capacitor is not as critical, but should be close. In each case, the capacitor should be connected between PVDD and PGND. In most systems, it will be natural to derive PVDD from the AVDD supply. A 5Ω to 10Ω resistor should be used to connect PVDD to the analog supply. This resistor in combination with the 10µF capacitor form a lowpass filter— keeping glitches on AVDD from affecting PVDD. Ideally, PVDD would originate from the analog supply (via the resistor) near the power connector for the printed circuit board. Likewise, PGND should connect to a large PCB trace or small ground plane which returns to the power supply connector underneath the PVDD supply path. The PGND “ground plane” should also extend underneath PLLIN and PLLOUT (pins 47 and 48). TABLE I. Typical Power Dissipation. LAYOUT The remaining portion of the AFE1104 should be considered analog. All AGND pins should be connected directly to a common analog ground plane and all AVDD pins should be connected to an analog 5V power plane. Both of these planes should have a low impedance path to the power supply. The analog front end of an HDSL system has a number of conflicting requirements. It must accept and deliver digital outputs at fairly high rates of speed, phase-lock to a highspeed digital clock, and convert the line input to a highprecision (14-bit) digital output. Thus, there are really three sections of the AFE1104: the digital section, the phaselocked loop, and the analog section. Ideally, all ground planes and traces and all power planes and traces should return to the power supply connector before being connected together (if necessary). Each ground and power pair should be routed over each other, should not overlap any portion of another pair, and the pairs should be separated by a distance of at least 0.25 inch (6mm). One exception is that the digital and analog ground planes should be connected together underneath the AFE1104 by a small trace. The power supply for the digital section of the AFE1104 can range from 3.3V to 5V. This supply should be decoupled to digital ground with a ceramic 0.1µF capacitor placed as close to DGND (pin 12) and DVDD (pin 13) as possible. Ideally, both a digital power supply plane and a digital ground plane should run up to and underneath the digital ® AFE1104 10 PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) TBD Lead/ Ball Finish (3) NRND SSOP DL 48 AFE1104E/1K NRND SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR AFE1104E/1KG4 NRND SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR AFE1104EG4 NRND SSOP DL 48 Call TI Samples (Requires Login) AFE1104E TBD Call TI MSL Peak Temp Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device AFE1104E/1K Package Package Pins Type Drawing SSOP DL 48 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 32.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 11.35 16.2 3.1 16.0 32.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AFE1104E/1K SSOP DL 48 1000 346.0 346.0 49.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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