AFE1231KG4

AFE1230 AFE 123 0 SBWS015A – AUGUST 2001 G.SHDSL ANALOG FRONT-END FEATURES q q q q q q q q q q E1, T1, AND SUBRATE OPERATION COMPLIES WITH G.SHDSL AND HDSL2 16-BIT, DELTA-SIGMA CONVERTERS ON-CHIP DRIVER AND PGA PROGRAMMABLE tx AND rx FILTERS SERIAL DIGITAL INTERFACE 750mW POWER DISSIPATION AT E1 +5V POWER (5V OR 3.3V DIGITAL) SSOP-28 PACKAGE –40°C TO +85°C TEMPERATURE RANGE SC (Switched Capacitor) low-pass filter, and a differential output line driver. The receiver section includes an input Programmable Gain Amplifier (PGA), a 16-bit, delta-sigma Analog-to-Digital (A/D) converter, and a programmable decimation filter. The AFE1230 receives a 16-bit data word plus an 8-bit control byte via the serial interface to facilitate the D/A conversion and control functions. The subsequent analog signal is sent to the on-chip line driver that provides 14.5dBm power into a 135Ω line for G.SHDSL operation. In addition, the on-chip line driver can be used as an output buffer with an external line driver, such as the OPA2677, to generate over 17dBm power into a 135Ω line for HDSL2 operation. With an appropriate DSP, the transmitted Power Spectral Density (PSD) complies with either the G.SHDSL standard or with the HDSL2 standard (via an OPA2677 used as an external driver). In the receive path, the input amplifier sums the signals from the line and hybrid path to perform first-order analog echo cancellation. The resultant signal is then digitized by the rest of the receive section into a 16-bit digital word that is sent to the external DSP. This IC operates on a single 5V supply, while the digital supply can be from 3.3V to 5V. It is housed in a SSOP-28 package. The typical power consumption is 750mW at E1 rates with G.SHDSL (560mW for HDSL2 operation) and an operation temperature range of –40°C to +85°C. DESCRIPTION Texas Instrument’s analog front-end chip, the AFE1230, is designed to greatly reduce the size and cost of G.SHDSL and HDSL2 application designs. It provides a transceiver as the line interface between the Digital Signal Processor (DSP) and the local loop. The AFE1230 is designed to handle upstream and downstream data transmission over a wide range of data rates from 64kbps to 2.5Mbps. Functionally, this unit consists of a transmitter and receiver section. The transmitter section consists of a digital interpolation filter, a 16-bit, delta-sigma Digital-to-Analog (D/A) converter, a digitally programmable fifth-order or seventh-order Digital Interpolation LPF ∆Σ 16-Bit D/A Converter Programmable SC LPF Driver/ Buffer txLINE txLINE MCLK txBaud txData rxBaud rxData tx and rx Digital Interface Registers hybINPUT Programmable Digital LPF ∆Σ 16-Bit A/D Converter PGA Input Amplifier hybINPUT rxINPUT rxINPUT AFE1230 Patents Pending Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001, Texas Instruments Incorporated www.ti.com ABSOLUTE MAXIMUM RATINGS Analog Input: Current ................................................ ±100mA, Momentary Analog Input: Current .................................................. ±10mA, Continuous Analog Input: Voltage ................................... AGND –0.3V to AVDD +0.3V Analog Outputs Short-Circuit to Ground (+25°C) ..................... Continuous AVDD to AGND ...................................................................... –0.3V to +6V DVDD to DGND ...................................................................... –0.3V to +6V Digital Input Voltage to DGND .................................. –0.3V to DVDD +0.3V Digital Output Voltage to DGND ............................... –0.3V to DVDD +0.3V AGND, DGND Differential Voltage ..................................................... 0.3V Junction Temperature (Tj) ............................................................... 150°C Storage Temperature Range .......................................... –40°C to +125°C Lead Temperature Range (soldering, 3s) ...................................... +260°C Power Dissipation ........................................................................ 1000mW ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER 324 PACKAGE DESIGNATOR DBQ " SPECIFIED TEMPERATURE RANGE –40°C to +85°C " PACKAGE MARKING AFE1230E ORDERING NUMBER(1) AFE1230E AFE1230E/1K TRANSPORT MEDIA Rail Tape and Reel PRODUCT AFE1230E AFE1230E/1K PACKAGE SSOP-28 " " " NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “AFE1230E/1K” will get a single 1000-piece Tape and Reel. The AFE1230E/1K can only be ordered in 1000-unit increments. PIN CONFIGURATION Top View SSOP PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME DVDD GNDD txBaud txData MCLK rxBaud rxData DVDD GNDD GNDA HybP HybM LineP LineM GNDA GNDA VREFP VCM VREFM AVDD AVDD AVDD GNDA txOutM AVDD txOutP GNDA GNDA TYPE Power Ground Input Input Input Input Output Power Ground Ground Input Input Input Input Ground Ground Output Output Output Power Power Power Ground Output Power Output Ground Ground DESCRIPTION Digital Supply Digital Ground Transmit Baud Clock Digital Input of Transmit Section Master Clock 48x Clock Recieve Baud Clock Digital Output of Recieve Section Digital Supply Digital Ground Analog Ground Positive Hybrid Input Negative Hybrid Input Positive Line Input Negative Line Input Analog Ground—Recieve Analog Ground—Reference Positive Reference Voltage, rx/tx Common-Mode Voltage, rx/tx Negative Reference Input, rx/tx Analog Supply—Reference Analog Supply—Recieve Analog Supply—Transmit Analog Ground/Driver Line Driver Output Negative Analog Supply/Driver Line Driver Output Positive Analog Ground/Driver Analog Ground Transmit DVDD GNDD txBaud txData MCLK rxBaud rxData DVDD GNDD GNDA HybP HybM LineP LineM 1 2 3 4 5 6 7 AFE1230 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GNDA GNDA txOutP AVDD txOutM GNDA AVDD AVDD AVDD VREFM VCM VREFP GNDA GNDA 2 AFE1230 SBWS015A ELECTRICAL CHARACTERISTICS All specifications are typical at 25°C, AVDD = +5V, DVDD = +3.3V, MCLK = 37.1MHz (E1 rate), unless otherwise noted. AFE1230E PARAMETER RECEIVE CHANNEL Number of Inputs Input Voltage Range Common-Mode Voltage A/D Converter Code Programmable Gain Range Gain Absolute Accuracy Gain Step Accuracy Settling Time for Gain Change Output Data Coding MCLK System Bit Rate Symbol Rate Output Word Rate (OWR) Filter Cutoff Frequency(3) TRANSMIT CHANNEL D/A Converter Code Output Line Power(4) CONDITIONS MIN TYP MAX UNITS Differential Balanced Differential(1) ∆Σ A/D Converter 3dB Steps RIN = 10kΩ 3dB Steps, Accuracy Relative to Gain = 1 Binary Two's Complement Master Clock Three Bits/Symbol Two rx Words/Symbol Period(2) Programmable 5th-Order LPF, 0.25x and 0.5x OWR ∆Σ D/A Converter Internal Line Driver, PAR = 3, Provides 14.5dBm at 135Ω Line with 1:3.7 Transformer Internal Line Buffer, PAR = 4, Load is External Driver OPA2677 Balanced Differential DC to 1MHz Binary Two's Complement Master Clock Three Bits/Symbol Three Bits/Symbol Two Words/Symbol Period 5th or 7th LPF, 0.25x, 0.38x, 0.5x IWR rxGAIN = 12dB 2 ±3.1 AVDD/2 16 0 ±20% ±0.5 6 16 1.28 80k 26.7 53.4 0.25 40.8 2.55M 850 1700 0.5 +21 V V Bits dB % dB Symbol Periods Bits MHz bps kHz kHz OWR 16 14.5 Bits dBm Output Power(5) Output Voltage Common-Mode Voltage, VCM Output Resistance Input Data Coding MCLK System Bit Rate Input Symbol Rate Input Word Rate (IWR) Filter Cutoff Frequency(6) TRASNSCEIVER PERFORMANCE Uncancelled Echo(7) DIGITAL INTERFACE Logic Levels: VIH VIL VOH VOL POWER Analog Power-Supply Voltage Analog Power-Supply Voltage Digital Power-Supply Voltage Digital Power-Supply Voltage Power Dissipation(8) Power Dissipation(9) PSRR TEMPERATURE RANGE Operating(10) 10 ±3.1 AVDD/2 0.2 16 1.28 80k 26.7 53.4 0.25 40.8 2.55M 850 1700 0.5 –80 dBm V V Ω Bits MHz bps kHz kHz IWR dB |IIH| < 10µA |IIL| < 10µA IOH = –20µA IOL = 20µA Specification Operating Range Specification Operating Range AVDD = 5V, DVDD = 3.3V, 14.5dBm at 135Ω Line, E1 AVDD = 5V, DVDD = 3.3V DVDD – 1 –0.3 DVDD – 0.5 DVDD + 0.3 +0.8 +0.4 5 V V V V V V V V mW mW dB 4.75 3.3 3.15 750 560 60 –40 5.25 5.25 +85 °C NOTES: (1) With a balanced differential signal, the positive input is 180° out-of-phase with the negative input, therefore, the actual voltage swing about the commonmode voltage on each pin is ±1.55V to achieve a total input range of ±3.1V or 6.2Vp-p. (2) The A/D converter oversamples the receive signal and outputs data words at twice the symbol rate; the A/D converter conversion rate is called the Output Word Rate (OWR). (3) The digital low-pass filter that is part of the A/D converter can be programmed by the user for a 3dB frequency of 1/2 of the OWR or 1/4 of the OWR. (4) The internal line driver is designed for G.SHDSL. (5) An external driver (OPA2677) should be used for HDSL2 application. (6) The cutoff frequencies are user programmable. (7) Uncancelled echo is the sum of all noise and distortion errors for both the transmit and receive channels. (8) For a random sequence of the symbol, using an internal driver providing 14.5dBm power to the line for G.SHDSL. (9) For a random sequence while driving an external line driver (OPA2677) for HDSL2. (10) Functionality only guaranteed over temperature range. AFE1230 SBWS015A 3 APPLICATION INFORMATION THEORY OF OPERATION The AFE1230 consists of a transmitter and receiver section, as shown in Figure 1; the transmitter section consists of a digital interpolation filter, a 16-bit, delta-sigma D/A converter, a programmable fifth-order or seventh-order SC low-pass filter, and a differential output line driver. The receiver section includes a digitally programmable gain amplifier, a 16-bit, delta-sigma A/D converter, and a decimation filter. The AFE1230 receives a 16-bit word plus an 8-bit control byte via the serial interface to facilitate the D/A conversion and control functions. The received 16-bit word is up sampled by two through the digital interpolation filter, then oversampled by the delta-sigma modulator by a factor of 12x where it is then processed by the multilevel D/A converter section before being filtered by the fifth-order or seventh-order Butterworth lowpass SC filter section. The subsequent analog signal is sent to the on-chip line driver where the analog signal can be driven into an appropriate transformer to provide up to 14.5dBm power into a 135Ω line for G.SHDSL. In addition, the on-chip line driver can be used as an output buffer to generate 17dBm into a 135Ω line via an external line driver (such as the OPA2677) for HDSL2. With an appropriate DSP, the transmitted PSD complies with either the G.SHDSL standard or, with an OPA2677 used as an external driver, the HDSL2 standard. In the receive path, the input amplifier sums the signals from the line and hybrid paths to perform first-order analog echo cancellation. The resultant signal is then digitized by a fourth-order cascaded delta-sigma A/D converter with an OSR (OverSampling Ratio) of 24x. The subsequent oversampled signal is processed by a sinc5 filter as well as a programmable IIR filter for droop compensation and additional quantization noise reduction. The resulting digital signal is sent to the serial interface for processing by the DSP. Transmit Filter The transmit filter consists of two sections, a digital interpolation filter and a programmable SC low-pass filter (SCLPF). The interpolation filter is an anti-imaging low-pass filter. The SCLPF serves two important functions. First it is designed to remove quantization noise from the delta-sigma D/A converter in the front end of the transmit path. Secondly, the filter is used to help shape the received digital signal’s spectral density in conjunction with pre-spectral shaping within the DSP. Depending on the particular response desired, the transmit filter section can be programmed for three different breakpoints, as shown in Table 1, as well as two filter order (fifth or seventh) configurations. The 3dB frequency listed in Table I is in relation to the designed breakpoint for the SC filter only. However, because the digital signal is sampled and held for 24 more samples (the AFE1230 increases the sample rate by 24x in relation to the input data rate), the actual transmit spectral curves contain a small amount of droop due to the sinc function performed by the sample and hold function of the delta-sigma modulator section of the transmit path. See Figures 2 and 3 for the overall spectral templates. tx CUTOFF (txData Bits 29, 28) 00 01 10 RATIO (Corner Frequency) 0.25 MCLK/24 0.38 MCLK/24 0.5 MCLK/24 TABLE I. tx Filter Cutoff Frequency Setting. Digital Interpolation LPF ∆Σ 16-Bit D/A Converter Programmable SC LPF Driver/ Buffer txLINE OPA2677 txLINE External Driver for HDSL2 MCLK txBaud txData rxBaud rxData tx and rx Digital Interface Registers VrRef hybINPUT Programmable Digital LPF ∆Σ 16-Bit A/D Converter PGA Input Amplifier hybINPUT rxINPUT rxINPUT AFE1230 Patents Pending FIGURE 1. Functional Block Diagram of the AFE1230. 4 AFE1230 SBWS015A 0 –50 –100 –150 –200 –250 –300 10–3 10–2 10–1 100 FIGURE 2. Overall Transmit Filter. D/A Converter Frequency Response, Fifth-Order with 0.25x, 0.38x, and 0.5x. 0 –50 –100 –150 –200 –250 –300 –350 10–3 10–2 10–1 100 FIGURE 3. Overall Transmit Filter. D/A Converter Frequency Response, Seventh-Order with 0.25x, 0.38x, and 0.5x. Receive Filter The receive filter consists of three independent sections used for both the removal of quantization noise as well as the reduction of data rate (otherwise known as downsampling). The first section is comprised of a sinc5 filter with a downsampling ratio of 12x. The resulting digital signal is then passed to a droop compensation filter before being sent through the final IIR filter section, while being downsampled by two. Two filter cutoff configurations are available, as seen in Table II. The corresponding cutoff frequencies relate to the full-rate low-pass filter spectral template of the filter, as seen from the inputs of Table II. rx CUTOFF (txData Bit 24) 0 1 RATIO (Corner Frequency) 0.25 MCLK/24 0.5 MCLK/24 TRANSMIT POWER BACK OFF CODE (txData Bits 25, 26) 00 01 10 11 TRANSMIT POWER REDUCTION 0dB –6dB –12dB –18dB TRANSMIT POWER G.SHDSL HDSL2 14.5dBm 8.5dBm 2.5dBm –4.5dBm 17.0dBm 11.0dBm 5.0dBm –1.0dBm Transmit Power The on-chip differential line driver is designed to drive G.SHDSL power levels directly, or it can be used as a low-power buffer for driving a higher power external driver (for example the OPA2677) for applications such as HDSL2. The AFE1230 driver will generate an output swing of 6.2V peak-to-peak differential. When used with a suitable transformer (see Figures 8 and 10), the AFE1230 can generate up to 14.5dBm of power into a 135Ω line load. When used as a buffer with an OPA2677 driver, 17dBm of power can be generated. Relative transmit power can be controlled digitally through control bits sent to the transmit section by the serial interface. Relative transmit power reduction can be set to 0, –6, –12, or –18dB, depending on the control bits presented to the AFE1230, as shown in Table III. TABLE II. rx Filter Cutoff Frequency Setting. TABLE III. Transmit Power Backoff. AFE1230 SBWS015A 5 Receive Amplifier The AFE1230 receive channel includes an input amplifier with a differential summer junction on-chip for echo cancellation, as shown in Figure 4. Four external resistors are needed with 10kΩ as the required value for each receiverinput pair as well as 20kΩ for each hybrid-input pair. The common-mode voltage of the receive amplifier is AVDD/2 (typical value is 2.5V). Serial Digital Interface Operation The AFE1230 digital interface uses a five-line serial interface, signal names are: Master Clock (MCLK), Transmit Baud Clock (txBaud), Transmit Data (txData), Receive Baud Clock (rxBaud), and Receive Data (rxData). MCLK, txBaud, rxBaud, and txData must come from the external DSP where data is transmitted in synchronization with MCLK. MCLK is used as the internal master clock to the AFE1230 and can run up to 40.8MHz. txBaud and rxBaud must be the same frequency and synchronous with MCLK, however, the phase of these signals may be different. Each baud period contains 48 MCLK cycles. During each baud cycle, txData will contain two 16-bit transmit words with two control bytes. Each bit is latched internally to the AFE at the rising edge of MCLK. Figures 5, 6, and 7 illustrate the bit designations as well as the proper timings required to operate the AFE1230. MCLK: The master clock of AFE1230 for both transmit and receive sections, generated by the DSP. It runs at 48x the symbol rate and can be varied from 1.28MHz to 40.8MHz (37.12MHz for E1). MCLK must use a 50/50 duty cycle. txBaud: The transmit data baud clock, generated by the DSP. txBaud is 517.33kHz for T1 and 773.33kHz for E1 (2.3Mbps). It may vary from 26.7kHz to 850kHz. A txBaud period consists of 48 periods of the MCLK. The time (tW) of the txBaud should not be smaller than one MCLK period. Within the period of 48 MCLK clocks, the rising edge of the txBaud can occur any time except in the period of tF, and the falling edge of txBaud can occur at any time of the tF period. txData: The input digital data of AFE1230. This signal comes from an external DSP with 48 bits per baud period. The 48 bits include two 16-bit words of D/A converter input data and two 8-bit control bytes (see Tables IV and V). The D/A converter is updated two times per symbol period and data is latched by the AFE1230 on the rising edge of MCLK. txData must be stable at least 2.5ns before the rising edge of MCLK and it must remain stable at least 2.5ns after the rising edge of MCLK. rxBaud: The receive data baud clock, generated by the DSP. rxBaud is 517.33kHz for T1 and 773.33kHz for E1 (2.3Mbps). It may vary from 26.7kHz to 850kHz. One rxBaud period consists of 48 periods of the MCLK. Within the period of 48 MCLK clocks, the rising edge of the rxBaud can occur at any time except in tF period, and the falling edge of rxBaud can occur at any time during tF. The width of the rxBaud pulse should be no shorter than one period of MCLK. rxData: The output digital data of AFE1230, sent to the external DSP with 48 bits per baud period. The 48 bits include two 16-bit words of receive data and two 8-bit control words (Reserved) (see Tables VI and VII). The A/D converter is updated two times per symbol period and rxData is changed by AFE1230 at the falling edge of MCLK. rxData is stable at least 2.5ns before the rising edge of MCLK and it remains stable at least 2.5ns after the rising edge of MCLK. RF R3 R4 Vhy Vrx R5 R6 External Circuit R3 = R5 = 20kΩ R4 = R6 = 10kΩ hy+ rx+ hy– rx– Internal Amp Vp-p ≤ 6.2V ∆Σ A/D Converter RF FIGURE 4. Internal Receive Amplifier. 6 AFE1230 SBWS015A txBaud, Transmit Baud Clock txData, Transmit Data G.SHDSL DSP MCLK, Master Clock (48x) rxBaud, Receive Baud Clock rxData, Receive Data AFE1230 FIGURE 5. AFE1230/DSP Digital Interface. tF tF txBaud tW MCLK 0 1 47 0 1 txData Bit 0 2.5ns Bit 47 2.5ns Bit 0 5ns Bit 47 FIGURE 6. AFE1230 Transmit Timing Diagram. tF rxBaud 6ns MCLK 0 1 47 0 1 rxData Bit 0 Bit 47 1ns Bit 0 5ns Bit 47 FIGURE 7. AFE1230 Receive Timing Diagram. AFE1230 SBWS015A 7 MSB 16 1 1 2 1 2 1 16 2 3 2 1 rx Cutoff Frequency tx Power Backoff tx Filter Order tx Cutoff Frequency Spare Low Power tx DAC Word 1 Spare Loopback rx Gain Spare tx DAC Word 2 TABLE IV. tx Data Structure. BIT 47-32 31 30 29-28 DESCRIPTION tx D/A Converter Word 1 Power Control Reserved(1) tx Cutoff Frequency Control BIT STATE XXXX 0 1 0 00 01 10 11 0 1 00 01 10 11 0 1 XXXX 00 000 001 010 011 100 101 110 111 00 01 10 11 0 OUTPUT STATE 16-Bit Binary Two's Complement Word to tx D/A Converter (MSB First) Normal Power, Any Speed Low Power, Low Speed (< 1/2 Full Word Rate) Reserved for Future Use 0.25x Word Rate 0.38x Word Rate 0.5x Word Rate Not Used Fifth-Order Butterworth Seventh-Order Butterworth Normal Transient Power Normal Transient Power –6dB Normal Transient Power –12dB Normal Transient Power –18dB 0.25x Word Rate 0.5x Word Rate 16-Bit Binary Two's Complement Word to tx D/A Converter (MSB First) Reserved for Future Use rx Gain = 0dB rx Gain = 3dB rx Gain = 6dB rx Gain = 9dB rx Gain = 12dB rx Gain = 15dB rx Gain = 18dB rx Gain = 21dB Normal Operation Loop-Back Mode Digital, tx Data to rx Data Hybrid Mode, Line Input Connected to VCM Line Mode, Hybrid Input Connected to VCM Reserved 27 26-25 tx Filter Order tx Power Backoff 24 23-8 7-6 5-3 rx Cutoff Frequency Control tx D/A Converter Word 2 Reserved(1) rx Gain Settings 2-1 Loop-Back Control 0 Reserved(1) NOTE: (1) Reserved Bits must be set to 0. TABLE V. tx Data Format. 8 AFE1230 SBWS015A MSB 16 8 16 8 Spare rx Data Word 2 Spare rx Data Word 1 TABLE VI. rx Data Structure. BIT 47-32 31-24 23-8 7-0 DESCRIPTION rx A/D Converter Word 1 Reserved rx A/D Converter Word 2 Reserved BIT STATE XXXX Set All Bits Always to 0 XXXX Set All Bits Always to 0 OUTPUT STATE 16-Bit Binary Two's Complement Word from rx A/D Converter (MSB First) Reserved for Future Use 16-Bit Binary Two's Complement Word from rx A/D Converter (MSB First) Reserved for Future Use TABLE VII. rx Data Format. Digital Data Scale The digital input and output data is coded in Binary Two’s complement with 16 bits; the scale is shown in Table VIII. ANALOG INPUT A/D CONVERTER DATA MSB Positive Full Scale Mid Scale Negative Full Scale 0111111111111111 0000000000000000 1000000000000000 LSB or txBaud symbol clocks move one MCLK period forward or backward, resulting in 49 or 47 MCLK cycles per rxBaud), the receive data will be invalid for six symbol periods while the data settles to the final value. Loop Back The AFE1230 includes digital and analog loop-back options, as shown in Table IX. Echo Cancellation in the AFE1230 The rxHYB input is designed to be subtracted from the rxLINE input for first-order echo cancellation. To accomplish this, note that the rxLINE input is connected to the same polarity signal at the transformer (+ to + and – to –), while the rxHYB input is connected to opposite polarity through the compromise hybrid (– to + and + to –). TABLE VIII. Digital Input/Output Data Scale. Sampling Phase The DSP will determine the sampling phase used for the AFE1230. In the case of a phase jump (i.e.: when the rxBaud LOOPBACK Loopback Loopback Loopback Loopback = = = = 00 01 10 11 OPERATION Normal Operation Digital Loopback: Data In is Shortened to Data Out. Analog Loopback: The rxLINE inputs are shortened to VCM, while the transmit and rxHYB inputs are connected normally. Analog Loopback: The rxHYB inputs are shortened to VCM, while the transmit and rxLINE inputs are connected normally. TABLE IX. Loopback Table. AFE1230 SBWS015A 9 APPLICATIONS AFE1230 BASIC APPLICATION CIRCUITS There are two basic circuits for AFE1230 evaluation and applications in this section. Figure 8 is a basic setting of a 135Ω line interface circuit, used to test the basic transmit and receive functions as well as uncancelled echo of the AFE1230. In the circuit, R1 and R2 are used to control far-end reflection and maximize the energy exchange between the transmitter and loop. The value of R1 and R2, (see Figure 8), is designed to match a 135Ω line with turns ratio of 1:3.7 (device:line) transformer from Midcom (51185 Rev6A). R4 and R6 are line input resistors; 10kΩ is a suggested value. R3 and R5 are hybrid input resistors that control the echo cancellation. The two 53nF capacitors are used for external transmit low-pass filters with a cutoff frequency about 600kHz. When Figure 8 is used for uncancelled echo test, it provides total noise measurement of AFE1230 transmit and receive paths (this includes linearity error, distortion, and noise). The measurement of uncancelled echo is made as follows: the AFE1230 is connected to the external circuit (see Figure 8) and the hybrid resistors can be different values. The line is simulated by a 135Ω resistor. A symbol sequence is generated by the tester and sent to both the AFE1230 and an external adaptive filter. The symbol sequence through the transmit path is then loopbacked to the hybrid input and line input. Different loopback conditions are applied in the test, such as line input disconnected, hybrid input disconnected, or 135Ω resistor shorted. The output of the adaptive filter is subtracted from the AFE1230 output to form the uncancelled echo signal. Since there is no far-end signal source, or additive line noise, the uncancelled echo contains only noise and linearity errors generated in transmit and receive channels of the AFE1230. The uncancelled echo is defined as a ratio of the rms uncancelled echo to the rms voltage of the nominal transmitted signal (for example 14.5dBm). Figure 8 also shows a basic setting for G.SHDSL applications that can provide 14.5dBm power directly to a 135Ω line. The typical performance is listed in Table X. A power spectrum density of a random sequence through this circuit with 30M bit rate is shown in Figure 9. PARAMETER Line Power Line Peak-to-Peak Voltage PAR Line Termination Resistance Transformer Turns Ratio AFE1230 Output Peak-to-Peak Voltage External tx Low-Pass Filter Cutoff Frequency External rx Low-Pass Filter (Optional) Cutoff Frequency VALUE 14.5dBm 11.7V 3.0 (Vp/Vrms) 135Ω 1:3.7 6.2Vp-p (Differential) ≅ 600kHz ≅ 600kHz Figure 10 is a basic application circuit with an external driver (OPA2677) to provide 17.3dBm power on a 135Ω loop for HDSL2 transmission. The analog signal from the AFE1230 has 6.2V peak-to-peak voltage and is loaded by a 1kΩ resistor. The OPA2677 is configured as a wideband power amplifier with a constant AC gain of 2.8V and 17.3V peak-to-peak output voltage. The output signal from the OPA2677 is filtered to minimize noise by a tx RC low-pass filter with a cutoff frequency of 600kHz. A 1:2.3 transformer from Midcom (51440R Rev00) is used. The receive amplifier receives farend signals from the line through the line transformer with 2.3 times of step down. The line input resistors of the AFE1230 are set to 10kΩ. The basic resistor network hybrid circuit is used to isolate transmit signals from receivers. The receive low-pass filter (optional) performs bandlimit to the receive signal to minimize aliasing. Table XI gives the line interface basic performance for HDSL2. PARAMETER Line Power PAR Line Termination Resistance Transformer Turns Ratio External Driver OPA2677 Power Supply DC Gain AC Gain (R Can Be Adjusted) AFE1230 Peak-to-Peak Output Voltage OPA2677 Peak-to-Peak Output Voltage AFE1230 Power Dissipation Transmit Low-Pass Filter Cutoff Frequency Receive Low-Pass Filter (Optional) Cutoff Frequency VALUE 16.8 ± 0.5dBm 4 (Vp/Vrms) 135Ω 1:2.3 OPA2677 +12V 1(v/v) 2.8 (v/v) 6.2Vp-p (Differential) 17.3V (Differential) 560mW ≅ 600kHz ≅ 600kHz TABLE XI. Typical Performance for HDSL2 Circuit, (See Figure 10). In practice, the line impedance is changed with frequency under the different loop conditions. An RC or RLC compromise network is generally inserted in the external hybrid path to track the impedance over the frequency band interested. The components of the compromise networks are adjustable for minimizing far-end, near-end, and trans-hybrid reflections. The coupling capacitance (0.1µF) on the tx and rx paths is used for AFE evaluation only. With the DSL external hybrid circuit, this capacitance should be adjusted. AFE1230 Power Dissipation When using the on-chip driver at E1 rates, 3.3V digital power supply (5V analog power supply) for G.SHDSL operation, with 14.5dBm power to the line, the AFE1230 power dissipation including both analog and digital circuitry is about 750mW. Most power dissipation on the chip is in the on-chip driver and other analog circuitry (about 120mW power dissipation is from digital circuitry). Digital power dissipation is reduced when the operating frequency decreases, but the analog power dissipation stays the same with the frequency changing. When an external driver (OPA2677) is used, the power dissipation of the AFE1230 is about 560mW. TABLE X. Typical Performance for G.SHDSL Circuit, Shown in Figure 8. 10 AFE1230 SBWS015A AVDD 10µF GND 0Ω AFE1230 DVDD 10µF 0Ω C(1) 1 2 3 4 5 6 7 8 C(1) 9 10 11 12 13 14 DVDD GNDD txBaud txData MCLK rxBaud rxData DVDD GNDD GNDA HybP HybM LineP LineM GNDA GNDA txOutP AVDD txOutM GNDA AVDD AVDD AVDD VREFM VCM VREFP GNDA GNDA 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R3 20kΩ 6.8pF(3) R5 20kΩ R4 10kΩ 3.3pF(3) 10pF(3) R6 10kΩ C(1) C(1) C(1) C(1) C(1) 0.1µF 0.1µF 0.1µF 0.1µF C(1) C(1) C(1) R2 4.99Ω R1 4.99Ω 1:3.7(2) 53nF Zi(f) 53nF 0.47µF 135Ω NOTES: (1) C = 0.1µF (Ceramic SMT). (2) Transformer = Midcom— 51185. (3) These components provide low-pass filtering to the input signal and are optional, since the AFE1230 provides an internal low-pass filter with 1MHz cutoff frequency on the front end of the receiver, as well as oversampling by the A/D converter. FIGURE 8. AFE1230 Line Interface with 14.5dBm Line Power for G.SHDSL. –30 –40 –50 0.25x 0.38x 0.5x PSD (dBm/Hz) –60 –70 –80 –90 –100 –110 –120 10k 100k Logarithmic Scale (10kHz to 1000kHz) 1M FIGURE 9. AFE1230 Transmit PSD with 30MHz of Master Clock, Seventh-Order tx Filter and Cutoff Frequency Ratio of 0.5x, 0.38x, and 0.25x. AFE1230 SBWS015A 11 +12V 499Ω AFE1230 1µF 0.1µF txLINE+ 2kΩ 1kΩ 0.1µF txLINE– OPA2677-b 1µF 49.9Ω 1.2nF 2kΩ 453Ω 453Ω 22nF 0.11µF R 453Ω 17.3Vp-p R2 10.9Ω 22nF Zi 0.47µF 135Ω 1:2.3 49.9Ω OPA2677-a R1 10.9Ω 499Ω Compromise Network Overload Protection R3 10kΩ rxHYBp 3.3pF(1) rxHYBm R4 10kΩ rxLINE+ 3.3pF(1) rxLINE– 10pF(1) R6 10kΩ 10pF(1) R5 10kΩ 0.1µF 0.1µF 0.1µF 0.1µF NOTE: (1) These components provide low-pass filtering and are optional, since the AFE1230 provides an internal low-pass filter with 1MHz cutoff frequency on the front end of the receiver, as well as oversampling by the A/D converter. FIGURE 10. AFE1230 Line Interface with OPA2677 for HDSL2. LAYOUT The AFE1230 has two conflicting requirements: it must accept and deliver high-speed digital signals and it must generate, drive, and convert precision analog signals. To achieve optimal system performance with the AFE1230, both the digital and the analog sections must be treated carefully in board layout design. The power supply for the digital section of AFE1230 can range from 3.3V to 5V. This supply should be decoupled to digital grounds with ceramic 0.1µF capacitors placed as close to the GNDD and DVDD pins as possible. DVDD may be supplied by a wide-printed circuit board trace. A digital ground plane underneath all digital pins is strongly recommended. All GNDA pins should be connected directly to a common analog ground plane and all the AVDD pins should be connected to an analog 5V power plane. Both of these planes should have a low impedance path to power supply. The analog power-supply pins should be decoupled to analog grounds with ceramic 0.1µF capacitors placed as close to the AFE1230 as possible. One 10µF tantalum capacitor should be used between the analog supply and analog ground. Ideally, all ground planes and traces and all power planes and traces should return to the power connector before being connected together (if necessary). Each ground and power pair should be routed over each other, and should not overlay any portion of another pair, and the pairs should be separated by a distance of 0.25 inches (6mm) at least. One exception is that the digital and analog ground planes should be connected together underneath the AFE1230 by a small trace. 12 AFE1230 SBWS015A PACKAGE DRAWING AFE1230 SBWS015A 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Mar-2005 PACKAGING INFORMATION Orderable Device AFE1230E AFE1230E/1K AFE1230E/1KG4 (1) Status (1) ACTIVE ACTIVE ACTIVE Package Type SSOP SSOP SSOP Package Drawing DB DB DB Pins Package Eco Plan (2) Qty 28 28 28 48 1000 None None Lead/Ball Finish CU SNPB CU SNPB CU NIPDAU MSL Peak Temp (3) Level-3-220C-168 HR Level-3-220C-168 HR Level-1-260C-UNLIM 1000 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. 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