Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
AMC1204 20-MHz, Second-Order, Isolated Delta-Sigma Modulator
for Current-Shunt Measurement
1 Features
3 Description
•
The AMC1204 and AMC1204B are 1-bit digital
output, isolated delta-sigma (ΔΣ) modulators that can
be clocked at up to 20 MHz. The digital isolation of
the modulator output is provided by a silicon dioxide
(SiO2) barrier that is highly resistant to magnetic
interference. This barrier has been certified to provide
basic galvanic isolation of up to 4000 VPEAK
(AMC1204) and 4250 VPEAK (AMC1204B) according
to UL1577, VDE V 0884-11, and CSA standards or
specifications.
1
•
•
•
•
•
•
±250-mV input voltage range optimized for shunt
resistors
Safety-related certifications:
– 4250-VPK (AMC1204B) basic isolation per DIN
VDE V 0884-11: 2017-01
– 3005-VRMS (AMC1204B) isolation for 1 minute
per UL1577
– CAN/CSA no. 5A-component acceptance
service notice and DIN EN 61010-1
– Working voltage: 1200 VPEAK
– Transient immunity: 15 kV/µs
High electromagnetic field immunity
(see SLLA181A application report)
Outstanding AC performance:
– SNR: 84 dB (minimum)
– THD: –80 dB (maximum)
Excellent DC precision:
– INL: ±8 LSB (maximum)
– Gain Error: ±2% (maximum)
External clock input for easier synchronization
Fully specified over the extended industrial
temperature range
2 Applications
•
The AMC1204 and AMC1204B provide a single-chip
solution for measuring the small signal of a shunt
resistor across an isolated barrier. These types of
resistors are typically used to sense currents in motor
control inverters, green energy generation systems,
and other industrial applications. The AMC1204 and
AMC1204B differential inputs easily connect to the
shunt resistor or other low-level signal sources. An
internal reference eliminates the need for external
components. When used with an appropriate external
digital filter, an effective number of bits (ENOB) of 14
is achieved at a data rate of 78 kSPS.
A 5-V analog supply (AVDD) is used by the
modulator while the isolated digital interface operates
from a 3-V, 3.3-V, or 5-V supply (DVDD). The
AMC1204 and AMC1204B are available in SOIC-16
(DW) and SOIC-8 (DWV) packages and are specified
from –40°C to 105°C.
Device Information(1)
Shunt resistor based current sensing in:
– Motor controls
– Green energy
– Inverter applications
– Uninterruptible power supplies
PART NUMBER
AMC1204
PACKAGE
BODY SIZE (NOM)
SOIC (16)
10.30 mm × 7.50 mm
SOIC (8)
5.85 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Device Block Diagram
AVDD
DS
Modulator
2.5V
Ref
AGND
Isolation Barrier
VINP
VINN
DVDD
DATA
CLKIN
DGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
1
1
1
2
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Power Ratings........................................................... 6
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 8
Safety Limiting Values .............................................. 8
Electrical Characteristics........................................... 9
Timing Requirements ............................................ 10
Insulation Characteristics Curves ......................... 11
Typical Characteristics .......................................... 12
Detailed Description ............................................ 19
7.1
7.2
7.3
7.4
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
19
20
22
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 25
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2015) to Revision F
Page
•
Changed Certified Digital Isolation bullet to Safety-related certifications and changed details as per ISO standard ............ 1
•
Deleted Long isolation barrier lifetime bullet from Features section ..................................................................................... 1
•
Changed VDE V 0884-10 to VDE V 0884-11 in Description section ..................................................................................... 1
•
Changed title of Device Block Diagram from Simplified Schematic ....................................................................................... 1
•
Changed Absolute Maximum Ratings condition statement.................................................................................................... 5
•
Added Power Ratings table .................................................................................................................................................... 6
•
Changed Insulation Specifications table per ISO standard .................................................................................................... 6
•
Changed Safety-Related Certification table per ISO standard............................................................................................... 8
•
Changed Safety Limiting Values table per ISO standard....................................................................................................... 8
•
Added Insulation Characteristics Curves as per ISO standard ............................................................................................ 11
•
Changed Related Documentation section ............................................................................................................................ 30
•
Deleted Related Links section .............................................................................................................................................. 30
Changes from Revision D (December 2013) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed first sub-bullet of Certified Digital Isolation Feature bullet: changed IEC60747-5-5 to VDE V 0884-10................. 1
•
Changed IEC60747-5-5 to VDE V 0884-10 in first paragraph of Description section............................................................ 1
2
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
AMC1204
www.ti.com
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
Changes from Revision C (August 2012) to Revision D
Page
•
Changed first sub-bullet of Certified Digital Isolation Feature bullet: changed IEC60747-5-2 to IEC60747-5-5.................... 1
•
Deleted chip photo.................................................................................................................................................................. 1
•
Added DWV (SSO-8) package to document .......................................................................................................................... 1
•
Changed IEC60747-5-2 to IEC60747-5-5 in first paragraph of Description section .............................................................. 1
•
Changed last paragraph of Description section ..................................................................................................................... 1
•
Added DWV pin out drawing .................................................................................................................................................. 4
•
Added DWV information to Pin Descriptions table ................................................................................................................. 4
•
Added DWV package to Thermal Information table ............................................................................................................... 5
•
Changed first paragraph of Digital Output section: changed 78.1% to 89.06% and 21.9% to 10.94% ............................... 22
Changes from Revision B (August 2011) to Revision C
Page
•
Changed Certified digital isolation, isolation voltage Feature bullet ....................................................................................... 1
•
Added AMC1204B to document ............................................................................................................................................. 1
•
Changed Description section to include AMC1204B.............................................................................................................. 1
•
Changed package name from TSSOP to SO......................................................................................................................... 4
•
Changed footnote 1 in Electrical Characteristics table........................................................................................................... 9
•
Changed Analog Inputs, VCM parameter minimum specification and unit in Electrical Characteristics table......................... 9
•
Changed Digital Output, COUT and CLOAD parameters unit specifications in Electrical Characteristics table ....................... 10
•
Updated Figure 53 ............................................................................................................................................................... 27
•
Updated Figure 55 ............................................................................................................................................................... 28
•
Updated Figure 56 ............................................................................................................................................................... 29
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
3
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
www.ti.com
5 Pin Configuration and Functions
DWV Package
8-Pin SOIC
Top View
DW Package
16-Pin SOIC
Top View
AVDD
1
8
DVDD
AVDD
1
16 DGND
VINP
2
7
CLKIN
VINP
2
15 NC
VINN
3
6
DATA
VINN
3
14 DVDD
AGND
4
5
DGND
AGND
4
13 CLKIN
(1)
5
12 NC
NC
6
11 DATA
NC
7
10 NC
AGND
8
9
NC
DGND
NC = no internal connection.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
8 PINS
16 PINS
AVDD
1
1
Power
VINP
2
2
Analog input
Noninverting analog input
VINN
3
3
Analog input
Inverting analog input
AGND
4
4, 8 (1)
Power
High-side ground
DGND
5
9, 16
Power
Controller-side ground
DATA
6
11
CLKIN
7
13
Digital input
DVDD
8
14
Power
NC
—
5-7, 10,
12, 15
—
(1)
4
High-side power supply
Digital output Modulator data output
Modulator clock input
Controller-side power supply
No internal connection; can be tied to any potential or left unconnected
Both pins are connected internally via a low-impedance path; thus, only one of the pins must be tied to the ground plane.
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
AMC1204
www.ti.com
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
6 Specifications
6.1 Absolute Maximum Ratings
see
(1)
Supply voltage, AVDD to AGND or DVDD to DGND
MIN
MAX
UNIT
–0.3
6
V
V
Analog input voltage at VINP, VINN
AGND – 0.5
AVDD + 0.5
Digital input voltage at CLKIN
DGND – 0.3
DVDD + 0.3
V
–10
10
mA
Input current to any pin except supply pins
Maximum virtual junction temperature, TJ
150
°C
Operating ambient temperature, TOA
–40
125
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per JEDEC standard 22, test method A114C.01 (1)
±3000
Charged-device model (CDM), per JEDEC standard 22, test method
C101 (2)
±1500
Machine model (MM), per JEDEC standard 22, test method A115A
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
TA
Operating ambient temperature
–40
105
°C
AVDD
High-side (analog) supply voltage
4.5
5
5.5
V
DVDD
Controller-side (digital) supply voltage
2.7
3.3
5.5
V
6.4 Thermal Information
AMC1204, AMC1204B
THERMAL METRIC
(1)
DW (SOIC)
DWV (SOIC)
16 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
78.5
106.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
41.3
53.6
°C/W
RθJB
Junction-to-board thermal resistance
50.2
60.3
°C/W
ψJT
Junction-to-top characterization parameter
11.5
18.5
°C/W
ψJB
Junction-to-board characterization parameter
41.2
58.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
5
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
www.ti.com
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
PD
Maximum power dissipation
(both sides)
PD1
Maximum power dissipation
(high-side supply)
PD2
Maximum power dissipation
(low-side supply)
MIN
TYP
MAX
AVDD = DVDD = 5.5 V
115.5
AVDD = 5.5 V, DVDD = 3.6 V
102.4
AVDD = 5.5 V
88.0
DVDD = 5.5 V
27.5
DVDD = 3.6 V
14.4
UNIT
mW
mW
mW
6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance (1)
CPG
(1)
DTI
External creepage
Distance through insulation
CTI
Comparative tracking index
Material group
Overvoltage category per IEC 60664-1
Shortest pin-to-pin distance through air, DW package
Shortest pin-to-pin distance through air, DWV package
≥8
≥ 8.5
Shortest pin-to-pin distance across the package
surface, DW package
≥8
Shortest pin-to-pin distance across the package
surface, DWV package
≥ 8.5
Minimum internal gap (internal clearance) of the
insulation
≥ 0.014
DIN EN 60112 (VDE 0303-11); IEC 60112, DW
package
≥ 400
DIN EN 60112 (VDE 0303-11); IEC 60112, DWV
package
≥ 175
mm
mm
mm
V
According to IEC 60664-1, DW package
II
According to IEC 60664-1, DWV package
III
Rated mains voltage ≤ 300 VRMS
I-IV
Rated mains voltage ≤ 600 VRMS
I-III
DIN VDE V 0884-11: 2017-01 (2)
VIORM
Maximum repetitive peak isolation voltage
VIOWM
Maximum-rated isolation working voltage
VIOTM
VIOSM
(1)
(2)
(3)
6
Maximum transient isolation voltage
Maximum surge isolation voltage (3)
At ac voltage (bipolar)
1200
VPK
At ac voltage (sine wave)
849
VRMS
At dc voltage
1200
VDC
VTEST = VIOTM, t = 60 s (qualification test), AMC1204B
4250
VTEST = 1.2 × VIOTM, t = 1 s (100% production test),
AMC1204B
5100
VTEST = VIOTM, t = 60 s (qualification test), AMC1204
4000
VTEST = 1.2 × VIOTM, t = 1 s (100% production test),
AMC1204
4800
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.3 × VIOSM = 6000 VPK (qualification)
4615
VPK
VPK
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
AMC1204
www.ti.com
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
Insulation Specifications (continued)
over operating ambient temperature range (unless otherwise noted)
PARAMETER
Apparent charge (4)
qpd
Barrier capacitance, input to output (5)
CIO
Insulation resistance, input to output (5)
RIO
TEST CONDITIONS
VALUE
Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.2 × VIORM = 1440 VPK, tm = 10 s
≤5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.3 × VIORM = 1560 VPK, tm = 10 s
≤5
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s,
Vpd(m) = 1.5 × VIORM = 1800 VPK, tm = 1 s
≤5
VIO = 0.5 VPP at 1 MHz
1.2
UNIT
pC
pF
12
VIO = 500 V at TA < 85°C
> 10
VIO = 500 V at 85°C < TA < 105°C
> 1011
VIO = 500 V at TS = 150°C
> 109
Pollution degree
2
Climatic category
40/125/21
Ω
UL1577
VISO
(4)
(5)
Withstand isolation voltage
VTEST = VISO = 3005 VRMS or 4250 VDC, t = 60 s
(qualification), VTEST = 1.2 × VISO = 3606 VRMS, t = 1 s
(100% production test), AMC1204B
3005
VTEST = VISO = 2500 VRMS or 4000 VDC, t = 60 s
(qualification), VTEST = 1.2 × VISO = 2800 VRMS, t = 1 s
(100% production test), AMC1204
2500
VRMS
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
7
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
www.ti.com
6.7 Safety-Related Certifications
VDE
Certified according to DIN VDE V 0884-11:
2017-01 and DIN EN 61010-1 (VDE 0411-1):
2011-07
UL
CSA
Recognized under 1577 component
recognition program
Recognized under CSA component
acceptance NO 5 program, IEC 60950-1,
and IEC 61010-1
Basic insulation
Single protection
Basic insulation
Certificate number: 40047657
File number: E181974
Certificate number: 2350550
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
IS
PS
TS
(1)
8
Safety input, output,
or supply current
Safety input, output,
or total power (1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DW-package, RθJA = 78.5°C/W, TJ = 150°C, TA
= 25°C,
AVDD = DVDD = 5.5 V, see Figure 2
289
DWV-package, RθJA =106.5°C/W, TJ = 150°C,
TA = 25°C,
AVDD = DVDD = 5.5 V, see Figure 2
213
DW-package, RθJA = 78.5°C/W, TJ = 150°C, TA
= 25°C,
see Figure 3
1592
mW
DWV-package, RθJA = 106.5°C/W, TJ = 150°C,
TA = 25°C,
see Figure 3
1173
mW
150
°C
Maximum safety
temperature
mA
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × AVDDmax + IS × DVDDmax, where AVDDmax is the maximum high-side supply voltage and DVDDmax is the maximum controllerside supply voltage.
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
AMC1204
www.ti.com
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
6.9 Electrical Characteristics
All minimum/maximum specifications at TA = –40°C to 105°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.7 V to 5.5 V, VINP = –250
mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted.
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
16
Bits
DC ACCURACY
TA = –40°C to 85°C
–8
±2
8
LSB
TA = –40°C to 105°C
–16
±5
16
LSB
1
LSB
INL
Integral linearity error (1)
DNL
Differential nonlinearity
–1
VOS
Offset error (2)
–1
±0.1
1
TCVOS
Offset error thermal drift
–3.5
±1
3.5
GERR
Gain error (2)
–2%
±0.5%
2%
TCGERR
Gain error thermal drift
PSRR
Power-supply rejection ratio
mV
μV/°C
±30
ppm/°C
79
dB
ANALOG INPUTS
FSR
Full-scale differential voltage input range
VINP – VINN
±320
mV
Specified FSR
–250
250
mV
VCM
Operating common-mode signal (3)
–160
AVDD
mV
CI
Input capacitance to AGND
CID
Differential input capacitance
RID
Differential input resistance
IIL
Input leakage current
CMTI
Common-mode transient immunity
CMRR
Common-mode rejection ratio
VINP or VINN
7
pF
3.5
pF
12.5
kΩ
VINP – VINN = ±250 mV
–10
10
μA
VINP – VINN = ±320 mV
–50
50
μA
15
kV/μs
VIN from 0 V to 5 V at 0 Hz
108
dB
VIN from 0 V to 5 V at 100 kHz
114
dB
EXTERNAL CLOCK
tCLKIN
Clock period
fCLKIN
Input clock frequency
DutyCLKIN
Duty cycle
45.5
50
200
ns
5
20
22
MHz
5 MHz ≤ fCLKIN < 20 MHz
40%
50%
60%
20 MHz ≤ fCLKIN ≤ 22 MHz
45%
50%
55%
fIN = 1kHz, TA = –40°C to 85°C
78
87
dB
fIN = 1kHz, TA = –40°C to 105°C
70
87
dB
fIN = 1kHz, TA = –40°C to 85°C
84
88
dB
fIN = 1kHz, TA = –40°C to 105°C
83
88
AC ACCURACY
SINAD
SNR
Signal-to-noise + distortion
Signal-to-noise ratio
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range
dB
fIN = 1kHz, TA = –40°C to 85°C
–96
–80
dB
fIN = 1kHz, TA = –40°C to 105°C
–96
–70
dB
fIN = 1kHz, TA = –40°C to 85°C
82
96
dB
fIN = 1kHz, TA = –40°C to 105°C
72
96
dB
DIGITAL INPUTS (3)
IIN
Input current
CIN
Input capacitance
VIN = DVDD to DGND
–10
10
5
μA
pF
CMOS Logic Family (CMOS With Schmitt-Trigger)
VIH
High-level input voltage
DVDD = 4.5V to 5.5V
0.7DVDD
DVDD + 0.3
V
VIL
Low-level input voltage
DVDD = 4.5V to 5.5V
–0.3
0.3DVDD
V
2
DVDD + 0.3
V
LVCMOS Logic Family
VIH
(1)
(2)
(3)
High-level input voltage
DVDD = 2.7 V to 3.6 V
Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified 500-mV input range.
Maximum values, including temperature drift, are ensured over the full specified temperature range.
Ensured by design.
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
9
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
www.ti.com
Electrical Characteristics (continued)
All minimum/maximum specifications at TA = –40°C to 105°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.7 V to 5.5 V, VINP = –250
mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted.
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
VIL
TEST CONDITIONS
Low-level input voltage
MIN
DVDD = 2.7 V to 3.6 V
TYP
–0.3
MAX
0.8
UNIT
V
DIGITAL OUTPUTS (3)
COUT
Output capacitance
CLOAD
Load capacitance
5
pF
30
pF
CMOS Logic Family
VOH
High-level output voltage
DVDD = 4.5 V, IOH = –100 µA
VOL
Low-level output voltage
DVDD = 4.5 V, IOL = 100 µA
4.4
V
0.5
V
LVCMOS Logic Family
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = 20 µA
DVDD – 0.1
V
IOH = –4 mA,
2.7 V ≤ DVDD ≤ 3.6 V
DVDD – 0.4
V
IOH = –4 mA,
4.5 V ≤ DVDD ≤ 5.5 V
DVDD – 0.8
V
IOL = 20 µA
0.1
V
IOL = 4 mA
0.4
V
V
POWER SUPPLY
AVDD
High-side supply voltage
4.5
5
5.5
DVDD
Controller-side supply voltage
2.7
3.3
5.5
V
IAVDD
High-side supply current
4.5 V ≤ AVDD ≤ 5.5 V
11
16
mA
IDVDD
Controller-side supply current
2.7 V ≤ DVDD ≤ 3.6 V
2
4
mA
PD
Power dissipation
4.5V ≤ DVDD ≤ 5.5 V
AVDD = 5.5 V, DVDD = 3.6 V
2.8
5
mA
61.6
102.4
mW
6.10 Timing Requirements
Over recommended ranges of supply voltage and operating free-air temperature, unless otherwise noted. (See Figure 1)
MIN
NOM
MAX
UNIT
45.5
50
200
ns
CLKIN clock high time
20
25
120
ns
tLOW
CLKIN clock low time
20
25
120
ns
tD
Delayed falling edge of CLKIN to DATA valid
15
ns
tCLK
CLKIN clock period
tHIGH
2
tCLK
tHIGH
CLKIN
tLOW
tD
DATA
Figure 1. Modulator Output Timing
10
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
AMC1204
www.ti.com
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
6.11 Insulation Characteristics Curves
2000
500
DW-package
DWV-package
DW-package
DWV-package
1800
400
1600
PS (mW)
IS (mA)
1400
300
200
1200
1000
800
600
100
400
200
0
0
0
25
50
75
TA (°C)
100
125
150
0
D001
Figure 2. Thermal Derating Curve for Safety-Limiting
Current per VDE
25
50
75
TA (°C)
100
125
150
D002
Figure 3. Thermal Derating Curve for Safety-Limiting
Power per VDE
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
11
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
www.ti.com
6.12 Typical Characteristics
at AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise
noted)
8
7
5
INL (LSB)
INL (LSB)
6
4
3
2
1
0
−250 −200 −150 −100 −50
0
50 100
Input Signal Amplitude (mV)
150
200
250
16
14
12
10
8
6
4
2
0
−2
−4
−6
−8
−10
−12
−14
−16
−40 −25 −10
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0
−0.2
−0.4
−0.4
−0.8
−1
−40 −25 −10
5.5
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0
−0.2
−0.4
12
110 125
−0.4
−0.8
25
Figure 8. Offset Error vs Clock Frequency
95
0
−0.6
20
80
−0.2
−0.8
15
Clock Freuency (MHz)
20 35 50 65
Temperature (°C)
0.2
−0.6
10
5
Figure 7. Offset Error vs Temperature
1
Offset Error (mV)
Offset Error (mV)
Figure 6. Offset Error vs Analog Supply Voltage
1
5
110 125
−0.2
−0.6
−1
95
0
−0.8
5
AVDD (V)
80
0.2
−0.6
−1
4.5
20 35 50 65
Temperature (°C)
Figure 5. Integral Nonlinearity vs Temperature
Offset Error (mV)
Offset Error (mV)
Figure 4. Integral Nonlinearity vs Input Signal Amplitude
5
−1
40
45
50
Clock Duty Cycle (%)
55
60
Figure 9. Offset Error vs Clock Duty Cycle
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
AMC1204
www.ti.com
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
Typical Characteristics (continued)
2
2
1.5
1.5
1
1
Gain Error (%)
Gain Error (%)
at AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise
noted)
0.5
0
−0.5
0.5
0
−0.5
−1
−1
−1.5
−1.5
−2
4.5
5
AVDD (V)
−2
−40 −25 −10
5.5
2
1.5
1.5
1
1
0.5
0
−0.5
−1.5
15
20
Clock Frequency (MHz)
110 125
−0.5
−1.5
10
95
0
−1
5
80
0.5
−1
−2
20 35 50 65
Temperature (°C)
Figure 11. Gain Error vs Temperature
2
Gain Error (%)
Gain Error (%)
Figure 10. Gain Error vs Analog Supply Voltage
5
−2
25
40
Figure 12. Gain Error vs Clock Frequency
45
50
Clock Duty Cycle (%)
55
60
Figure 13. Gain Error vs Clock Duty Cycle
100
140
130
Unfiltered
sinc3, OSR = 256
90
CMRR (dB)
PSRR (dB)
120
80
110
100
70
90
60
0.1
1
10
100
80
0.1
Frequency (kHz)
Figure 14. Power-Supply Rejection Ratio vs Frequency
1
10
100
Input Signal Frequency (kHz)
1000
Figure 15. Common-Mode Rejection Ratio vs Input Signal
Frequency
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
13
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
www.ti.com
Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise
noted)
100
100
SINAD
SNR
90
SINAD and SNR (dB)
SINAD and SNR (dB)
SINAD
SNR
80
70
60
4.5
5
AVDD (V)
90
80
70
60
−40 −25 −10
5.5
Figure 16. SINAD and SNR vs Analog Supply Voltage
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 17. SINAD and SNR vs Temperature
100
100
SINAD
SNR
SINAD
SNR
90
SINAD and SNR (dB)
SINAD & SNR (dB)
80
90
80
70
70
60
50
40
30
20
10
60
0.1
1
10
Input Signal Frequency (kHz)
0
0.1
100
Figure 18. SINAD and SNR vs Input Signal Frequency
100
SINAD
SNR
90
SINADand SNR (dB)
SINAD and SNR (dB)
SINAD
SNR
80
70
5
10
15
20
Clock Frequency (MHz)
25
Figure 20. SINAD and SNR vs Clock Frequency
14
1000
Figure 19. SINAD and SNR vs Input Signal Amplitude
100
60
1
10
100
Input Signal Amplitude (mVpp)
90
80
70
60
40
45
50
Clock Duty Cycle (%)
55
60
Figure 21. SINAD and SNR vs Clock Duty Cycle
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
AMC1204
www.ti.com
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
Typical Characteristics (continued)
−60
−60
−70
−70
−80
−80
THD (dB)
THD (dB)
at AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise
noted)
−90
−90
−100
−100
−110
−110
−120
4.5
5
AVDD (V)
−120
−40 −25 −10
5.5
Figure 22. Total Harmonic Distortion vs Analog Supply
Voltage
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 23. Total Harmonic Distortion vs Temperature
−60
0
−10
−70
−20
−30
−40
THD (dB)
THD (dB)
−80
−90
−50
−60
−70
−100
−80
−110
−100
−90
−110
−120
0.1
1
10
Input Signal Frequency (kHz)
−120
0.1
100
−60
−60
−70
−70
−80
−80
−90
−90
−100
−100
−110
−110
−120
5
10
15
20
Clock Frequency (MHz)
25
Figure 26. Total Harmonic Distortion vs Clock Frequency
1000
Figure 25. Total Harmonic Distortion vs Input Signal
Amplitude
THD (dB)
THD (dB)
Figure 24. Total Harmonic Distortion vs Input Signal
Frequency
1
10
100
Input Signal Amplitude (mVpp)
−120
40
45
50
Clock Duty Cycle (%)
55
60
Figure 27. Total Harmonic Distortion vs Clock Duty Cycle
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
15
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
www.ti.com
Typical Characteristics (continued)
120
120
110
110
100
100
SFDR (dB)
SFDR (dB)
at AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise
noted)
90
90
80
80
70
70
60
4.5
5
AVDD (V)
60
−40 −25 −10
5.5
Figure 28. Spurious-Free Dynamic Range vs Analog Supply
Voltage
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 29. Spurious-Free Dynamic Range vs Temperature
120
120
110
110
100
90
80
SFDR (dB)
SFDR (dB)
100
90
80
70
60
50
40
30
70
20
10
60
0.1
1
10
Input Signal Frequency (kHz)
0
0.1
100
120
120
110
110
100
100
90
80
70
70
5
10
15
20
Clock Frequency (MHz)
25
Figure 32. Spurious-Free Dynamic Range vs Clock
Frequency
16
90
80
60
1000
Figure 31. Spurious-Free Dynamic Range vs Input Signal
Amplitude
SFDR (dB)
SFDR (dB)
Figure 30. Spurious-Free Dynamic Range vs Input Signal
Frequency
1
10
100
Input Signal Amplitude (mVpp)
60
40
45
50
Clock Duty Cycle (%)
55
60
Figure 33. Spurious-Free Dynamic Range vs Clock Duty
Cycle
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
AMC1204
www.ti.com
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
Typical Characteristics (continued)
0
0
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
at AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise
noted)
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
5
10
15
20
25
30
35
40
0
5
10
15
Frequency (kHz)
16
16
14
14
12
12
10
10
8
6
2
2
0
−40 −25 −10
5.5
16
14
14
12
12
10
10
8
6
2
2
25
20 35 50 65
Temperature (°C)
80
95
110 125
6
4
15
20
Clock Frequency (MHz)
5
8
4
10
40
Figure 37. Analog Supply Current vs Temperature
16
IDVDD (mA)
IAVDD (mA)
Figure 36. Analog Supply Current vs Analog Supply Voltage
5
35
6
4
0
30
8
4
5
AVDD (V)
25
Figure 35. Frequency Spectrum (4096 Point FFT, fIN = 5 kHz,
0.56 VPP)
IAVDD (mV)
IAVDD (mA)
Figure 34. Frequency Spectrum (4096 Point FFT, fIN = 1 kHz,
0.56 VPP)
0
4.5
20
Frequency (kHz)
0
2.7
3
3.3
3.6
DVDD (V)
Figure 38. Analog Supply Current vs Clock Frequency
Figure 39. Digital Supply Current vs Digital Supply Voltage
(3 V)
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
17
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
www.ti.com
Typical Characteristics (continued)
16
16
14
14
12
12
10
10
IDVDD (mA)
IDVDD (mA)
at AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise
noted)
8
6
8
6
4
4
2
2
0
4.5
5
DVDD (V)
5.5
Figure 40. Digital Supply Current vs Digital Supply Voltage
(5 V)
DVDD = 3.3V
DVDD = 5V
0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 41. Digital Supply Current vs Temperature
16
DVDD = 3.3V
DVDD = 5V
14
IDVDD (mA)
12
10
8
6
4
2
0
5
10
15
20
Clock Frequency (MHz)
25
Figure 42. Digital Supply Current vs Clock Frequency
18
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
AMC1204
www.ti.com
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
7 Detailed Description
7.1 Overview
The AMC1204 and AMC1204B are single-channel, second-order, delta-sigma (ΔΣ) modulators designed for
medium- to high-resolution analog-to-digital conversions. The isolated output of the converter (DATA) provides a
stream of digital ones and zeros accurately representing the analog input voltage over time. The time average of
this serial output is proportional to the analog input voltage.
The Functional Block Diagram shows a detailed block diagram of the AMC1204 and AMC1204B. The analog
input range is tailored to directly accommodate the voltage drop across a shunt resistor used for current sensing.
The SiO2-based capacitive isolation barrier supports a high level of magnetic field immunity as described in the
ISO72x Digital Isolator Magnetic-Field Immunity application report. The external clock input simplifies the
synchronization of multiple current sense channels on system level. The extended frequency range of up to 20
MHz supports higher performance levels compared to the other solutions available on the market.
7.2 Functional Block Diagram
Isolation Barrier
2nd-Order
DS Modulator
VINN
+
Interface Circuit
VINP
VREF
+
3-State
Output
Buffer
DATA
-
POR
+
Buffer
-
2.5V
VREF
+
VREF
CLKIN
-
Figure 43. Detailed Block Diagram
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
19
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
www.ti.com
7.3 Feature Description
7.3.1 Analog Input
The differential analog input of the AMC1204 and AMC1204B is implemented with a switched-capacitor circuit.
The AMC1204 and AMC1204B measure the differential input signal VIN = (VINP – VINN) against the internal
reference of 2.5 V using internal capacitors that are continuously charged and discharged. Figure 44 shows the
simplified schematic of the AMC1204 and AMC1204B input circuitry; the right side of Figure 44 illustrates the
input circuitry with the capacitors and switches replaced by an equivalent circuit.
In Figure 44, the S1 switches close during the input sampling phase. With the S1 switches closed, CDIFF charges
to the voltage difference across VINP and VINN. For the discharge phase, both S1 switches open first and then
both S2 switches close. CDIFF discharges approximately to AGND + 0.8 V during this phase. This two-phase
sample/discharge cycle repeats with a period of tCLKIN = 1/fCLKIN. fCLKIN is the operating frequency of the
modulator. The capacitors CIP and CIN are of parasitic nature and caused by bonding wires and the internal ESD
protection structure.
AVDD
AGND
AGND
CIP = 3pF
3pF
200W
VINP
S1
S2
AGND + 0.8V
Equivalent
Circuit
VINP
REFF = 12.5kW
CDIFF = 4pF
S1
VINN
200W
S2
VINN
AGND + 0.8V
3pF
CIN = 3pF
AGND
REFF =
AGND
1
fCLKIN ´ CDIFF
AGND
(fCLKIN = 20MHz)
Figure 44. Equivalent Analog Input Circuit
There are two restrictions on the analog input signals VINP and VINN. First, if the input voltage exceeds the
range AGND – 0.5 V to AVDD + 0.3 V, the input current must be limited to 10 mA because the input protection
diodes on the front end of the converter begin to turn on. In addition, the linearity and the noise performance of
the device are ensured only when the differential analog input voltage remains within ±250 mV.
7.3.2 Modulator
The modulator topology of the AMC1204 and AMC1204B is fundamentally a second-order, switched-capacitor,
ΔΣ modulator, such as the one conceptualized in Figure 45. The analog input voltage (X(t)) and the output of the
1-bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage (X2) at the input of the first
integrator or modulator stage. The output of the first integrator is further differentiated with the DAC output; the
resulting voltage (X3) feeds the input of the second integrator stage. When the value of the integrated signal (X4)
at the output of the second stage equals the comparator reference voltage, the output of the comparator
switches from high to low, or vice versa, depending on its previous state. In this case, the 1-bit DAC responds on
the next clock pulse by changing its analog output voltage (X6), causing the integrators to progress in the
opposite direction, while forcing the value of the integrator output to track the average of the input.
20
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
AMC1204
www.ti.com
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
Feature Description (continued)
fCLK
X(t)
X2
X3
Integrator 1
Integrator 2
X4
DATA
fS
VREF
Comparator
X6
DAC
Figure 45. Block Diagram Of A Second-Order Modulator
The modulator shifts the quantization noise to high frequencies, as shown in Figure 46; therefore, a low-pass
digital filter should be used at the output of the device to increase the overall performance. This filter is also used
to convert from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate
(decimation). A digital signal processor (DSP), microcontroller (µC), or field programmable gate array (FPGA)
can be used to implement the filter.
TI's microcontroller family TMS320F28x7x offers a suitable programmable, hardwired filter structure termed a
sigma-delta filter module (SDFM) optimized for usage with the AMC1204, AMC1304 and AMC1305 devices.
Also, the SD24_B converters on the MSP430F677x microcontrollers offer a path to directly access the integrated
sinc-filters, thus offering a system-level solution for multichannel isolated current sensing. Another option is to
use a suitable application-specific device such as the AMC1210, a four-channel digital sinc-filter.
0
Magnitude (dB)
-20
-40
-60
-80
-100
-120
-140
10
100
1k
10k
100k
1G
10G
Frequency (Hz)
Figure 46. Quantization Noise Shaping
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
21
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
www.ti.com
Feature Description (continued)
7.3.3 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time and
low 50% of the time. A differential input of 250 mV produces a stream of ones and zeros that are high 89.06% of
the time. A differential input of –250 mV produces a stream of ones and zeros that are high 10.94% of the time.
This is also the specified linear input range of the modulator with the performance as specified in this data sheet.
The range between 250 mV and 320 mV (absolute values) is the non-linear range of the modulator. The output
of the modulator clips with a stream of only zeros with an input less than or equal to –320 mV or with a stream of
only ones with an input greater than or equal to 320 mV. The input voltage versus the output modulator signal is
shown in Figure 47.
The system clock of the AMC1204 and AMC1204B is typically 20 MHz and is provided externally at the CLKIN
pin. The data are synchronously provided at 20 MHz at the DATA output pin. The data are changing at the falling
edge of CLKIN; for more details see the Timing Requirements section.
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
Figure 47. Analog Input Versus Amc1204 Modulator Output
7.4 Device Functional Modes
The AMC1204 is operational when the power supplies AVDD and DVDD are applied as specified in the
Recommended Operating Conditions section.
The AMC1204 has no additional functional modes.
22
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
AMC1204
www.ti.com
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Digital Filter Usage
The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort
and hardware, is a sinc3-type filter, as shown in Equation 1:
3
H(z) =
1 - z-OSR
1 - z-1
(1)
This filter provides the best output performance at the lowest hardware size (count of digital gates). For an
oversampling rate (OSR) in the range of 16 to 256, this filter is a good choice. All the characterization in this
document is also done with a sinc3 filter with OSR = 256 and an output word width of 16 bits.
In a sinc3 filter response (shown in Figure 48 and Figure 49), the location of the first notch occurs at the
frequency of output data rate fDATA = fCLK/OSR. The –3-dB point is located at half the Nyquist frequency or
fDATA/4. For some applications, it may be necessary to use another filter type with different frequency response.
Performance can be improved, for example, by using a cascaded filter structure. The first decimation stage could
be built of a sinc3 filter with a low OSR and the second stage using a high-order filter.
0
30k
fDATA = 20MHz/64 = 312.5kHz
-3dB: 81.9kHz
OSR = 64
-10
fMOD = 20MHz
OSR = 64
FSR = 32768
ENOB = 12 Bits
Settling Time =
3 ´ 1/fDATA = 9.6ms
25k
Output Code
Gain (dB)
-20
-30
-40
-50
20k
15k
10k
-60
5k
-70
0
-80
0
200
400
600
800 1000
Frequency (kHz)
1200
1400
1600
Figure 48. Frequency Response Of The Sinc3 Filter
0
5
10
15
20
25
30
Number of Output Clocks
35
40
Figure 49. Pole Response Of The Sinc3 Filter
The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators.
Figure 51 illustrates the ENOB of the AMC1204 and AMC1204B with different oversampling ratios. In this data
sheet, this number is calculated from SNR using Equation 2:
SNR = 1.76dB + 6.02dB ´ ENOB
(2)
An example code for an implementation of a sinc3 filter in an FPGA follows. For more information, see the
Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control Applications application
note, available for download at www.ti.com.
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: AMC1204
23
AMC1204
SBAS512F – APRIL 2011 – REVISED FEBRUARY 2020
www.ti.com
Application Information (continued)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FLT is
port(RESN, MOUT, MCLK, CNR : in std_logic;
CN5 : out std_logic_vector(23 downto 0));
end FLT;
architecture RTL of FLT is
signal DN0, DN1, DN3, DN5 : std_logic_vector(23 downto 0);
signal CN1, CN2, CN3, CN4 : std_logic_vector(23 downto 0);
signal DELTA1 : std_logic_vector(23 downto 0);
begin
process(MCLK, RESn)
begin
if RESn = '0' then
DELTA1 '0');
elsif MCLK'event and MCLK = '1' then
if MOUT = '1' then
DELTA1
工商网监
湘ICP备2023018690号
