bq24155
www.ti.com
SLUS942 – FEBRUARY 2010
Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance
Check for Samples: bq24155
FEATURES
1
•
•
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Charge Faster than Linear Chargers
High-Accuracy Voltage and Current Regulation
– Input Current Regulation Accuracy: ±5%
(100 mA and 500 mA)
– Charge Voltage Regulation Accuracy:
±0.5% (25°C), ±1% (0°C-125°C)
– Charge Current Regulation Accuracy: ±5%
High-Efficiency Mini-USB/AC Battery Charger
for Single-Cell Li-Ion and Li-Polymer Battery
Packs
20-V Absolute Maximum Input Voltage Rating
6-V Maximum Operating Input Voltage
Built-In Input Current Sensing and Limiting
Integrated Power FETs for Up To 1.25-A
Charge Rate
Programmable Charge Parameters through
I2C™ Compatible Interface (up to 3.4 Mbps):
– Input Current
– Fast-Charge/Termination Current
– Charge Voltage (3.5 V to 4.44 V)
– Safety Timer with Reset Control
– Termination Enable
Synchronous Fixed-Frequency PWM
Controller Operating at 3 MHz with 0% to
99.5% Duty Cycle
Automatic High Impedance Mode for Low
Power Consumption
Robust Protection
– Reverse Leakage Protection Prevents
Battery Drainage
– Thermal Regulation and Protection
– Input/Output Overvoltage Protection
Status Output for Charging and Faults
USB Friendly Boot-Up Sequence
Automatic Charging
Power Up System without Battery
3.5 mm x 3.5 mm 14-Pin QFN Package
APPLICATIONS
•
•
•
Mobile and Smart Phones
MP3 Players
Handheld Devices
DESCRIPTION
The bq24155 is a compact, flexible, high-efficiency,
USB-friendly switch-mode charge management
device for single-cell Li-ion and Li-polymer batteries
used in a wide range of portable applications. The
charge parameters can be programmed through an
I2C interface. The bq24155 integrates a synchronous
PWM controller, power FETs, input current sensing,
high-accuracy current and voltage regulation, and
charge termination, into a small WCSP package.
The bq24155 charges the battery in three phases:
conditioning, constant current and constant voltage.
The input current is automatically limited to the value
set by the host. Charge is terminated based on
user-selectable minimum current level. A safety timer
with reset control provides a safety backup for I2C
interface. During normal operation, bq24155
automatically restarts the charge cycle if the battery
voltage falls below an internal threshold and
automatically enters sleep mode or high impedance
mode when the input supply is removed. The charge
status is reported to the host using the I2C compatible
interface.
Typical Application Circuit
LO 1.0 mH
VBUS
C IN
VBUS
bq24155
PMID
C IN
VAUX
10 kW
SCL
SDA
STAT
ISEL
10 kW
10 kW
HOST
BOOT
10nF
PACK +
0.1 mF
PGND
4.7 mF
10 kW
CO
1 0mF
C BOOT
U1
1 mF
R SNS
SW
+
CSIN
I2C BUS
SCL
SDA
STAT
ISEL
SGND
PACK -
CSOUT
AUXPWR
VREF
C AUXPWR
C VREF
1mF
1mF
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Philips Electronics.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
bq24155
SLUS942 – FEBRUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION CONTINUED
During the charging process, the bq24155 monitors its junction temperature (TJ) and reduces the charge current
once TJ increases to approximately 125°C. The bq24155 is available in 14-pin QFN package.
8
VREF
13
12
3
7
AUXPWR
SW
11
CSOUT
Thermal
Pad
PMID
PGND
10
ISEL
2
4
STAT
14
5
SDA
VBUS
1
6
SCL
BOOT
SGND
9
RGY PACKAGE
(Top View)
CSIN
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
CSOUT
6
I
Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 mF) to
PGND if there are long inductive leads to battery.
VBUS
14
I
Charger input voltage. Bypass it with a 1-mF ceramic capacitor from VBUS to PGND.
PMID
13
O
Connection point between reverse blocking FET and high-side switching FET. Bypass it with a
minimum of 3.3-mF capacitor from PMID to PGND.
SW
12
O
Internal switch to output inductor connection.
BOOT
1
O
Bootstrap capacitor connection for the high-side FET gate driver. Connect a 10-nF ceramic capacitor
(voltage rating above 10 V) from BOOT pin to SW pin.
PGND
11
CSIN
9
I
Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-mF
ceramic capacitor to PGND is required.
SCL
2
I
I2C interface clock. Open drain output, connect a 10-kΩ pullup resistor to 1.8V rail
SDA
3
I/O
I2C interface data. Open drain output, connect a 10-kΩ pullup resistor to 1.8V rail
STAT
4
O
Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a
128mS pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can
be used to drive a LED or communicate with a host processor.
VREF
8
O
Internal bias regulator voltage. Connect a 1-mF ceramic capacitor from this output to PGND. External
load on VREF is not allowed.
AUXPWR
7
I
Auxiliary power supply, connected to the battery pack to provide power in high-impedance mode.
Bypass it with a 1-mF ceramic capacitor from this pin to PGND.
ISEL
5
I
Input current limiting selection pin. In 32 minutes mode, the ISEL pin is default to be used as the input
current limiting selection pin. When ISEL = High, Iin – limit = 500 mA and when ISEL = Low, Iin – limit
= 100 mA, see the Control Register for details.
SGND
10
-
Signal ground
Thermal pad
pad
-
There is an internal electrical connection between the exposed thermal pad and the PGND pin of the
device. The thermal pad must be connected to the same potential as the PGND pin on the printed
circuit board. Do not use the thermal pad as the primary ground input for the device. PGND/SGND
must be connected to ground at all times.
2
Power ground
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SLUS942 – FEBRUARY 2010
ORDERING INFORMATION (1)
MARKING
MEDIUM
QUANTITY
bq24155RGYR
Part NO.
bq24155
Tape and Reel
3000
bq24155RGYT
bq24155
Tape and Reel
250
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
DISSIPATION RATINGS (1)
RqJA
RqJC
TA ≤ 25°C
POWER RATING
DERATING FACTOR
TA > 25°C
55°C/W (2)
15°C/W
1.82 W
0.018 W/°C
PACKAGE
QFN-14
(1)
(2)
(1)
Maximum power dissipation is a function of TJ(max), RqJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = [TJ(max)-TA] / RqJA.
This data is based on using a JEDEC High-K 4-layer board and the exposed die pad is connected to a Cu pad on the board. The pad is
connected to the ground plane by a via matrix.
ABSOLUTE MAXIMUM RATINGS (1)
(2)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
–0.3 to 20 (3)
V
SCL, SDA, ISEL, CSIN, CSOUT, AUXPWR
–0.3 to 7
V
PMID, STAT
–0.3 to 20
V
6.5
V
–0.7 to 20
V
±7
V
VSS
Supply voltage range (with
respect to PGND)
VBUS
VI
Input voltage range (with
respect to and PGND)
VO
Output voltage range (with
respect to and PGND)
VREF
SW, BOOT
Voltage difference between CSIN and CSOUT inputs (V(CSIN) -V(CSOUT) )
Voltage difference between BOOT and SW inputs (V(BOOT) -V(SW) )
–0.3 to 7
V
10
mA
1.25
A
Operating free-air temperature range
–40 to 85
°C
Junction temperature
–40 to 150
°C
Storage temperature
–65 to 150
°C
Output sink
STAT
IO
Output current (average)
SW
TA
TJ
Tstg
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal.
The bq24155 family can withstand up to 10.6 V continuously and 20 V for a minimum of 432 hours.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VBUS
Supply voltage, VBUS
4
6 (1)
V
TJ
Operating junction temperature range
0
+125
°C
(1)
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight
layout minimizes switching noise.
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ELECTRICAL CHARACTERISTICS
Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), TJ = 0°C to 125°C, TJ = 25°C for
typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VBUS > VBUS(min), PWM switching
10
VBUS > VBUS(min), PWM NOT switching
I(VBUS)
VBUS supply current control
Ilkg
mA
5
0°C < TJ < 85°C, VBUS = 5 V, HZ_MODE = 1,
V(AUXPWR) > V(LOWV), SCL, SDA, ISEL = 0 V or
1.8 V
20
mA
0°C < TJ < 85°C, VBUS = 5 V, HZ_MODE = 1,
V(AUXPWR) < V(LOWV), 32 S mode, SCL, SDA, ISEL
= 0 V or 1.8 V
35
mA
Leakage current from battery to
VBUS pin
0°C < TJ < 85°C, V(AUXPWR) = 4.2 V, High
impedance mode
5
mA
Battery discharge current in High
Impedance mode, (CSIN,
CSOUT, AUXPWR, SW pins)
0°C < TJ < 85°C, V(AUXPWR) = 4.2 V, High
impedance mode,
VBUS = 0 V,
SCL, SDA, ISEL = 0 V or 1.8 V
20
mA
3.5
4.44
V
–0.5%
0.5%
–1%
1%
VOLTAGE REGULATION
V(OREG)
Output charge voltage
Voltage regulation accuracy
Operating in voltage regulation, programmable
TA = 25°C
CURRENT REGULATION (FAST CHARGE)
IO(CHARGE)
Output charge current
programmable range
V(LOWV) ≤ V(AUXPWR) < V(OREG), VBUS > V(SLP),
R(SNS) = 68 mΩ Programmable
Regulation accuracy for charge
current across R(SNS)
V(IREG) = IO(CHARGE) × R(SNS)
20 mV ≤ V(IREG) ≤ 40 mV
–5%
5%
40 mV < V(IREG)
–3%
3%
3.4
3.7
550
1250
mA
WEAK BATTERY DETECTION
V(LOWV)
Weak battery voltage threshold
programmable range
Programmable
Weak battery voltage accuracy
–5%
Hysteresis for V(LOWV)
Battery voltage falling
Deglitch time for weak battery
threshold
Rising voltage, 2 mV overdrive, tRISE = 100 ns
V
5%
100
mV
30
ms
ISEL PIN LOGIC LEVEL
VIL
Input low threshold level
VIH
Input high threshold level
0.4
1.3
V
V
CHARGE TERMINATION DETECTION
I(TERM)
Termination charge current
programmable range
V(AUXPWR) > V(OREG) – V(RCH),
VBUS > V(SLP), R(SNS) = 68 mΩ Programmable
Deglitch time for charge
termination
Both rising and falling, 2 mV overdrive, tRISE, tFALL
= 100 ns
Voltage regulation accuracy for
termination current across R(SNS)
V(IREG_TERM) = IO(TERM) × R(SNS)
50
400
30
mA
ms
3.4 mV ≤ V(IREG_TERM) < 6.8 mV
–25%
25%
6.8 mV ≤ V(IREG_TERM) < 13.6 mV
–10%
10%
13.6 mV ≤ V(IREG_TERM) ≤ 27.2 mV
–5%
5%
INPUT POWER SOURCE DETECTION
Input voltage lower limit
VIN(min)
tINT
Input power source detection, Input voltage falling
Deglitch time for VBUS rising
above VIN(min)
Rising voltage, 2 mV overdrive, tRISE = 100 ns
Hysteresis for VIN(min)
Input voltage rising
Detection Interval
Input power source detection
3.6
3.8
4
30
100
V
ms
200
2
mV
S
INPUT CURRENT LIMITING
IIN
Input current limiting threshold
USB charge mode
IIN = 100 mA
88
93
98
IIN = 500 mA
450
475
500
mA
VREF BIAS REGULATOR
VREF
4
Internal bias regulator voltage
VBUS >VIN(min) or V(AUXPWR) > V(BAT)min,
I(VREF) = 1 mA, C(VREF) = 1 mF
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2
6.5
V
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq24155
bq24155
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SLUS942 – FEBRUARY 2010
ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), TJ = 0°C to 125°C, TJ = 25°C for
typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VREF output short current limit
TYP
MAX
UNIT
30
mA
BATTERY RECHARGE THRESHOLD
V(RCH)
Recharge threshold voltage
Below V(OREG)
Deglitch time
V(AUXPWR) decreasing below threshold,
tFALL = 100ns, 10 mV overdrive
Low-level output saturation
voltage, STAT
IO = 10 mA, sink current
High-level leakage current for
STAT
Voltage on STAT pin is 5 V
100
120
150
mV
130
ms
STAT OUTPUTS
VOL(STAT)
0.4
V
1
mA
0.4
V
0.4
V
1
mA
I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS
VOL
Output low threshold level
VIL
Input low threshold level
VIH
Input high threshold level
I(BIAS)
Input bias current
f(SCL)
SCL clock frequency
IO = 10 mA, sink current
1.2
V
V(pull-up) = 1.8 V, SDA and SCL
3.4
MHz
BATTERY DETECTION
I(DETECT)
Battery detection current before
charge done (sink current) (1)
Begins after termination detected,
V(AUXPWR) ≤ V(OREG)
Battery detection time
–0.45
mA
262
ms
SLEEP COMPARATOR
V(SLP)
V(SLP_EXIT)
Sleep-mode entry threshold,
VBUS - VAUXPWR
2.3 V ≤ V(AUXPWR) ≤ V(OREG), VBUS falling
Sleep-mode exit hysteresis
2.3 V ≤ V(AUXPWR) ≤ V(OREG)
Deglitch time for VBUS rising
above V(SLP) + V(SLP_EXIT)
Rising voltage, 2-mV overdrive, tRISE = 100ns
0
40
100
mV
40
100
160
mV
30
ms
UNDERVOLTAGE LOCKOUT
UVLO
IC active threshold voltage
VBUS rising
3.05
3.3
UVLO(HYS)
IC active hysteresis
VBUS falling from above UVLO
120
150
3.55
Voltage from BOOT pin to SW
pin
During charge or boost operation
Internal top reverse blocking FET
on-resistance
IIN(LIMIT) = 500 mA, Measured from VBUS to
PMID
180
250
Internal top N-channel Switching
FET on-resistance
Measured from PMID to SW, VBOOT - VSW = 4 V
120
250
Internal bottom N-channel FET
on-resistance
Measured from SW to PGND
110
200
V
mV
PWM
f(OSC)
6.5
Oscillator frequency
Maximum duty cycle
D(MIN)
Minimum duty cycle
Synchronous mode to
non-synchronous mode transition
current threshold (2)
mΩ
3
Frequency accuracy
D(MAX)
V
–10%
MHz
10%
99.5%
0
Low side FET cycle by cycle current sensing
100
mA
CHARGE MODE PROTECTION
V(OVP-IN)
V(OVP)
(1)
(2)
Input VBUS OVP threshold
voltage
Threshold over VBUS to turn off converter during
charge
V(OVP_IN) hysteresis
VBUS falling from above V(OVP_IN)
Output OVP threshold voltage
V(CSOUT) threshold over V(OREG) to turn off charger
during charge
V(OVP) hysteresis
Lower limit for V(CSOUT) falling from above V(OVP)
6.3
6.5
6.7
V
140
110
117
mV
121
%V (OREG)
11
Negative charge current means the charge current flows from the battery to charger (discharging battery).
Bottom N-channel FET always turns on for Ⅹ60 ns and then turns off if current is too low.
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ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), TJ = 0°C to 125°C, TJ = 25°C for
typical values (unless otherwise noted)
PARAMETER
I(LIMIT)
V(SHORT)
I(SHORT)
TEST CONDITIONS
MIN
TYP
MAX
Charge mode operation
1.5
2.3
3
Short-circuit voltage threshold
V(AUXPWR) falling
1.9
2
2.1
V(SHORT) hysteresis
V(AUXPWR) rising from below V(SHORT)
Short-circuit current
V(AUXPWR) ≤ V(SHORT)
Cycle-by-cycle current limit for
charge
UNIT
A
V
100
5
mV
10
15
mA
PROTECTION
T(SHTDWN)
Thermal trip
165
Thermal hysteresis
10
T(CF)
Thermal regulation threshold (3)
Charge current begins to reduce
T(32S)
Time constant for the 32 second
timer
32 Second mode
(3)
°C
120
12
32
s
Verified by design
TYPICAL APPLICATION CIRCUITS
VBUS = 5 V, I(CHARGE) = 1250 mA, VBAT = 3.5 V to 4.44 V (adjustable), Safety Timer = 32 minutes or 32
seconds.
LO 1.0 mH
V BUS
VBUS
C IN
68 mW
C BOOT
U1
bq24155
1 mF
R SNS
SW
V BAT
CO
10 mF
10 nF
C IN 4.7 mF
PMID
PACK +
BOOT
CCSIN
PGND
VAUX
+
0.1 mF
CSIN
10 kW
10 kW 10 kW 10 kW
I
2C BUS
SDA
STAT
ISEL
AUXPWR
VREF
ISEL
10 kW
PACK -
CSOUT
SCL
SCL
SDA
STAT
CAUXPWR
C VREF
SGND
HOST
1 mF
1 mF
Figure 1. I2C Controlled 1-Cell Charger Application Circuit
VBUS = 5 V, I(IN_LIMIT) = 500 mA, VOUT = 3.5 V to 4.44 V (adjustable), Safety Timer = 32 minutes or 32 seconds.
6
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TYPICAL APPLICATION CIRCUITS (continued)
LO 1.0 mH
VBUS
VBUS
CIN
CIN 4.7 mF
SCL
SDA
STAT
2
10 kW 10 kW 10 kW I C BUS
ISEL
10 kW
V OUT
CO
10 mF
Q
CCSIN 0.1 mF
PGND
Host
Charge
Controller
CSIN
CSOUT
SCL
SDA
STAT
ISEL
SGND
HostControlled
Switch
10nF
BOOT
PMID
VAUX
10 kW
68 mW
CBOOT
U1
bq24155
1 mF
RSNS
SW
AUXPWR
VREF
CAUXPWR
C VREF
1 mF
CCSOUT
0.1 mF
VSYS
PACK +
+
PACK -
1 mF
HOST
Figure 2. I2C Controlled 1-Cell Pre-Regulator Application
TYPICAL CHARACTERISTICS
Using circuit shown in Figure 1, TA = 25°C, unless otherwise specified.
ADAPTER INSERTION
BATTERY INSERTION/REMOVAL
VBAT
2 V/div
VBUS
2 V/div
Vbus =5 V, Iin_limit = 500 mA,
32S Mode
VSW
5 V/div
VSW
5 V/div
Vbus = 0–5 V, Vbat = 3.5 V Charge mode
IBAT
0.5 A/div
IBAT
0.5 A/div
1S/div
500 mS/div
Figure 3.
Figure 4.
PWM CHARGING WAVEFORMS
POOR SOURCE DETECTION
VBUS
2 V/div
VSW
2 V/div
VSW
5 V/div
IL
0.5 A/div
Vbus = 5 V, Vbat = 2.6 V, Voreg = 4.2 V, Ichg = 1250 mA
IBUS
0.1 A/div
Vbus = 5 V @ 10 mA, Iin_limit = 100 mA,
Vbat = 3.2 V, Ichg = 550 mA
2 mS/div
100 nS/div
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
BATTERY DETECTION AT POWER UP
CYCLE BY CYCLE CURRENT LIMIT IN CHARGE MODE
VBUS
5 V/div
VSW
2 V/div
VIN = 0-5 V,
No Battery,
COUT = 100 mF,
RLOAD = 5 kW
VBAT
1 V/div
ISEL
5 V/div
IL
0.5 A/div
Vbus = 5 V, Vbat = 3.6 V Charge mode
operation
IBAT
50 mA/div
20 mS/div
2 mS/div
Figure 7.
Figure 8.
INPUT CURRENT CONTROL
CHARGER EFFICIENCY
92
Vbus = 5 V, Iin_limit = 100/500 mA,
(ISEL Control, 32 Minute Mode),
VBUS = 5 V
Vbat = 4 V
2
Iin_limit = 100 mA (I C Control, 32 Second Mode)
90
Vbat = 3.6 V
ISEL
5 V/div
32 Minute
Mode
IBUS
0.2 A/div
32 Second
Mode
Efficiency - %
88
86
84
Vbat = 3 V
82
0.5 S/div
80
0
100 200 300 400 500 600 700 800 900 10001100 1200 1300
Charge Current - mA
Figure 9.
8
Figure 10.
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FUNCTIONAL BLOCK DIAGRAM (Charge Mode)
PMID
bq24155
PMID
PMID
VPMID
NMOS
VBUS
NMOS
Q2
Q1
VREF1
OSC
Charge
Pump
-
PWM
Controller
CBC
Current
Limiting
Q3
ILIMIT
IIN_LIMIT
-
TCF
+
TJ
-
VBUS
+
VUVLO
-
VBUS
+
-
+
-
VBUS UVLO
+
VOVP_IN
-
TJ
PGND
CSIN
IOCHARGE
PWM_CHG
VREF
VREF
BOOT
VPMID
VBUS OVP
Thermal
Shutdown
CHARGE CONTROL
,
TIMER and DISPLAY
LOGIC
VBAT
VREF
ISHORT
AUXPWR
+
VOVP
-
VOUT
VCSIN
ITERM
VCSIN
Poor Input
-
VOUT
VOUT
VOREG
REFERNCES
& BIAS
+
TSHTDWN
VOREG-VRCH
CSOUT
VREF1
VBUS
VBUS
VOUT
-
VIN(MIN)
VBAT
NMOS
+
+
PGND
SW
SW
SW
VBUS
VBUS
+
+
-
*
Battery OVP
*
LINEAR _CHG
Sleep
STAT
* Recharge
ISEL
Termination
-
+
*
VBAT
+
-
*
VSHORT
-
(I2 C Control)
Decoder
DAC
PGND
SCL
SDA
PWM Charge
Mode
* Signal Deglitched
Figure 11. Function Block Diagram of bq24155 in Charge Mode
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq24155
9
bq24155
SLUS942 – FEBRUARY 2010
www.ti.com
OPERATIONAL FLOW CHART
VAUXPWRVUVLO
POR
Load I2C Registers
with Default Value
High Impedance Modeor Host
Controlled Operation Mode
No
Yes
Reset and Start
32-Minute Timer
Disable Charge
/CE=LOW
Charge Configure
Mode
/CE=HIGH
Any Charge State
Disable Charge
Wait Mode
Delay TINT
Indicate Power
not Good
Yes
No
Enable ISHORT
Yes
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