BQ24210DQCT

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents bq24210 SLUSA76B – DECEMBER 2010 – REVISED JANUARY 2015 bq24210 800-mA, Single-Input, Single-Cell Li-Ion Battery Solar Charger 1 Features 2 Applications • • • • • • 1 • • • • • • • • • • • • Input Voltage Dynamic Power Management Feature (VBUS_DPM) Selectable Battery Tracking Mode to Maximize the Charge Rate from Solar Panel Using DPM Feature Load Mode to Support Loads Connected at VBUS Pin 20-V Input Rating, With Overvoltage Protection (OVP) 1% Battery Voltage Regulation Accuracy Current Charge up to 800 mA With 10% Charge Current Accuracy Thermal Regulation Protection for Output Current Control Low Battery Leakage Current BAT Short-Circuit Protection NTC Input Monitoring Built-In Safety Timer With Reset Control Status Indication – Charging/Power Present Available in Small 2-mm × 3-mm 10-Pin WSON Package Smart Phones PDAs MP3 Players Low-Power Handheld Devices Auxiliary Solar Chargers 3 Description The bq24210 device is a highly integrated Li-Ion linear charger targeted at space-limited portable applications. The battery is charged in three phases: conditioning, constant current and constant voltage with an IC thermal protection and safety timer. The charge current value is programmable through an external resistor.The high input voltage range with input overvoltage protection supports low-cost unregulated adapters. The input voltage regulation loop with programmable input voltage regulation threshold make it suitable for charging from alternative power sources, such as solar panel or inductive charging pad. Furthermore, when no input source is present, the IC has a load mode to power peripherals by connecting the battery to the VBUS. Load mode has current limiting function to prevent overload. Device Information(1) PART NUMBER PACKAGE bq24210 WSON (10) BODY SIZE (NOM) 2.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Typical Application Schematic bq24210 VIN Q2 BAT 10 Q1 1 System Load VBUS CHG 8 1mF ` PG 1mF 6 VTSB 4 7 EN RT1 TS 5 Host VDPM 9 ISET 2 TEMP PACK + VSS 3 PACK - 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. bq24210 SLUSA76B – DECEMBER 2010 – REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Typical Application Schematic............................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 4 4 4 5 5 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 8.1 Overview ................................................................... 9 8.2 Functional Block Diagram ....................................... 10 8.3 Feature Description................................................. 11 8.4 Device Functional Modes........................................ 12 9 Application and Implementation ........................ 20 9.1 Application Information............................................ 20 9.2 Typical Application ................................................. 20 10 Power Supply Recommendations ..................... 22 11 Layout................................................................... 22 11.1 Layout Guidelines ................................................. 22 11.2 Layout Example .................................................... 22 12 Device and Documentation Support ................. 23 12.1 12.2 12.3 12.4 Device Support...................................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 13 Mechanical, Packaging, and Orderable Information ........................................................... 23 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May 2011) to Revision B • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Changes from Original (December 2010) to Revision A Page • Changed from Product Preview to Production Data............................................................................................................... 1 • Changed VBUS description in PIN FUNCTIONS table ......................................................................................................... 3 • Added values to the Thermal Information table...................................................................................................................... 5 • Changed titles in Figure 1 and Figure 2 ................................................................................................................................. 8 • Changed paragraph under Load Mode section.................................................................................................................... 15 • Changed Figure 13............................................................................................................................................................... 20 2 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24210 bq24210 www.ti.com SLUSA76B – DECEMBER 2010 – REVISED JANUARY 2015 6 Pin Configuration and Functions DQC Package 10 Pins Top View 1 VBUS BAT 10 2 ISET VDPM 9 3 VSS CHG 8 4 VTSB EN 7 5 TS PG 6 Pin Functions PIN NAME NO. I/O DESCRIPTION BAT 10 I/O Battery Connection. System Load may be connected. Expected range of bypass capacitors 1 μF to 10 μF, connected from BAT to VSS. CHG 8 O Charge Status indication, Low (FET ON) indicates charging, and High impedance (open drain FET OFF) in other cases EN 7 I Chip enable control. Low to enable charge or load mode, and high to enable suspend mode. ISET 2 I Programs the Fast-charge current setting. External resistor from ISET to VSS defines fast charge current value. PG 6 O Power Present indication. LOW (FET ON) When input voltage is in normal range (VBUS>BAT and VBUS>UVLO), High impedance (open drain FET OFF) in other cases. TS 5 I Temperature sense pin, connected to NTC Thermistor in the battery pack. Pulling High puts part in limited power charging mode. Must not be left floating. VBUS 1 I/O VDPM 9 I Programs the input voltage regulation threshold. Expected range of programming resistor is 1 kΩ to 10 kΩ, connected from VDPM to VSS. When VDPM is floating, the VIN DPM loop operates in battery tracking mode, and the VIN DPM threshold is BAT+100 mV (BAT>3.6 V) or 3.7 V (BAT≤3.6 V) in this case. VIN DPM threshold should be programmed higher than battery voltage to ensure proper operation. VSS 3 – Ground terminal VTSB 4 O TS bias reference voltage pin, regulated output. No external capacitor is required from VTSB to VSS. Only enabled during charge. Thermal PAD and Package – – There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times. For charging mode, input for charging source, connect to external DC supply (ie, Solar Panel, Inductive charging PAD, or Wall Adapter) For load mode, output for current limited battery voltage. Expected range of bypass capacitors 1 μF to 10 μF, connected from VBUS to VSS. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24210 3 bq24210 SLUSA76B – DECEMBER 2010 – REVISED JANUARY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating temperature range (unless otherwise noted) (1) (2) Input Voltage MIN MAX VBUS (with respect to VSS) –0.3 20 BAT (with respect to VSS) –0.3 7 VDPM, VTSB, ISET, TS, EN, CHG, PG (with respect to VSS) –0.3 7 UNIT V Input Current VBUS 1.25 A Output Current (Continuous) BAT 1.25 A Output Sink Current CHG, PG 15 mA Junction temperature, TJ –40 150 °C Storage Temperature, Tstg –65 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±3000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions VBUS MIN MAX Voltage range 3.5 18 Operating voltage range, Restricted by UVLO and OVP 3.5 7.0 UNIT V IBUS Input current, VBUS pin 0.8 A IBAT Current, BAT pin 0.8 A TJ Junction Temperature RVDPM Programs input voltage regulation Thresholds RISET Fast-charge current programming resistor VTS Voltage across NTC Thermistor for charging CBAT By-pass capacitor on BAT pin 1 10 µF CVBUS By-pass capacitor on VBUS pin 1 10 µF CVTSB By-pass capacitor on VTSB pin 0.1 µF 4 Submit Documentation Feedback 0 125 °C 1k 10k Ω 675 10.8K Ω 12 57 %VTSB Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24210 bq24210 www.ti.com SLUSA76B – DECEMBER 2010 – REVISED JANUARY 2015 7.4 Thermal Information bq24210 THERMAL METRIC (1) DQC UNIT 10 PINS RθJA Junction-to-ambient thermal resistance 60.7 RθJC(top) Junction-to-case (top) thermal resistance 53.1 RθJB Junction-to-board thermal resistance 22.2 ψJT Junction-to-top characterization parameter 0.8 ψJB Junction-to-board characterization parameter 22.1 RθJC(bot) Junction-to-case (bottom) thermal resistance 4.7 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics Over junction temperature range 0°C ≤ TJ ≤ 125°C, VBUS=5 V, charge mode (EN = Low) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT VUVLO Undervoltage lock-out Exit VBUS: 0 V → 4 V 3.15 3.3 3.45 V VHYS_UVLO Hysteresis on VUVLO Falling VBUS: 4 V→0 V,VUVLO_FALL = VUVLO–VHYS-UVLO 175 227 280 mV VBUS-DT Input Power Good detection threshold VBUS above BAT (Input power good if VBUS > BAT + VBUS-DT); BAT = 3.6 V, VBUS: 3.5 V → 4 V 150 200 250 mV VHYS-VBUSDT Hysteresis on VBUS-DT Falling BAT = 3.6 V, VBUS: 4 V → 3.5 V 250 mV tDGL(PG_PWR) Deglitch time on exiting sleep Time measured from VBUS: 0 V → 5 V 1-μs risetime to PG = Low, BAT=3.6 V 90 µs tDGL(PG_NO-PWR) Deglitch time on VHYS-VBUSDT power down. Same as entering sleep. Time measured from VBUS: 5 V → 3.2 V 1-μs falltime to PG = Open Circuit 29 ms VOVP Input overvoltage protection threshold VBUS: 5 V → 8 V VHYS-OVP Hysteresis on OVP VBUS: 11 V → 5 V 200 mV tBLK(OVP) Input overvoltage blanking time VBUS: 5 V → 12 V 113 μs tDGL(PG_OVP) Deglitch time exiting OVP Time measured from VBUS: 12 V → 5 V 1-μs falltime to PG = Low 5 ms VBUS-DPM Input voltage regulation threshold. Restricts lout at VBUS-DPM 7.3 7.5 7.7 Programmable, the programming resistor at VDPM pin RVDPM = 1kΩ 3.55 3.65 3.75 Programmable, the programming resistor at VDPM pin RVDPM = 10kΩ 4.8 5 5.1 V V KVBUS_DPM Term Factor BAT > VLOWV, VBUS = 5 V, RVDPM = 1 kΩ to 10 kΩ; RVDPM = KVBUS_DPM × (VBUS_DPM–VBUS_DPM_1) 0.135 0.15 0.165 V/KΩ VBUS_DPM_1 Initial voltage for VBUS_DPM threshold setting BAT > VLOWV, VBUS = 5 V, RVDPM = 1 kΩ to 10 kΩ 3.41 3.5 3.59 V VBUS_DPM_0 VBUS_DPM threshold when VDPM is shorted to VSS BAT > VLOWV, VBUS = 5 V, RVDPM < 500 Ω IVBUS_DPM Current for programming VBUS_DPM V 75 μA BAT ≤ 3.6 V 3.65 3.7 3.75 BAT > 3.6 V BAT +0.07 BAT +0.10 BAT +0.145 VTRK Battery voltage tracking threshold for VBUS DPM loop VDPM pin Float (open circuit, RTS > 500 kΩ), BAT rising VTRK_HYS Hysteresis for VTRK BAT falling VBUS_CHG Input voltage to enable CHG pin, VBUSEN=LOW, VBUS rising above VIN DPM threshold VBUS_DPM or VBUS-VTRK VBUS_CHG_HYS Hysteresis for VBUS_CHG tDGL_CHG Deglitch time for CHG pin status change EN=LOW, VBUS falling 3.65 60 mV 80 mV 160 mV 5 mS Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24210 V 5 bq24210 SLUSA76B – DECEMBER 2010 – REVISED JANUARY 2015 www.ti.com Electrical Characteristics (continued) Over junction temperature range 0°C ≤ TJ ≤ 125°C, VBUS=5 V, charge mode (EN = Low) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 200 250 300 Ω ISET SHORT CIRCUIT TEST RISET_MAX Highest Resistor value considered a fault (short). Monitored for Iout>90mA Riset: 600 Ω → 250 Ω, Iout latches off. Cycle power to Reset. Fault range >1.10 A tDGL-SHORT Deglitch time transition from ISET Short to Iout Disable Clear fault by cycling IN or CHGEN IOUT_CL Maximum OUT current limit regulation (Clamp) 1 0.95 ms 1.4 A mA BATTERY SHORT PROTECTION IBAT(SC) Source current out BAT pin during short-circuit detection BAT(SC) BAT pin short-circuit detection threshold/ Pre-Charge Threshold BAT:3 V → 0.5 V, no deglitch BAT(SC-HYS) BAT pin Short Hysteresis Recovery → BAT(SC) + BAT(SC-HYS); Rising, no Deglitch 13 17 21 0.75 0.8 0.85 77 V mV QUIESCENT CURRENT IOUT(DONE) BAT pin current, charging terminated EN=Low, VBUS = 6 V, Terminated 9 μA IOUT(STDBY) Suspend current into BAT pin EN=High, VBUS =0 V, BAT = 4.2 V 5 μA IBUS(STDBY) Suspend current into VBUS pin EN=High, VBUS ≤ 6 V 100 175 μA ICC Active supply current, VBUS pin No load on VTSB pin, EN=Low, VBUS = 6 V, no load on BAT pin, BAT > VO(REG), IC enabled 0.8 1.2 mA ICC_REV Active supply current, BAT pin in load mode EN = Low, BAT = 4 V, no load on VBUS pin 50 80 µA BATTERY CHARGER FAST-CHARGE VO(REG) Battery regulation voltage VBUS = 5.5 V, IOUT = 25 mA, (VTS_0C