bq24272
www.ti.com
SLUSB09 – JUNE 2012
2.5A, Single Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path
Management
Check for Samples: bq24272
FEATURES
– JEITA Compatible
Thermal Regulation Protection for Output
Current Control
BAT Short-Circuit Protection
Soft-Start Feature to Reduce Inrush Current
Thermal Shutdown and Protection
Available in Small 49-ball WCSP or QFN-24
Packages
1
•
•
•
•
•
•
High-Efficiency Switch Mode Charger with
Separate Power Path Control
– Instantly Startup System from a Deeply
Discharged Battery or No Battery
20V input rating, with 10.5V Over-Voltage
Protection (OVP)
Integrated FETs for Up to 2.5A Charge Rate
Highly Integrated Battery N-Channel MOSFET
Controller for Power Path Management
Safe and Accurate Battery Management
Functions
– 0.5% Battery Regulation Accuracy
– 10% Charge Current Accuracy
Voltage-based, NTC Monitoring Input (TS)
•
•
•
•
•
APPLICATIONS
•
•
•
•
Handheld Products
Portable Media Players
Portable Equipment
Tablets and Portable Internet Devices
APPLICATION SCHEMATIC
SW
IN
System
Load
PMID
BOOT
SYS
HOST
SCL
SDA
CD
INT
BAT
BYP
PGND
STAT
TS
DRV
TEMP
PACK+
–
+
PACK–
DESCRIPTION
The bq24272 is a highly integrated single cell Li-Ion battery charger and system power path management device
targeted for space-limited, portable applications with high capacity batteries. The single cell charger operates
from a dedicated power source such as a wall adapter or wireless power supply for a versatile solution.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
bq24272
SLUSB09 – JUNE 2012
www.ti.com
The power path management feature allows the bq24272 to power the system from a high efficiency DC to DC
converter while simultaneously and independently charging the battery. The charger monitors the battery current
at all times and reduces the charge current when the system load requires current above the input current limit.
This allows for proper charge termination and timer operation. The system voltage is regulated to the battery
voltage but will not drop below 3.5V. This minimum system voltage support enables the system to run with a
defective or absent battery pack and enables instant system turn-on even with a totally discharged battery or no
battery. The power-path management architecture also permits the battery to supplement the system current
requirements when the adapter cannot deliver the peak system currents. This enables the use of a smaller
adapter.
The battery is charged in three phases: conditioning, constant current and constant voltage. In all charge phases,
an internal control loop monitors the IC junction temperature and reduces the charge current if the internal
temperature threshold is exceeded. Additionally, the bq24272 offers a voltage-based battery pack thermistor
monitoring input (TS) that monitors battery temperature for safe charging.
2
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SLUSB09 – JUNE 2012
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
PART NUMBER
OVP
NTC MONITORING
(TS)
JEITA COMPATIBLE
MINIMUM SYSTEM VOLTAGE
PACKAGE
bq24272YFFR
10.5 V
Yes
No
3.5 V
WCSP
WCSP
bq24272YFFT
10.5 V
Yes
No
3.5 V
bq24272RGER
10.5 V
Yes
No
3.5 V
QFN
bq24272RGET
10.5 V
Yes
No
3.5 V
QFN
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
IN
Pin voltage range (with
respect to VSS)
MAX
UNIT
–2
20
V
BYP, PMID, BOOT
–0.3
20
V
SW
–0.7
12
V
SYS, BAT, BGATE, DRV, STAT, INT, SDA, SCL, CD, TS
–0.3
7
V
–0.3
7
V
4.5
A
BOOT to SW
Output Current (Continuous)
MIN
SW
SYS
Input Current (Continuous)
IN
Output Sink Current
STAT, INT
3.5
a
2.75
A
10
mA
Operating free-air temperature range
–40
85
°C
Junction temperature, TJ
–40
125
°C
Storage temperature, TSTG
–65
150
°C
300
°C
Lead temperature (soldering, 10 s)
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
THERMAL INFORMATION
THERMAL METRIC (1)
bq24272
49 PINS (YFF)
24 PINS (QFN)
θJA
Junction-to-ambient thermal resistance
49.8
32.6
θJCtop
Junction-to-case (top) thermal resistance
0.2
30.5
θJB
Junction-to-board thermal resistance
1.1
3.3
ψJT
Junction-to-top characterization parameter
1.1
0.4
ψJB
Junction-to-board characterization parameter
6.6
9.3
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
2.6
UNITS
°C/W
spacer
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
MIN
VIN
4.2
18 (1)
IN operating range
4.2
10
IIN
Input current
ISYS
Output current from SW, DC
IBAT
TJ
(1)
MAX UNITS
IN voltage range
2.5
A
3
A
Charging
2.5
Discharging, using internal battery FET
2.5
Operating junction temperature range
0
V
A
125
°C
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight
layout minimizes switching noise.
ELECTRICAL CHARACTERISTICS
Circuit of , VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, TJ = 0°C – 125°C and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
VUVLO < VIN < VOVP AND VIN > VBAT+VSLP,
PWM switching
TYP
MAX
UNITS
15
mA
IIN
Input quiescent current
VUVLO < VIN < VOVP AND VIN > VBAT+VSLP,
PWM NOT switching
IBATLEAK
Leakage current from BAT to the supply
0°C< TJ < 85°C, VBAT = 4.2V, VIN = 0V
IBAT_HIZ
Battery discharge current in high impedance mode,
(BAT, SW, SYS)
0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 0 V or 5 V, High-Z
mode
5
0°C< TJ < 85°C, High-Z Mode
175
μA
5
μA
55
μA
V
POWER PATH MANAGEMENT
VSYS(REG)
VBAT < VMINSYS
System regulation voltage
VSYSREGFETOFF
VMINSYS
Battery FET turned off, Charge disable or termination
Minimum system regulation voltage
VBSUP1
VBAT < VMINSYS, Input current limit or VINDPM active
Enter supplement mode threshold
3.6
3.7
3.82
VBATREG
+1.5%
VBATREG
+3.0%
VBATREG
+4.17%
3.5
3.62
3.4
V
VBAT > 2.5 V
VBAT
–30mV
V
VBAT
–10mV
V
7
A
250
μs
60
ms
VBSUP2
Exit supplement mode threshold
VBAT > 2.5 V
ILIM(Discharge)
Current limit, discharge or supplement mode
Current monitored in internal FET only
tDGL(SC1)
Deglitch Time, OUT short circuit during discharge or
supplement mode
Measured from
(VBAT -VSYS) = 300 mV to
VBGATE = (VBAT - 600 mV)
tREC(SC1)
Recovery time, OUT short circuit during discharge or
supplement mode
Battery range for BGATE operation
2.5
4.5
V
BATTERY CHARGER
RON(BAT-CS+)
Measured from BAT to SYS,
VBAT = 4.2V
Internal battery charger MOSFET on-resistance
Battery regulation voltage
VBATREG
TA = 25°C
Battery regulation voltage accuracy
Over temperature
Charge current programmable range
VBATSHRT < VBAT < VBATREG
Fast charge current accuracy
0°C to 125°C
VBATSHRT
Battery short threshold
VBAT Rising, 100 mV Hysteresis
IBATSHRT
Battery short current
VBAT < VBATSHRT
tDGL(BATSHRT)
Deglitch time for battery short to fast charge transition
ICHARGE
ITERM
Termination charge current accuracy
YFF pkg
37
57
RGE pkg
50
70
mΩ
3.5
4.44
–0.5%
0.5%
–1%
1%
550
2000
–10%
10%
2.9
3.0
32
35%
ICHARGE > 50 mA
–15%
15%
VRCH
Recharge threshold voltage
Below VBATREG
tDGL(RCH)
Deglitch time
VBAT falling below VRCH, tFALL = 100ns
During battery detection source cycle
3.3
During battery detection sink cycle
3.0
VDETECT
4
V
ms
–35%
Deglitch time for charge termination
mA
mA
ICHARGE = 50 mA
Both rising and falling, 2-mV over-drive,
tRISE, tFALL = 100 ns
tDGL(TERM)
3.1
50.0
V
32
ms
120
mV
32
ms
Battery detection voltage threshold
V
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ELECTRICAL CHARACTERISTICS (continued)
Circuit of , VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, TJ = 0°C – 125°C and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER
IDETECT
TEST CONDITIONS
MIN
Battery detection current before charge done (sink
current)
tDETECT
Battery detection time
VIH(CD)
CD input high logic level
VIL(CD)
CD input low logic level
TYP
MAX
UNITS
2.5
mA
250
ms
1.3
V
0.4
V
INPUT PROTECTION
IINLIM
VIN_DPM
Input current limit
VIN=5V, DC current pulled from SW
IINLIM = 1.5 A
1.35
1.5
1.65
IINLIM = 2.5 A
2.3
2.5
2.8
A
Input DPM threshold
4.2
4.76
Input DPM accuracy
–2%
2%
VDRV
Internal bias regulator voltage
IDRV
DRV Output current
5
VDO_DRV
DRV Dropout voltage (VIN – VDRV)
IIN = 1A, VIN = 5V, IDRV = 10mA
VUVLO
IC active threshold voltage
VIN rising, 150 mV hysteresis
VSLP
Sleep-mode entry threshold, VIN-VBAT
2.0 V ≤ VBAT ≤ VOREG, VIN falling
VSLP_EXIT
Sleep-mode exit hysteresis
2.0 V ≤ VBAT ≤ VOREG
Deglitch time for supply rising above VSLP+VSLP_EXIT
Rising voltage, 2-mV over drive, tRISE=100ns
VOVP
Input supply OVP threshold voltage
IN, VIN Rising, 100 mV hysteresis
VBOVP
Battery OVP threshold voltage
VBAT threshold over VOREG to turn off charger during charge
VBOVP hysteresis
Lower limit for VBAT falling from above VBOVP
5.2
5.45
10
V
V
mA
450
mV
3.6
3.8
4.0
V
0
40
100
mV
40
100
160
mV
30
ms
10.3
10.5
10.7
V
1.025 ×
VBATREG
1.05 ×
VBATREG
1.075 ×
VBATREG
V
% of
VBATREG
1
VBATUVLO
Battery UVLO threshold voltage
2.5
V
VBAT_SOURCE
Bad source detection threshold
VIN_DPM –
80mV
V
Bad source detection deglitch
ILIMIT
Cycle by cycle current limit
TSHUTDWN
Thermal shutdown
TREG
Thermal regulation threshold
32
4.1
10°C Hysteresis
4.9
ms
5.6
165
120
Safety timer accuracy
–20%
A
C
C
20%
STAT, INT
IIH
High-level leakage current
V/CHG = V/PG = 5 V
VOL
Low-level output saturation voltage
IO = 10 mA, sink current
1
µA
0.4
V
PWM CONVERTER
Internal top reverse blocking MOSFET on-resistance
IIN_LIMIT = 1.5 A, Measured from VIN to PMIDU
45
80
mΩ
Internal top N-channel Switching MOSFET onresistance
Measured from PMID to SW
65
110
mΩ
Internal bottom N-channel MOSFET on-resistance
Measured from SW to PGND
fOSC
Oscillator frequency
DMAX
Maximum duty cycle
DMIN
Minimum duty cycle
1.35
65
115
mΩ
1.50
1.65
MHz
%VDRV
95%
0
BATTERY-PACK NTC MONITOR
VHOT
High temperature threshold
VTS falling, 1%VDRV Hysteresis
29.7
30
30.5
VCOLD
Low temperature threshold
VTS rising, 1%VDRV Hysteresis
59.5
60
60.4
%VDRV
TSOFF
TS Disable threshold
VTS rising, 2%VDRV Hysteresis
70
73
%VDRV
tDGL(TS)
Deglitch time on TS change
VIH
Input high threshold
VPULLUP = 1.8 V, SDA and SCL
VIL
Input low threshold
VPULLUP = 1.8 V, SDA and SCL
0.4
VOL
Output low threshold
ISDA = 10 mA, sink current
0.4
IIH
Input high leakage current
VPULLUP = 1.8 V, SDA and SCL
tWATCHDOG
Watchdog timer timeout
50
ms
1.3
V
1
30
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V
V
µA
s
5
bq24272
SLUSB09 – JUNE 2012
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PIN CONFIGURATION
49-Ball WCSP (Top View)
1
2
3
4
5
6
7
A
IN
IN
IN
IN
AGND
AGND
AGND
B
PMIDI
PMIDI
PMIDI
PMIDI
BYP
BYP
BYP
C
SW
SW
SW
SW
SW
SW
SW
D
PGND
PGND
PGND
PGND
PGND
PGND
PGND
E
AGND
N.C.
N.C.
CD
SDA
SCL
BOOT
F
SYS
SYS
SYS
SYS
BGATE
INT
DRV
G
BAT
BAT
BAT
BAT
TS
STAT
AGND
PMID
BOOT
19
AGND
22
20
BYP
23
21 IN
CD
24
24-PIN QFN (Top View)
N.C.
1
18
SW
N.C.
2
17
PGND
SCL
3
16
PGND
bq24272
12
SYS
BAT
13
11
6
BAT
DRV
10
SYS
BGATE
14
9
5
TS
AGND
8
PGND
STAT
15
7
4
INT
SDA
(Contact the factory for the latest pinout)
6
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PIN FUNCTIONS
PIN NAME
PIN NO. bq24272
I/O
DESCRIPTION
21
I
Input power supply. IN is connected to the external DC supply (AC adapter or alternate power source). Bypass
IN to PGND with at least a 1μF ceramic capacitor.
B1–B4
20
O
Reverse Blocking MOSFET and High Side MOSFET Connection Point for High Power Input. Bypass PMID to
GND with at least a 4.7μF ceramic capacitor. Use caution when connecting an external load to PMID. The
PMID output is not current limited. Any short on PMID will result in damage to the IC.
BYP
B5–B7
23
O
Bypass for internal circuits. Bypass BYP to GND with at least 0.1µF of capacitance. Do not connect any
external load to BYP.
SW
C1–C7
18
O
Inductor Connection. Connect to the switched side of the external inductor.
AGND
A5–A7,
E1, G7
5, 22
—
Ground terminal.
PGND
D1–D7
15, 16, 17
—
N.C.
E2, E3
1, 2
I
No connection. Leave N.C. unconnected.
CD
E4
24
I
IC Hardware Disable Input. Drive CD high to place the bq24272 in High-Z mode. Drive CD low for normal
operation.
YFF
RGE
IN
A1–A4
PMID
Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.
SDA
E5
4
I/O
I2C Interface Data. Connect SDA to the logic rail through a 10kΩ resistor.
SCL
E6
3
I
I2C Interface Clock. Connect SCL to the logic rail through a 10kΩ resistor.
BOOT
E7
19
I
High Side MOSFET Gate Driver Supply. Connect a 0.01µF ceramic capacitor (voltage rating > 10V) from
BOOT to SW to supply the gate drive for the high side MOSFETs.
SYS
F1–F4
13, 14
I
System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the output bulk
capacitors. Bypass SYS locally with 10μF.
BGATE
F5
10
O
External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET to provide a
very low resistance discharge path. Connect BGATE to the gate of the external MOSFET. BGATE is low during
supplement mode and when no input is connected.
INT
F6
7
O
Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls low during
charging. INT is high impedance when charging is complete or the charger is disabled. When a fault occurs, a
128μs pulse is sent out as an interrupt for the host. INT is enabled /disabled using the EN_STAT bit in the
control register. Connect INT to a logic rail through a 100kΩ resistor to communicate with the host processor.
DRV
F7
6
O
Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass DRV to PGND
with a 1μF ceramic capacitor. DRV may be used to drive external loads up to 10mA. DRV is active whenever
the input is connected and VIN > VUVLO and VSUPPLY > (VBAT + VSLP)
BAT
G1–G4
11, 12
I/O
Battery Connection. Connect to the positive terminal of the battery. Additionally, bypass BAT to GND with a
1μF capacitor.
TS
G5
9
I
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The NTC is
connected from TS to GND. The TS function provides 4 thresholds for JEITA compatibility. TS faults are
reported by the I2C interface. See the NTC Monitor section for more details on operation and selecting the
resistor values.
STAT
G6
8
O
Status Output. STAT is an open-drain output that signals charging status and fault interrupts. STAT pulls low
during charging. STAT is high impedance when charging is complete or the charger is disabled. When a fault
occurs, a 128μs pulse is sent out as an interrupt for the host. STAT is enabled /disabled using the EN_STAT
bit in the control register. Connect STAT to a logic rail using an LED for visual indication or through a 10kΩ
resistor to communicate with the host processor.
Thermal
PAD
—
Pad
—
There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The
thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use
the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times.
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TYPICAL APPLICATION CIRCUIT
ADAPTER
1.5 mH
SW
IN
PMID
0.01 mF
1 mF
4.7 mF
System
Load
BOOT
SYS
10 mF
BYP
PGND
1 mF
BGATE
DRV
BAT
VDRV
1 mF
1 mF
STAT
PACK+
TS
TEMP
VSYS
(1.8 V)
PACK-
bq24272
INT
HOST
GPIO1
SDA
SDA
SCL
SCL
Figure 1. bq24272 Application Circuit, External Discharge FET Connected
8
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DETAILED DESCRIPTION
The bq24272 is a highly integrated single cell Li-Ion battery charger and system power path management
devices targeted for space-limited, portable applications with high capacity batteries. The single-input, single cell
charger operates from a dedicated power source (i.e. wall adapter or wireless power input).
The power path management feature allows the bq24272 to power the system from a high efficiency DC to DC
converter while simultaneously and independently charging the battery. The charger monitors the battery current
at all times and reduces the charge current when the system load requires current above the input current limit.
This allows for proper charge termination and enables the system to run with a defective or absent battery pack.
Additionally, this enables instant system turn-on even with a totally discharged battery or no battery. The powerpath management architecture also permits the battery to supplement the system current requirements when the
adapter cannot deliver the peak system currents. This enables the use of a smaller adapter. The charge
parameters are programmable using the I2C interface.
The battery is charged in three phases: conditioning, constant current and constant voltage. In all charge phases,
an internal control loop monitors the IC junction temperature and reduces the charge current if the internal
temperature threshold is exceeded.
Charge Mode Operation
Charge Profile
The internal battery MOSFET is used to charge the battery. When the battery is above the MINSYS voltage, the
internal FET is on to maximize efficiency and the PWM converter regulates the charge current into the battery.
When battery is less than MINSYS, the SYS is regulated to VSYS(REG) and battery is charged using the battery
FET to regulate the charge current. There are 5 loops that influence the charge current:
• Constant current loop (CC)
• Constant voltage loop (CV)
• Thermal-regulation loop
• Minimum system-voltage loop (MINSYS)
• Input-voltage dynamic power-management loop (VIN-DPM)
During the charging process, all five loops are enabled and the one that is dominant takes control. The bq24272
supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. The Dynamic Power Path
Management (DPPM) feature regulates the system voltage to a minimum of VMINSYS, so that startup is enabled
even for a missing or deeply discharged battery. Figure 2 shows a typical charge profile including the minimum
system output voltage feature.
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Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
voltage
Charge Current
Regulation
Threshold
System Voltage
V SYS
(3.6 V)
VBATSHORT
(3.0 V)
Battery
Voltage
Charge Current
Termination
Current
Threshold
I BATSHORT
50 mA Precharge to
Close Pack Protector
Linear Charge
to Maintain
Minimum
System
Voltage
Battery
FET
is OFF
Battery FET is ON
Figure 2. Typical Charging Profile for bq24272
PWM Controller in Charge Mode
The bq24272 provides an integrated, fixed-frequency 1.5MHz voltage-mode controller to power the system and
supply the charge current. The voltage loop is internally compensated and provides enough phase margin for
stable operation, allowing the use of small ceramic capacitors with very low ESR. The input scheme for the
bq24272 prevents battery discharge when the supply voltages are lower than VBAT. The high-side N-MOSFET
(Q1) switches to control the power delivered to the output. The DRV LDO provides a supply for the gate drive for
the low side MOSFET, while a bootstrap circuit (BST) with an external bootstrap capacitor is used to boost up
the gate drive voltage for Q1.
The input is protected by a cycle-by-cycle current limit that is sensed through the internal sense MOSFETs for
Q1. The threshold for the current limit is set to a nominal 5-A peak current. The input also utilizes an input
current limit that limits the current from the power source.
Battery Charging Process
When the battery is deeply discharged or shorted (VBAT VSYS(REG), the battery FET is turned on and the SYS output is
connected to BAT. If the SYS voltage falls to VSYS(REG), it is regulated to that point to maintain the system output
even with a deeply discharged or absent battery. In this mode, the SYS output voltage is regulated by the buck
converter and the battery FET linearly regulates the charge current into the battery. The current from the supply
is shared between charging the battery and powering the system load at SYS. The dynamic power path
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management (DPPM) circuitry of the bq24272 monitors the current limits continuously and if the SYS voltage
falls to the VMINSYS voltage, it adjusts charge current to maintain the minimum system voltage and supply the load
on SYS. If the charge current is reduced to zero and the load increases further, the bq24272 enters battery
supplement mode. During supplement mode, the battery FET is turned on and the battery supplements the
system load.
2000mA
1800 mA
I SYS
800 mA
0mA
1500mA
IIN
~ 850 mA
0 mA
1A
I BAT
0 mA
-200mA
3.75 V
3.55 V
DPPM loop active
VOUT
~3.1 V
Supplement
Mode
Figure 3. Example DPPM Response (VSupply=5V, VBAT = 3.1V, 1.5A Input current limit)
VBAT(REG) should never be programmed less than VBAT. If the battery is ever 5% above the regulation threshold,
the battery OVP circuit shuts the PWM converter off and the battery FET is turned on to discharge the battery to
safe operating levels. Battery OVP errors are shown in the I2C status registers.
Battery Only Connected
When a battery voltage > VBATUVLO is connected with no input source, the battery FET is turned on similar to
supplement mode. In this mode, the current is not regulated; however, there is a short circuit current limit. If the
short circuit limit is reached, the battery FET is turned off for the deglitch time. After the deglitch time, the battery
FET is turned on to test and see if the short has been removed. If it has not, the FET turns off and the process
repeats until the short is removed. This process is to protect the internal FET from over current. If an external
FET is used for discharge, the body diode prevents the load on SYS from being disconnected from the battery. If
the battery voltage is less than VBATUVLO, the battery FET (Q3) remains off and BAT is high-impedance. This
prevents further discharging deeply discharged batteries.
Battery Discharge FET (BGATE)
The bq24272 contains a MOSFET driver to drive an external discharge FET between the battery and the system
output. This external FET provides a low impedance path when supplying the system from the battery. Connect
BGATE to the gate of the external discharge MOSFET. BGATE is on under the following conditions:
1. No input supply connected.
2. HZ_MODE = 1
3. CD pin connected high
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DEFAULT Mode
DEFAULT mode is used when I2C communication is not available. DEFAULT mode is entered in the following
situations:
1. When the charger is enabled and VBAT VBAT+ VSLP, the STATx and FAULT_x
bits are cleared and the device initiates a new charge cycle.
Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage will decease. Once the supply drops to VIN_DPM (default 4.2V), the input
current limit is reduced down to prevent further supply droop. When the IC enters this mode, the charge current
is lower than the set value and the DPM_STATUS bit is set (Bit 5 in Register 05H). This feature ensures IC
compatibility with adapters with different current capabilities without a hardware change. Figure 7 shows the VINDPM behavior to a current limited source. In this figure the input source has a 750mA current limit and the
charging is set to 750mA. The SYS load is then increased to 1.2A.
16
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VIN
5 V Adapter
rated for 750 mA
IIN
VSYS
IBAT
ISYS
Figure 7. bq24272 VIN-DPM
Bad Source Detection
When a source is connected to IN, the bq24272 runs a Bad Source Detection procedure to determine if the
source is strong enough to provide some current to charge the battery. A current sink is turned on (75mA) for
32ms. If the source is valid after the 32ms (VBADSOURCE < VIN < VOVP), the buck converter starts up and normal
operation continues. If the supply voltage falls below VBAD_SOURCE during the detection, the current sink shuts off
for 2s and then retries, a single 128μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x
bits of the status registers and the battery/supply status registers are updated in the I2C. The detection circuits
retries continuously until either a new source is connected to the other input or a valid source is detected after
the detection time. If during normal operation the source falls to VBAD_SOURCE, the bq24272 turns off the PWM
converter, turns the battery FET and BGATE on, sends a single 128μs pulse is sent on the STAT and INT
outputs and the STATx and FAULT_x bits of the status registers and the battery/supply status registers are
updated in the I2C. Once a good source is detected, the STATx and FAULT_x bits are cleared and the device
returns to normal operation.
Input Over-Voltage Protection
The bq24272 provides over-voltage protection on the input that protects downstream circuitry. The built-in input
over-voltage protection to protect the device and other components against damage from overvoltage on the
input supply (Voltage from VIN to PGND). During normal operation, if VIN > VOVP, the bq24272 turns off the PWM
converter, turns the battery FET and BGATE on, sends a single 128μs pulse is sent on the STAT and INT
outputs and the STATx and FAULT_x bits of the status registers and the battery/supply status registers are
updated in the I2C. Once the OVP fault is removed, the STATx and FAULT_x bits are cleared and the device
returns to normal operation.
Charge Status Outputs (STAT, INT)
The STAT output is used to indicate operation conditions for bq24272. STAT is pulled low during charging when
EN_STAT bit in the control register (0x02h) is set to “1”. When charge is complete or disabled, STAT is high
impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of STAT
during different operation conditions is summarized in Table 1. STAT drives an LED for visual indication or can
be connected to the logic rail for host communication. The EN_STAT bit in the control register (00H) is used to
enable/disable the charge status for STAT. The interrupt pulses are unaffected by EN_STAT and will always be
shown. The INT output is identical to STAT and is used to interface with a low voltage host processor.
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Table 1. STAT Pin Summary
CHARGE STATE
STAT AND INT BEHAVIOR
Charge in progress and EN_STAT=1
Low
Other normal conditions
High-Impedance
Status Changes: Supply Status Change (plug in or removal), safety timer fault, watchdog
expiration, sleep mode, battery temperature fault (TS), battery fault (OVP or absent),
thermal shutdown
128-µs pulse, then High Impedance
REGISTER DESCRIPTION
Status/Control Register (READ/WRITE)
Memory location: 00, Reset state: 0xxx 0xxx
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
TMR_RST
Read/Write
Write: TMR_RST function, write “1” to reset the watchdog timer (auto clear)
Read: Always 0
B6
STAT_2
Read only
B5
STAT_1
Read only
B4
STAT_0
Read only
000- No Valid Source Detected
001- IN Ready
010- NA
011- Charging
100101- Charge Done
110- NA
111- Fault
B3
NA
Read/Write
NA
000-Normal
001- Thermal Shutdown
010- Battery Temperature Fault
011- Watchdog Timer Expired
100- Safety Timer Expired
101- Supply Fault
110- NA
111- Battery Fault
B2
FAULT_2
Read only
B1
FAULT_1
Read only
Battery/ Supply Status Register (READ/WRITE)
Memory location: 01, Reset state: xxxx 0xxx
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
STAT1
Read Only
B6
STAT0
Read Only
00-Normal
01-Supply OVP
10-Weak Source Connected (No Charging)
11- VIN THOT(Charging suspended)
10 – TCOOL > TS temp > TCOLD (Charge current reduced by half)
11 – TWARM < TS temp < THOT (Charge voltage reduced by 140mV)
B0(LSB)
LOW_CHG
Read/Write
0 – Charge current as programmed in Register 0x05
1 – Charge current half programmed value in Register 0x05 (default 0)
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LOW_CHG Bit (Low Charge Mode Enable)
The LOW_CHG bit is used to reduce the charge current from the programmed value. This feature is used by
systems where battery NTC is monitored by the host and requires a reduced charge current setting or by
systems that need a “preconditioning” current for low battery voltages. Write a “1” to this bit to charge at half of
the programmed charge. Write a “0” to this bit to charge at the programmed charge current.
22
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APPLICATION INFORMATION
Output Inductor and Capacitor Selection Guidelines
When selecting an inductor, several attributes must be examined to find the right part for the application. First,
the inductance value should be selected. The bq24272 is designed to work with 1.5µH to 2.2µH inductors. The
chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some
efficiency gain is reached using the 2.2µH inductor, however, due to the physical size of the inductor, this may
not be a viable option. The 1.5µH inductor provides a good tradeoff between size and efficiency.
Once the inductance has been selected, the peak current must be calculated in order to choose the current
rating of the inductor. Use equation 2 to calculate the peak current.
æ %
ö
IPEAK = ILOAD(MAX) ´ ç 1 + RIPPPLE ÷
2
è
ø
(3)
The inductor selected must have a saturation current rating less than or equal to the calculated IPEAK. Due to the
high currents possible with the bq24272, a thermal analysis must also be done for the inductor. Many inductors
have 40°C temperature rise rating. This is the DC current that will cause a 40°C temperature rise above the
ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted for the duty
cycle of the load transients. For example, if the application requires a 1.5A DC load with peaks at 2.5A 20% of
the time, a Δ40°C temperature rise current must be greater than 1.7A:
ITEMPRISE = ILOAD + D ´ (IPEAK - ILOAD ) = 1.5A + 0.2 ´ (2.5A - 1.5A ) = 1.7A
(4)
The bq24272 provides internal loop compensation. Using this scheme, the bq24272 is stable with 10µF to 200µF
of local capacitance. The capacitance on the BAT rail can be higher if distributed amongst the rail. To reduce the
output voltage ripple, a ceramic capacitor with the capacitance between 10µF and 47µF is recommended for
local bypass to SYS.
PCB Layout Guidelines
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND, must be
placed as close as possible to the bq24272
• Place 4.7µF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current
loop area as small as possible. Place 1µF input capacitor GNDs as close to the respective PMID cap GND
and PGND pins as possible to minimize the ground difference between the input and PMID_.
• The local bypass capacitor from SYS to GND should be connected between the SYS pin and PGND of the
IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the
PGND pin.
• Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noisecoupling and ground-bounce issues. A single ground plane for this design gives good results. With this small
layout and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
• The high-current charge paths into IN, BAT, SYS and from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
• For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance as the board pulls heat away from the IC.
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Sample Layout
QFN I2C PART
WCSP I2C PART
GND
GND
PMID
IN
BOOT
BYP
PMID
BYP
SW
IN
BOOT
PGND
SW
SW
SYS
PGND
BAT
SYS
SYS
SYS
BAT
Package Summary
1
2
3
4
5
6
7
A
IN
IN
IN
IN
PGND
PGND
PGND
B
PMIDI
PMIDI
PMIDI
PMIDI
BYP
BYP
BYP
C
SW
SW
SW
SW
SW
SW
SW
D
PGND
PGND
PGND
PGND
PGND
PGND
PGND
E
PGND
N.C.
N.C.
CD
SDA
SCL
BOOT
F
SYS
SYS
SYS
SYS
BGATE
INT
DRV
G
BAT
BAT
BAT
BAT
TS
STAT
PGND
TI YMLLLLS
bq24272
D
0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code,
LLLL-Lot Trace Code, S-Assembly Site Code
E
CHIP SCALE PACKAGING DIMENSIONS
The bq2427x devices are available in a 49-bump chip scale package (YFF, NanoFreeTM). The package dimensions are:
D – 2.78 mm ± 0.05 mm
E – 2.78 mm ± 0.05 mm
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ24272RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
24272
BQ24272RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
24272
BQ24272YFFR
ACTIVE
DSBGA
YFF
49
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24272
BQ24272YFFT
ACTIVE
DSBGA
YFF
49
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24272
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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