Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
bq24600
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
bq24600 Stand-Alone Synchronous Switch-Mode Li-Ion or Li-Polymer Battery Charger
with Low Iq
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Portable Equipment Handle Terminals
Industrial and Medical Equipment
Power Tools Appliance
Mobile Internet Device, and Ultra-Mobile PC
3 Description
The bq24600 is a highly integrated Li-ion or Lipolymer switch-mode battery-charge controller. It
offers a constant-frequency synchronous PWM
controller with high-accuracy charge current and
voltage
regulation,
charge
preconditioning,
termination, and charge status monitoring,
The bq24600 charges the battery in three phases:
preconditioning, constant current, and constant
voltage. Charge is terminated when the current
reaches a minimum level. An internal charge timer
provides a safety backup. The bq24600 automatically
restarts the charge cycle if the battery voltage falls
below an internal threshold, and enters a lowquiescent-current sleep mode when the input voltage
falls below the battery voltage.
Device Information(1)
PART NUMBER
PACKAGE
bq24600
BODY SIZE (NOM)
VQFN (16)
3.50 mm x 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
ADAPTER +
R11
2 kW
D2
MBRS540T3
ADAPTER C2
2.2 µF
C8
10 µF
R6
10 W
VREF
HIDRV
VCC
C7
1 µF
R7
100 kW
PH
R8
22.1 kW
REGN
VREF
bq24600
LODRV
STAT
GND
R14 10 kW
D4
PG
SRP
VREF
SRN
R5
100 W
TS
R10
430 kW
0.1 μF
RSR
0.010 Ω
VBAT
3.3 µH*
C10
0.1 µF
PACK+
PACK-
C13
C12
10 µF* 10 µF*
Q5
SiR426
CE
D3
ADAPTER +
R9
9.31 kW
D1
BAT54
C6
0.1 µF
C5
1 µF
C4
1 µF
R13 10 kW
Q4
SiR426
L1
BTST
ISET
Pack
Thermistor
Sense
C9
10 µF
N
•
1.2-MHz NMOS-NMOS Synchronous Buck
Converter
Stand-Alone Charger Support for Li-Ion or LiPolymer
5-V – 28-V VCC Input Voltage Range and
Supports 1S-6S Battery Cells
Up to 10-A Charge Current and Adapter Current
High-Accuracy Voltage and Current Regulation
– ±0.5% Charge-Voltage Accuracy
– ±3% Charge-Current Accuracy
Integration
– Internal Loop Compensation
– Internal Soft Start
Safety
– Input Overvoltage Protection
– Battery Thermistor Sense Hot/Cold Charge
Suspend
– Battery Detection
– Built-In Safety Timer
– Charge Overcurrent Protection
– Battery Short Protection
– Battery Overvoltage Protection
– Thermal Shutdown
Status Outputs
– Adapter Present
– Charger Operation Status
Charge Enable Pin
6-V Gate Drive for Synchronous Power Converter
30-ns Driver Dead-Time and 99.5% Max. Effective
Duty Cycle
16-Pin 3.5-mm × 3.5-mm QFN package
Energy Star Low Quiescent Current Iq
– < 15-μA Off-State Battery Discharge Current
– < 1.5-mA Off-State Input Quiescent Current
N
1
C11
0.1 µF
R2
900 kW
Cff
22 pF
R1
100 kW
VFB
PwrPad
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24600
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
8
9
Absolute Maximum Ratings .....................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application ................................................. 21
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 28
11 Device and Documentation Support ................. 29
11.1
11.2
11.3
11.4
Trademarks ...........................................................
Third-Party Products Disclaimer ...........................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2011) to Revision B
Page
•
Changed Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Device and Documentation ........................................ 1
•
Changed feature text From: "Supports 1-6 Battery Cells" To: "Supports 1S-6S Battery Cells"............................................. 1
•
Changed the Application list .................................................................................................................................................. 1
•
Deleted the Table of Graphs from the Typical Characteristics section ................................................................................. 9
•
Changed the Description of D3, D4 in Table 4 From: "LED diode, green, 2.1 V, 10 mΩ, Vishay-Dale,
WSL2010R0100F" To:"LED diode, green, 2.1 V, 20 mA, LTST-C190GKT"........................................................................ 22
Changes from Original (February 2010) to Revision A
Page
•
Changed descriptions of PH and BTST pins in Pin Description table.................................................................................... 3
•
Changed VHTF to VTCO in two places in Equation 5 .............................................................................................................. 14
•
Changed Equation 15 .......................................................................................................................................................... 23
2
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
bq24600
www.ti.com
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
5 Pin Configuration and Functions
BTST
HIDRV
PH
LODRV
RVA Package
(Top View)
16
15
14
13
CE
2
11 GND
STAT
3
10 SRP
TS
4
9
PG
5
6
7
8
VFB
12 REGN
ISET
1
VREF
VCC
SRN
Pin Functions
PIN
I/O
FUNCTION DESCRIPTION
NAME
NO.
VCC
1
I
IC power positive supply. Connect, through a 10-Ω resistor to the common-source (diode-OR) point: source of high-side Pchannel MOSFET and source of reverse-blocking power P-channel MOSFET. Or connect through a 10-Ω resistor to the
cathode of the input diode. Place a 1-μF ceramic capacitor from VCC to the GND pin close to the IC.
CE
2
I
Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1MΩ pull-down resistor.
STAT
3
I
Open-drain charge status pin to indicate various charger operation (See Table 2)
TS
4
I
Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot and cold
temperature window with a resistor divider from VREF to TS to GND.
PG
5
O
Open-drain power-good status output. The transistor turns on when a valid VCC is detected. It is turned off in the sleep mode.
PG can be used to drive an LED or communicate with a host processor. It can be used to drive ACFET and BATFET.
VREF
6
O
3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to the GND pin close to the IC. This voltage could
be used for programming of voltage and current regulation and for programming the TS threshold.
ISET
7
I
Charge current set input. The voltage of ISET pin programs the charge current regulation, pre-charge current and termination
current set-point.
VFB
8
O
Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this
node to adjust the output battery regulation voltage.
SRN
9
I
Charge-current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differentialmode filtering. An optional 0.1-μF ceramic capacitor is placed from SRN pin to GND for common-mode filtering.
SRP
10
I
Charge-current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differentialmode filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to GND for common-mode filtering.
GND
11
--
Low-current sensitive analog/digital ground. On PCB layout, connect with thermal pad underneath the IC.
REGN
12
O
PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to the PGND pin, close to the
IC. Use for low-side driver and high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to
BTST.
LODRV
13
O
PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
PH
14
I
PWM high-side driver negative supply. Connect to the phase-switching node (junction of the low-side power MOSFET drain,
high-side power MOSFET source, and output inductor).
HIDRV
15
O
PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
BTST
16
I
PWM high-side driver negative supply. Connect the 0.1-μF bootstrap capacitor from PH to BTST, and a bootstrap Schottky
diode from REGN to BTST.
Thermal
pad
--
--
Exposed pad beneath the IC. Always solder thermal pad to the board, and have vias on the thermal pad plane starconnecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
3
bq24600
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings (1)
(2) (3)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
–0.3
33
V
PH
–2
36
V
VFB
–0.3
16
V
REGN, LODRV, TS
–0.3
7
V
BTST, HIDRV with respect to GND
–0.3
39
V
VREF, ISET
–0.3
3.6
V
SRP–SRN
–0.5
0.5
V
–40
155
ºC
VCC, SRP, SRN, CE, STAT, PG
Voltage range
Maximum difference voltage
Junction temperature range, TJ
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
Must have a series resistor between battery pack and VFB if battery-pack voltage is expected to be greater than 16 V. Usually the
resistor-divider top resistor takes care of this.
6.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
UNIT
°C
–55
155
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
–1000
1000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
–250
250
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VALUE
UNIT
–0.3 to 28
V
PH
–2 to 30
V
VFB
–0.3 to 14
V
REGN, LODRV, TS
–0.3 to 6.5
V
BTST, HIDRV with respect to GND
–0.3 to 34
V
ISET
–0.3 to 3.3
V
VREF
3.3
V
–0.2 to 0.2
V
0 to 125
ºC
VCC, SRP, SRN, CE, STAT, PG
Voltage range
Maximum difference voltage
SRP–SRN
Junction temperature range, TJ
4
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
bq24600
www.ti.com
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
6.4 Thermal Information
RVA
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
16
ψJT
Junction-to-top characterization parameter
0.6
ψJB
Junction-to-board characterization parameter
15.77
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4
(1)
UNIT
16 PINS
43.8
81
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CONDITIONS
VVCC_OP
VCC input voltage operating range
5
28
V
15
μA
QUIESCENT CURRENTS
IBAT
IAC
Total battery discharge current (sum of
currents into VCC, BTST, PH, SRP,
SRN, VFB), VFB ≤ 2.1 V
Adapter supply current
(current into VCC pin)
VVCC < VSRN, VVCC > VUVLO (SLEEP)
VVCC > VSRN, VVCC > VUVLO CE = LOW (IC quiescent
current)
1
1.5
VVCC > VSRN, VVCC >VVCCLOW, CE = HIGH, charge
done
2
5
VVCC > VSRN, VVCC >VVCCLOW, CE = HIGH, Charging,
Qg_total = 20 nC, VVCC= 20 V
mA
50
CHARGE VOLTAGE REGULATION
VFB
Feedback regulation voltage
Charge voltage regulation accuracy
IVFB
Leakage Current into VFB pin
2.1
V
TJ = 0°C to 85°C
–0.5%
0.5%
TJ = –40°C to 125°C
–0.7%
0.7%
VFB = 2.1 V
100
100
nA
CURRENT REGULATION – FAST CHARGE
VISET
ISET voltage range
VIREG_CHG
SRP-SRN current sense voltage range
VIREG_CHG = VSRP – VSRN
KISET
Charge current set factor (amps of
charge current per volt on ISET pin)
RSENSE = 10 mΩ
Charge current regulation accuracy
IISET
Leakage current into ISET pin
2
5
V
mV
A/V
VIREG_CHG = 40 mV
–3%
VIREG_CHG = 20 mV
–4%
3%
4%
VIREG_CHG = 5 mV
–25%
25%
VIREG_CHG = 1.5 mV (VSRN > 3.1 V)
–40%
40%
VISET = 2 V
100
nA
CURRENT REGULATION – PRECHARGE
KPRECH
Precharge current range
RSENSE = 10 mΩ
ICHARGE/10
Precharge current set factor (amps of
precharge current per volt on ISET pin)
RSENSE = 10 mΩ
0.5
Precharge current regulation accuracy
A
A/V
VIREG_PRECH = 10 mV
–10%
10%
VIREG_PRECH = 5 mV
–25%
25%
VIREG_PRECH = 1.5 mV (VSRN < 3.1 V)
–55%
55%
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
5
bq24600
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
www.ti.com
Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHARGE TERMINATION
KTERM
Termination current range
RSENSE = 10 mΩ
ICHARGE/10
Termination current set factor (amps of
termination current per volt on ISET pin)
RSENSE = 10 mΩ
0.5
Termination current accuracy
IQUAL
Termination qualification current
A
A/V
VITERM = 10 mV
–10%
10%
VITERM = 5 mV
–25%
25%
VITERM = 1.5 mV
–45%
Discharge current once termination is detected
45%
2
mA
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)
VUVLO
AC undervoltage rising threshold
VUVLO_HYS
AC undervoltage hysteresis, falling
Measure on VCC
3.65
3.85
4
350
V
mV
VCC LOWV COMPARATOR
Falling threshold, disable charge
Measure on VCC
4.1
Rising threshold, resume charge
V
4.35
4.5
V
100
150
mV
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
VSLEEP
_FALL
VSLEEP_HYS
SLEEP falling threshold
VVCC – VSRN to enter SLEEP
40
SLEEP hysteresis
500
mV
BAT LOWV COMPARATOR
VLOWV
Precharge to fast-charge transition
(LOWV threshold)
VLOWV_HYS
LOWV hysteresis
Measured on VFB pin
1.534
1.55
1.566
100
V
mV
RECHARGE COMPARATOR
Recharge threshold (with respect
to.VREG)
VRECHG
Measured on VFB pin
35
50
65
mV
BAT OVER-VOLTAGE COMPARATOR
VOV_RISE
Overvoltage rising threshold
As percentage of VFB
104%
VOV_FALL
Overvoltage falling threshold
As percentage of VFB
102%
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
VACOV
AC overvoltage rising threshold on VCC
VACOV_HYS
AC overvoltage falling hysteresis
31.04
32
32.96
V
1
V
145
°C
15
°C
THERMAL SHUTDOWN COMPARATOR
TSHUT
Thermal shutdown rising temperature
TSHUT_HYS
Thermal shutdown hysteresis
Temperature increasing
THERMISTOR COMPARATOR
VLTF
Cold temperature rising threshold
As percentage to VVREF
72.5%
73.5%
VLTF_HYS
Rising hysteresis
As percentage to VVREF
0.2%
0.4%
74.5%
0.6%
VHTF
Hot temperature rising threshold
As percentage to VVREF
36.2%
37%
37.8%
VTCO
Cutoff temperature rising threshold
As percentage to VVREF
33.7%
34.4%
35.1%
Deglitch time for temperature out of
range detection
VTS > VLTF, or VTS < VTCO, or VTS < VHTF
Deglitch time for temperature in valid
range detection
VTS < VLTF – VLTF_HYS or VTS >VTCO, or VTS > VHTF
400
ms
20
ms
45.5
mV
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
Charge overcurrent falling threshold
VOC
Current rising, in non-synchronous mode, mesure on
V(SRP-SRN), VSRP < 2 V
Current rising, as percentage of V(IREG_CHG), in
synchronous mode, VSRP > 2.2 V
160%
Charge overcurrent threshold floor
Minimum OCP threshold in synchronous mode,
measure on V(SRP-SRN), VSRP > 2.2 V
50
mV
Charge over-current threshold ceiling
Maximum OCP threshold in synchronous mode,
measure on V(SRP-SRN), VSRP > 2.2 V
180
mV
CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
VISYNSET
6
Charge under-current falling threshold
VSRP>2.2 V, switch from CCM to DCM
Submit Documentation Feedback
1
5
9
mV
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
bq24600
www.ti.com
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BATTERY SHORTED COMPARATOR (BATSHORT)
VBATSHT
BAT Short falling threshold, forced nonsyn mode
VBATSHT_HYS
BAT short rising hysteresis
VSRP falling
2
V
200
mV
1.25
mV
1.25
mV
LOW CHARGE CURRENT COMPARATOR
VLC
Low charge current (average) falling
threshold to force into non-sync mode
VLC_HYS
Low charge current rising hysteresis
Measure V(SRP-SRN)
VREF REGULATOR
VVREF_REG
VREF regulator voltage
VVCC > VUVLO (0 - 35-mA load)
3.267
IVREF_LIM
VREF current limit
VVREF = 0 V, VVCC > VUVLO
35
3.3
3.333
V
mA
REGN REGULATOR
VREGN_REG
REGN regulator voltage
VVCC > 10 V, CE = HIGH (0 - 40 mA load)
5.7
IREGN_LIM
REGN current limit
VREGN = 0 V, VVCC > VUVLO
40
RSENSE = 10 mΩ
50
6.0
6.3
V
mA
BATTERY DETECTION
IWAKE
Wake current
IDISCHARGE
Discharge current
8
mA
IFAULT
Fault current after a timeout fault
2
mA
VWAKE
Wake threshold (relative to VREG)
Voltage on VFB to detect battery absent during wake
50
mV
Discharge threshold
Voltage on VFB to detect battery absent during
discharge
VDISCH
125
200
1.55
mA
V
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON
High-side driver (HSD) turnon resistance
VBTST – VPH = 5.5 V
3.3
6
Ω
RDS_HI_OFF
High-side driver turnoff resistance
VBTST – VPH = 5.5 V
1
1.3
Ω
VBTST_REFRESH
Bootstrap refresh comparator threshold
voltage
VBTST – VPH when low side refresh pulse is
requested
4
4.2
V
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON
Low-side driver (LSD) turnon resistance
RDS_LO_OFF
Low-side driver turnoff resistance
4.1
7
Ω
1
1.4
Ω
PWM OSCILLATOR
VRAMP_HEIGHT
PWM ramp height
As percentage of VCC
PWM switching frequency (1)
7%
1020
1200
1380
kHz
INTERNAL SOFT START (8 steps to regulation current ICHARGE)
Soft-start steps
8
step
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power up
Delay from when CE = 1 to when the charger is
allowed to turn on
1.5
s
LOGIC IO PIN CHARACTERISTICS (CE, STAT, PG)
VIN_LO
CE input low threshold voltage
VIN_HI
CE input high threshold voltage
VBIAS_CE
CE input bias current
V = 3.3 V (CE has internal 1MΩ pulldown resistor)
VOUT_LO
STAT, PG output low saturation voltage
Sink current = 5 mA
0.5
V
IOUT_HI
Leakage current
V = 32 V
1.2
µA
(1)
0.8
V
6
μA
2.1
Specified by design.
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
7
bq24600
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
www.ti.com
6.6 Timing Requirements
MIN
TYP
MAX
UNIT
CHARGE TERMINATION
Deglitch time for termination (both
edges)
tQUAL
Termination qualification time
ms
100
VBAT > VRECH and ICHARGE < ITERM
250
ms
1
µs
30
ms
100
ms
30
ms
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
SLEEP rising delay
VCC falling below SRN, delay to pull up
PG
SLEEP falling delay
VCC rising above SRN, delay to pull down
PG
SLEEP rising shutdown deglitch
VCC falling below SRN, delay to enter
SLEEP mode
SLEEP falling powerup deglitch
VCC rising above SRN, delay to come out
of SLEEP mode
BAT LOWV COMPARATOR
LOWV rising deglitch
VFB falling below VLOWV
25
ms
LOWV falling deglitch
VFB rising above VLOWV + VLOWV_HYS
25
ms
RECHARGE COMPARATOR
Recharge rising deglitch
VFB decreasing below VRECHG
10
ms
Recharge falling deglitch
VFB increasing above VRECHG
10
ms
AC overvoltage rising deglitch
1
ms
AC overvoltage falling deglitch
1
ms
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
VACOV_HYS
THERMISTOR COMPARATOR
Thermal shutdown rising deglitch
Temperature increasing
100
μs
Thermal shutdown falling deglitch
Temperature decreasing
10
ms
1
μs
1
μs
BATTERY SHORTED COMPARATOR (BATSHORT)
VBATSHT_DEG
Deglitch on both edges
LOW CHARGE CURRENT COMPARATOR
VLC_DEG
Deglitch on both edges
SAFETY TIMER
tPRECHG
Precharge safety timer range (1)
tCHARGE
Internal five hour safety timer (1)
Precharge time before fault occurs
1440
1800
2160
s
4.25
5
5.75
hr
BATTERY DETECTION
tWAKE
Wake timer
Max time charge is enabled
tDISCHARGE
Discharge timer
Max time discharge current is applied
500
ms
1
s
30
ns
1.6
ms
PWM DRIVERS TIMING
Driver dead time
Dead time when switching between LSD
and HSD, no load at LSD and HSD
INTERNAL SOFT START (8 steps to regulation current ICHARGE)
Soft-start step time
(1)
8
Specified by design.
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
bq24600
www.ti.com
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
10 V/div
10 V/div
6.7 Typical Characteristics
PH
2 A/div
IBAT
REGN
5 V/div
CE
5 V/div
2 V/div
VREF
5 V/div
/PG
2 V/div
VCC
LODRV
t − Time = 200 ms/div
t − Time = 4 ms/div
CE = 1
Figure 2. Charge Enable
10 V/div
10 V/div
Figure 1. REF REGN and PG Power Up
PH
IL
5 V/div
0.2 V/div 5 V/div
CE
2 A/div
PH
LODRV
2 A/div
LODRV
20 V/div
IL
VBAT
t − Time = 1 μs/div
t − Time = 4 ms/div
Figure 4. Battery-to-GND Short Protection
Figure 3. Charge Disable
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
9
bq24600
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
www.ti.com
7 Detailed Description
7.1 Overview
The bq24600 is a highly integrated Li-ion or Li-polymer switch-mode battery charge controller.
7.2 Functional Block Diagram
bq24600
VCC
-
SRN+100mV
+
VCC
-
VUVLO
+
SLEEP
3.3V
LDO
UVLO
VCC
VREF
VREF
INTERNAL
REFERENCE
CE
1M
COMP
ERROR
AMPLIFIER
BTST
CE
+
+
1V
PWM
-
VFB
+
LEVEL
SHIFTER
-
2.1 V
HIDRV
BAT_OVP
20uA
SRP
SRP-SRN
+
SYNCH
PH
20xV(SRP-SRN)
+
IBAT_ REG
SRN
BTST
_+
PH
20μA
REFRESH
-
VCC
CE
-
+
20X
-
PWM
CONTROL
LOGIC
+
5 mV -
6V LDO
ENA_BIAS
4.2V
FAULT
LODRV
+
V(SRP-SRN)
CHG_OCP
CHARGE
-
160% X IBAT_REG
2mA
REGN
+
GND
CHARGE
DISCHARGE
FAULT
IC Tj
+
145degC
-
BAT
104% X VBAT_REG
ISET
ISET
TSHUT
BAT_OVP
STATE
MACHINE
LOGIC
IBAT_ REG
ISET
10
LOWV
VFB
-
LOWV
VCC
+
1.55V +-
STAT
STAT
-
Safety Timer
+
8mA
+
BATTERY
DETECTION
LOGIC
PG
PG
DISCHARGE
VREF
ACOV
LTF
VACOV +-
+
TS
VFB
-
SUSPEND
HTF
RCHRG
+
-
+
2.05 V +RCHRG
10
-
bq24600
ISET
10
TERM
TERM
TCO
+
-
+
20xV(SRP-SRN)
TERMINATE CHARGE
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
bq24600
www.ti.com
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
7.3 Feature Description
7.3.1 Battery Voltage Regulation
The bq24600 uses a high-accuracy voltage band gap and regulator for the high-accuracy charging voltage. The
charge voltage is programmed via a resistor divider from the battery to ground, with the midpoint tied to the VFB
pin. The voltage at the VFB pin is regulated to 2.1 V, giving the following equation for the regulation voltage:
é R2 ù
VBAT = 2.1 V ´ ê1+
ú
ë R1 û
(1)
where R2 is connected from VFB to the battery and R1 is connected from VFB to GND.
7.3.2 Battery Current Regulation
The ISET input sets the maximum charging current. Battery current is sensed by resistor RSR connected between
SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a 10-mΩ sense
resistor, the maximum charging current is 10 A. The equation for charge current is:
VISET
ICHARGE =
20 ´ RSR
(2)
VISET, The input voltage range of ISET is between 0 and 2 V. The SRP and SRN pins are used to sense voltage
across RSR with default value of 10 mΩ. However, resistors of other values can also be used. A larger sense
resistor gives a larger sense voltage and a higher regulation accuracy, but at the expense of higher conduction
loss.
7.3.3 Precharge
On power up, if the battery voltage is below the VLOWV threshold, the bq24600 applies the precharge current to
the battery. This feature is intended to revive deeply discharged cells. If the VLOWV threshold is not reached within
30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins.
The precharge current is fixed 1/10th of the programmed charge current, which is determined by the voltage on
the ISET pin according to Equation 3:
I
VISET
IPRECHARGE = CHARGE =
10
200 ´ RSR
(3)
The minimum precharge current is clamped to be around 125 mA with default 10-mΩ sensing resistor.
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
11
bq24600
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
www.ti.com
Feature Description (continued)
Regulation Voltage
VRECH
Regulation Current
Fastcharge Current
Regulation Phase
Precharge
Current
Regulation
Phase
Fastcharge Voltage
Regulation Phase
Termination
Charge
Current
Charge
Voltage
VLOWV
IPRECH & ITERM
Precharge
Time
Fastcharge Safety Time
Figure 5. Typical Charging Profile
7.3.4 Charge Termination, Recharge, and Safety Timer
The bq24600 monitors the charging current during the voltage regulation phase. Termination is detected while
the voltage on the VFB pin is higher than the VRECH threshold AND the charge current is less than the ITERM
threshold, which is fixed at 1/10th of the programmed charge current, as calculated in Equation 4:
VISET
ITERM =
200 ´ RSR
(4)
As a safety backup, the bq24600 also provides an internal 5-hour safety timer for fast charge.
A
•
•
•
new charge cycle is initiated and safety timer is reset when one of the following conditions occurs:
The battery voltage falls below the recharge threshold
A power-on-reset (POR) event occurs
CE is toggled
7.3.5 Power Up
The bq24600 uses a SLEEP comparator to determine the source of power on the VCC pin, because VCC can be
supplied either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, bq24600 exits
the SLEEP mode. If all other conditions are met for charging, bq24600 then attempts to charge the battery (see
Enable and Disable Charging). If the SRN voltage is greater than VCC, bq24600 enters a low-quiescent-current
( VRECH
No
0.5s timer
expired
Yes
Yes
Disable 125mA
Charge
No
Battery Present,
Begin Charge
Battery Absent
Figure 8. Battery Detection Flowchart
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
17
bq24600
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
www.ti.com
Once the device has powered up, an 8-mA discharge current is applied to the SRN terminal. If the battery
voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is
turned on at low charge current (125 mA). If the battery voltage rises above the recharge threshold within 500
ms, no battery is present and the cycle restarts. If either the 500-ms or 1-second timer times out before the
respective thresholds are hit, a battery is detected and a charge cycle is initiated.
Battery not detected
VREG
VRECH
(VWAKE)
Battery
inserted
VLOWV
(VDISH)
Battery detected
t LOWV_DEG
t WAKE
tRECH_DEG
Figure 9. Battery-Detect Timing Diagram
Care must be taken that the total output capacitance at the battery node is not so large that the discharge current
source cannot pull the voltage below the LOWV threshold during the 1-second discharge time. The maximum
output capacitance can be calculated as shown in Equation 8.
´ tDISCH
I
CMAX = DISCH
é R ù
0.5 ´ ê1+ 2 ú
ë R1 û
(8)
Where CMAX is the maximum output capacitance, IDISCH is the discharge current, tDISCH is the discharge time, and
R2 and R1 are the voltage feedback resistors from the battery to the VFB pin. The 0.5 factor is the difference
between the RECHARGE and the LOWV thresholds at the VFB pin.
7.3.20.1 Example
For a 3-cell Li+ charger with R2 = 500 kΩ, R1 = 100kΩ (giving 12.6 V for voltage regulation), IDISCH = 8 mA,
tDISCH = 1 second,
8mA ´ 1sec
CMAX =
= 2.7mF
é 500 kW ù
0.5 ´ ê1+
ú
ë 100 kW û
(9)
Based on these calculations, no more than 2.7 mF should be allowed on the battery node for proper operation of
the battery-detection circuit.
18
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
bq24600
www.ti.com
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
7.4 Device Functional Modes
7.4.1 Converter Operation
The synchronous buck PWM converter uses a fixed-frequency voltage mode with a feed-forward control scheme.
A type-III compensation network allows using ceramic capacitors at the output of the converter. The
compensation input stage is connected internally between the feedback output (FBO) and the error amplifier
input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error
amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 17 kHz–25 kHz for the
bq24600, where the resonant frequency, fo, is given by Equation 10:
1
fo =
2p Lo Co
(10)
An internal sawtooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is 7% of the input adapter voltage, making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop
compensation. The ramp is offset by 300 mV in order to allow zero-percent duty cycle when the EAO signal is
below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to get a 100% dutycycle PWM request. Internal gate-drive logic allows achieving 99.5% duty cycle while ensuring the N-channel
upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below 4.2 V for
more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side n-channel power
MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver
returns to 100% duty-cycle operation until the (BTST–PH) voltage is detected to fall low again due to leakage
current discharging the BTST capacitor below 4.2 V, and the reset pulse is reissued.
The fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region.
7.4.2 Synchronous and Non-Synchronous Operation
The charger operates in synchronous mode when the SRP-SRN voltage is above 5 mV (0.5-A inductor current
for a 10-mΩ sense resistor). During synchronous mode, the internal gate-drive logic ensures there is breakbefore-make complementary switching to prevent shoot-through currents. During the 30-ns dead time where both
FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the low-side
FET turn on keeps the power dissipation low, and allows safely charging at high currents. During synchronous
mode, the inductor current is always flowing and the converter operates in continuous-conduction mode (CCM),
creating a fixed two-pole system.
The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5 mV (0.5-A inductor
current for a 10-mΩ sense resistor). The charger is forced into non-synchronous mode when battery voltage is
lower than 2 V or when the average SRP-SRN voltage is lower than 1.25 mV.
During non-synchronous operation, the body diode of the low-side MOSFET can conduct the positive inductor
current after the high-side n-channel power MOSFET turns off. When the load current decreases and the
inductor current drops to zero, the body diode is naturally turned off and the inductor current becomes
discontinuous. This mode is called discontinuous-conduction mode (DCM). During DCM, the low-side n-channel
power MOSFET turns on for around 80 ns when the bootstrap capacitor voltage drops below 4.2 V; then the lowside power MOSFET turns off and stays off until the beginning of the next cycle, where the high-side power
MOSFET is turned on again. The 80-ns low-side MOSFET on-time is required to ensure the bootstrap capacitor
is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important
for battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a voltage and
can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between high and
low-side MOSFETs) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80
ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring.
At very low currents during non-synchronous operation, there may be a small amount of negative inductor
current during the 80-ns recharge pulse. The charge should be low enough to be absorbed by the input
capacitance. Whenever the converter goes into zero-percent duty cycle, the high-side MOSFET does not turn on,
and the low-side MOSFET does not turn on (only 80-ns recharge pulse) either, and there is almost no discharge
from the battery.
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
19
bq24600
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
www.ti.com
Device Functional Modes (continued)
During the DCM mode, the loop response automatically changes and has a single-pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage.
POR
SLEEP MODE
VCC > SRN
No
Indicate SLEEP
Yes
Enable VREF LDO &
Chip Bias
Indicate battery
absent
Initiate battery
detect algorithm
Battery
present?
No
See Enabling and Disabling
Charge Section
Yes
Conditions met
for charge?
Indicate NOT
CHARGING,
Suspend timers
No
No
Conditions met
for charge?
No
Yes
Yes
Regulate
precharge current
VFB < VLOWV
Start 30 minute
precharge timer
Yes
Indicate ChargeIn-Progress
Start Fastcharge
timer
No
Indicate NOT
CHARGING,
Suspend timers
VFB < VLOWV
Yes
No
Regulate
fastcharge current
No
Conditions met
for charge?
Yes
Precharge
timer expired?
Yes
Indicate ChargeIn-Progress
No
Turn off charge,
Enable IDISCHG for 1
second
Yes
Indicate Charge In
Progress
VFB > VRECH
&
ICHG < ITERM
FAULT
Enable IFAULT
No
Fastcharge
Timer Expired?
Yes
Indicate FAULT
No
Charge Complete
VFB > VRECH
VFB < VRECH
No
Yes
Indicate DONE
Battery Removed
Yes
Indicate BATTERY
ABSENT
Figure 10. Operational Flowchart for bq24600
20
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
bq24600
www.ti.com
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The evaluation module (EVM) is a complete charger module for evaluating a stand-alone single multi-cell Li-ion
charger using the bq241600 device.
8.2 Typical Application
The typical application shown is a 28-V input, 5-cell Li-ion, 3-A charger.
ADAPTER +
D2
MBRS540T3
VREF
HIDRV
VCC
C7
1 µF
R7
100 kW
PH
R8
22.1 kW
REGN
VREF
D1
BAT54
C6
0.1 µF
C5
1 µF
C4
1 µF
bq24600
R13 10 kW
D3
LODRV
STAT
GND
R14 10 kW
D4
PG
TS
R10
430 kW
PACK+
PACK-
C13
C12
10 µF* 10 µF*
C10
0.1 µF
C11
0.1 µF
R2
900 kW
Cff
22 pF
R1
100 kW
SRN
R5
100 W
VBAT
3.3 µH*
SRP
VREF
R9
9.31 kW
RSR
0.010 Ω
Q5
SiR426
CE
ADAPTER +
Q4
SiR426
L1
BTST
ISET
Pack
Thermistor
Sense
C9
10 µF
N
C2
2.2 µF
C8
10 µF
R6
10 W
N
R11
2 kW
ADAPTER -
VFB
PwrPad
0.1 μF
VIN = 28 V, BAT = 5-cell Li-Ion, Icharge = 3 A, Ipre-charge = Iterm = 0.3 A
Figure 11. Typical Application Circuit
8.2.1 Design Requirements
For this design example, use the parameters shown in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
Input voltage
28 V
Battery Charge Voltage
21 V
Battery Charge Current
3A
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
21
bq24600
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
www.ti.com
Table 4. Supporting Components for Figure 11
PART DESIGNATOR
QTY
DESCRIPTION
Q4, Q5
2
N-channel MOSFET, 40 V, 30 A, PowerPAK SO-8, Vishay-Siliconix, SiR426DN
D1
1
Diode, dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C
D2
1
Schottky diode, 40V, 5A, SMC, ON Semiconductor, MBRS540T3
RSR
2
Sense resistor, 10 mΩ, 1%, 1 W, 2010, Vishay-Dale, WSL2010R0100F
L1
1
Inductor, 3.3 μH, 5.5 A, Vishay-Dale, IHLP2525CZ
C8, C9, C12, C13
4
Capacitor, ceramic, 10 μF, 35 V, 10%, X7R
C2
1
Capacitor, ceramic, 2.2µF, 50 V, 10%, X7R
C4, C5
2
Capacitor, ceramic, 1 μF, 16V, 10%, X7R
C7
1
Capacitor, ceramic, 1µF, 50 V, 10%, X7R
C1, C6, C11
4
Capacitor, ceramic, 0.1 μF, 16 V, 10%, X7R
Cff
1
Capacitor, ceramic, 22 pF, 35 V, 10%, X7R
C10
1
Capacitor, ceramic, 0.1 μF, 50V, 10%
R1, R7
2
Resistor, chip, 100 kΩ, 1/16W, 0.5%
R2
1
Resistor, chip, 900 kΩ, 1/16W, 0.5%
R8
1
Resistor, chip, 22.1 kΩ, 1/16W, 0.5%
R9
1
Resistor, chip, 9.31 kΩ, 1/16W, 1%
R10
1
Resistor, chip, 430 kΩ, 1/16W, 1%
R11
1
Resistor, chip, 2Ω, 1W, 5%
R13, R14
2
Resistor, chip, 10 kΩ, 1/16W, 5%
R5
1
Resistor, chip, 100 Ω, 1/16W, 0.5%
R6
1
Resistor, chip, 10 Ω, 1W, 5%
D3, D4
2
LED diode, green, 2.1 V, 20 mA, LTST-C190GKT
22
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
bq24600
www.ti.com
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
8.2.2 Detailed Design Procedure
8.2.2.1 Inductor Selection
The bq24600 has a 1.2-MHz switching frequency to allow the use of small inductor and capacitor values.
Inductor saturation current should be higher than the charging current (ICHARGE) plus half the ripple current
(IRIPPLE):
ISAT ³ ICHG + (1/2) IRIPPLE
(11)
The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fs) and
inductance (L):
V ´ D ´ (1 - D)
IRIPPLE = IN
fS ´ L
(12)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging
voltage range is from 9 V to 12.6 V for a 3-cell battery pack. For a 20-V adapter voltage, 10-V battery voltage
gives the maximum inductor ripple current. Another example is a 4-cell battery, for which the battery voltage
range is from 12 V to 16.8 V, and 12-V battery voltage gives the maximum inductor ripple current.
Usually, inductor ripple is designed in the range of 20%–40% of maximum charging current as a trade-off
between inductor size and efficiency for a practical design.
The bq24600 has cycle-by-cycle charge undercurrent protection (UCP) by monitoring the charging-currentsensing resistor to prevent negative inductor current. The typical UCP threshold is 5 mV falling edge,
corresponding to 0.5-A falling edge for a 10-mΩ charging-current-sensing resistor.
8.2.2.2 Input Capacitor
The input capacitor should have enough ripple-current rating to absorb the input switching-ripple current. The
worst-case rms ripple current is half of the charging current when the duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst-case capacitor rms current ICIN occurs where the duty cycle is closest
to 50% and can be estimated by the following equation:
ICIN = ICHG ´
D ´ (1 - D)
(13)
8.2.2.3 Output Capacitor
A low-ESR ceramic capacitor such as X7R or X5R is preferred for the input decoupling capacitor and should be
placed near the drain of the high-side MOSFET and the source of the low-side MOSFET as close as possible.
The voltage rating of the capacitor must be higher than the normal input voltage level. A 25-V rating or higher
capacitor is preferred for a 20-V input voltage. A 10-µF to 20-µF capacitance is suggested for typical of 3-A to 4A charging current.
The output capacitor also should have enough ripple-current rating to absorb the output switching ripple current.
The output capacitor rms current ICOUT is given:
I
ICOUT = RIPPLE » 0.29 ´ IRIPPLE
2 ´ 3
(14)
The output capacitor voltage ripple can be calculated as follows:
DVo =
1
8LCfs2
æ
V 2
ç VBAT - BAT
ç
VIN
è
ö
÷
÷
ø
(15)
At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The bq24600 has an internal loop compensator. To get good loop stability, the resonant frequency of the output
inductor and output capacitor should be designed between 17 kHz and 25 kHz. The preferred ceramic capacitor
for a 4-cell application has a 25-V or higher rating and X7R or X5R dielectric.
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
23
bq24600
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
www.ti.com
8.2.2.4 Power MOSFET Selection
Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6 V of gate drive voltage. 30-V or higher voltage rating MOSFETs are
preferred for 20-V input voltage, and 40-V or higher rating MOSFETs are preferred for 20-V to 28-V input
voltage.
Figure-of-merit (FOM) is usually used for selecting the proper MOSFET based on a tradeoff between the
conduction loss and switching loss. For a top-side MOSFET, FOM is defined as the product of a MOSFET onresistance, rDS(on), and the gate-to-drain charge, QGD. For a bottom-side MOSFET, FOM is defined as the product
of the MOSFET on-resistance, rDS(on), and the total gate charge, QG.
FOM top = RDS(on) ´ QG D
FOMbottom = RDS(on) ´ QG
(16)
The lower the FOM value, the lower the total power loss. Usually lower rDS(on) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D =
VOUT/VIN), charging current (ICHARGE), the MOSFET on-resistance rDS(on)), input voltage (VIN), switching frequency
(fS), turnon time (ton) and turnoff time (ttoff):
1
Ptop = D ´ ICHG2 ´ RDS(on) +
´ VIN ´ ICHG ´ (t on + t off ) ´ fS
2
(17)
The first item represents the conduction loss. Usually, MOSFET rDS(on) increases by 50% with a 100ºC junctiontemperature rise. The second term represents the switching loss. The MOSFET turnon and turnoff times are
given by:
Q
Q
ton = SW , t off = SW
Ion
Ioff
(18)
where Qsw is the switching charge, Ion is the turnon gate-drive current and Ioff is the turnoff gate-drive current. If
the switching charge is not given in the MOSFET data sheet, it can be estimated by gate-to-drain charge (QGD)
and gate-to-source charge (QGS):
1
QSW = QGD +
´ QGS
2
(19)
Total gate-drive current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on
gate resistance (Ron) and turn-off gate resistance Roff) of the gate driver:
VREG N - Vplt
Vplt
Ion =
, Ioff =
Ron
Roff
(20)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous-conduction mode:
Pbottom = (1 - D) ´ ICHG 2 ´ RDS(on)
(21)
If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into non-synchronous mode when the
average SRP-SRN voltage is lower than 1.25 mV), the low side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current.
As a result, all the freewheeling current goes through the body diode of the bottom-side MOSFET. The maximum
charging current in non-synchronous mode can be up to 0.9 A (0.5 A typ.) for a 10-mΩ charging-current sensing
resistor considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or body
diode capable of carrying the maximum non-synchronous-mode charging current.
MOSFET gate driver power loss contributes to the dominant losses on the controller IC when the buck converter
is switching. Choosing a MOSFET with a small Qg_total largely reduces the IC power loss to avoid thermal
shutdown.
PICLoss_driver = VIN × Qg_total × fs
(22)
where Qg_total is the total gate charge for both upper and lower MOSFETs at 6-V VREGN.
24
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
bq24600
www.ti.com
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
8.2.2.5 Input Filter Design
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a secondorder system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and damage IC.
The input filter must be carefully designed and tested to prevent an overvoltage event on the VCC pin.
There are several methods for damping or limiting the overvoltage spike during adapter hot plug-in. An
electrolytic capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC
maximum pin voltage rating. A high-current-capability TVS Zener diode can also limit the overvoltage level to an
IC-safe level. However these two solutions may not have low cost or small size.
A cost-effective and small-size solution is shown in Figure 12. R1 and C1 comprise a damping RC network to
damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used for
reverse voltage protection for the VCC pin (it can be the input Schottky diode or the body diode of input ACFET).
C2 is the VCC pin decoupling capacitor and it should be placed as close as possible to the VCC pin. R2 and C2
form a damping RC network to further protect the IC from high dv/dt and high-voltage spikes. The C2 value
should be less than the C1 value so R1 can be dominant over the ESR of C1 to get enough damping effect for
hot plug-in. The R1 and R2 packages must be sized to handle inrush-current power loss according to resistor
manufacturer’s datasheet. The filter component values must always be verified with the real application and
minor adjustments may be needed to fit in the real application circuit.
D1
Adapter
connector
R1
2W
C1
2.2 mF
(2010)
R2 (1206)
4.7 -30W
VCC pin
C2
0.1-1 mF
Figure 12. Input Filter
10 V/div
20 V/div 20 V/div
8.2.3 Application Curves
CE
5 V/div
2 A/div
IBAT
PH
HIDRV
LODRV
2 A/div
5 V/div
LODRV
5 V/div
PH
IL
t − Time = 4 ms/div
t − Time = 40 ns/div
CE = 1
Figure 13. Current Soft-Start
Figure 14. Continuous-Conduction-Mode Switching
Waveforms
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
25
bq24600
www.ti.com
10 V/div
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
5 V/div
PH
2 A/div
2 A/div 5 V/div
5 V/div
PH
LODRV
IL
VBAT
IL
t − Time = 40 ns/div
t − Time = 200 ms/div
Figure 15. Cycle-by-Cycle Synchronous to
Nonsynchronous
Figure 16. Battery Insertion
105
Efficiency - %
100
28 Vin, 6 cell
24 Vin, 5 cell
95
90
20 Vin, 4 cell
20 Vin, 3 cell
85
12 Vin, 2 cell
12 Vin, 1 cell
80
0
1
2
5
4
3
IBAT - Output Current - A
7
6
8
Figure 17. Efficiency vs Output Current
9 Power Supply Recommendations
The bq24600 requires a voltage source between 5 V and 28 V connected to VCC. and VCC can be supplied
either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, bq24600 exits the
SLEEP mode. If the SRN voltage is greater than VCC, bq24600 enters a low-quiescent current (< 15 µA) SLEEP
mode to minimize current drain from the battery.
26
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
bq24600
www.ti.com
10
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
Layout
10.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high-frequency current-path loop (see Figure 19) is important to prevent electrical and
magnetic field radiation and high-frequency resonant problems. Here is a PCB priority list for proper layout.
Layout of the PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to switching the MOSFET supply and ground connections, and
use the shortest possibloe copper trace connection. These parts should be placed on the same layer of PCB
instead of on different layers, using vias to make this connection.
2. The IC should be placed close to the switching MOSFET gate terminals to keep the gate-drive signal traces
short for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching
MOSFET.
3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging-current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 18 for Kelvin connection for
best current accuracy). Place the decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Route the analog ground separately from the power ground and use a single ground connection to tie the
charger power ground to the charger analog ground. Just beneath the IC, use copper pour for analog
ground, but avoid the power pins to reduce inductive and capacitive noise coupling. Connect the analog
ground to GND. Connect the analog ground and power ground together using the thermal pad as the single
ground connection point. Or use a 0-Ω resistor to tie the analog ground to power ground (the thermal pad
should tie to analog ground in this case). A star connection under the thermal pad is highly recommended.
8. It is critical that the exposed thermal pad on the back side of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC connecting to the ground plane on the other
layers.
9. Place decoupling capacitors next to the IC pins, and make trace connections as short as possible.
10. All via sizes and numbers should be enough for a given current path.
See the EVM design (SLUU410) for the recommended component placement with trace and via locations.
For QFN information, see SCBA017 and SLUA271.
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
27
bq24600
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
www.ti.com
10.2 Layout Example
Current Direction
R SNS
Current Sensing Direction
To SRP - SRN pin
Figure 18. Sensing Resistor PCB Layout
SW
L1
V BAT
R1
High
Frequency
VIN
BAT
Current
C1
Path
PGND
C2
C3
Figure 19. High Frequency Current Path
28
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
bq24600
www.ti.com
SLUS891B – FEBRUARY 2010 – REVISED NOVEMBER 2014
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: bq24600
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ24600RVAR
ACTIVE
VQFN
RVA
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OAQ
BQ24600RVAT
ACTIVE
VQFN
RVA
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OAQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
