BQ24725RGRR

bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 2-4 Cell Li+ Battery SMBus Charge Controller with N-Channel Power MOSFET Selector and Advanced Circuit Protection Check for Samples: bq24725 FEATURES 1 APPLICATIONS • • • • • Portable Notebook Computers, UMPC, UltraThin Notebook, and Netbook Personal Digital Assistant Handheld Terminal Industrial and Medical Equipment Portable Equipment BTST REGN 20 19 18 17 16 ACN 1 15 LODRV ACP 2 14 GND CMSRC 3 13 SRP ACDRV 4 12 SRN ACOK 5 11 BATDRV bq24725 6 7 8 9 10 ILIM • • • The bq24725 charges two, three or four series Li+ cells, and is available in a 20-pin, 3.5 x 3.5 mm2 QFN package. SCL • • • The bq24725 uses internal input current register or external ILIM pin to throttle down PWM modulation to reduce the charge current. HIDRV • SMBus controlled input current, charge current, and charge voltage DACs allow for high regulation accuracies that can be programmed by the system power management micro-controller. SDA • The bq24725 uses two charge pumps to separately drive n-channel MOSFETs (ACFET, RBFET and BATFET) for automatic system power source selection. PHASE • The bq24725 is a high-efficiency, synchronous battery charger, offering low component count for space-constraint, multi-chemistry battery charging applications. IOUT • DESCRIPTION VCC • SMBus Host-Controlled NMOS-NMOS Synchronous Buck Converter with Programmable 615kHz, 750kHz, and 885kHz Switching Frequencies Automatic N-channel MOSFET Selection of System Power Source from Adapter or Battery Driven by Internal Charge Pumps Enhanced Safety Features for Over Voltage Protection, Over Current Protection, Battery, Inductor and MOSFET Short Circuit Protection Programmable Input Current, Charge Voltage, Charge Current Limits – ±0.5% Charge Voltage Accuracy up to 19.2V – ±3% Charge Current Accuracy up to 8.128A – ±3% Input Current Accuracy up to 8.064A – ±2% 20x Adapter Current or Charge Current Amplifier Output Accuracy Programmable Battery Depletion Threshold, and Battery LERAN Function Programmable Adapter Detection and Indicator Integrated Soft Start Integrated Loop Compensation Real Time System Control on ILIM pin to Limit Charge Current AC Adapter Operating Range 9V-24V 5µA Off-State Battery Discharge Current 20-pin 3.5 x 3.5 mm2 QFN Package ACDET • 2 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DEVICE INFORMATION Reverse Input Protection Adapter + Adapter - Q6 BSS138W R12 1M R13 3.01M Q1 (ACFET) FDS6680A C17 2200pF Ri 2? Ci 2.2µF D2 BAT54C Q2 (RBFET) FDS6680A RAC 10m? C16 0.1µF C1 0.1µF SYSTEM Total Csys 220µF R9 10Ω C3 0.1µF C2 0.1µF R10 4.02k U2 IMD2A EN C5 1µF ACN VCC ACP BATDRV R6 4.02k R11 4.02k CMSRC Q5 (BATFET) FDS6680A C15 0.01µF C6 1µF REGN ACDRV R1 430k BTST D1 BAT54 C8 10uF ACDET R2 66.5k HIDRV R8 100k ILIM R7 316k +3.3V HOST R3 10k R4 10k U1 bq24725 R5 10k C7 0.047µF Q3 Sis412DN C9 10uF RSR 10m? Pack + PHASE L1 4.7µH Q4 Sis412DN LODRV C10 10µF SDA SMBus C11 10µF Pack - GND SCL SRP Dig I/O ACOK ADC Dig I/O IOUT EN PowerPad R14 10Ω * R15 7.5Ω * C13 0.1µF SRN C4 100p C14 0.1µF Fs = 750kHz, IADPT = 4.096A, ICHRG = 2.944A, ILIM = 4A, VCHRG = 12.592V, 90W adapter and 3S2P battery pack See the application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection. Figure 1. Typical System Schematic with Two NMOS Selector 2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 D3 PDS1040 Adapter + Adapter - Q1 (ACFET) FDS6680A C17 2200pF Ri 2? Ci 2.2µF RAC 10m? SYSTEM C16 0.1µF C1 0.1µF C3 0.1µF C2 0.1µF R10 4.02k Total Csys 220µF R9 10Ω C5 1µF ACN VCC ACP BATDRV R6 4.02k R11 4.02k CMSRC Q5 (BATFET) FDS6680A C15 0.01µF C6 1µF REGN D1 BAT54 ACDRV R1 430k BTST R2 66.5k HIDRV R8 100k ILIM R7 549k +3.3V HOST R3 10k R4 10k U1 bq24725 R5 10k C7 0.047µF C9 10uF C8 10uF ACDET Q3 Sis412DN RSR 10m? Pack + PHASE L1 4.7µH C10 10µF Q4 Sis412DN LODRV C11 10µF Pack - SDA SMBus GND SCL SRP Dig I/O ACOK ADC IOUT PowerPad R14 10Ω * R15 7.5Ω * C13 0.1µF SRN C4 100p C14 0.1µF Fs = 750kHz, IADPT = 2.688A, ICHRG = 1.984A, ILIM = 2.54A, VCHRG = 12.592V, 65W adapter and 3S2P battery pack See the application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection. Figure 2. Typical System Schematic with One NMOS Selector and Schottky Diode ORDERING INFORMATION PART NUMBER IC MARKING PACKAGE bq24725 BQ725 20-PIN 3.5 x 3.5mm2 QFN ORDERING NUMBER (Tape and Reel) QUANTITY bq24725RGRR 3000 bq24725RGRT 250 THERMAL INFORMATION THERMAL METRIC (1) θJA Junction-to-ambient thermal resistance (2) ψJT Junction-to-top characterization parameter (3) ψJB (1) (2) (3) (4) Junction-to-board characterization parameter bq24725 RGR (20 PIN) UNITS 46.8 0.6 (4) °C/W 15.3 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 3 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE SRN, SRP, ACN, ACP, CMSRC, VCC Voltage range Maximum difference voltage UNIT –0.3 to 30 PHASE –2 to 30 ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK –0.3 to 7 BTST, HIDRV, ACDRV, BATDRV –0.3 to 36 SRP–SRN, ACP–ACN V –0.5 to 0.5 Junction temperature range, TJ –40 to 155 °C Storage temperature range, Tstg –55 to 155 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) SRN, SRP, ACN, ACP, CMSRC, VCC PHASE Voltage range Maximum difference voltage MIN NOM MAX 0 24 -2 24 ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK 0 6.5 BTST, HIDRV, ACDRV, BATDRV 0 30 SRP–SRN, ACP–ACN Junction temperature range, TJ Storage temperature range, Tstg UNIT V –0.2 0.2 V 0 125 °C –55 150 °C ELECTRICAL CHARACTERISTICS 4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING CONDITIONS VVCC_OP VCC Input voltage operating range 4.5 24 V 19.2 V 16.884 V CHARGE VOLTAGE REGULATION VBAT_REG_RNG BAT voltage regulation range 1.024 ChargeVoltage() = 0x41A0H VBAT_REG_ACC Charge Voltage Regulation Accuracy ChargeVoltage() = 0x3130H ChargeVoltage() = 0x20D0H 4 Submit Documentation Feedback 16.716 16.8 -0.5% 12.529 0.5% 12.592 –0.5% 8.35 –0.6% 12.655 V 0.5% 8.4 8.45 V 0.6% Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) 4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 81.28 mV 4219 mA CHARGE CURRENT REGULATION VIREG_CHG_RNG Charge Current Regulation Differential Voltage Range VIREG_CHG = VSRP - VSRN 0 3973 ChargeCurrent() = 0x1000H 1946 ChargeCurrent() = 0x0800H ICHRG_REG_ACC Charge Current Regulation Accuracy 10mΩ current sensing resistor 4096 –3% 3% 2048 –5% 410 ChargeCurrent() = 0x0200H 172 512 64 614 mA 20% 256 –33% ChargeCurrent() = 0x0080H mA 5% –20% ChargeCurrent() = 0x0100H 2150 340 mA 33% 128 192 mA –50% 50% 0 80.64 mV 4219 mA INPUT CURRENT REGULATION VIREG_DPM_RNG Input current regulation differential voltage range VIREG_DPM = VACP – VACN 3973 InputCurrent() = 0x1000H 1946 InputCurrent() = 0x0800H IDPM_REG_ACC 4096 –3% 3% 2048 –5% Input current regulation accuracy 10mΩ current sensing resistor 870 InputCurrent() = 0x0400H 384 mA 5% 1024 –15% InputCurrent() = 0x0200H 2150 1178 mA 15% 512 –25% 640 mA 25% INPUT CURRENT OR CHARGE CURRENT SENSE AMPLIFIER VACP/N_OP Input common mode range Voltage on ACP/ACN 4.5 24 V VSRP/N_OP Output Common Mode Range Voltage on SRP/SRN 0 19.2 V VIOUT IOUT Output Voltage Range 0 1.6 IIOUT IOUT Output Current 0 1 AIOUT Current Sense Amplifier Gain V(ICOUT)/V(SRP-SRN) or V(ACP-ACN) 20 V(SRP-SRN) or V(ACP-ACN) = 40.96mV VIOUT_ACC CIOUT_MAX Current Sense Output Accuracy Maximum Output Load Capacitance –2% V mA V/V 2% V(SRP-SRN) or V(ACP-ACN) = 20.48mV –4% 4% V(SRP-SRN) or V(ACP-ACN) = 10.24mV –15% 15% V(SRP-SRN) or V(ACP-ACN) = 5.12mV –20% 20% V(SRP-SRN) or V(ACP-ACN) = 2.56mV –33% 33% V(SRP-SRN) or V(ACP-ACN) = 1.28mV –50% 50% For stability with 0 to 1mA load 100 pF 6.5 V REGN REGULATOR VREGN_REG IREGN_LIM CREGN REGN regulator voltage REGN current limit VVCC > 6.5V, VACDET > 0.6V (0-55mA load) 5.5 6 VREGN = 0V, VVCC > UVLO charge enabled and not in TSHUT 65 80 7 16 VREGN = 0V, VVCC > UVLO charge disabled or in TSHUT REGN Output Capacitor Required for Stability ILOAD = 100µA to 65mA mA mA 1 µF INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO) UVLO Under voltage rising threshold VVCC rising Under voltage hysteresis, falling VVCC falling 3.5 3.75 4 340 V mV Fast DPM comparator (FAST_DPM) VFAST_DPM Fast DPM comparator stop charging rising threshold with respect to input current limit, voltage across input sense resistor rising edge (Specified by design) 108% Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 5 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) 4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT QUIESCENT CURRENT IBAT_BATFET_OFF Battery BATFET OFF STATE Current, BATFET off, ISRP + ISRN + IPHASE + IACP + IACN VVBAT = 16.8V, VCC disconnect from battery, BATFET charge pump off, BATFET turns off, TJ = 0 to 85°C IBAT_BATFET_ON Battery BATFET ON STATE Current, BATFET on, ISRP + ISRN + IPHASE + IVCC + IACP + IACN VVBAT = 16.8V, VCC connect from battery, BATFET charge pump on, BATFET turns on, TJ = 0 to 85°C ISTANDBY Standby quiescent current, IVCC + IACP + IACN VVCC > UVLO, VACDET > 0.6V, charge disabled, TJ = 0 to 85°C IAC_NOSW Adapter bias current during charge, IVCC + IACP + IACN IAC_SW Adapter bias current during charge, IVCC + IACP + IACN 5 µA 20 µA 0.5 1 mA VVCC > UVLO, 2.4V < VACDET < 3.15V, charge enabled, no switching, TJ = 0 to 85°C 1.5 3 mA VVCC > UVLO, 2.4V < VACDET < 3.15V, charge enabled, switching, MOSFET Sis412DN 10 mA ACOK COMPARATOR VACOK_RISE ACOK rising threshold VVCC > UVLO, VACDET rising 2.376 2.4 2.424 VACOK_FALL_HYS ACOK falling hysteresis VVCC> UVLO, VACDET falling 35 55 75 mV VVCC> UVLO, VACDET rising above 2.4V, First time OR ChargeOption() bit [15] = 0 (Default) 100 150 200 ms VVCC> UVLO, VACDET rising above 2.4V, (NOT First time) AND ChargeOption() bit [15] = 1 0.9 1.3 1.7 s 0.57 0.8 V VACOK_RISE_DEG ACOK rising deglitch (Specified by design) VWAKEUP_RISE WAKEUP detect rising threshold VVCC> UVLO, VACDET rising VWAKEUP_FALL WAKEUP detect falling threshold VVCC> UVLO, VACDET falling 0.3 0.51 V V VCC to SRN COMPARATOR (VCC_SRN) VVCC-SRN_FALL VCC-SRN falling threshold VVCC falling towards VSRN 70 125 180 mV VVCC-SRN VCC-SRN rising hysteresis VVCC rising above VSRN 100 150 200 mV 120 200 280 mV 40 80 120 mV ChargeOption() bit [8:7] = 00 200 300 450 ChargeOption() bit [8:7] = 01 330 500 700 ChargeOption() bit [8:7] = 10 (Default) 450 700 1000 ChargeOption() bit [8:7] = 11 600 900 1250 40 110 160 _RHYS ACN to SRN COMPARATOR (ACN_SRN) VACN-SRN_FALL ACN to BAT falling threshold VACN falling towards VSRN VACN-SRN_RHYS ACN to BAT rising hysteresis VACN rising above VSRN HIGH SIDE IFAULT COMPARATOR (IFAULT_HI) (1) VIFAULT_HI_RISE ACP to PHASE rising threshold mV LOW SIDE IFAULT COMPARATOR (IFAULT_LOW) VIFAULT_LOW_RISE PHASE to GND rising threshold mV INPUT OVER VOLTAGE COMPARATOR (ACOV) VACOV ACDET over voltage rising threshold VACDET rising 3.05 3.15 3.25 V VACOV_HYS ACDET over voltage falling hysteresis VACDET falling 50 75 100 mV INPUT OVER CURRENT COMPARATOR (ACOC) (1) Adapter over current rising threshold with respect to input current limit, voltage across input sense resistor rising edge ChargeOption() bit [2:1] = 01 120% 133% 145% ChargeOption() bit [2:1] = 10 (Default) 150% 166% 180% ChargeOption() bit [2:1] = 11 200% 222% 240% VACOC_min Min ACOC threshold clamp voltage ChargeOption() Bit [2:1] = 01 (133%), InputCurrent () = 0x0400H (10.24mV) 40 45 50 mV VACOC_max Max ACOC threshold clamp voltage ChargeOption() Bit [2:1] = 11 (222%), InputCurrent () = 0x1F80H (80.64mV) 140 150 160 mV tACOC_DEG ACOC deglitch time (Specified by design) Voltage across input sense resistor rising to disable charge 1.7 2.5 3.3 ms 103% 104% 106% VACOC BAT OVER VOLTAGE COMPARATOR (BAT_OVP) VOVP_RISE Over voltage rising threshold as percentage of VBAT_REG VSRN rising VOVP_FALL Over voltage falling threshold as percentage of VBAT_REG VSRN falling (1) 6 102% User can adjust threshold via SMBus ChargeOption() REG0x12. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) 4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ChargeCurrent()=0x0xxxH 54 60 66 ChargeCurrent()=0x1000H – 0x17C0H 80 90 100 mV ChargeCurrent()=0x1800 H– 0x1FC0H 110 120 130 mV 1 5 9 mV CHARGE OVER CURRENT COMPARATOR (CHG_OCP) VOCP_RISE Charge over current rising threshold, measure voltage drop across current sensing resistor mV CHARGE UNDER CURRENT COMPARATOR (CHG_UCP) VUCP_FALL Charge undercurrent falling threshold VSRP falling towards VSRN LIGHT LOAD COMPARATOR (LIGHT_LOAD) VLL_FALL Light load falling threshold VLL_RISE_HYST Light load rising hysteresis Measure the voltage drop across current sensing resistor 1.25 mV 1.25 mV BATTERY DEPLETION COMPARATOR (BAT_DEPL) [1] VBATDEPL_FALL VBATDEPL_RHYST tBATDEPL_RDEG ChargeOption() bit [12:11] Battery Depletion Falling Threshold, ChargeOption() bit [12:11] percentage of voltage regulation limit, VSRN ChargeOption() bit [12:11] falling ChargeOption() bit [12:11] Battery Depletion Rising Hysteresis, VSRN rising Battery Depletion Rising Deglitch (Specified by design) = 00 55.53% 59.19% 62.84% = 01 58.68% 62.65% 66.62% = 10 62.17% 66.55% 70.93% = 11 (Default) 66.06% 70.97% 75.88% ChargeOption() bit [12:11] = 00 225 305 385 mV ChargeOption() bit [12:11] = 01 240 325 410 mV ChargeOption() bit [12:11] = 10 255 345 435 mV ChargeOption() bit [12:11] = 11 (Default) 280 370 460 mV Delay to turn off ACFET and turn on BATFET during LEARN cycle 600 ms BATTERY LOWV COMPARATOR (BAT_LOWV) VBATLV_FALL Battery LOWV falling threshold VSRN falling VBATLV_RHYST Battery LOWV rising hysteresis VSRN rising 2.4 200 2.5 2.6 mV V IBATLV Battery LOWV charge current limit 10 mΩ current sensing resistor 0.5 A THERMAL SHUTDOWN COMPARATOR (TSHUT) TSHUT Thermal shutdown rising temperature Temperature rising 155 °C TSHUT_HYS Thermal shutdown hysteresis, falling Temperature falling 20 °C ILIM COMPARATOR VILIM_FALL ILIM as CE falling threshold VILIM falling 60 75 90 mV VILIM_RISE ILIM as CE rising threshold VILIM rising 90 105 120 mV 0.8 V 1 μA LOGIC INPUT (SDA, SCL) VIN_ LO Input low threshold VIN_ HI Input high threshold IIN_ LEAK Input bias current 2.1 V=7V V –1 LOGIC OUTPUT OPEN DRAIN (ACOK, SDA) VOUT_ LO Output saturation voltage 5 mA drain current 500 mV IOUT_ LEAK Leakage current V=7V –1 1 μA Input bias current V=7V –1 1 μA FSW PWM switching frequency ChargeOption () bit [9] = 0 (Default) 600 750 900 kHz FSW+ PWM increase frequency ChargeOption() bit [10:9] = 11 665 885 1100 kHz FSW– PWM decrease frequency ChargeOption() bit [10:9] = 01 465 615 765 kHz 40 60 VBATDRV - VSRN when VSRN > UVLO 5.5 6.1 ANALOG INPUT (ACDET, ILIM) IIN_ LEAK PWM OSCILLATOR BATFET GATE DRIVER (BATDRV) IBATFET BATDRV charge pump current limit VBATFET Gate drive voltage on BATFET RBATDRV_LOAD Minimum load resistance between BATDRV and SRN RBATDRV_OFF BATDRV turn-off resistance µA 6.5 500 I = 30µA 5 kΩ 6.2 7.4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 V kΩ 7 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) 4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ACFET GATE DRIVER (ACDRV) IACFET ACDRV charge pump current limit VACFET Gate drive voltage on ACFET RACDRV_LOAD Minimum load resistance between ACDRV and CMSRC RACDRV_OFF ACDRV turn-off resistance VACFET_LOW ACDRV Turn-Off when Vgs voltage is low (Specified by design) VACDRV–VCMSRC when VVCC> UVLO 40 60 5.5 6.1 μA 6.5 500 I = 30µA 5 V kΩ 6.2 7.4 5.9 kΩ V PWM HIGH SIDE DRIVER (HIDRV) RDS(on) VBTST_REFRESH High side driver (HSD) turn-on resistance VBTST – VPH = 5.5 V, I = 10mA 12 20 Ω High side driver turn-off resistance VBTST – VPH = 5.5 V, I = 10mA 0.65 1.3 Ω Bootstrap refresh comparator threshold voltage VBTST – VPH when low side refresh pulse is requested 4.3 4.7 V 3.85 PWM LOW SIDE DRIVER (LODRV) RDS(on) Low side driver (LSD) turn-on resistance VREGN = 6 V, I = 10 mA 15 25 Ω Low side driver turn-off resistance VREGN = 6 V, I = 10 mA 0.9 1.4 Ω PWM DRIVER TIMING tLOW_HIGH Driver dead time from low side to high side 20 ns tHIGH_LOW Driver dead time from high side to low side 20 ns 64 mA 240 μs INTERNAL SOFT START ISTEP Soft start current step tSTEP Soft start current step time In CCM mode 10mΩ current sensing resistor SMBus TIMING CHARACTERISTICS 1 μs tR SCLK/SDATA rise time tF SCLK/SDATA fall time tW(H) SCLK pulse width high 4 tW(L) SCLK Pulse Width Low 4.7 μs tSU(STA) Setup time for START condition 4.7 μs tH(STA) START condition hold time after which first clock pulse is generated 4 μs tSU(DAT) Data setup time 250 ns tH(DAT) Data hold time 300 ns tSU(STOP) Setup time for STOP condition 4 µs t(BUF) Bus free time between START and STOP condition 4.7 FS(CL) Clock Frequency 10 100 kHz 35 ms 300 ns 50 μs μs HOST COMMUNICATION FAILURE ttimeout SMBus bus release timeout (2) 25 tBOOT Deglitch for watchdog reset signal 10 Watchdog timeout period, ChargeOption() bit [14:13] = 01 (3) 35 44 53 s Watchdog timeout period, ChargeOption() bit [14:13] = 10 (3) 70 88 105 s Watchdog timeout period, ChargeOption() bit [14:13] = 11 (3) (Default) 140 175 210 s tWDI (2) (3) 8 ms Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms). User can adjust threshold via SMBus ChargeOption() REG0x12. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 Figure 3. SMBus Communication Timing Waveforms Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 9 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS Table 1. Table of Graphs FIGURE NO. Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 VCC, ACDET, REGN and ACOK Power up Charge Enable by ILIM Current Soft-start Charge Disable by ILIM Continuous Conduction Mode Switching Waveforms Cycle-by-Cycle Synchronous to Non-synchronous 100% Duty and Refresh Pulse System Load Transient (Input DPM) Battery Insertion Battery to Ground Short Protection Battery to Ground Short Transition Efficiency vs Output Current SPACER SPACER CH1: VCC, 10V/div, CH2: ACDET, 2V/div, CH3: ACOK, 5V/div, CH4: REGN, 5V/div, 40ms/div Figure 4. VCC, ACDET, REGN and ACOK Power Up CH1: Vin, 10V/div, CH2: LODRV, 5V/div, CH3: PHASE, 10V/div, CH4: inductor current, 2A/div, 2ms/div Figure 6. Current Soft-Start 10 CH1: ILIM, 1V/div, CH4: inductor current, 1A/div, 20ms/div Figure 5. Charge Enable by ILIM CH1: ILIM, 1V/div, CH4: inductor current, 1A/div, 4us/div Submit Documentation Feedback Figure 7. Charge Disable by ILIM Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 CH1: HIDRV, 10V/div, CH2: LODRV, 5V/div, CH3: PHASE, 10V/div, CH4: inductor current, 2A/div, 400ns/div Figure 8. Continuous Conduction Mode Switching Waveforms CH1: HIDRV, 10V/div, CH2: LODRV, 5V/div, CH3: PHASE, 10V/div, CH4: inductor current, 1A/div, 400ns/div Figure 9. Cycle-by-Cycle Synchronous to Non-synchronous CH1: PHASE, 10V/div, CH2: LODRV, 5V/div, CH4: inductor current, 2A/div, 4us/div Figure 10. 100% Duty and Refresh Pulse CH2: battery current, 2A/div, CH3: adapter current, 2A/div, CH4: system load current, 2A/div, 100us/div Figure 11. System Load Transient (Input DPM) CH1: PHASE, 20V/div, CH2: battery voltage, 5V/div, CH3: LODRV, 10V/div, CH4: inductor current, 2A/div, 400us/div Figure 12. Battery Insertion CH1: PHASE, 20V/div, CH2: LODRV, 10V/div, CH3: battery voltage, 5V/div, CH4: inductor current, 2A/div, 2ms/div Figure 13. Battery to Ground Short Protection Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 11 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com 98 4-cell 16.8 V 97 96 Efficiency - % 95 3-cell 12.6 V 94 93 2-cell 8.4 V 92 91 VI = 20 V, f = 750 kHz, L = 4.7 mH 90 89 88 0 0.5 CH1: PHASE, 20V/div, CH2: LODRV, 10V/div, CH3: battery voltage, 5V/div, CH4: inductor current, 2A/div, 4us/div Figure 14. Battery to Ground Short Transition 1 1.5 2 2.5 Charge Current 3 3.5 4 4.5 Figure 15. Efficiency vs Output Current PIN FUNCTIONS – 20-PIN QFN PIN NO. FUNCTION DESCRIPTION NAME 1 ACN Input current sense resistor negative input. Place an optional 0.1 µF ceramic capacitor from ACN to GND for commonmode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential mode filtering. 2 ACP Input current sense resistor positive input. Place a 0.1µF ceramic capacitor from ACP to GND for common-mode filtering. Place a 0.1 µF ceramic capacitor from ACN to ACP to provide differential-mode filtering. 3 CMSRC ACDRV charge pump source input. Place a 4kΩ resistor from CMSRC to the common source of ACFET (Q1) and RBFET (Q2) limit the in-rush current on the CMSRC pin. 4 ACDRV Charge pump output to drive both adapter input n-channel MOSFET (ACFET) and reverse blocking n-channel MOSFET (RBFET). ACDRV voltage is 6V above CMSRC when voltage on ACDET pin is between 2.4V to 3.15V, voltage on VCC pin is above UVLO and voltage on VCC pin is 275mV above voltage on SRN pin so that ACFET and RBFET can be turned on to power the system by AC adapter. Place a 4kΩ resistor from ACDRV to the gate of ACFET and RBFET limits the in-rush current on ACDRV pin. 5 ACOK AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external pull-up resistor when voltage on ACDET pin is between 2.4V and 3.15V, and voltage on VCC is above UVLO and voltage on VCC pin is 275mV above voltage on SRN pin, indicating a valid adapter is present to start charge. If any one of the above conditions can not meet, it is pulled LOW to GND by internal MOSFET. Connect a 10kΩ pull up resistor from ACOK to the pull-up supply rail. 6 ACDET Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to ACDET pin to GND pin. When ACDET pin is above 0.6V and VCC is above UVLO, REGN LDO is present, ACOK comparator and IOUT are both active. 7 IOUT Buffered adapter or charge current output, selectable with SMBus command ChargeOption(). IOUT voltage is 20 times the differential voltage across sense resistor. Place a 100pF or less ceramic decoupling capacitor from IOUT pin to GND. 8 SDA SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. Connect a 10kΩ pullup resistor according to SMBus specifications. 9 SCL SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. Connect a 10kΩ pull-up resistor according to SMBus specifications. 10 ILIM Charge current limit input. Program ILIM voltage by connecting a resistor divider from system reference 3.3V rail to ILIM pin to GND pin. The lower of ILIM voltage or DAC limit voltage sets charge current regulation limit. To disable the control on ILIM, set ILIM above 1.6V. Once voltage on ILIM pin falls below 75mV, charge is disabled. Charge is enabled when ILIM pin rises above 105mV. 11 BATDRV Charge pump output to drive Battery to System n-channel MOSFET (BATFET). BATDRV voltage is 6V above SRN to turn on BATFET (Q5) to power the system from battery. BATDRV voltage is SRN voltage to turn off BATFET to power system from AC adapter. Place a 4kΩ resistor from BATDRV to the gate of BATFET limits the in-rush current on BATDRV pin. 12 SRN Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect the SRN pin to a 7.5Ω resistor first then from resistor another terminal connect a 0.1µF ceramic capacitor to GND for common-mode filtering and connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide differential mode filtering. See the application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection by adding small resistor. 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 PIN FUNCTIONS – 20-PIN QFN (continued) PIN NO. FUNCTION DESCRIPTION NAME 13 SRP Charge current sense resistor positive input. Connect the SRP pin to a 10Ω resistor first then from resistor another terminal connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide differential mode filtering. See the application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection by adding small resistor. 14 GND IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through the power pad underneath IC. 15 LODRV Low side power MOSFET driver output. Connect to low side n-channel MOSFET gate. 16 REGN Linear regulator output. REGN is the output of the 6V linear regulator supplied from VCC. The LDO is active when voltage on ACDET pin is above 0.6V and voltage on VCC is above UVLO. Connect a 1µF ceramic capacitor from REGN to GND. 17 BTST High side power MOSFET driver power supply. Connect a 0.047µF capacitor from BTST to PHASE, and a bootstrap Schottky diode from REGN to BTST. 18 HIDRV High side power MOSFET driver output. Connect to the high side n-channel MOSFET gate. 19 PHASE High side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET. 20 VCC Input supply, diode OR from adapter or battery voltage. Use 10Ω resistor and 1µF capacitor to ground as low pass filter to limit inrush current. PowerPAD™ Exposed pad beneath the IC. Analog ground and power ground star-connected only at the PowerPAD plane. Always solder PowerPAD to the board, and have vias on the PowerPAD plane connecting to analog ground and power ground planes. It also serves as a thermal pad to dissipate the heat. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 13 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM ** Threshold or deglitch time is adjustable by ChargeOption () 3.75V UVLO VCC 20 EN_REGN ACOK_DRV ACN WAKEUP ACDET 6 CMSRC+6V ACN-SRN ACDRV CHARGE PUMP SRN+200mV 0.6V 4 ACDRV ACDRV-CMSRC ACDRV ACOVP CMSRC+5.9V 3.15V ACGOOD ACOC 3 CMSRC Selector Logic SRN+6V Latch off VCC_SRN ** 2.4V ACOK 5 71% of VREF_VREG ACOK_DRV LEARN 11 BATDRV BATDEPL SRN 150ms rising deglitch** SRN WATCHDOG TIMER VREF_IAC ACP 2 20X WATCHDOG TIMEOUT ACN 1 IOUT 7 1X BATDRV CHARGE PUMP Type III Compensation MUX FBO 175s ** EN_CHRG ACOK_DRV EAI Latch off CHARGE_INHIBIT 17 BTST IOUT_SEL DAC_VALID ILIM 10 HSON 18 HIDRV EAO PWM SRP 13 20X SRN 12 19 PHASE VREF_ICHG RAMP Frequency 200mV VFB EN_REGN ** REGN LDO 16 REGN ILIM LSON CE 15 LODRV 105mV VREF_VREG 10uA 4mA in BATOVP Tj 14 GND TSHUT 155oC WAKEUP Driver Logic SRP-SRN DAC_VALID SMBus Interface SDA 8 SCL 9 ChargeOption() ChargeCurrent() ChargeVoltage() InputCurrent() ManufactureID() DeviceID() CHG_OCP 60mV/90mV/120mV CHARGE_INHIBIT LEARN VREF_VREG 5mV CHG_UCP SRP-SRN VREF_ICHG 1.25mV LIGHT_LOAD VREF_IAC SRP-SRN IOUT_SEL ACP-PH 700mV IFAULT_HI ** PH-GND IFAULT_LO 110mV ACP-ACN 1.66xVREF_IAC ** ACP-ACN ACOC FAST_DPM 1.08xVREF_IAC 4.3V REFRESH BTST-PH VFB BATOVP 104%VREF_VREG 2.5V BAT_LOWV SRN VCC VCC-SRN SRN+275mV Figure 16. Functional Block Diagram for bq24725 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 DETAILED DESCRIPTION SMBus Interface The bq24725 operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. The bq24725 uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq24725 uses the SMBus Read-Word and Write-Word protocols (see Figure 17) to communicate with the smart battery. The bq24725 performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In addition, the bq24725 has two identification registers a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH). SMBus communication is enabled with the following conditions: • VVCC is above UVLO; • VACDET is above 0.6V; The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pull-up resistors (10kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a START condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 18 and Figure 19 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24725 because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24725 supports the charger commands as described in Table 2. a) Write-Word Format S SLAVE ADDRESS COMMAND BYTE ACK 1b 8 BITS 0 MSB LSB W ACK 7 BITS 1b MSB LSB 0 Preset to 0b0001001 LOW DATA BYTE ACK 1b 8 BITS 1b 8 BITS 0 MSB LSB 0 MSB LSB D7 ChargeCurrent() = 0x14H ChargeVoltage() = 0x15H InputCurrent() = 0x3FH ChargeOption() = 0x12H HIGH DATA BYTE D0 D15 ACK P 1b 0 D8 b) Read-Word Format S COMMAND BYTE ACK 1b 8 BITS 1b 0 MSB LSB 0 SLAVE ADDRESS W ACK 7 BITS 1b MSB LSB 0 S SLAVE ADDRESS R ACK 7 BITS 1b 1b 1 0 MSB LSB LOW DATA BYTE 8 BITS MSB LSB ACK 1b 0 HIGH DATA BYTE 8 BITS MSB LSB NACK P 1b 1 Preset to 0b0001001 DeviceID() = 0xFFH Preset to D7 D0 D15 D8 ManufactureID() = 0xFEH 0b0001001 ChargeCurrent() = 0x14H ChargeVoltage() = 0x15H InputCurrent() = 0x3FH ChargeOption() = 0x12H LEGEND: S = START CONDITION OR REPEATED START CONDITION P = STOP CONDITION ACK = ACKNOWLEDGE (LOGIC-LOW) NACK = NOT ACKNOWLEDGE (LOGIC-HIGH) W = WRITE BIT (LOGIC-LOW) R = READ BIT (LOGIC-HIGH) MASTER TO SLAVE SLAVE TO MASTER Figure 17. SMBus Write-Word and Read-Word Protocols Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 15 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com Figure 18. SMBus Write Timing A B tLOW C D E F G H I J K t HIGH SMBCLK SMBDATA A = START CONDITION E = SLAVE PULLS SMBDATA LINE LOW I = ACKNOWLEDGE CLOCK PULSE B = MSB OF ADDRESS CLOCKED INTO SLAVE F = ACKNOWLEDGE BIT CLOCKED INTO MASTER J = STOP CONDITION C = LSB OF ADDRESS CLOCKED INTO SLA VE G = MSB OF DATA CLOCKED INTO MASTER K = NEW START CONDITION D = R/W BIT CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO MASTER Figure 19. SMBus Read Timing Battery-Charger Commands The bq24725 supports six battery-charger commands that use either Write-Word or Read-Word protocols, as summarized in Table 2. ManufacturerID() and DeviceID() can be used to identify the bq24725. The ManufacturerID() command always returns 0x0040H and the DeviceID() command always returns 0x0008H. Table 2. Battery Charger Command Summary 16 REGISTER ADDRESS REGISTER NAME READ/WRITE DESCRIPTION 0x12H ChargeOption() Read or Write Charger Options Control POR STATE 0x7904H 0x14H ChargeCurrent() Read or Write 7-Bit Charge Current Setting 0x0000H 0x15H ChargeVoltage() Read or Write 11-Bit Charge Voltage Setting 0x0000H 0x3FH InputCurrent() Read or Write 6-Bit Input Current Setting 0x1000H 0XFEH ManufacturerID() Read Only Manufacturer ID 0x0040H 0xFFH DeviceID() Read Only Device ID 0x0008H Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 Setting Charger Options By writing ChargeOption() command (0x12H or 0b00010010), bq24725 allows users to change several charger options after POR (Power On Reset) as shown in Table 3. Table 3. Charge Options Register (0x12H) BIT BIT NAME [15] ACOK Deglitch Time Adjust ACOK deglitch time. Adjust To change this option, VCC pin voltage must above UVLO and ACDET pin voltage must above 0.6V to enable IC SMBus communication. After POR the bit default value is 0 and ACOK rising edge deglitch time is 150ms. The long deglitch timer will only be enabled after ACFET turns on and turns off one time this makes first time adapter plug in deglitch time always 150ms 0: ACOK rising edge deglitch time 150ms 1: ACOK rising edge deglitch time 1.3s DESCRIPTION [14:13] WATCHDOG Timer Adjust Set maximum delay between consecutive SMBus Write charge voltage or charge current command. The charge will be suspended if IC does not receive write charge voltage or write charge current command within the watchdog time period and watchdog timer is enabled. The charge will be resumed after receive write charge voltage or write charge current command when watchdog timer expires and charge suspends. 00: Disable Watchdog Timer 01: Enabled, 44 sec 10: Enabled, 88 sec 11: Enable Watchdog Timer (175s) [12:11] BAT Depletion Comparator Threshold Adjust This is used for LEARN function. During LEARN cycle, when IC detect battery voltage is below depletion voltage threshold IC will turn off BATFET and turn on ACFET to power the system from AC adapter instead of battery. The rising edge hysteresis is typical 305mV to 370mV. 00: Falling Threshold = 59.19% of voltage regulation limit (~2.486V/cell) 01: Falling Threshold = 62.65% of voltage regulation limit (~2.631V/cell) 10: Falling Threshold = 66.55% of voltage regulation limit (~2.795V/cell) 11: Falling Threshold = 70.97% of voltage regulation limit (~2.981V/cell) < default at POR> [10] EMI Switching Frequency Adjust 0: Reduce PWM switching frequency by 18% 1: Increase PWM switching frequency by 18% [9] EMI Switching Frequency Enable 0: Disable adjust PWM switching frequency 1: Enable adjust PWM switching frequency IFAULT_HI Comparator Threshold Adjust Short circuit protection high side MOSFET voltage drop comparator threshold. 00: 300mV 01: 500mV 10: 700mV 11: 900mV [6] LEARN Enable Set this bit 1 start battery learn cycle. IC turns off ACFET and turns on BATFET to discharge battery capacity. When battery voltage reaches threshold defined in bit [12;11], the BATFET is turned off and ACFET is turned on to finish battery learn cycle. After finished learn cycle, this bit is automatically reset to 0. Set this bit 0 will stop battery learn cycle. IC turns off BATFET and turns on ACFET. 0: Disable LEARN Cycle 1: Enable LEARN Cycle [5] IOUT Selection 0: IOUT is the 20x adapter current amplifier output 1: IOUT is the 20x charge current amplifier output [4] Not In Use 0 at POR [3] Not In Use 0 at POR ACOC Threshold Adjust 00: Disable ACOC 01: 1.33X of input current regulation limit 10: 1.66X of input current regulation limit 11: 2.22X of input current regulation limit Charge Inhibit 0: Enable Charge 1: Inhibit Charge [8:7] [2:1] [0] Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 17 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com Setting the Charge Current To set the charge current, write a 16bit ChargeCurrent() command (0x14H or 0b00010100) using the data format listed in Table 4. With 10mΩ sense resistor, the bq24725 provides a charge current range of 128mA to 8.128A, with 64mA step resolution. Sending ChargeCurrent() below 128mA or above 8.128A clears the register and terminates charging. Upon POR, charge current is 0A. A 0.1µF capacitor between SRP and SRN for differential mode filtering is recommended, 0.1µF capacitor between SRN and ground for common mode filtering, and an optional 0.1µF capacitor between SRP and ground for common mode filtering. Meanwhile, the capacitance on SRP should not be higher than 0.1µF in order to properly sense the voltage across SRP and SRN for cycle-bycycle under-current and over current detection. The SRP and SRN pins are used to sense RSR with default value of 10mΩ. However, resistors of other values can also be used. For a larger sense resistor, a larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss. If the current sensing resistor value is too high, it may trigger an over current protection threshold because the current ripple voltage is too high. In such a case, either a higher inductance value or a lower current sensing resistor value should be used to limit the current ripple voltage level. A current sensing resistor value no more than 20mΩ is suggested. To provide secondary protection, the bq24725 has an ILIM pin with which the user can program the maximum allowed charge current. Internal charge current limit is the lower one between the voltage set by ChargeCurrent(), and voltage on ILIM pin. To disable this function, the user can pull ILIM above 1.6V, which is the maximum charge current regulation limit. Equation 1 shows the voltage set on ILIM pin with respect to the preferred charge current limit: VILIM = 20 × (VSRP - VSRN ) = 20 ´ ICHG ´ RSR (1) Table 4. Charge Current Register (0x14H), Using 10mΩ Sense Resistor 18 BIT BIT NAME 0 – DESCRIPTION Not used. 1 – Not used. 2 – Not used. 3 – Not used. 4 – Not used. 5 – Not used. 6 Charge Current, DACICHG 0 0 = Adds 0mA of charger current. 1 = Adds 64mA of charger current. 7 Charge Current, DACICHG 1 0 = Adds 0mA of charger current. 1 = Adds 128mA of charger current. 8 Charge Current, DACICHG 2 0 = Adds 0mA of charger current. 1 = Adds 256mA of charger current. 9 Charge Current, DACICHG 3 0 = Adds 0mA of charger current. 1 = Adds 512mA of charger current. 10 Charge Current, DACICHG 4 0 = Adds 0mA of charger current. 1 = Adds 1024mA of charger current. 11 Charge Current, DACICHG 5 0 = Adds 0mA of charger current. 1 = Adds 2048mA of charger current. 12 Charge Current, DACICHG 6 0 = Adds 0mA of charger current. 1 = Adds 4096mA of charger current. 13 – Not used. 14 – Not used. 15 – Not used. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 Setting the Charge Voltage To set the output charge regulation voltage, write a 16bit ChargeVoltage() command (0x15H or 0b00010101) using the data format listed in Table 5. The bq24725 provides charge voltage range from 1.024V to 19.200V, with 16mV step resolution. Sending ChargeVoltage() below 1.024V or above 19.2V clears the register and terminates charging. Upon POR, charge voltage limit is 0V. The SRN pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery as possible, and place a decoupling capacitor (0.1µF recommended) as close to IC as possible to the decouple high frequency noise. Table 5. Charge Voltage Register (0x15H) BIT BIT NAME 0 - DESCRIPTION Not used. 1 - Not used. 2 - Not used. 3 - Not used. 4 Charge Voltage, DACV 0 0 = Adds 0mV of charger voltage. 1 = Adds 16mV of charger voltage. 5 Charge Voltage, DACV 1 0 = Adds 0mV of charger voltage. 1 = Adds 32mV of charger voltage. 6 Charge Voltage, DACV 2 0 = Adds 0mV of charger voltage. 1 = Adds 64mV of charger voltage. 7 Charge Voltage, DACV 3 0 = Adds 0mV of charger voltage. 1 = Adds 128mV of charger voltage. 8 Charge Voltage, DACV 4 0 = Adds 0mV of charger voltage. 1 = Adds 256mV of charger voltage. 9 Charge Voltage, DACV 5 0 = Adds 0mV of charger voltage. 1 = Adds 512mV of charger voltage. 10 Charge Voltage, DACV 6 0 = Adds 0mV of charger voltage. 1 = Adds 1024mV of charger voltage. 11 Charge Voltage, DACV 7 0 = Adds 0mV of charger voltage. 1 = Adds 2048mV of charger voltage. 12 Charge Voltage, DACV 8 0 = Adds 0mV of charger voltage. 1 = Adds 4096mV of charger voltage. 13 Charge Voltage, DACV 9 0 = Adds 0mV of charger voltage. 1 = Adds 8192mV of charger voltage. 14 Charge Voltage, DACV 10 0 = Adds 0mV of charger voltage. 1 = Adds 16384mV of charger voltage. 15 - Not used. Setting Input Current System current normally fluctuates as portions of the system are powered up or put to sleep. With the input current limit, the output current requirement of the AC wall adapter can be lowered, reducing system cost. The total input current, from a wall cube or other DC source, is the sum of the system supply current and the current required by the charger. When the input current exceeds the set input current limit, the bq24725 decreases the charge current to provide priority to system load current. As the system current rises, the available charge current drops linearly to zero. Thereafter, all input current goes to system load and input current increases. During DPM regulation, the total input current is the sum of the device supply current IBIAS, the charger input current, and the system load current ILOAD, and can be estimated as follows: éI ´ VBATTERY ù IINPUT = ILOAD + ê BATTERY ú + IBIAS VIN ´ η ë û (2) where η is the efficiency of the charger buck converter (typically 85% to 95%). Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 19 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com To set the input current limit, write a 16-bit InputCurrent() command (0x3FH or 0b00111111) using the data format listed in Table 6. When using a 10mΩ sense resistor, the bq24725 provides an input-current limit range of 128mA to 8.064A, with 128mA resolution. The suggested input current limit is set to no less than 512mA. Sending InputCurrent() below 128mA or above 8.064A clears the register and terminates charging. Upon POR, the default input current limit is 4096mA. The ACP and ACN pins are used to sense RAC with default value of 10mΩ. However, resistors of other values can also be used. For a larger sense resistor, larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss. If input current rises above 108% of input current limit set point, the charger will shut down immediately to allow the input current drop. After charging stops, the charger will soft restart to charge the battery if the adapter still has power left to charge the battery. This prevents a crash if the adapter is overloaded when the system has a high and fast loading transient. The waiting time between shut down and restart charging is a natural response time of the input current limit loop. Table 6. Input Current Register (0x3FH), Using 10mΩ Sense Resistor BIT BIT NAME 0 – Not used. DESCRIPTION 1 – Not used. 2 – Not used. 3 – Not used. 4 – Not used. 5 – Not used. 6 – Not used. 7 Input Current, DACIIN 0 0 = Adds 0mA of input current. 1 = Adds 128mA of input current. 8 Input Current, DACIIN 1 0 = Adds 0mA of input current. 1 = Adds 256mA of input current. 9 Input Current, DACIIN 2 0 = Adds 0mA of input current. 1 = Adds 512mA of input current. 10 Input Current, DACIIN 3 0 = Adds 0mA of input current. 1 = Adds 1024mA of input current. 11 Input Current, DACIIN 4 0 = Adds 0mA of input current. 1 = Adds 2048mA of input current. 12 Input Current, DACIIN 5 0 = Adds 0mA of input current. 1 = Adds 4096mA of input current. 13 – Not used. 14 – Not used. 15 – Not used. Adapter Detect and ACOK Output The bq24725 uses an ACOK comparator to determine the source of power on VCC pin, either from the battery or adapter. An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage, but lower than the maximum allowed adapter voltage. The open drain ACOK output requires external pull up resistor to system digital rail for a high level. It can be pulled to external rail under the following conditions: • VVCC > UVLO; • 2.4V < VACDET < 3.15V (not in ACOVP condition, nor in low input voltage condition); • VVCC–VSRN > 275mV (not in sleep mode); 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 The rising edge delay default is 150ms after ACDET has a valid voltage to make ACOK pull high. The first time after IC POR always gives a 150ms ACOK rising edge delay no matter what the ChargeOption register value. To change this option, the VCC pin voltage must above UVLO, and the ACDET pin voltage must above 0.6V which enables the IC SMBus communication and sets ChargeOption() bit[15] to 1 which sets the ACOK rising deglitch time to be 1.3s. Only after the ACDET pin voltage is pulled below 2.4V (but not below 0.6V which will reset IC and force the ACOK rising edge deglitch time to be 150ms) and ACDRV has been turned off at least one time, the 1.3s delay time is effective for next time the ACDET pin voltage goes above 2.4V. The purpose of the option 1.3s rising edge deglitch time is to turn off the ACFET long enough when the ACDET pin is pulled below 2.4V by excessive system current, such as over current or short circuit. Adapter Over Voltage (ACOVP) When the ACDET pin voltage is higher than 3.15V, it is considered as adapter over voltage. ACOK will be pulled low, and charge will be disabled. ACFET will be turned off to disconnect the high voltage adapter to system during ACOVP. BATFET will be turned on if turns on conditions are valid. See the System Power Selection section for details. When ACDET pin voltage falls below 3.15V and above 2.4V, it is considered as adapter voltage returns back to normal voltage. ACOK will be pulled high by external pull up resistor. BATFET will be turned off and ACFET and RBFET will be turned on to power the system from adapter. The charge can be resumed if enable charge conditions are valid. See the Enable and Disable Charging section for details. System Power Selection The bq24725 automatically switches adapter or battery power to system. The battery is connected to system at POR if battery exists. The battery is disconnected from system and the adapter is connected to system after default 150ms delay (can be change to 1.3s delay) if ACOK goes HIGH. An automatic break-before-make logic prevents shoot-through currents when the selectors switch. The ACDRV drives a pair of common-source (CMSRC) n-channel power MOSFETs (ACFET and RBFET) between adapter and ACP (see Figure 1 for details). The ACFET separates adapter from battery or system, and provides a limited di/dt when plugging in adapter by controlling the ACFET turn-on time. Meanwhile it protects adapter when system or battery is shorted. The RBFET provides negative input voltage protection and battery discharge protection when adapter is shorted to ground, and minimizes system power dissipation with its low RDS(on) compared to a Schottky diode. When the adapter is not present, ACDRV is pulled to CMSRC to keep ACFET and RBFET off, disconnecting adapter from system. BATDRV stays at VSRN + 6V to connect battery to system if all the following conditions are valid: • VVCC > UVLO; • VSRN > UVLO; • VACN < 200mV above VSRN (ACN_SRN comparator); Approximately 150ms (default, can be changed to 1.3s) after the adapter is detected (ACDET pin voltage between 2.4V and 3.15V), the system power source begins to switch from battery to adapter if all the following conditions are valid: • Not in LEARN mode or in LEARN mode and VSRN is lower than battery depletion threshold; • ACOK high The gate drive voltage on ACFET and RBFET is VCMSRC + 6V. If the ACFET/RBFET have been turned on for 20ms, and the voltage across gate and source is still less than 5.9V, ACFET and RBFET will be turned off. After 1.3s delay, it resumes turning on ACFET and RBFET. If such a failure is detected seven times within 90 seconds, ACFET/RBFET will be latched off and an adapter removal and system shut down is required to force ACDET < 0.6V to reset the IC. After IC reset from latch off, ACFET/RBFET can be turned on again. After 90 seconds, the failure counter will be reset to zero to prevent latch off. With ACFET/RBFET off, charge is disabled. To turn off ACFET/RBFET, one of the following conditions must be valid: • In LEARN mode and VSRN is above battery depletion threshold; • ACOK low To limit the in-rush current on ACDRV pin, CMSRC pin and BATDRV pin, a 4kΩ resistor is recommended on each of the three pins. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 21 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com To limit the adapter inrush current when ACFET is turned on to power system from adapter, the Cgs and Cgd external capacitor of ACFET must be carefully selected. The larger the Cgs and Cgd capacitance, the slower turn on of ACFET will be and less inrush current of adapter. However, if Cgs or Cgd is too large, the ACDRV-CMSRC voltage may still go low after the 20ms turn on time window is expired. To make sure ACFET will not be turned on when adapter is hot plugged in, the Cgs value should be 20 times or higher than Cgd. The most cost effective way to reduce adapter in-rush current is to minimize system total capacitance. Battery LEARN Cycle A battery LEARN cycle can be activated via SMBus command (ChargeOption() bit[6]=1 enable LEARN cycle, bit[6]=0 disable LEARN cycle). When LEARN is enabled with ACFET/RBFET connected, the system power selector logic is over-driven to switch to battery by turning off ACFET/RBFET and turning on BATFET. LEARN function allows the battery to discharge in order to calibrate the battery gas gauge over a complete discharge/charge cycle. The controller automatically exits LEARN cycle when the battery voltage is below battery depletion threshold, and the system switches back to adapter input by turning off BATFET and turning on ACFET/RBFET. After LEARN cycle, the LEARN bit is automatically reset to 0. The battery depletion threshold can be set to 59.19%, 62.65%, 66.55%, and 70.97% of voltage regulation level via SMBus command (ChargeOption() bit[12:11]). Enable and Disable Charging In • • • • • Charge mode, the following conditions have to be valid to start charge: Charge is enabled via SMBus (ChargeOption() bit [0]=0, default is 0, charge enabled); ILIM pin voltage higher than 105mV; All three regulation limit DACs have valid value programmed; ACOK is valid (See the Adapter Detect and ACOK Output section for details); ACFET and RBFET turns on and gate voltage is high enough (See the System Power Selection section for details); • VSRN does not exceed BATOVP threshold; • IC Temperature doesn’t exceed TSHUT threshold; • Not in ACOC condition (See the Input Over Current Protection (ACOC) section for details); One of the following conditions will stop on-going charging: • Charge is inhibited via SMBus (ChargeOption() bit[0]=1); • ILIM pin voltage lower than 75mV; • One of three regulation limit DACs is set to 0 or out of range; • ACOK is pulled low (See the Adapter Detect and ACOK Output section for details); • ACFET turns off; • VSRN exceeds BATOVP threshold; • TSHUT IC temperature threshold is reached; • ACOC is detected (See the Input Over Current Protection (ACOC) section for details); • Short circuit is detected (See the Inductor Short, MOSFET Short Protection section for details); • Watchdog timer expires if watchdog timer is enabled (See the Charger Timeout section for details); Automatic Internal Soft-Start Charger Current Every time the charge is enabled, the charger automatically applies soft-start on charge current to avoid any overshoot or stress on the output capacitors or the power converter. The charge current starts at 128mA, and the step size is 64mA in CCM mode for a 10mΩ current sensing resistor. Each step lasts around 240µs in CCM mode, till it reaches the programmed charge current limit. No external components are needed for this function. During DCM mode, the soft start up current step size is larger and each step lasts for longer time period due to the intrinsic slow response of DCM mode. 22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 High Accuracy Current Sense Amplifier As an industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current or the charge current, selectable via SMBUS (ChargeOption() bit[5]=0 select the input current, bit[5]=1 select the charge current) by host. The CSA senses voltage across the sense resistor by a factor of 20 through the IOUT pin. Once VCC is above UVLO and ACDET is above 0.6V, CSA turns on and IOUT output becomes valid. If the user wants to lower the voltage on current monitoring, then use a resistor divider from IOUT to GND, and still achieve accuracy over temperature. A 100pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay. Charge Timeout The bq24725 includes a watchdog timer to terminate charging if the charger does not receive a write ChargeVoltage() or write ChargeCurrent() command within 175s (adjustable via ChargeOption() command). If a watchdog timeout occurs all register values keep unchanged but charge is suspended. Write ChargeVoltage() or write ChargeCurrent() commands must be re-sent to reset watchdog timer and resume charging. The watchdog timer can be disabled, or set to 44s, 88s or 175s via SMBus command (ChargeOption() bit[14:13]). After watchdog timeout write ChargeOption() bit[14:13] to disable watchdog timer also resume charging. Converter Operation The synchronous buck PWM converter uses a fixed frequency voltage mode control scheme and internal type III compensation network. The LC output filter gives a characteristic resonant frequency 1 ¦o = 2p Lo Co (3) The resonant frequency fo is used to determine the compensation to ensure there is sufficient phase margin and gain margin for the target bandwidth. The LC output filter should be selected to give a resonant frequency of 10–20 kHz nominal for the best performance. Suggest component value as charge current of 750kHz default switching frequency is shown in Table 7. Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. Table 7. Suggest Component Value as Charge Current of Default 750kHz Switching Frequency Charge Current 2A 3A 4A 6A 8A Output Inductor Lo (µH) 6.8 or 8.2 5.6 or 6.8 3.3 or 4.7 3.3 2.2 Output Capacitor Co (µF) 20 20 20 30 40 Sense Resistor (mΩ) 10 10 10 10 10 The bq24725 has three loops of regulation: input current, charge current and charge voltage. The three loops are brought together internally at the error amplifier. The maximum voltage of the three loops appears at the output of the error amplifier EAO. An internal saw-tooth ramp is compared to the internal error control signal EAO (see Figure 16) to vary the duty-cycle of the converter. The ramp has offset of 200mV in order to allow 0% duty-cycle. When the battery charge voltage approaches the input voltage, EAO signal is allowed to exceed the saw-tooth ramp peak in order to get a 100% duty-cycle. If voltage across BTST and PHASE pins falls below 4.3V, a refresh cycle starts and low-side n-channel power MOSFET is turned on to recharge the BTST capacitor. It can achieve duty cycle of up to 99.5%. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 23 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com Continuous Conduction Mode (CCM) With sufficient charge current the bq24725’s inductor current never crosses zero, which is defined as continuous conduction mode. The controller starts a new cycle with ramp coming up from 200mV. As long as EAO voltage is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle, ramp gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. During CCM mode, the inductor current is always flowing and creates a fixed two-pole system. Having the LSFET turn-on keeps the power dissipation low, and allows safely charging at high currents. Discontinuous Conduction Mode (DCM) During the HSFET off time when LSFET is on, the inductor current decreases. If the current goes to zero, the converter enters Discontinuous Conduction Mode. Every cycle, when the voltage across SRP and SRN falls below 5mV (0.5A on 10mΩ), the under current-protection comparator (UCP) turns off LSFET to avoid negative inductor current, which may boost the system via the body diode of HSFET. During the DCM mode the loop response automatically changes. It changes to a single pole system and the pole is proportional to the load current. Both CCM and DCM are synchronous operation with LSFET turn-on every clock cycle. If the average charge current goes below 125mA on 10mΩ current sensing resistor or the battery voltage falls below 2.5V, the LSFET keeps turn-off. The battery charger operates in non-synchronous mode and the current flows through the LSFET body diode. During non-synchronous operation, the LSFET turns on only for a refreshing pulse to charge the BTST capacitor. If the average charge current goes above 250mA on 10mΩ current sensing resistor, the LSFET exits non-synchronous mode and enters synchronous mode to reduce LSFET power loss. Input Over Current Protection (ACOC) The bq24725 cannot maintain the input current level if the charge current has been already reduced to zero. After the system current continues increasing to the 1.66X of input current DAC set point (with 2.5ms blank out time), ACFET/RBFET is turned off and charge is disabled for 1.3s and will soft start again for charge if the ACOC condition goes away. If such a failure is detected seven times in 90 seconds, the ACFET and RBFET latch off and an adapter removal and system shutdown is required to force ACDET < 0.6V to reset IC. After IC reset from latch off, ACFET/RBFET can be turned on again. After 90 seconds, the failure counter will be reset to zero to prevent latch off. The ACOC function can be disabled or the threshold can be set to 1.33X, 1.66X or 2.22X of input DPM current via SMBus command (ChargeOption() bit [2:1]). Charge Over Current Protection (CHGOCP) The bq24725 has a cycle-by-cycle peak over current protection. It monitors the voltage across SRP and SRN, and prevents the current from exceeding of the threshold based on the DAC charge current set point. The highside gate drive turns off for the rest of the cycle when the over current is detected, and resumes when the next cycle starts. The charge OCP threshold is automatically set to 6A, 9A, and 12A on a 10mΩ current sensing resistor based on charge current register value. This prevents the threshold to be too high which is not safe or too low which can be triggered in normal operation. Proper inductance should be selected to prevent OCP triggered in normal operation due to high inductor current ripple. Battery Over Voltage Protection (BATOVP) The bq24725 will not allow the high-side and low-side FET to turn-on when the battery voltage at SRN exceeds 104% of the regulation voltage set-point. If BATOVP last over 30ms, charger is completely disabled. This allows quick response to an over voltage condition – such as occurs when the load is removed or the battery is disconnected. A 4mA current sink from SRN to GND is on only during BATOVP and allows discharging the stored output inductor energy that is transferred to the output capacitors. 24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 Battery Shorted to Ground (BATLOWV) The bq24725 will disable charge for 1ms if the battery voltage on SRN falls below 2.5V. After 1ms reset, the charge is resumed with soft-start if all the enable conditions in the Enable and Disable Charging sections are satisfied. This prevents any overshoot current in inductor which can saturate inductor and may damage the MOSFET. The charge current is limited to 0.5A on 10mΩ current sensing resistor when BATLOWV condition persists and LSFET keeps off. The LSFET turns on only for a refreshing pulse to charge the BTST capacitor. Thermal Shutdown Protection (TSHUT) The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off for selfprotection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction temperature falls below 135°C. During thermal shut down, the REGN LDO current limit is reduced to 16mA. Once the temperature falls below 135°C, charge can be resumed with soft start. EMI Switching Frequency Adjust The charger switching frequency can be adjusted ±18% to solve EMI issue via SMBus command. ChargeOption() bit [9]=0 disable the frequency adjust function. To enable frequency adjust function, set ChargeOption() bit[9]=1. Set ChargeOption() bit [10]=0 to reduce switching frequency, set bit[10]=1 to increase switching frequency. If frequency is reduced, for a fixed inductor the current ripple is increased. The inductor value must be carefully selected, so that it will not trigger a cycle-by-cycle peak over current protection even for the worst condition such as higher input voltage, 50% duty cycle, lower inductance and lower switching frequency. Inductor Short, MOSFET Short Protection The bq24725 has a unique short circuit protection feature. Its cycle-by-cycle current monitoring feature is achieved through monitoring the voltage drop across RDS(on) of the MOSFETs after a certain amount of blanking time. In case of MOSFET short or inductor short circuit, the over current condition is sensed by two comparators and two counters will be triggered. After seven times of short circuit events, the charger will be latched off and ACFET and RBFET is turned off to disconnect adapter from system. BATFET is turned on to connect battery pack to system. To reset the charger from latch-off status, the IC VCC pin must be pulled below UVLO or the ACDET pin must be pulled below 0.6V. This can be achieved by removing the adapter and shut down the operation system . The low side MOSFET short circuit voltage drop threshold is fixed to typical 110mV. The high side MOSFET short circuit voltage drop threshold can be adjusted via SMBus command. ChargeOption() bit[8:7] = 00, 01, 10, 11 set the threshold 300mV, 500mV, 700mV and 900mV respectively. Due to the certain amount of blanking time to prevent noise when MOSFET just turns on, the cycle-by-cycle charge over current protection may detect high current and turn off MOSFET first before the short circuit protection circuit can detect short condition because the blanking time has not finished. In such a case the charge may not be able to detect shorts circuit and counter may not be able to count to seven then latch off. Instead the charge may continuously keep switching with very narrow duty cycle to limit the cycle-by-cycle current peak value. However, the charger should still be safe and will not cause failure because the duty cycle is limited to a very short of time and MOSFET should be still inside the safety operation area. During a soft start period, it may takes long time instead of just seven switching cycles to detect short circuit based on the same blanking time reason. Table 8. Component List for Typical System Circuit of Figure 1 PART DESIGNATOR QTY DESCRIPTION C1, C2, C3, C13, C14, C16 6 Capacitor, Ceramic, 0.1µF, 25V, 10%, X7R, 0603 C4 1 Capacitor, Ceramic, 100pF, 25V, 10%, X7R, 0603 C5, C6 2 Capacitor, Ceramic, 1µF, 25V, 10%, X7R, 0603 C7 1 Capacitor, Ceramic, 0.047µF, 25V, 10%, X7R, 0603 C8, C9, C10, C11 4 Capacitor, Ceramic, 10µF, 25V, 10%, X7R, 1206 C15 1 Capacitor, Ceramic, 0.01µF, 25V, 10%, X7R, 0603 C17 1 Capacitor, Ceramic, 2200pF, 25V, 10%, X7R, 0603 Ci 1 Capacitor, Ceramic, 2.2µF, 25V, 10%, X7R, 1210 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 25 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com Table 8. Component List for Typical System Circuit of Figure 1 (continued) PART DESIGNATOR QTY DESCRIPTION Csys 1 Capacitor, Electrolytic, 220µF, 25V D1 1 Diode, Schottky, 30V, 200mA, SOT-23, Fairchild, BAT54 D2 1 Diode, Dual Schottky, 30V, 200mA, SOT-23, Fairchild, BAT54C Q1, Q2, Q5 3 N-channel MOSFET, 30V, 12.5A, SO-8, Fairchild, FDS6680A Q3, Q4 2 N-channel MOSFET, 30V, 12A, PowerPAK 1212-8, Vishay Siliconix, SiS412DN Q6 1 N-channel MOSFET, 50V, 0.2A, SOT-323, Diodes, BSS138W L1 1 Inductor, SMT, 4.7µH, 5.5A, Vishay Dale, IHLP2525CZER4R7M01 R1 1 Resistor, Chip, 430kΩ, 1/10W, 1%, 0603 R2 1 Resistor, Chip, 66.5kΩ, 1/10W, 1%, 0603 R3, R4, R5 3 Resistor, Chip, 10kΩ, 1/10W, 1%, 0603 R6, R10, R11 3 Resistor, Chip, 4.02kΩ, 1/10W, 1%, 0603 R7 1 Resistor, Chip, 316kΩ, 1/10W, 1%, 0603 R8 1 Resistor, Chip, 100kΩ, 1/10W, 1%, 0603 R9 1 Resistor, Chip, 10Ω, 1/4W, 1%, 1206 R12 1 Resistor, Chip, 1.00MΩ, 1/10W, 1%, 0603 R13 1 Resistor, Chip, 3.01MΩ, 1/10W, 1%, 0603 R14 1 Resistor, Chip, 10Ω, 1/10W, 5%, 0603 R15 1 Resistor, Chip, 7.5Ω, 1/10W, 5%, 0603 RAC, RSR 2 Resistor, Chip, 0.01Ω, 1/2W, 1%, 1206 Ri 1 Resistor, Chip, 2Ω, 1/2W, 1%, 1210 U1 1 Charger controller, 20 pin VQFN, TI, bq24725RGR U2 1 Dual digital transistor, 40V, 30mA, SC-74, Rohm, IMD2A APPLICATION INFORMATION Negative Output Voltage Protection Reversely insert the battery pack into the charger output during production or hard shorts on battery to ground will generate negative output voltage on SRP and SRN pin. IC internal electrostatic-discharge (ESD) diodes from GND pin to SRP or SRN pins and two anti-parallel (AP) diodes between SRP and SRN pins can be forward biased and negative current can pass through the ESD diodes and AP diodes when output has negative voltage. Insert two resistors for SRP and SRN pins to limit the negative current level when output has negative voltage. Suggest resistor value is 10Ω for SRP pin and 7-8Ω for SRN pin. After adding small resistors, the suggested precharge current is at least 192mA for a 10mΩ current sensing resistor. Reverse Input Voltage Protection Q6, R12 and R13 in Figure 1 gives system and IC protection from reversed adapter voltage. In normal operation, Q6 is turned off by negative Vgs. When adapter voltage is reversed, Q6 Vgs is positive. As a result, Q6 turns on to short gate and source of Q2 so that Q2 is off. Q2 body diode blocks negative voltage to system. However, CMSRC and ACDRV pins need R10 and R11 to limit the current due to the ESD diode of these pins when turned on. Q6 must has low Vgs threshold voltage and low Qgs gate charge so it turns on before Q2 turns on. R10 and R11 must have enough power rating for the power dissipation when the ESD diode is on. In Figure 2, the Schottky diode D3 gives the reverse adapter voltage protection, no extra small MOSFET and resistors are needed. Reduce Battery Quiescent Current When the adapter is not present, if VCC is powered with voltage higher than UVLO directly or indirectly (such as through a LDO or switching converter) from battery, the internal BATFET charge pump gives the BATFET pin 6V higher voltage than the SRN pin to drive the n-channel BATFET. As a result, the battery has higher quiescent current. This is only necessary when the battery powers the system due to a high system current that goes through the MOSFET channel instead of the body diode to reduce conduction loss and extend the battery 26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 working life. When the system is totally shutdown, it is not necessary to let the internal BATFET charge pump work. The host controller can use a digital signal EN to disconnect the battery power path to the VCC pin by U2 in Figure 1. As a result, battery quiescent current can be minimized. The host controller still can get power from BATFET body diode because the total system current is the lowest when the system is shutdown, so there is no high conduction loss of the body diode. Inductor Selection The bq24725 has three selectable fixed switching frequency. Higher switching frequency allows the use of smaller inductor and capacitor values. Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE): ISAT ³ ICHG + (1/2) IRIPPLE (4) The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fS) and inductance (L): V ´ D ´ (1 - D) IRIPPLE = IN fS ´ L (5) The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging voltage range is from 9V to 12.6V for 3-cell battery pack. For 20V adapter voltage, 10V battery voltage gives the maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12V to 16.8V, and 12V battery voltage gives the maximum inductor ripple current. Usually inductor ripple is designed in the range of (20-40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design. The bq24725 has charge under current protection (UCP) by monitoring charging current sensing resistor cycleby-cycle. The typical cycle-by-cycle UCP threshold is 5mV falling edge corresponding to 0.5A falling edge for a 10mΩ charging current sensing resistor. When the average charging current is less than 125mA for a 10mΩ charging current sensing resistor, the low side MOSFET is off until BTST capacitor voltage needs to refresh the charge. As a result, the converter relies on low side MOSFET body diode for the inductor freewheeling current. Input Capacitor Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and can be estimated by Equation 6: ICIN = ICHG ´ D × (1 - D) (6) Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred for 19-20V input voltage. 10-20μF capacitance is suggested for typical of 3-4A charging current. Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. Output Capacitor Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current is given: I ICOUT = RIPPLE » 0.29 ´ IRIPPLE 2 ´ 3 (7) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 27 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com The bq24725 has internal loop compensator. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 10 kHz and 20 kHz. The preferred ceramic capacitor is 25V X7R or X5R for output capacitor. 10-20μF capacitance is suggested for a typical of 3-4A charging current. Place the capacitors after charging current sensing resistor to get the best charge current regulation accuracy. Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. Power MOSFETs Selection Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are internally integrated into the IC with 6V of gate drive voltage. 30V or higher voltage rating MOSFETs are preferred for 19-20V input voltage. Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance, RDS(ON), and the gate-to-drain charge, QGD. For the bottom side MOSFET, FOM is defined as the product of the MOSFET's on-resistance, RDS(ON), and the total gate charge, QG. FOMtop = RDS(on) x QGD; FOMbottom = RDS(on) x QG (8) The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same package size. The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D=VOUT/VIN), charging current (ICHG), MOSFET's on-resistance (RDS(ON)), input voltage (VIN), switching frequency (fS), turn on time (ton) and turn off time (toff): 1 Ptop = D ´ ICHG2 ´ RDS(on) + ´ VIN ´ ICHG ´ (t on + t off ) ´ f s 2 (9) The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100°C junction temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are given by: Q Q t on = SW , t off = SW Ion Ioff (10) where Qsw is the switching charge, Ion is the turn-on gate driving current and Ioff is the turn-off gate driving current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge (QGD) and gate-to-source charge (QGS): 1 ´ QGS QSW = QGD + 2 (11) Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on gate resistance (Ron) and turn-off gate resistance (Roff) of the gate driver: VREGN - Vplt Vplt Ion = , Ioff = Ron Roff (12) The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in synchronous continuous conduction mode: Pbottom = (1 - D) x ICHG 2 x RDS(on) (13) When charger operates in non-synchronous mode, the bottom-side MOSFET is off. As a result all the freewheeling current goes through the body-diode of the bottom-side MOSFET. The body diode power loss depends on its forward voltage drop (VF), non-synchronous mode charging current (INONSYNC), and duty cycle (D). PD = VF x INONSYNC x (1 - D) 28 (14) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 The maximum charging current in non-synchronous mode can be up to 0.25A for a 10mΩ charging current sensing resistor or 0.5A if battery voltage is below 2.5V. The minimum duty cycle happens at lowest battery voltage. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the maximum non-synchronous mode charging current. Input Filter Design During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second order system. The voltage spike at VCC pin maybe beyond IC maximum voltage rating and damage IC. The input filter must be carefully designed and tested to prevent over voltage event on VCC pin. There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level. However these two solutions may not have low cost or small size. A cost effective and small size solution is shown in Figure 20. The R1 and C1 are composed of a damping RC network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used for reverse voltage protection for VCC pin. C2 is VCC pin decoupling capacitor and it should be place to VCC pin as close as possible. C2 value should be less than C1 value so R1 can dominant the equivalent ESR value to get enough damping effect. R2 is used to limit inrush current of D1 to prevent D1 getting damage when adapter hot plug-in. R2 and C2 should have 10us time constant to limit the dv/dt on VCC pin to reduce inrush current when adapter hot plug in. R1 has high inrush current. R1 package must be sized enough to handle inrush current power loss according to resistor manufacturer’s datasheet. The filter components value always need to be verified with real application and minor adjustments may need to fit in the real application circuit. D1 Adapter connector R1(2010) 2Ω C1 2.2μF R2(1206) 10-20 Ω VCC pin C2 0.47-1μF Figure 20. Input Filter bq24725 Design Guideline The bq24725 has a unique short circuit protection feature. Its cycle-by-cycle current monitoring feature is achieved through monitoring the voltage drop across RDS(on) of the MOSFETs after a certain amount of blanking time. For a MOSFET short or inductor short circuit, the over current condition is sensed by two comparators, and two counters are triggered. After seven occurrences of a short circuit event, the charger will be latched off. To reset the charger from latch-off status, reconnect the adapter. Figure 21 shows the bq24725 short circuit protection block diagram. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 29 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com Adapter ACP RAC ACN R PCB BTST High-Side MOSFET SCP1 PHASE L REGN COMP1 Adapter Plug in COMP2 Count to 7 CLR RDC Low-Side MOSFET SCP2 Battery C Latch off Charger Figure 21. Block Diagram of bq24725 Short Circuit Protection In normal operation, the low side MOSFET current is from source to drain which generates a negative voltage drop when it turns on, as a result the over current comparator can not be triggered. When the high side switch short circuit or inductor short circuit happens, the large current of low side MOSFET is from drain to source and can trig low side switch over current comparator. bq24725 senses the low side switch voltage drop through the PHASE pin and GND pin. The high-side FET short is detected by monitoring the voltage drop between ACP and PHASE. As a result, it not only monitors the high side switch voltage drop, but also the adapter sensing resistor voltage drop and PCB trace voltage drop from ACN terminal of RAC to charger high side switch drain. Usually, there is a long trance between input sensing resistor and charger converting input, a careful layout will minimize the trace effect. To prevent unintentional charger shut down in normal operation, MOSFET RDS(on) selection and PCB layout is very important. Figure 22 shows a improvement PCB layout example and its equivalent circuit. In this layout, the system current path and charger input current path is not separated, as a result, the system current causes voltage drop in the PCB copper and is sensed by the IC. The worst layout is when a system current pull point is after charger input; as a result all system current voltage drops are counted into over current protection comparator. The worst case for IC is when the total system current and charger input current sum equals the DPM current. When the system pulls more current, the charger IC tries to regulate the RAC current as a constant current by reducing the charging current. I DPM R AC System Path PCB Trace System current R AC R PCB I SYS I CHRGIN Charger input current Charger Input PCB Trace To ACP ACP ACN Charger I BAT To ACN (a) PCB Layout (b) Equivalent Circuit Figure 22. Need improve PCB layout example. Figure 23 shows the optimized PCB layout example. The system current path and charge input current path is separated, as a result the IC only senses charger input current caused PCB voltage drop and minimized the possibility of unintentional charger shut down in normal operation. This also makes PCB layout easier for high system current application. 30 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 R AC System Path PCB Trace I DPM System current Single point connection at RAC I SYS R AC R PCB Charger input current ACP To ACP To ACN ACN I CHRGIN Charger I BAT Charger Input PCB Trace (a) PCB Layout (b) Equivalent Circuit Figure 23. Optimized PCB layout example. The total voltage drop sensed by IC can be express as the following equation. Vtop = RAC x IDPM + RPCB x (ICHRGIN + (IDPM - ICHRGIN) x k) + RDS(on) x IPEAK (15) where the RAC is the AC adapter current sensing resistance, IDPM is the DPM current set point, RPCB is the PCB trace equivalent resistance, ICHRGIN is the charger input current, k is the PCB factor, RDS(on) is the high side MOSFET turn on resistance and IPEAK is the peak current of inductor. Here the PCB factor k equals 0 means the best layout shown in Figure 23 where the PCB trace only goes through charger input current while k equals 1 means the worst layout shown in Figure 22 where the PCB trace goes through all the DPM current. The total voltage drop must below the high side short circuit protection threshold to prevent unintentional charger shut down in normal operation. The low side MOSFET short circuit voltage drop threshold is fixed to typical 110mV. The high side MOSFET short circuit voltage drop threshold can be adjusted via the SMBus command. ChargeOption() bit[8:7] = 00, 01, 10, 11 sets the threshold at 300mV, 500mV, 700mV and 900mV respectively. For a fixed PCB layout, the host should set the proper short circuit protection threshold level to prevent unintentional charger shut down in normal operation. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 31 bq24725 SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 www.ti.com PCB Layout The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 24) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential. 1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on different layers and using vias to make this connection. 2. The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching MOSFETs. 3. Place inductor input terminal to switching MOSFET’s output terminal as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane. 4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see Figure 25 for Kelvin connection for best current accuracy). Place decoupling capacitor on these traces next to the IC 5. Place output capacitor next to the sensing resistor output and ground 6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor ground before connecting to system ground. 7. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling 8. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using power pad as the single ground connection point. Or using a 0Ω resistor to tie analog ground to power ground (power pad should tie to analog ground in this case if possible). 9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible 10. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers. 11. The via size and number should be enough for a given current path. See the EVM design for the recommended component placement with trace and via locations. For the QFN information, See SCBA017 and SLUA271. PHASE VIN C1 High Frequency Current Path R1 L1 VBAT BAT GND C2 Figure 24. High Frequency Current Path 32 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 bq24725 www.ti.com SLUS702A – JULY 2010 – REVISED NOVEMBER 2010 Charge Current Direction R SNS To Inductor To Capacitor and battery Current Sensing Direction To SRP and SRN pin Figure 25. Sensing resistor PCB layout. SPACRE REVISION HISTORY Changes from Original (July 2010) to Revision A Page • Changed the Functional Block Diagrams, Figure 1 and Figure 2 ......................................................................................... 2 • Updated the Test Conditions for QUIESCENT CURRENT .................................................................................................. 6 • Updated the description for the SRN and SRP pins ........................................................................................................... 12 • Deleted C12, added R14 and R15 in Table 8 .................................................................................................................... 25 • Added section: Negative Output Voltage Protection .......................................................................................................... 26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Links :bq24725 33 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) BQ24725RGRR ACTIVE VQFN RGR 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ725 BQ24725RGRT ACTIVE VQFN RGR 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ725 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of