bq24726
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SLUSA79A – JULY 2010 – REVISED NOVEMBER 2010
1-4 Cell Li+ Battery SMBus Charge Controller with N-Channel Reverse Blocking MOSFET
Gate Driver and Advanced Circuit Protection
Check for Samples: bq24726
FEATURES
1
•
•
•
•
•
Portable Notebook Computers, UMPC,
Ultra-Thin Notebook, and Netbook
Personal Digital Assistant
Handheld Terminal
Industrial and Medical Equipment
Portable Equipment
BTST
REGN
The bq24726 charges one, two, three or four series
Li+ cells, and is available in a 20-pin, 3.5 x 3.5 mm2
QFN package.
20
19
18
17
16
ACN 1
ACP
CMSRC
2
bq24726
3
ACDRV 4
ACOK
15
LODRV
14
GND
13
SRP
12
SRN
11 IFAULT
5
6
7
8
9
10
ILIM
APPLICATIONS
The bq24726 provides an IFAULT output to alarm if
any MOSFET fault or input over current occurs. This
alarm output allows users to turn off input power
selectors when the fault occurs.
SCL
•
•
•
•
•
The bq24726 uses internal input current register or
external ILIM pin to throttle down PWM modulation to
reduce the charge current.
HIDRV
•
SMBus controlled input current, charge current, and
charge voltage DACs allow for high regulation
accuracies that can be programmed by the system
power management micro-controller.
SDA
•
The bq24726 utilize charge pump to drive n-channel
RBFET to improve system efficiency.
PHASE
•
The bq24726 is a high-efficiency, synchronous
battery charger, offering low component count for
space-constraint, multi-chemistry battery charging
applications.
IOUT
•
DESCRIPTION
VCC
•
SMBus Host-Controlled NMOS-NMOS
Synchronous Buck Converter with
Programmable 615kHz, 750kHz, and 885kHz
Switching Frequency
Internal Charge Pump Driving Reverse
Blocking MOSFET (RBFET)
Real Time System Control on ILIM pin to Limit
Charge Current
Enhanced Safety Features for Over Voltage
Protection, Over Current Protection, Battery,
Inductor, and MOSFET Short Circuit Protection
Programmable Input Current, Charge Voltage,
Charge Current Limits
– ±0.5% Charge Voltage Accuracy up to 19.2V
– ±3% Charge Current Accuracy up to 8.128A
– ±3% Input Current Accuracy up to 8.064A
– ±2% 20x Adapter Current or Charge Current
Amplifier Output Accuracy
Programmable Adapter Detection and
Indicator
Integrated Soft Start
Integrated Loop Compensation
AC Adapter Operating Range 5V-24V
15µA Off-State Battery Discharge Current
20-pin 3.5 x 3.5 mm2 QFN Package
ACDET
•
2
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
bq24726
SLUSA79A – JULY 2010 – REVISED NOVEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Reverse
Input
Protection
Q6
BSS138W
R12
1M
R13
3.01M
Q1 (ACFET)
Si4435DDY
Adapter +
Ri
2?
Ci
2.2µF
Adapter -
D2
BAT54C
Q2 (RBFET)
FDS6680A
RAC 10m?
SYSTEM
C1
0.1µF
Controlled
By Host
C3
0.1µF
R11
4.02k
C5
1µF
ACN
C2
0.1µF
R10
4.02k
Total
Csys
220µF
R9
10Ω
VCC
Q5 (BATFET)
Si4435DDY
Controlled
By Host
ACP
D3
BAT30K
C6
1µF
CMSRC
REGN
D4
RB751V40
BTST
C8
10uF
ACDET
+1.5V
If no adapter,
and Iout is
needed, this
rail is on
D1
BAT54
ACDRV
R1
430k
R2
66.5k
R14
100k
R8
100k
MODADJ
+3.3V
HOST
Q7
MMST3904
R3
10k
R4
10k
R5
10k
HIDRV
ILIM
R7
316k
U1
bq24726
R6
10k
C7
0.047µF
Q3
Sis412DN
C9
10uF
RSR
10m?
Pack +
PHASE
L1
4.7µH
Q4
Sis412DN
LODRV
C10
10µF
C11
10µF
Pack -
SDA
SMBus
GND
SCL
SRP
ACOK
Dig I/O
*
R16
7.5Ω
*
C13
0.1µF
SRN
IFAULT
ADC
R15
10Ω
C14
0.1µF
IOUT
C4
100p
PowerPad
Fs = 750kHz, Iadpt = 4.096A, Ichrg = 2.944A, Ilim = 4A, Vchrg = 12.592V, 90W adapter and 3S2P battery pack
See the application information about negative output voltage protection for hard shorts on battery to ground or
battery reverse connection.
Figure 1. Typical System Schematic
ORDERING INFORMATION
2
PART NUMBER
IC MARKING
PACKAGE
bq24726
BQ726
20-PIN 3.5 x 3.5mm2 QFN
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ORDERING NUMBER
(Tape and Reel)
QUANTITY
bq24726RGRR
3000
bq24726RGRT
250
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) :bq24726
bq24726
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SLUSA79A – JULY 2010 – REVISED NOVEMBER 2010
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
(2)
VALUE
SRN, SRP, ACN, ACP, CMSRC, VCC
Voltage range
Maximum difference voltage
UNIT
–0.3 to 30
PHASE
–2 to 30
ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK, IFAULT
–0.3 to 7
BTST, HIDRV, ACDRV
–0.3 to 36
SRP–SRN, ACP–ACN
–0.5 to 0.5
V
Junction temperature range, TJ
–40 to 155
°C
Storage temperature range, Tstg
–55 to 155
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
THERMAL INFORMATION
bq24726
THERMAL METRIC
(1)
RGR
UNITS
20 PINS
qJA
Junction-to-ambient thermal resistance (2)
yJT
Junction-to-top characterization parameter (3)
Junction-to-board characterization parameter
yJB
(1)
(2)
(3)
(4)
46.8
0.6
(4)
°C/W
15.3
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX
SRN, SRP, ACN, ACP, CMSRC, VCC
Voltage range
Maximum difference voltage
PHASE
ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK, IFAULT
0
24
-2
24
0
6.5
UNIT
V
BTST, HIDRV, ACDRV
0
30
SRP–SRN, ACP–ACN
–0.2
0.2
V
0
125
°C
–55
150
°C
Junction temperature range, TJ
Storage temperature range, Tstg
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bq24726
SLUSA79A – JULY 2010 – REVISED NOVEMBER 2010
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ELECTRICAL CHARACTERISTICS
4.5 V ≤ V(VCC) ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CONDITIONS
VVCC_OP
VCC Input voltage operating range
4.5
24
V
19.2
V
16.884
V
CHARGE VOLTAGE REGULATION
VBAT_REG_RNG
BAT voltage regulation range
1.024
ChargeVoltage() = 0x41A0H
ChargeVoltage() = 0x3130H
VBAT_REG_ACC
Charge Voltage Regulation Accuracy
ChargeVoltage() = 0x20D0H
ChargeVoltage() = 0x1060H
16.716
16.8
-0.5%
12.529
0.5%
12.592
–0.5%
8.35
V
0.5%
8.4
–0.6%
4.163
12.655
8.45
V
0.6%
4.192
4.221
V
–0.7%
0.7%
0
81.28
mV
4219
mA
CHARGE CURRENT REGULATION
VIREG_CHG_RNG
Charge Current Regulation Differential
Voltage Range
VIREG_CHG = VSRP - VSRN
ChargeCurrent() = 0x1000H
ChargeCurrent() = 0x0800H
ICHRG_REG_ACC
Charge Current Regulation Accuracy 10mΩ
current sensing resistor
ChargeCurrent() = 0x0200H
ChargeCurrent() = 0x0100H
ChargeCurrent() = 0x0080H
3973
4096
–3%
1946
3%
2048
–5%
410
512
614
mA
20%
256
–33%
64
mA
5%
–20%
172
2150
340
mA
33%
128
192
mA
–50%
50%
0
80.64
mV
4219
mA
INPUT CURRENT REGULATION
VIREG_DPM_RNG
Input current regulation differential voltage
range
VIREG_DPM = VACP – VACN
InputCurrent() = 0x1000H
InputCurrent() = 0x0800H
IDPM_REG_ACC
Input current regulation accuracy 10mΩ
current sensing resistor
InputCurrent() = 0x0400H
InputCurrent() = 0x0200H
3973
4096
–3%
1946
3%
2048
–5%
870
mA
5%
1024
–15%
384
2150
1178
mA
15%
512
–25%
640
mA
25%
INPUT CURRENT OR CHARGE CURRENT SENSE AMPLIFIER
VACP/N_OP
Input common mode range
Voltage on ACP/ACN
4.5
24
V
VSRP/N_OP
Output Common Mode Range
Voltage on SRP/SRN
0
19.2
V
VIOUT
IOUT Output Voltage Range
0
1.6
IIOUT
IOUT Output Current
0
1
AIOUT
Current Sense Amplifier Gain
V(ICOUT)/V(SRP-SRN) or V(ACP-ACN)
V(SRP-SRN) or V(ACP-ACN) = 40.96mV
VIOUT_ACC
CIOUT_MAX
4
Current Sense Output Accuracy
Maximum Output Load Capacitance
20
–2%
V/V
2%
V(SRP-SRN) or V(ACP-ACN) = 20.48mV
–4%
4%
V(SRP-SRN) or V(ACP-ACN) = 10.24mV
–15%
15%
V(SRP-SRN) or V(ACP-ACN) = 5.12mV
–20%
20%
V(SRP-SRN) or V(ACP-ACN) = 2.56mV
–33%
33%
V(SRP-SRN) or V(ACP-ACN) = 1.28mV
–50%
50%
For stability with 0 to 1mA load
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V
mA
100
pF
Copyright © 2010, Texas Instruments Incorporated
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bq24726
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SLUSA79A – JULY 2010 – REVISED NOVEMBER 2010
ELECTRICAL CHARACTERISTICS (continued)
4.5 V ≤ V(VCC) ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6.5
UNIT
REGN REGULATOR
VREGN_REG
REGN regulator voltage
IREGN_LIM
REGN current limit
CREGN
REGN Output Capacitor Required for
Stability
VVCC > 6.5V, VACDET > 0.6V (0-55mA load)
5.5
6
VREGN = 0V, VVCC > UVLO charge enabled and not in
TSHUT
65
80
7
16
VREGN = 0V, VVCC > UVLO charge disabled or in
TSHUT
ILOAD = 100µA to 65mA
V
mA
1
µF
INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)
UVLO
AC Under-voltage rising threshold
VVCC rising
AC Under-voltage hysteresis, falling
VVCC falling
3.5
3.75
4
340
V
mV
FAST DPM COMPARATOR (FAST_DPM)
VFAST_DPM
Fast DPM comparator stop charging rising
threshold with respect to input current limit,
voltage across input sense resistor rising
edge (specified by design)
108%
QUIESCENT CURRENT
IBAT
Total battery leakage current to ISRP + ISRN
+ IPHASE + IVCC + IACP + IACN
VVCC < VBAT = 16.8V, TJ = 0 to 85°C
ISTANDBY
Standby quiescent current, IVCC + IACP +
IACN
VVCC > UVLO, VACDET > 0.6V, charge disabled,
TJ = 0 to 85°C
IAC_NOSW
Adapter bias current during charge,
IVCC + IACP + IACN
IAC_SW
Adapter bias current during charge,
IVCC + IACP + IACN
15
µA
0.5
1
mA
VVCC > UVLO, 2.4V < VACDET < 3.15V,
charge enabled, no switching, TJ = 0 to 85°C
1.5
3
mA
VVCC > UVLO, 2.4V < VACDET < 3.15V,
charge enabled, switching, MOSFET Sis412DN
10
mA
ACOK COMPARATOR
VACOK_RISE
ACOK rising threshold
VVCC>VUVLO, VACDET rising
2.376
2.4
2.424
VACOK_FALL_HYS
ACOK falling hysteresis
VVCC>VUVLO, VACDET falling
35
55
75
mV
1.3
1.7
s
ACOK rising deglitch (Specified by design)
VVCC>VUVLO, VACDET rising above 2.4V,
ChargeOption() bit [15] = 0 (default)
0.9
tACOK_RISE_DEG
10
50
0.57
0.8
VVCC>VUVLO, VACDET rising above 2.4V,
ChargeOption() bit [15] = 1
VWAKEUP_RISE
WAKEUP detect rising threshold
VVCC>VUVLO, VACDET rising
VWAKEUP_FALL
WAKEUP detect falling threshold
VVCC>VUVLO, VACDET falling
0.3
0.51
V
ms
V
V
VCC to SRN COMPARATOR (VCC_SRN)
VVCC-SRN_FALL
VCC-SRN falling threshold
VVCC falling towards VSRN
70
125
180
mV
VVCC-SRN
VCC-SRN rising hysteresis
VVCC rising above VSRN
70
120
170
mV
_RHYS
CMSRC to SRN COMPARATOR (CMSRC_SRN)
VCS-SRN_RISE
CMSRC to SRN rising threshold
VCMSRC rising above VSRN
300
390
480
mV
VCS-SRN_FHYS
CMSRC to SRN falling hysteresis
VCMSRC falling towards VSRN
180
240
300
mV
ChargeOption() bit [8:7] = 00
200
300
450
ChargeOption() bit [8:7] = 01
330
500
700
ChargeOption() bit [8:7] = 10 (default)
450
700
1000
ChargeOption() bit [8:7] = 11
600
900
1250
40
110
160
HIGH SIDE IFAULT COMPARATOR (IFAULT_HI) (1)
VIFAULT_HI_RISE
ACP to PHASE rising threshold
mV
LOW SIDE IFAULT COMPARATOR (IFAULT_LOW)
VIFAULT_LOW_RISE
PHASE to GND rising threshold
mV
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
VACOV
ACDET over-voltage rising threshold
VACDET rising
3.05
3.15
3.25
V
VACOV_HYS
ACDET over-voltage falling hysteresis
VACDET falling
50
75
100
mV
(1)
User can adjust threshold via SMBus ChargeOption() REG0x12.
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bq24726
SLUSA79A – JULY 2010 – REVISED NOVEMBER 2010
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ELECTRICAL CHARACTERISTICS (continued)
4.5 V ≤ V(VCC) ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ChargeOption() bit [2:1] = 01
120%
133%
145%
ChargeOption() bit [2:1] = 10 (default)
150%
166%
180%
ChargeOption() bit [2:1] = 11
200%
222%
240%
40
45
50
mV
INPUT OVER-CURRENT COMPARATOR (ACOC) (2)
Adapter over-current rising threshold with
respect to input current limit, voltage across
input sense resistor rising edge
VACOC
VACOC_min
Min ACOC threshold clamp voltage
ChargeOption() Bit [2:1] = 01 (133%), InputCurrent ()
= 0x0400H (10.24mV)
VACOC_max
Max ACOC threshold clamp voltage
ChargeOption() Bit [2:1] = 11 (222%), InputCurrent ()
= 0x1F80H (80.64mV)
140
150
160
mV
tACOC_DEG
ACOC deglitch time (specified by design)
Voltage across input sense resistor rising to disable
charge
1.7
2.5
3.3
ms
103%
104%
106%
BAT OVER-VOLTAGE COMPARATOR (BAT_OVP)
VOVP_RISE
Over-voltage rising threshold as percentage VSRN rising
of VBAT_REG
VOVP_FALL
Over-voltage falling threshold as
percentage of VBAT_REG
VSRN falling
102%
CHARGE OVERCURRENT COMPARATOR (CHG_OCP)
Charge over current rising threshold,
measure voltage drop across current
sensing resistor
VOCP
ChargeCurrent()=0x0xxxH
54
60
66
ChargeCurrent()=0x1000H – 0x17C0H
80
90
100
ChargeCurrent()=0x1800 H– 0x1FC0H
110
120
130
1
5
9
mV
CHARGE UNDER-CURRENT COMPARATOR (CHG_UCP)
VUCP_FALL
Charge undercurrent falling threshold
VSRP falling towards VSRN
mV
LIGHT LOAD COMPARATOR (LIGHT_LOAD)
VLL_FALL
Light load falling threshold
Measure voltage drop across current sensing resistor
1.25
mV
VLL_RISE_HYST
Light load rising hysteresis
Measure voltage drop across current sensing resistor
1.25
mV
BATTERY LOWV COMPARATOR (BAT_LOWV)
VBATLV_FALL
Battery LOWV falling threshold
VSRN falling
VBATLV_RHYST
Battery LOWV rising hysteresis
VSRN rising
2.4
200
2.5
2.6
mV
V
IBATLV
Battery LOWV charge current limit
10 mΩ current sensing resistor
0.5
A
THERMAL SHUTDOWN COMPARATOR (TSHUT)
TSHUT
Thermal shutdown rising temperature
Temperature rising
155
°C
TSHUT_HYS
Thermal shutdown hysteresis, falling
Temperature falling
20
°C
VILIM_FALL
ILIM as CE falling threshold
VILIM falling
60
75
90
mV
VILIM_RISE
ILIM as CE rising threshold
VILIM rising
90
105
120
mV
0.8
V
1
mA
ILIM COMPARATOR
LOGIC INPUT (SDA, SCL)
VIN_
VIN_
IIN_
LO
Input low threshold
HI
Input high threshold
Input bias current
LEAK
2.1
V=7V
V
–1
LOGIC OUTPUT OPEN DRAIN (ACOK, SDA, IFAULT)
VOUT_ LO
Output saturation voltage
5 mA drain current
500
mV
IOUT_ LEAK
Leakage current
V=7V
–1
1
mA
Input bias current
V=7V
–1
1
mA
FSW
PWM switching frequency
ChargeOption () bit [9] = 0 (Default)
600
750
900
kHz
FSW+
PWM increase frequency
ChargeOption() bit [10:9] = 11
665
885
1100
kHz
FSW–
PWM decrease frequency
ChargeOption() bit [10:9] = 01
465
615
765
kHz
ANALOG INPUT (ACDET, ILIM)
IIN_
LEAK
PWM OSCILLATOR
(2)
6
User can adjust threshold via SMBus ChargeOption() REG0x12.
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SLUSA79A – JULY 2010 – REVISED NOVEMBER 2010
ELECTRICAL CHARACTERISTICS (continued)
4.5 V ≤ V(VCC) ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RBFET GATE DRIVER (ACDRV)
IRBFET
ACDRV charge pump current limit
VRBFET
Gate drive voltage on RBFET
RACDRV_LOAD
Minimum load resistance between ACDRV
and CMSRC
RACDRV_OFF
ACDRV turn-off resistance
VACFET_LOW
Stop charging when Vgs voltage is low
(specified by design)
VACDRV–VCMSRC when VVCC> UVLO
40
60
5.5
6.1
mA
6.5
500
I = 30µA
5
V
kΩ
6.2
7.4
5.9
kΩ
V
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON
High side driver (HSD) turn-on resistance
VBTST – VPH = 5.5 V, I = 10mA
12
20
Ω
RDS_HI_OFF
High side driver turn-off resistance
VBTST – VPH = 5.5 V, I = 10mA
0.65
1.3
Ω
VBTST_REFRESH
Bootstrap refresh comparator threshold
voltage
VBTST – VPH when low side refresh pulse is requested
4.3
4.7
3.85
V
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON
Low side driver (LSD) turn-on resistance
VREGN = 6 V, I = 10 mA
15
25
Ω
RDS_LO_OFF
Low side driver turn-off resistance
VREGN = 6 V, I = 10 mA
0.9
1.4
Ω
PWM DRIVER TIMING
tLOW_HIGH
Driver dead time from low side to high side
20
ns
tHIGH_LOW
Driver dead time from high side to low side
20
ns
INTERNAL SOFT START
ISTEP
Soft start current step
In CCM mode 10mΩ current sensing resistor
64
mA
tSTEP
Soft start current step time
In CCM mode 10mΩ current sensing resistor
240
ms
SMBus TIMING CHARACTERISTICS
tR
SCLK/SDATA rise time
tF
SCLK/SDATA fall time
1
tW(H)
SCLK pulse width high
4
tW(L)
SCLK Pulse Width Low
4.7
ms
tSU(STA)
Setup time for START condition
4.7
ms
tH(STA)
START condition hold time after which first
clock pulse is generated
4
ms
tSU(DAT)
Data setup time
250
ns
tH(DAT)
Data hold time
300
ns
tSU(STOP)
Setup time for STOP condition
4
µs
t(BUF)
Bus free time between START and STOP
condition
4.7
ms
FS(CL)
Clock Frequency
10
100
kHz
35
ms
ms
300
ns
50
ms
HOST COMMUNICATION FAILURE
ttimeout
SMBus bus release timeout (3)
25
tBOOT
Deglitch for watchdog reset signal
10
tWDI
Watchdog timeout period, ChargeOption()
bit [14:13] = 01 (4)
35
44
53
s
tWDI
Watchdog timeout period, ChargeOption()
bit [14:13] = 10 (4)
70
88
105
s
tWDI
Watchdog timeout period, ChargeOption()
bit [14:13] = 11 (4) (default)
140
175
210
s
(3)
(4)
ms
Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
User can adjust threshold via SMBus ChargeOption() REG0x12.
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Figure 2. SMBus Communication Timing Waveforms
8
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TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
FIGURE NO.
VCC, ACDET, REGN and ACOK Power up
Figure 3
Charge Enable by ILIM
Figure 4
Current Soft-start
Figure 5
Charge Disable by ILIM
Figure 6
Continuous Conduction Mode Switching Waveforms
Figure 7
Cycle-by-Cycle Synchronous to Non-synchronous
Figure 8
100% Duty and Refresh Pulse
Figure 9
System Load Transient (Input DPM)
Figure 10
Battery Insertion
Figure 11
Battery to Ground Short Protection
Figure 12
Battery to Ground Short Transition
Figure 13
Efficiency vs Output Current
Figure 14
CH1: VCC, 10V/div, CH2: ACDET, 2V/div, CH3: ACOK, 5V/div,
CH4: REGN, 5V/div, 200ms/div
Figure 3. VCC, ACDET, REGN and ACOK Power Up
CH2: ILIM, 1V/div, CH4: inductor current, 1A/div, 10ms/div
CH1: PHASE, 10V/div, CH2: Vin, 10V/div, CH3: LODRV, 5V/div,
CH4: inductor current, 2A/div, 2ms/div
Figure 5. Current Soft-Start
CH2: ILIM, 1V/div, CH4: inductor current, 1A/div, 4us/div
Figure 4. Charge Enable by ILIM
Figure 6. Charge Disable by ILIM
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CH1: HIDRV, 10V/div, CH2: LODRV, 5V/div, CH3: PHASE, 10V/div,
CH4: inductor current, 2A/div, 400ns/div
Figure 7. Continuous Conduction Mode Switching
Waveforms
CH1: HIDRV, 10V/div, CH2: LODRV, 5V/div, CH3: PHASE, 10V/div,
CH4: inductor current, 1A/div, 400ns/div
Figure 8. Cycle-by-Cycle Synchronous to
Non-synchronous
CH1: PHASE, 10V/div, CH2: LODRV, 5V/div, CH4: inductor current,
2A/div, 4us/div
Figure 9. 100% Duty and Refresh Pulse
CH2: battery current, 2A/div, CH3: adapter current, 2A/div, CH4:
system load current, 2A/div, 100us/div
CH1: PHASE, 20V/div, CH2: battery voltage, 5V/div, CH3: LODRV,
10V/div, CH4: inductor current, 2A/div, 400us/div
CH1: PHASE, 20V/div, CH2: LODRV, 10V/div, CH3: battery voltage,
5V/div, CH4: inductor current, 2A/div, 2ms/div
Figure 12. Battery to Ground Short Protection
Figure 11. Battery Insertion
10
Figure 10. System Load Transient (Input DPM)
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98
4-cell 16.8 V
97
96
Efficiency - %
95
3-cell 12.6 V
94
93
2-cell 8.4 V
92
91
VI = 20 V,
f = 750 kHz,
L = 4.7 mH
90
89
88
0
0.5
CH1: PHASE, 20V/div, CH2: LODRV, 10V/div, CH3: battery voltage,
5V/div, CH4: inductor current, 2A/div, 4us/div
Figure 13. Battery to Ground Short Transition
1
1.5
2
2.5
Charge Current
3
3.5
4
4.5
Figure 14. Efficiency vs Output Current
PIN FUNCTIONS – 20-PIN QFN
PIN
NO.
DESCRIPTION
NAME
1
ACN
Input current sense resistor negative input. Place an optional 0.1 µF ceramic capacitor from ACN to GND for
common-mode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential mode filtering.
2
ACP
Input current sense resistor positive input. Place a 0.1µF ceramic capacitor from ACP to GND for common-mode
filtering. Place a 0.1 µF ceramic capacitor from ACN to ACP to provide differential-mode filtering.
3
CMSRC
ACDRV charge pump source input. Place a 4kΩ resistor from CMSRC to the reverse-blocking n-channel MOSFET
REFET (Q2) source and parallel with a diode with cathode connect to CMSRC pin.
4
ACDRV
Charge pump output to drive reverse-blocking n-channel MOSFET (RBFET). ACDRV voltage is 6V above CMSRC
when voltage on ACDET pin is above 0.6V, voltage on VCC pin is above UVLO and voltage on CMSRC pin is 390mV
above voltage on SRN pin so that ACFET is turned on forward bias RBFET body diode. Place a 4kΩ resistor from
ACDRV to the gate of RBFET limits the in-rush current on ACDRV pin.
5
ACOK
AC adapter detect open drain output. It is pulled HIGH to external pull-up supply rail by external pull-up resistor when
voltage on ACDET pin is between 2.4V and 3.15V, voltage on VCC pin is above UVLO and voltage on VCC pin is
245mV above voltage on SRN pin, indicating a valid adapter is present to start charge. If any one of the above
conditions can not meet, it is pulled LOW to GND by internal MOSFET. Connect a 10kΩ pull up resistor from ACOK pin
to the pull-up supply rail.
6
ACDET
Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to
ACDET pin to GND pin. When ACDET pin is above 0.6V and VCC above UVLO, REGN LDO is present, ACOK
comparator and IOUT are both active.
7
IOUT
Buffered adapter or charge current output, selectable with SMBus command ChargeOption(). IOUT voltage is 20 times
the differential voltage across sense resistor. Place a 100pF or less ceramic decoupling capacitor from IOUT pin to
GND.
8
SDA
SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. Connect a 10kΩ
pull-up resistor according to SMBus specifications.
9
SCL
SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. Connect a 10kΩ
pull-up resistor according to SMBus specifications.
10
ILIM
Charge current limit input. Program ILIM voltage by connecting a resistor divider from system reference 3.3V rail to ILIM
pin to GND pin. The lower of ILIM voltage or DAC limit voltage sets charge current regulation limit. To disable the
control on ILIM, set ILIM above 1.6V. Once voltage on ILIM pin falls below 75mV, charge is disabled. Charge is enabled
when ILIM pin rises above 105mV.
11
IFAULT
Open-drain output, it is pulled LOW by internal MOSFET when ACOC or short circuit is detected. It is pulled HIGH to
external pull-up supply rail by external pull-up resistor in normal condition.
12
SRN
Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect the SRN pin to a
7.5Ω resistor first then from resistor another terminal connect a 0.1µF ceramic capacitor to GND for common-mode
filtering and connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to
provide differential mode filtering. See the application information about negative output voltage protection for hard
shorts on battery to ground or battery reverse connection by adding small resistor.
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PIN FUNCTIONS – 20-PIN QFN (continued)
PIN
NO.
DESCRIPTION
NAME
13
SRP
Charge current sense resistor positive input. Connect SRP pin to a 10Ω resistor first then from resistor another terminal
connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide
differential mode filtering. See application information about negative output voltage protection for hard shorts on battery
to ground or battery reverse connection by adding small resistor.
14
GND
IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through the power
pad underneath IC.
15
LODRV
Low side power MOSFET driver output. Connect to low side n-channel MOSFET gate.
16
REGN
Linear regulator output. REGN is the output of the 6V linear regulator supplied from VCC. The LDO is active when
voltage on ACDET pin is above 0.6V and voltage on VCC is above UVLO. Connect a 1µF ceramic capacitor from
REGN to GND.
17
BTST
High side power MOSFET driver power supply. Connect a 0.047µF capacitor from BTST to PHASE, and a bootstrap
Schottky diode from REGN to BTST.
18
HIDRV
High side power MOSFET driver output. Connect to the high side n-channel MOSFET gate.
19
PHASE
High side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET.
20
VCC
Input supply, diode OR from adapter or battery voltage. Use 10Ω resistor and 1µF capacitor to ground as low pass filter
to limit inrush current.
PowerPAD™
Exposed pad beneath the IC. Analog ground and power ground star-connected only at the PowerPad plane. Always
solder PowerPAD to the board, and have vias on the PowerPAD plane connecting to analog ground and power ground
planes. It also serves as a thermal pad to dissipate the heat.
12
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FUNCTIONAL BLOCK DIAGRAM
3.75V
bq24726 Block Diagram
UVLO
** Threshold or deglitch time is adjustable by ChargeOption()
VCC 20
EN_REGN
CMSRC+6V
WAKEUP
ACDET 6
CMSRC
0.6V
ACDRV
CHARGE
PUMP
CMSRC-SRN
SRN+390mV
4 ACDRV
EN_REGN
ACOVP
3 CMSRC
3.15V
ACGOOD
WATCHDOG
TIMER
175s **
VCC_SRN
2.4V
ACOK 5
EN_CHRG
WATCHDOG
TIMEOUT
ACOK_DRV
1.3s rising deglitch**
11 IFAULT
VREF_IAC
ACDRV
ACP 2
ACDRV-CMSRC
IFAULT
20X
CMSRC+5.9V
ACN 1
IOUT 7
1X
Type III
Compensation
MUX
FBO
EAI
ACOK_DRV
CHARGE_INHIBIT
17 BTST
IOUT_SEL
DAC_VALID
ILIM 10
HSON
18 HIDRV
EAO
PWM
SRP 13
20X
SRN 12
19 PHASE
VREF_ICHG
RAMP
Frequency **
200mV
VFB
EN_REGN
REGN
LDO
16 REGN
ILIM
LSON
CE
15 LODRV
105mV
VREF_VREG
10uA
4mA in
BATOVP
Tj
14 GND
TSHUT
WAKEUP
155?C
Driver Logic
SRP-SRN
DAC_VALID
SMBus Interface
SDA 8
SCL 9
ChargeOption()
ChargeCurrent()
ChargeVoltage()
InputCurrent()
ManufactureID()
DeviceID()
CHARGE_INHIBIT
VREF_VREG
VREF_ICHG
CHG_OCP
60mV/90mV/120mV
5mV
CHG_UCP
SRP-SRN
VREF_IAC
IOUT_SEL
1.25mV
LIGHT_LOAD
SRP-SRN
ACP-PH
IFAULT_HI
700mV **
PH-GND
IFAULT_LO
110mV
ACP-ACN
ACOC
1.66xVREF_IAC **
ACP-ACN
FAST_DPM
1.08xVREF_IAC
4.3V
REFRESH
BTST-PH
VFB
BATOVP
104%VREF_VREG
2.5V
BAT_LOWV
SRN
VCC
VCC-SRN
SRN+245mV
Figure 15. Functional Block Diagram for bq24726
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DETAILED DESCRIPTION
SMBus Interface
The bq24726 operates as a slave, receiving control inputs from the embedded controller host through the SMBus
interface. The bq24726 uses a simplified subset of the commands documented in System Management Bus
Specification V1.1, which can be downloaded from www.smbus.org. The bq24726 uses the SMBus Read-Word
and Write-Word protocols (see Figure 16) to communicate with the smart battery. The bq24726 performs only as
a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In
addition, the bq24726 has two identification registers a 16-bit device ID register (0xFFH) and a 16-bit
manufacturer ID register (0xFEH).
SMBus communication is enabled with the following conditions:
• VVCC is above UVLO;
• VACDET is above 0.6V;
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose
pull-up resistors (10kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.
Communication starts when the master signals a START condition, which is a high-to-low transition on SDA,
while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a
low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 17 and
Figure 18 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and
data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is
low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising
edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24726 because either the
master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24726
supports the charger commands as described in Table 2.
a) Write-Word Format
S
SLAVE
ADDRESS
W
ACK
7 BITS
1b
MSB LSB
0
LOW DATA
BYTE
ACK
1b
8 BITS
0
MSB LSB
COMMAND
BYTE
ACK
1b
8 BITS
0
MSB LSB
Preset to 0b0001001
ChargeCurrent() = 0x14H D7
ChargeVoltage() = 0x15H
InputCurrent() = 0x3FH
ChargeOption() = 0x12H
HIGH DATA
BYTE
ACK
1b
8 BITS
1b
0
MSB LSB
0
D0
D15
P
D8
b) Read-Word Format
S
SLAVE
ADDRESS
W
ACK
7 BITS
1b
MSB LSB
0
COMMAND
BYTE
ACK
1b
8 BITS
1b
0
MSB LSB
0
S
SLAVE
ADDRESS
7 BITS
MSB
LSB
R
ACK
1b
1b
1
0
LOW DATA
BYTE
8 BITS
MSB
LSB
ACK
1b
0
HIGH DATA
BYTE
8 BITS
MSB
LSB
NACK
P
1b
1
Preset to 0b0001001
DeviceID() = 0xFFH
Preset to
D7 D0
D15 D8
ManufactureID() = 0xFEH
0b0001001
ChargeCurrent() = 0x14H
ChargeVoltage() = 0x15H
InputCurrent() = 0x3FH
ChargeOption() = 0x12H
LEGEND:
S = START CONDITION OR REPEATED START CONDITION
P = STOP CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW)
NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
W = WRITE BIT (LOGIC-LOW)
R = READ BIT (LOGIC-HIGH)
MASTER TO SLAVE
SLAVE TO MASTER
Figure 16. SMBus Write-Word and Read-Word Protocols
14
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Figure 17. SMBus Write Timing
A
B
tLOW
C
D
E
F
G
H
I
J
K
t HIGH
SMBCLK
SMBDATA
A = START CONDITION
E = SLAVE PULLS SMBDATA LINE LOW
I = ACKNOWLEDGE CLOCK PULSE
B = MSB OF ADDRESS CLOCKED INTO SLAVE
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
J = STOP CONDITION
C = LSB OF ADDRESS CLOCKED INTO SLA VE
G = MSB OF DATA CLOCKED INTO MASTER
K = NEW START CONDITION
D = R/W BIT CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO MASTER
Figure 18. SMBus Read Timing
Battery-Charger Commands
The bq24726 supports six battery-charger commands that use either Write-Word or Read-Word protocols, as
summarized in Table 2. ManufacturerID() and DeviceID() can be used to identify the bq24726. The
ManufacturerID() command always returns 0x0040H and the DeviceID() command always returns 0x0009H.
Table 2. Battery Charger Command Summary
REGISTER ADDRESS
REGISTER NAME
READ/WRITE
DESCRIPTION
POR STATE
0x12H
ChargeOption()
Read or Write
Charger Options Control
0x7904H
0x14H
ChargeCurrent()
Read or Write
7-Bit Charge Current Setting
0x0000H
0x15H
ChargeVoltage()
Read or Write
11-Bit Charge Voltage Setting
0x0000H
0x3FH
InputCurrent()
Read or Write
6-Bit Input Current Setting
0x1000H
0XFEH
ManufacturerID()
Read Only
Manufacturer ID
0x0040H
0xFFH
DeviceID()
Read Only
Device ID
0x0009H
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Setting Charger Options
By writing ChargeOption() command (0x12H or 0b00010010), bq24726 allows users to change several charger
options after POR (Power On Reset) as shown in Table 3.
Table 3. Charge Options Register (0x12H)
BIT
BIT NAME
[15]
DESCRIPTION
ACOK Deglitch Time Adjust ACOK deglitch time.
Adjust
0: ACOK deglitch time 1.3s
1: ACOK deglitch time set to minimum ( UVLO;
• 2.4V < VACDET < 3.15V (not in ACOVP condition, nor in low input voltage condition);
• VVCC–VSRN > 245mV (not in sleep mode);
The default delay is 1.3s after ACDET has valid voltage to make ACOK pull high. It can be reduced by SMBus
command (ChargeOption() bit[15]=0 ACOK delay 1.3s, bit[15]=1 ACOK no delay). To change this option, VCC
pin voltage must above UVLO and ACDET pin voltage must above 0.6V to enable IC SMBus communication and
set ChargeOption() bit[15] to 1 to disable the ACOK deglitch timer.
Adapter Over Voltage (ACOVP)
When ACDET pin voltage is higher than 3.15V, it is considered as adapter over voltage. ACOK will be pulled low
and charge will be disabled during ACOVP. RBFET will keep on as long as the turns on conditions are valid. See
the RBFET Turn on and off section for details. System can use ACOK signal to turn off ACFET for adapter over
voltage protection. After ACFET is turned off, RBFET will be turned off when turns off conditions are valid.
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When ACDET pin voltage falls below 3.15V and above 2.4V, it is considered as adapter voltage returns back to
normal voltage. ACOK will be pulled high by external pull up resistor and charge can be resumed if enable
charge conditions are valid. See the Enable and Disable Charging section for details.
RBFET Turn On and Off
The bq24726 has ACDRV pin drive n-channel power MOSFET (RBFET), between CMSRC and ACP (see the
typical application diagram for details). The p-channel ACFET and BATFET are separately driven by system
discrete logic. The RBFET provides reverse adapter voltage protection and battery discharge protection when
adapter is shorted to ground, and minimizes system power dissipation with its low RDS(ON) compared to a
Schottky diode.
When adapter is not present, ACFET turns off by system discrete logic. ACDRV is shorted to CMSRC, and
RBFET has body diode which is reverse biased if battery is connected to system.
When adapter is present IC gives ACOK signal after default 1.3 second delay to system. System discrete logic
can turn on ACFET based on ACOK signal or by its own judgment. When ACFET is turned on the RBFET body
diode will be forward biased and ACDRV voltage will be CMSRC voltage plus 6V to turn on RBFET when the
following conditions are valid:
• VVCC > UVLO;
• VACDET > 0.6V (Not in shut down mode, IC wake up);
• VCMSRC > VSRN + 390mV (RBFET body diode is forward biased);
The gate drive voltage on RBFET is VCMSRC+6V. If the RBFET has been turned on for 10ms, and the voltage
across gate and source is still less than 5.9V, RBFET keeps on, but charge will be disabled to reduce RBFET
power loss. If such failure is detected seven times within 90 seconds, charge will be latched off and an adapter
removal and system shut down (make ACDET < 0.6V to reset IC) is required to start charge again. After 90
seconds, the failure counter will be reset to zero to prevent latch off.
To
•
•
•
turn off RBFET, one of the following conditions should be valid:
VVCC < UVLO;
VACDET < 0.6V (in shut down mode);
VCMSRC < VSRN + 150mV (RBFET body diode almost exits from forward bias condition);
In order to limit the in-rush current on ACDRV pin and CMSRC pin, a 4kΩ resistor is recommended on each of
the pins.
Enable and Disable Charging
In
•
•
•
•
•
•
•
•
Charge mode, the following conditions have to be valid to start charge:
Charge is enabled via SMBus (ChargeOption() bit [0]=0, default is 0, charge enabled);
ILIM pin voltage higher than 105mV;
All three regulation limit DACs have valid value programmed;
ACOK is valid (See the Adapter Detect and ACOK Output section for details);
RBFET turns on and gate voltage is high enough (See "RBFET Turn on and of" for details);
VSRN does not exceed BATOVP threshold;
IC Temperature doesn’t exceed TSHUT threshold;
Not in ACOC condition (See the Input Over Current Protection (ACOC) section for details);
One of the following conditions will stop on-going charging:
• Charge is inhibited via SMBus (ChargeOption() bit[0]=1);
• ILIM pin voltage lower than 75mV;
• One of three regulation limit DACs is set to 0 or out of range;
• ACOK is pulled low (See the Adapter Detect and ACOK Output section for details);
• RBFET gate voltage is not high enough (See the RBFET Turn on and off section for details);
• VSRN exceeds BATOVP threshold;
• TSHUT IC temperature threshold is reached ;
• ACOC is detected (See the Input Over Current Protection (ACOC) section for details);
20
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•
•
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Short circuit is detected (See the Inductor Short, MOSFET Short Protection section for details);
Watchdog timer expires if watchdog timer is enabled (See the Charger Timeout section for details);
Automatic Internal Soft-Start Charger Current
Every time the charge is enabled, the charger automatically applies soft-start on charge current to avoid any
overshoot or stress on the output capacitors or the power converter. The charge current starts at 128mA, and the
step size is 64mA in CCM mode for a 10mΩ current sensing resistor. Each step lasts around 240µs in CCM
mode, till it reaches the programmed charge current limit. No external components are needed for this function.
During DCM mode, the soft start up current step size is larger and each step lasts for longer time period due to
the intrinsic slow response of DCM mode.
High Accuracy Current Sense Amplifier
As an industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current or the
charge current, selectable via SMBUS (ChargeOption() bit[5]=0 select the input current, bit[5]=1 select the
charge current) by host. The CSA senses voltage across the sense resistor by a factor of 20 through the IOUT
pin. Once VCC is above UVLO and ACDET is above 0.6V, CSA turns on and IOUT output becomes valid. If the
user wants to lower the voltage on current monitoring, they could use a resistor divider from IOUT to GND, and
still achieve accuracy over temperature.
A 100pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional
RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay.
Charge Timeout
The bq24726 includes a watchdog timer to terminate charging if the charger does not receive a write
ChargeVoltage() or write ChargeCurrent() command within 175s (adjustable via ChargeOption() command). If a
watchdog timeout occurs all register values keep unchanged but charge is suspended. Write ChargeVoltage() or
write ChargeCurrent() commands must be re-sent to reset watchdog timer and resume charging. The watchdog
timer can be disabled, or set to 44s, 88s or 175s via SMBus command (ChargeOption() bit[14:13]). After
watchdog timeout write ChargeOption() bit[14:13] to disable watchdog timer also resume charging.
Converter Operation
The synchronous buck PWM converter uses a fixed frequency voltage mode control scheme and internal type III
compensation network. The LC output filter gives a characteristic resonant frequency
1
¦o =
2p Lo Co
(3)
The resonant frequency fo is used to determine the compensation to ensure there is sufficient phase margin and
gain margin for the target bandwidth. The LC output filter should be selected to give a resonant frequency of
10–20 kHz nominal for the best performance. Suggest component value as charge current of 750kHz default
switching frequency is shown in Table 7.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is
applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data
sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
Table 7. Suggest Component Value as Charge Current of Default 750kHz
Switching Frequency
Charge Current
2A
3A
4A
6A
8A
Output Inductor Lo (µH)
6.8 or 8.2
5.6 or 6.8
3.3 or 4.7
3.3
2.2
Output Capacitor Co (µF)
20
20
20
30
40
Sense Resistor (mΩ
10
10
10
10
10
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The bq24726 has three loops of regulation: input current, charge current and charge voltage. The three loops are
brought together internally at the error amplifier. The maximum voltage of the three loops appears at the output
of the error amplifier EAO (see Figure 15). An internal saw-tooth ramp is compared to the internal error control
signal EAO to vary the duty-cycle of the converter. The ramp has offset of 200mV in order to allow 0%
duty-cycle.
When the battery charge voltage approaches the input voltage, EAO signal is allowed to exceed the saw-tooth
ramp peak in order to get a 100% duty-cycle. If voltage across BTST and PHASE pins falls below 4.3V, a refresh
cycle starts and low-side n-channel power MOSFET is turned on to recharge the BTST capacitor. It can achieve
duty cycle of up to 99.5%.
Continuous Conduction Mode (CCM)
With sufficient charge current the bq24726’s inductor current never crosses zero, which is defined as continuous
conduction mode. The controller starts a new cycle with ramp coming up from 200mV. As long as EAO voltage is
above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO
voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle, ramp gets reset and
LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to prevent
cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the
low-side power MOSFET conducts the inductor current.
During CCM mode, the inductor current is always flowing and creates a fixed two-pole system. Having the
LSFET turn-on keeps the power dissipation low, and allows safely charging at high currents.
Discontinuous Conduction Mode (DCM)
During the HSFET off time when LSFET is on, the inductor current decreases. If the current goes to zero, the
converter enters Discontinuous Conduction Mode. Every cycle, when the voltage across SRP and SRN falls
below 5mV (0.5A on 10mΩ), the under-current-protection comparator (UCP) turns off LSFET to avoid negative
inductor current, which may boost the system via the body diode of HSFET.
During the DCM mode the loop response automatically changes. It changes to a single pole system and the pole
is proportional to the load current.
Both CCM and DCM are synchronous operation with LSFET turn-on every clock cycle. If the average charge
current goes below 125mA on 10mΩ current sensing resistor or the battery voltage falls below 2.5V, the LSFET
keeps turn-off. The battery charger operates in non-synchronous mode and the current flows through the LSFET
body diode. During non-synchronous operation, the LSFET turns on only for refreshing pulse to charge BTST
capacitor. If the average charge current goes above 250mA on 10mΩ current sensing resistor, the LSFET exits
non-synchronous mode and enters synchronous mode to reduce LSFET power loss.
Input Over Current Protection (ACOC)
The bq24726 cannot maintain the input current level if the charge current has been already reduced to zero.
After the system current continues increasing to the 1.66X of input current DAC set point (with 2.5ms blank out
time), IFAULT is pulled to low and the charge is disabled for 1.3s and will soft start again for charge if ACOC
condition goes away. If such failure is detected seven times in 90 seconds, charge will be latched off and an
adapter removal and system shut down (make ACDET < 0.6V to reset IC) is required to start charge again. After
90 seconds, the failure counter will be reset to zero to prevent latch off.
The ACOC function can be disabled or the threshold can be set to 1.33X, 1.66X or 2.22X of input DPM current
via SMBus command (ChargeOption() bit [2:1]).
Charge Over Current Protection (CHGOCP)
The bq24726 has a cycle-by-cycle peak over-current protection. It monitors the voltage across SRP and SRN,
and prevents the current from exceeding of the threshold based on the DAC charge current set point. The
high-side gate drive turns off for the rest of the cycle when the over-current is detected, and resumes when the
next cycle starts.
The charge OCP threshold is automatically set to 6A, 9A, and 12A on a 10mΩ current sensing resistor based on
charge current register value. This prevents the threshold to be too high which is not safe or too low which can
be triggered in normal operation. Proper inductance should be selected to prevent OCP triggered in normal
operation due to high inductor current ripple.
22
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Battery Over Voltage Protection (BATOVP)
The bq24726 will not allow the high-side and low-side FET to turn-on when the battery voltage at SRN exceeds
104% of the regulation voltage set-point. If BATOVP last over 30ms, charger is completely disabled. This allows
quick response to an over-voltage condition – such as occurs when the load is removed or the battery is
disconnected. A 4mA current sink from SRN to GND is on only during BATOVP and allows discharging the
stored output inductor energy that is transferred to the output capacitors.
Battery Shorted to Ground (BATLOWV)
The bq24726 will disable charge for 1ms if the battery voltage on SRN falls below 2.5V. After 1ms reset, the
charge is resumed with soft-start if all the enable conditions in the Enable and Disable Charging sections are
satisfied. This prevents any overshoot current in inductor which can saturate inductor and may damage the
MOSFET. The charge current is limited to 0.5A on 10mΩ current sensing resistor when BATLOWV condition
persists and LSFET keeps off. The LSFET turns on only for refreshing pulse to charge BTST capacitor.
Thermal Shutdown Protection (TSHUT)
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off for
self-protection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction
temperature falls below 135°C. During thermal shut down, the REGN LDO current limit is reduced to 16mA.
Once the temperature falls below 135°C, charge can be resumed with soft start.
EMI Switching Frequency Adjust
The charger switching frequency can be adjusted ±18% to solve EMI issue via SMBus command.
ChargeOption() bit [9]=0 disable the frequency adjust function. To enable frequency adjust function, set
ChargeOption() bit[9]=1. Set ChargeOption() bit [10]=0 to reduce switching frequency, set bit[10]=1 to increase
switching frequency. If frequency is reduced, for a fixed inductor the current ripple is increased. Inductor value
must be carefully selected so that it will not trig cycle-by-cycle peak over current protection even for the worst
condition such as higher input voltage, 50% duty cycle, lower inductance and lower switching frequency.
Inductor Short, MOSFET Short Protection
The bq24726 has a unique short circuit protection feature. Its cycle-by-cycle current monitoring feature is
achieved through monitoring the voltage drop across RDS(on) of the MOSFETs after a certain amount of blanking
time. In case of MOSFET short or inductor short circuit, the over current condition is sensed by two comparators
and two counters will be triggered. After seven times of short circuit events, the charger will be latched off. To
reset the charger from latch-off status, the IC Vcc pin must be pulled down below UVLO or ACDET pin must be
pulled down below 0.6V. This can be achieved by removing the adapter and shut down the operation system.
The low side MOSFET short circuit voltage drop threshold is fixed to typical 110mV. The high side MOSFET
short circuit voltage drop threshold can be adjusted via SMBus command. ChargeOption() bit[8:7] = 00, 01, 10,
11 set the threshold 300mV, 500mV, 700mV and 900mV respectively.
Due to the certain amount of blanking time to prevent noise when MOSFET just turns on, the cycle-by-cycle
charge over-current protection may detect high current and turn off MOSFET first before the short circuit
protection circuit can detect short condition because the blanking time has not finished. In such a case the
charge may not be able to detect shorts circuit and counter may not be able to count to seven then latch off.
Instead the charge may continuously keep switching with very narrow duty cycle to limit the cycle-by-cycle
current peak value. However, the charger should still be safe and will not cause failure because the duty cycle is
limited to a very short of time and MOSFET should be still inside the safety operation area. During a soft start
period, it may takes long time instead of just seven switching cycles to detect short circuit based on the same
blanking time reason.
Table 8. Component List for Typical System Circuit of Figure 1
PART DESIGNATOR
QTY
DESCRIPTION
C1, C2, C3, C13, C14
5
Capacitor, Ceramic, 0.1µF, 25V, 10%, X7R, 0603
C4
1
Capacitor, Ceramic, 100pF, 25V, 10%, X7R, 0603
C5, C6
2
Capacitor, Ceramic, 1µF, 25V, 10%, X7R, 0603
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Table 8. Component List for Typical System Circuit of Figure 1 (continued)
PART DESIGNATOR
QTY
DESCRIPTION
C7
1
Capacitor, Ceramic, 0.047µF, 25V, 10%, X7R, 0603
C8, C9, C10, C11
4
Capacitor, Ceramic, 10µF, 25V, 10%, X7R, 1206
Ci
1
Capacitor, Ceramic, 2.2µF, 25V, 10%, X7R, 1210
Csys
1
Capacitor, Electrolytic, 220µF, 25V
D1
1
Diode, Schottky, 30V, 200mA, SOT-23, Fairchild, BAT54
D2
1
Diode, Dual Schottky, 30V, 200mA, SOT-23, Fairchild, BAT54C
D3
1
Diode, Schottky, 30V, 300mA, SOD-323, ST, BAT30K
D4
1
Diode, Schottky, 40V 120mA, SOD-323, NXP, RB751V40
Q1, Q5
2
P-channel MOSFET, –30V, –9.4A, SO-8, Vishay Siliconix, Si4435DDY
Q2
1
N-channel MOSFET, 30V, 12.5A, SO-8, Fairchild, FDS6680A
Q3, Q4
2
N-channel MOSFET, 30V, 12A, PowerPAK 1212-8, Vishay Siliconix, SiS412DN
Q6
1
N-channel MOSFET, 50V, 0.2A, SOT-323, Diodes, BSS138W
Q7
1
NPN transistor, 60V, 200mA, SOT-323, Diodes, MMST3904
L1
1
Inductor, SMT, 4.7µH, 5.5A, Vishay Dale, IHLP2525CZER4R7M01
R1
1
Resistor, Chip, 430kΩ, 1/10W, 1%, 0603
R2
1
Resistor, Chip, 66.5kΩ, 1/10W, 1%, 0603
R3, R4, R5, R6
4
Resistor, Chip, 10kΩ, 1/10W, 1%, 0603
R7
1
Resistor, Chip, 316kΩ, 1/10W, 1%, 0603
R8, R14
2
Resistor, Chip, 100kΩ, 1/10W, 1%, 0603
R9
1
Resistor, Chip, 10Ω, 1/4W, 1%, 1206
R10, R11
2
Resistor, Chip, 4.02kΩ, 1/10W, 1%, 0603
R12
1
Resistor, Chip, 1.00MΩ, 1/10W, 1%, 0603
R13
1
Resistor, Chip, 3.01MΩ, 1/10W, 1%, 0603
R15
1
Resistor, Chip, 10Ω, 1/10W, 5%, 0603
R16
1
Resistor, Chip, 7.5Ω, 1/10W, 5%, 0603
RAC, RSR
2
Resistor, Chip, 0.01Ω, 1/2W, 1%, 1206
Ri
1
Resistor, Chip, 2Ω, 1/2W, 1%, 1210
U1
1
Charger controller, 20 pin VQFN, TI, bq24726RGR
APPLICATION INFORMATION
Negative Output Voltage Protection
Reversely insert the battery pack into the charger output during production or hard shorts on battery to ground
will generate negative output voltage on SRP and SRN pin. IC internal electrostatic-discharge (ESD) diodes from
GND pin to SRP or SRN pins and two anti-parallel (AP) diodes between SRP and SRN pins can be forward
biased and negative current can pass through the ESD diodes and AP diodes when output has negative voltage.
Insert two small resistors for SRP and SRN pins to limit the negative current level when output has negative
voltage. Suggest resistor value is 10 Ω for SRP pin and 7-8Ω for SRN pin. After adding resistors, the suggested
pre-charge current is at least 192mA for a 10mΩ current sensing resistor.
Reverse Input Voltage Protection
Q6, R12 and R13 in Figure 1 gives system and IC protection from reversed adapter voltage. In normal operation,
Q6 is turned off by negative Vgs. When adapter voltage is reversed, Q6 Vgs is positive. As a result, Q6 turns on
to short gate and source of Q2 so that Q2 is off. Q2 body diode blocks negative voltage to system. However,
CMSRC and ACDRV pin need R10 and R11 to limit the current due to ESD diode of these pins are turned on.
Q6 must has low Vgs threshold voltage and low Qgs gate charge so it turns on fast enough before Q2 turns on.
R10 and R11 must have enough power rating for the power dissipation when ESD diode is on.
24
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Inductor Selection
The bq24726 has three selectable fixed switching frequencies. Higher switching frequency allows the use of
smaller inductor and capacitor values. Inductor saturation current should be higher than the charging current
(ICHG) plus half the ripple current (IRIPPLE):
ISAT ³ ICHG + (1/2) IRIPPLE
(4)
The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fS) and
inductance (L):
V ´ D ´ (1 - D)
IRIPPLE = IN
fS ´ L
(5)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging
voltage range is from 9V to 12.6V for 3-cell battery pack. For 20V adapter voltage, 10V battery voltage gives the
maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12V to
16.8V, and 12V battery voltage gives the maximum inductor ripple current.
Usually inductor ripple is designed in the range of (20-40%) maximum charging current as a trade-off between
inductor size and efficiency for a practical design.
The bq24726 has charge under current protection (UCP) by monitoring charging current sensing resistor
cycle-by-cycle. The typical cycle-by-cycle UCP threshold is 5mV falling edge corresponding to 0.5A falling edge
for a 10mΩ charging current sensing resistor. When the average charging current is less than 125mA for a 10mΩ
charging current sensing resistor, the low side MOSFET is off until BTST capacitor voltage needs to refresh
charge. As a result, the converter relies on low side MOSFET body diode for the inductor freewheeling current.
Input Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at
50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and
can be estimated by Equation 6:
ICIN = ICHG ´
D × (1 - D)
(6)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred
for 19-20V input voltage. 10-20mF capacitance is suggested for typical of 3-4A charging current.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is
applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's data
sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current is given:
I
ICOUT = RIPPLE » 0.29 ´ IRIPPLE
2 ´ 3
(7)
The bq24726 has internal loop compensator. To get good loop stability, the resonant frequency of the output
inductor and output capacitor should be designed between 10 kHz and 20 kHz. The preferred ceramic capacitor
is 25V X7R or X5R for output capacitor. 10-20mF capacitance is suggested for typical of 3-4A charging current.
Place capacitors after charging current sensing resistor to get the best charge current regulation accuracy.
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Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is
applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data
sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
Power MOSFETs Selection
Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6V of gate drive voltage. 30V or higher voltage rating MOSFETs are
preferred for 19-20V input voltage.
Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction
loss and switching loss. For top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,
RDS(ON), and the gate-to-drain charge, QGD. For bottom side MOSFET, FOM is defined as the product of the
MOSFET's on-resistance, RDS(ON), and the total gate charge, QG.
FOMtop = RDS(on) x QGD; FOMbottom = RDS(on) x QG
(8)
The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle
(D=VOUT/VIN), charging current (ICHG), MOSFET's on-resistance (RDS(ON)), input voltage (VIN), switching frequency
(fS), turn on time (ton) and turn off time (toff):
1
Ptop = D ´ ICHG2 ´ RDS(on) +
´ VIN ´ ICHG ´ (t on + t off ) ´ f s
2
(9)
The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100°C junction
temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are
given by:
Q
Q
t on = SW , t off = SW
Ion
Ioff
(10)
where Qsw is the switching charge, Ion is the turn-on gate driving current and Ioff is the turn-off gate driving
current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge
(QGD) and gate-to-source charge (QGS):
1
QSW = QGD +
´ QGS
2
(11)
Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on
gate resistance (Ron) and turn-off gate resistance (Roff) of the gate driver:
VREGN - Vplt
Vplt
Ion =
, Ioff =
Ron
Roff
(12)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous conduction mode:
Pbottom = (1 - D) ´ ICHG2 ´ RDS(on)
(13)
When charger operates in non-synchronous mode, the bottom-side MOSFET is off. As a result all the
freewheeling current goes through the body-diode of the bottom-side MOSFET. The body diode power loss
depends on its forward voltage drop (VF), non-synchronous mode charging current (INONSYNC), and duty cycle (D).
PD = VF x INONSYNC x (1 - D)
(14)
The maximum charging current in non-synchronous mode can be up to 0.25A for a 10mΩ charging current
sensing resistor or 0.5A if battery voltage is below 2.5V. The minimum duty cycle happens at lowest battery
voltage. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the
maximum non-synchronous mode charging current.
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Input Filter Design
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second
order system. The voltage spike at VCC pin maybe beyond IC maximum voltage rating and damage IC. The
input filter must be carefully designed and tested to prevent over voltage event on VCC pin.
There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic
capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin
voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level.
However these two solutions may not have low cost or small size.
A cost effective and small size solution is shown in Figure 19. The R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used
for reverse voltage protection for VCC pin. C2 is VCC pin decoupling capacitor and it should be place to VCC pin
as close as possible. C2 value should be less than C1 value so R1 can dominant the equivalent ESR value to
get enough damping effect. R2 is used to limit inrush current of D1 to prevent D1 getting damage when adapter
hot plug-in. R2 and C2 should have 10us time constant to limit the dv/dt on VCC pin to reduce inrush current
when adapter hot plug in. R1 has high inrush current. R1 package must be sized enough to handle inrush current
power loss according to resistor manufacturer’s datasheet. The filter components value always need to be
verified with real application and minor adjustments may need to fit in the real application circuit.
D1
Adapter
connector
R1(2010)
2Ω
C1
2.2μF
R2(1206)
10-20 Ω
VCC pin
C2
0.47-1μF
Figure 19. Input Filter
bq24726 Design Guideline
The bq24726 has a unique short circuit protection feature. Its cycle-by-cycle current monitoring feature is
achieved through monitoring the voltage drop across Rdson of the MOSFETs after a certain amount of blanking
time. In case of MOSFET short or inductor short circuit, the over current condition is sensed by two comparators
and two counters will be triggered. After seven times of short circuit events, the charger will be latched off. The
way to reset the charger from latch-off status is reconnect adapter. Figure 20 shows the bq24726 short circuit
protection block diagram.
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Adapter
ACP
RAC
ACN R
PCB
BTST
High-Side
MOSFET
SCP1
PHASE
L
REGN
COMP1
Adapter
Plug in
COMP2
Count to 7
CLR
RDC
Low-Side
MOSFET
SCP2
Battery
C
Latch off
Charger
Figure 20. Block Diagram of bq24726 Short Circuit Protection
In normal operation, low side MOSFET current is from source to drain which generates negative voltage drop
when it turns on, as a result the over current comparator can not be triggered. When high side switch short circuit
or inductor short circuit happens, the large current of low side MOSFET is from drain to source and can trig low
side switch over current comparator. bq24726 senses low side switch voltage drop by PHASE pin and GND pin.
The high-side FET short is detected by monitoring the voltage drop between ACP and PHASE. As a result, it not
only monitors the high side switch voltage drop, but also the adapter sensing resistor voltage drop and PCB trace
voltage drop from ACN terminal of RAC to charger high side switch drain. Usually, there is a long trance between
input sensing resistor and charger converting input, a careful layout will minimize the trace effect.
To prevent unintentional charger shut down in normal operation, MOSFET RDS(on) selection and PCB layout is
very important. Figure 21 shows a need improve PCB layout example and its equivalent circuit. In this layout,
system current path and charger input current path is not separated, as a result, the system current causes
voltage drop in the PCB copper and is sensed by IC. The worst layout is when a system current pull point is after
charger input; as a result all system current voltage drops are counted into over current protection comparator.
The worst case for IC is the total system current and charger input current sum equals DPM current. When
system pull more current, the charger IC try to regulate RAC current as a constant current by reducing charging
current.
I DPM
R AC
System Path PCB Trace
System current
R AC
R PCB
I SYS
I CHRGIN
Charger input current
Charger Input PCB Trace
To ACP
ACP
ACN
Charger
I BAT
To ACN
(a) PCB Layout
(b) Equivalent Circuit
Figure 21. Need Improve PCB Layout Example
Figure 22 shows the optimized PCB layout example. The system current path and charge input current path is
separated, as a result the IC only senses charger input current caused PCB voltage drop and minimized the
possibility of unintentional charger shut down in normal operation. This also makes PCB layout easier for high
system current application.
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R AC
System Path PCB Trace
I DPM
System current
Single point connection at RAC
I SYS
R AC
R PCB
Charger input current
ACP
To ACP
To ACN
ACN
I CHRGIN
Charger
I BAT
Charger Input PCB Trace
(a) PCB Layout
(b) Equivalent Circuit
Figure 22. Optimized PCB Layout Example
The total voltage drop sensed by IC can be express as the following equation.
Vtop = RAC x IDPM + RPCB x (ICHRGIN + (IDPM - ICHRGIN) x k) + RDS(on) x IPEAK
(15)
where the RAC is the AC adapter current sensing resistance, IDPM is the DPM current set point, RPCB is the PCB
trace equivalent resistance, ICHRGIN is the charger input current, k is the PCB factor, RDS(on) is the high side
MOSFET turn on resistance and IPEAK is the peak current of inductor. Here the PCB factor k equals 0 means the
best layout shown in Figure 22 where the PCB trace only goes through charger input current while k equals 1
means the worst layout shown in Figure 21 where the PCB trace goes through all the DPM current. The total
voltage drop must below the high side short circuit protection threshold to prevent unintentional charger shut
down in normal operation.
The low side MOSFET short circuit voltage drop threshold is fixed to typical 110mV. The high side MOSFET
short circuit voltage drop threshold can be adjusted via SMBus command. ChargeOption() bit[8:7] = 00, 01, 10,
11 set the threshold 300mV, 500mV, 700mV and 900mV respectively. For a fixed PCB layout, host should set
proper short circuit protection threshold level to prevent unintentional charger shut down in normal operation.
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PCB Layout
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 23) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential.
1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use
shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on
different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal
traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching
MOSFETs.
3. Place inductor input terminal to switching MOSFET’s output terminal as close as possible. Minimize the
copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 24 for Kelvin connection for
best current accuracy). Place decoupling capacitor on these traces next to the IC
5. Place output capacitor next to the sensing resistor output and ground
6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC
use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling
8. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using power pad as the single ground
connection point. Or using a 0Ω resistor to tie analog ground to power ground (power pad should tie to
analog ground in this case if possible).
9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible
10. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
11. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the QFN
information, See SCBA017 and SLUA271.
PHASE
VIN
C1
High
Frequency
Current
Path
R1
L1
VBAT
BAT
GND
C2
Figure 23. High Frequency Current Path
30
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) :bq24726
bq24726
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SLUSA79A – JULY 2010 – REVISED NOVEMBER 2010
Charge Current Direction
R SNS
To Inductor
To Capacitor and battery
Current Sensing Direction
To SRP and SRN pin
Figure 24. Sensing Resistor PCB Layout
Spacer
REVISION HISTORY
Changes from Original (July 2010) to Revision A
Page
•
Changed the Functional Block Diagram, Figure 1 ................................................................................................................ 2
•
Updated the description for the SRN and SRP pins ........................................................................................................... 11
•
Deleted C12, added R15 and R16 in Table 8 .................................................................................................................... 23
•
Added section: Negative Output Voltage Protection .......................................................................................................... 24
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) :bq24726
31
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
BQ24726RGRR
ACTIVE
VQFN
RGR
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ24726RGRT
ACTIVE
VQFN
RGR
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ24726RGRR
VQFN
RGR
20
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
BQ24726RGRR
VQFN
RGR
20
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
BQ24726RGRT
VQFN
RGR
20
250
180.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
BQ24726RGRT
VQFN
RGR
20
250
180.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24726RGRR
VQFN
RGR
20
3000
346.0
346.0
29.0
BQ24726RGRR
VQFN
RGR
20
3000
552.0
346.0
36.0
BQ24726RGRT
VQFN
RGR
20
250
552.0
185.0
36.0
BQ24726RGRT
VQFN
RGR
20
250
210.0
185.0
35.0
Pack Materials-Page 2
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