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bq24770, bq24773
SLUSC03C – AUGUST 2014 – REVISED DECEMBER 2016
bq2477x NVDC Battery Charge Controller With System Power Monitor
and Processor Hot Indicator
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
Host-controlled NVDC-1 1S-4S Battery Charge
Controller with 4.5-24 V Input Range
– Support SMBus (bq24770) and I2C (bq24773)
– System Instant-on Operation with no Battery or
Deeply Discharged Battery
– Supplement Mode with Synchronous BATFET
Control when Adaptor is fully loaded
Ultra Fast Input Current DPM at 100 μs
Ultra Low Quiescent Current of 600 µA and High
PFM Light Load Efficiency >80% at 20 mA Load
to Meet Energy Star and ErP Lot6.
High Accuracy Power / Current Monitor for CPU
Throttling
– Comprehensive PROCHOT Profile
– Input and Battery Current Monitor (IADP/IBAT)
– System Power Monitor (PMON)
Programmable Input Current Limit, Charge
Voltage, Charge Current and Minimum System
Voltage Regulation
– ±0.5% Charge Voltage (16 mV/step)
– ±2% Input/charge Current (64 mA/step)
– ±2% 40x Input / 16x Discharge / 20x Charge
Current Monitor
Support Battery LEARN Function
High Integration
– NMOS ACFET and RBFET Driver
– PMOS battery FET Gate Driver
– Internal Loop Compensation
– Independent Comparator
– Automatic Trickle Charge to Wake up Gas
Gauge
600kHz to 1.2MHz Programmable Switching
Frequency
Ultrabook, Notebook, Detachable, and Tablet PC
Handheld Terminal
Industrial, Medical, Portable Equipment
3 Description
The bq2477x is high-efficiency, synchronous, NVDC1 battery charge controllers, offering low component
count for space-constraint, multi-chemistry battery
charging applications.
The power path management allows the system to be
regulated at battery voltage but does not drop below
system minimum voltage (programmable). With this
feature, the system keeps operating even when the
battery is completely discharged or removed. The
power path management allows the battery to provide
supplement current to the system to keep the input
supply from being overloaded.
The bq2477x provides drivers and power path
management for N-channel ACFET and reverse
blocking FET. The devices provides driver to control
NVDC operation of external P-channel battery FET. It
also drives high-side and low-side MOSFETs of the
switching regulator.
The bq2477x monitors adapter current (IADP),
battery charge/discharge current (IBAT) and system
power (PMON). The flexibly programmed PROCHOT
output goes directly to CPU for throttle back when
needed.
Device Information(1)
PART NUMBER
bq24770
bq24773
PACKAGE
BODY SIZE (NOM)
WQFN (28-Pin)
4.00mm x 4.00mm2
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
Simplified Schematic
Light Load Efficiency (VIN = 19.5 V)
100
R AC
Adapter
4.5-24V
95
Enhanced Safety:
OCP, OVP, FET Short
90
N-FET Driver
SMBus Controls V and I
with high accuracy
SMBus
SYS
bq24770
P-FET Driver
NVDC Charge
Controller
RSR
Efficiency (%)
85
Adapter Detection
80
75
70
65
60
HOST
VSYS = 9.0V
VSYS = 13.5V
55
IADP, IDCHG,
PMON, PROCHOT
50
0
Copyright © 2016, Texas Instruments Incorporated
0.02
0.04
0.06
0.08
0.1
System Load Current (A)
0.12
0.14
D003
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24770, bq24773
SLUSC03C – AUGUST 2014 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Requirements .............................................. 12
Typical Characteristics ............................................ 13
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 21
8.5 Programming........................................................... 21
8.6 Register Maps ......................................................... 26
9
Application and Implementation ........................ 36
9.1 Application Information............................................ 36
9.2 Typical Application, bq24770 ................................. 36
10 Power Supply Recommendations ..................... 44
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example ................................................... 45
12 Device and Documentation Support ................. 46
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
46
46
46
46
46
46
13 Mechanical, Packaging, and Orderable
Information ........................................................... 46
4 Revision History
Changes from Revision B (October 2014) to Revision C
•
Page
First public release of the full data sheet ............................................................................................................................... 1
Changes from Revision A (October 2014) to Revision B
Page
•
Changed text in the Simplified Schematic From; "Hybrid Power Boost Charge" To NVDC Charge" ................................... 1
•
Changed Equation 1 From: "V = K(PMON)..." To:" I = K(PMON)..." ........................................................................................... 17
•
Changed 0x2011H to 0x0211H in the POS STATE column of Table 4 .............................................................................. 26
•
Changed 0x4854H to 0x4B54H in the POS STATE column of Table 4 .............................................................................. 26
•
Changed Table 7, column "SMBus 0x3CH" To: "SMBus 0x38H" ........................................................................................ 29
Changes from Original (August 2014) to Revision A
Page
•
Changed the equation in the description of pin 21 From: V(ILIM) = 20 × IDPM × (V(ACP) – V(ACN)) To: V(ILIM) = 20 ×
IDPM × RAC ............................................................................................................................................................................ 4
•
Changed the tf MAX value From 300 µs To: 300 ns ........................................................................................................... 12
•
Added a new first paragraph to the Learn Mode section ..................................................................................................... 19
•
Added a NOTE to the Application and Implementation section .......................................................................................... 36
•
Changed Figure 21 .............................................................................................................................................................. 36
•
Changed Figure 36 .............................................................................................................................................................. 43
2
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SLUSC03C – AUGUST 2014 – REVISED DECEMBER 2016
5 Device Comparison Table
bq24770
bq24773
Communication Interface
SMBus
I2C
Communication Address
0x12H (0x00010010)
D4H (0x11010100)
Default Switching Frequency
800kHz
1.2MHz
Default Input Current Limit
3200mA
2944mA
Device ID
0x0114H
0x41H
6 Pin Configuration and Functions
VCC
PHASE
HIDRV
BTST
REGN
LODRV
GND
RUY Package
28-Pin WQFN
Top View
28
27
26
25
24
23
22
3
19 SRN
ACDRV
4
18 BATDRV
ACOK
5
17 BAT
ACDET
6
16 CELL
IADP
7
15 BATPRES
8
9
10
11
12
13
14
CMPOUT
CMSRC
CMPIN
20 SRP
SCL
2
SDA
ACP
PROCHOT
21 ILIM
PMON
1
IBAT
ACN
Pin Functions
PIN
NAME
DESCRIPTION
1
ACN
Input current sense resistor negative input. Place an optional 0.1-µF ceramic capacitor from ACN to GND for
common-mode filtering. Place a 0.1-µF ceramic capacitor from ACN to ACP to provide differential mode filtering.
2
ACP
Input current sense resistor positive input. Place a 1-µF and 0.1-µF ceramic capacitor from ACP to GND for
common-mode filtering. Place a 0.1-µF ceramic capacitor from ACN to ACP to provide differential-mode filtering.
3
CMSRC
ACDRV charge pump source input. Place a 4 kΩ resistor from CMSRC to the common source of ACFET (Q1) and
RBFET (Q2) limits the in-rush current on CMSRC pin.
When CMSRC is grounded, ACDRV pin becomes logic output internally puled up to REGN. ACDRV HIGH indicates
to external driver that ACFET/RBFET can be turned on. It directly drives CMOS logic.
4
ACDRV
Charge pump output to drive both adapter input n-channel MOSFET (ACFET) and reverse blocking n-channel
MOSFET (RBFET). ACDRV voltage is 6 V above CMSRC to turn on ACFET/RBFET when ACOK goes HIGH.
Place a 4 kΩ resistor from ACDRV to the gate of ACFET and RBFET limits the in-rush current on ACDRV pin.
When CMSRC is grounded, ACDRV pin becomes logic output internally pulled up to REGN. ACDRV HIGH
indicates that ACFET/RBFET can be turned on. It directly drives CMOS logic.
5
ACOK
Active HIGH AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external
pull-up resistor when a valid adapter is present (ACDET above 2.4 V, VCC above UVLO but below ACOV and VCC
above BAT). If any of the above conditions is not valid, ACOK is pulled LOW by internal MOSFET. Connect a 10kΩ pull up resistor from ACOK to the pull-up supply rail.
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Pin Functions (continued)
PIN
4
NAME
DESCRIPTION
6
ACDET
Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to
ACDET pin to GND pin.
When ACDET pin is above 0.6 V and VCC is above UVLO, REGN LDO is present, ACOK comparator, and input
current monitor buffer (IADP) are all active. Independent comparator, IBAT buffer, PMON buffer and PROCHOT
can be enabled with SMBus/I2C.
When ACDET pin is above 2.4 V, and VCC is above BAT, but below ACOV, ACOK goes HIGH. ACFET/RBFET
turns on.
7
IADP
Buffered adapter current output. V(IADP) = 40 or 80 × (V(ACP) – V(ACN))
The ratio of 40x and 80x is selectable with SMBus/I2C. Place 100pF or less ceramic decoupling capacitor from
IADP pin to GND. This pin can be floating if it is not in use. IADP output voltage is clamped below 3.3 V.
8
IBAT
Buffered battery current selected by SMBus/I2C. V(IBAT) = 20 × (V(SRP) – V(SRN)) for charge current, or V(IBAT) = 8 or
16 × (V(SRN) – V(SRP)) for discharge current, with ratio selectable through SMBus/I2C. Place 100pF or less ceramic
decoupling capacitor from IBAT pin to GND. This pin can be floating if not in use. Its output voltage is clamped
below 3.3 V.
9
PMON
Current mode system power monitor. The output voltage is proportional to the total power from the adapter and
battery. The gain is selectable through SMBus/I2C. This pin can be floating if not in use. Its output voltage is
clamped below 3.3 V. The maximum cap on PMON is 100 pF.
10
PROCHOT
Active low open drain output of “processor hot” indicator. It monitors adapter input current, battery discharge
current, and system voltage. After any event in the PROCHOT profile is triggered, a minimum 10-ms pulse is
asserted.
11
SDA
SMBus/I2C open-drain data I/O. Connect to data line from the host controller or smart battery. Connect a 10-kΩ
pull-up resistor according to SMBus/I2C specifications.
12
SCL
SMBus/I2C clock input. Connect to clock line from the host controller or smart battery. Connect a 10-kΩ pull-up
resistor according to SMBus/I2C specifications.
13
CMPIN
Input of independent comparator. Internal reference, output polarity and deglitch time is selectable by SMBus/I2C.
With polarity HIGH (0x3B[6]=1), place a resistor between CMPIN and CMPOUT to program hysteresis. With polarity
LOW (0x3B[6]=0), the internal hysteresis is 100 mV. If the independent comparator is not in use, tie CMPIN to
ground.
14
CMPOUT
Open-drain output of independent comparator. Place 10kΩ pull-up resistor from CMPOUT to pull-up supply rail.
Internal reference, output polarity and deglitch time are selectable by SMBus/I2C.
15
BATPRES
Active low battery present input signal. LOW indicates battery present, HIGH indicates battery absent. When
BATPRES pin goes from LOW to HIGH, the device exits LEARN mode, and disable charge. REG 0x15() value
goes back to default. Host can enable IDPM and charge through SMBus/I2C when BATPRES is HIGH.
16
CELL
Battery cell selection pin. GND for 1-cell, Float for 2-cell, and HIGH for 3- or 4-cell. CELL pin is biased from REGN.
Before host writes to MaxChargeVoltage(), MaxChargeVotage() follows the CELL pin setting.
CELL pin also sets SYSOVP threshold. GND for 5 V, Float for 12 V and HIGH for 18.5 V. When REG 0x15() is
above 15V, SYSOVP is disabled.
17
BAT
Battery-voltage remote sense. Directly connect a Kelvin sense trace from the battery-pack positive terminal to the
BAT pin to accurately sense the battery pack voltage. Place a 0.1-μF capacitor from BAT to GND close to the IC to
filter high-frequency noise.
18
BATDRV
P-channel battery FET (BATFET) gate driver output. It is shorted to SRN to turn off the BATFET. It goes below
SRN to turn on BATFET. BATFET is in linear mode to regulate SYS at minimum system voltage when battery is
depleted. BATFET is fully on during fast charge and supplement mode.
Connect the source of the BATFET to charge current sensing node SRN pin, and the drain of the BATFET to the
battery pack positive node BAT pin.
19
SRN
Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin with
a 0.1µF ceramic capacitor to GND for common-mode filtering. Connect a 0.1-µF ceramic capacitor from SRP to
SRN to provide differential mode filtering.
20
SRP
Charge current sense resistor positive input. Connect a 0.1-µF ceramic capacitor from SRP to SRN to provide
differential mode filtering.
21
ILIM
Input current limit input. Program ILIM voltage by connecting a resistor divider from supply rail to ILIM pin to GND
pin. The ILIM voltage is calculated as: V(ILIM) = 20 × IDPM × RAC, in which IDPM is the target regulation current.
The lower of ILIM voltage and DAC limit voltage sets input current regulation limit. Host can ignore the IDPM setting
from ILIM pin by setting 0x38[7]=0.
22
GND
IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through the
power pad underneath IC.
23
LODRV
Low side power MOSFET driver output. Connect to low side n-channel MOSFET gate.
24
REGN
5.4V linear regulator output supplied from VCC. The LDO is active when ACDET above 0.6V, VCC above UVLO.
Connect a 1µF ceramic capacitor from REGN to power ground.
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Pin Functions (continued)
PIN
NAME
DESCRIPTION
25
BTST
High side power MOSFET driver power supply. Connect a 0.047-µF capacitor from BTST to PHASE. The bootstrap
diode between REGN and BTST is integrated.
26
HIDRV
High side power MOSFET driver output. Connect to the high side n-channel MOSFET gate.
27
PHASE
High side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET.
28
VCC
Input supply from adapter or battery. Place Schottky diode-OR from adapter/battery. After the Schottky diode, place
10-Ω resistor and 1-µF capacitor to ground as low pass filter to limit inrush current.
Thermal Pad
Exposed pad beneath the IC. Analog ground and power ground star-connected only at the thermal pad plane.
Always solder thermal pad to the board, and have vias on the thermal pad plane connecting to analog ground and
power ground planes. It also serves as a thermal pad to dissipate the heat.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
SRN, SRP, ACN, ACP, CMSRC, VCC, BAT, BATDRV
–0.3
30
V
PHASE
–2.0
30
V
BTST, HIDRV, ACDRV
–0.3
36
V
LODRV (2% duty cycle)
–4.0
7
V
HIDRV (2% duty cycle)
–4.0
36
V
PHASE (2% duty cycle)
–4.0
30
V
ACDET, SDA, SCL, LODRV, REGN, IADP, IBAT, PMON, BATPRES,
ACOK, CELL, CMPIN, CMPOUT, ILIM
–0.3
7
V
PROCHOT
–0.3
5.5
V
BTST-PHASE, HIDRV-PHASE
–0.3
7
V
SRP–SRN, ACP–ACN
–0.5
0.5
V
Junction temperature range, TJ
–40
155
°C
Storage temperature range, Tstg
–55
155
°C
Voltage range
Differential voltage
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
7.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
MIN
MAX
UNIT
0
2
kV
0
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
UNIT
ACN, ACP, CMSRC, VCC
0
24
V
BATDRV, BAT, SRN, SRP
0
19.2
V
–2
24
V
BTST, HIDRV, ACDRV
0
30
V
ACDET, SDA, SCL, LODRV, REGN, IADP, IBAT, PMON, BATPRES, ACOK,
CELL, CMPIN, CMPOUT, ILIM
0
6.5
V
–0.3
5.3
V
V
PHASE
Voltage range
MAX
PROCHOT
0
6.5
–0.35
0.35
V
Junction temperature range, TJ
–20
125
°C
Operating free-air temperature range, TA
–40
85
°C
Differential voltage
BTST-PHASE, HIDRV-PHASE
SRP–SRN, ACP–ACN
7.4 Thermal Information
bq2477x
THERMAL METRIC
(1)
RUY (WQFN)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
33.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.7
°C/W
RθJB
Junction-to-board thermal resistance
6.5
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
6.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
4.5V ≤ V(VCC) ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
OPERATING CONDITIONS
V(IN_OP)
Input voltage operating range
4.5
24
V
19.2
V
MINIMUM SYSTEM VOLTAGE REGULATION (0x3E REGISTER)
V(SYSMIN_RNG)
System voltage regulation range
1.024
MinsystemVoltage()=0x2400H
V(MINSYS_REG_ACC)
Minimum system voltage regulation
accuracy
MinsystemVoltage()=0x1800H
MinsystemVoltage()=0x0E00H
9.216
–2%
V
2%
6.144
–3%
V
3%
3.584
–3%
V
3%
MAXIMUM SYSTEM VOLTAGE REGULATION (0x15 REGISTER, CHARGE DISABLE)
V(SYSMAX_RNG)
System voltage regulation range
1.024
MaxChargVoltage() = 0x34C0H
V(MAXSYS_REG_ACC)
Maximum system voltage regulation
accuracy
MaxChargVoltage() = 0x2330H
MaxChargVoltage() = 0x1130H
6
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19.2
13.504
–2%
V
2%
9.008
–3%
V
3%
4.4
–3%
V
V
3%
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Electrical Characteristics (continued)
4.5V ≤ V(VCC) ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
19.2
V
CHARGE VOLTAGE REGULATION (0x15 REGISTER, CHARGE ENABLE)
V(BAT_RGN)
Battery voltage range
1.024
16.8
ChargeVoltage() = 0x41A0H
–0.5%
12.592
ChargeVoltage() = 0x3130H
V(BAT_REG_ACC)
V
0.5%
–0.5%
Battery voltage regulation accuranc (0°C 85°C)
V
0.5%
8.4
ChargeVoltage() = 0x20D0H
–0.6%
V
0.6%
4.208
ChargeVoltage() = 0x1070H
V
–1%
1%
0
81.28
CHARGE CURRENT REGULATION
V(IREG_CHG_RNG)
Charge current regulation differential
voltage range
V(IREG_CHG) = V(SRP) – V(SRN)
4096
ChargeCurrent() = 0x1000H
I(CHRG_REG_ACC)
Charge current regulation accuracy 10 Ω
current sensing resistor, VBAT > V(SYSMIN)
(0°C - 85°C)
–2%
–4%
mA
3%
1024
ChargeCurrent() = 0x0400H
–6%
mA
5%
512
ChargeCurrent() = 0x0200H
I(CLAMP)
mA
2%
2048
ChargeCurrent() = 0x0800H
mV
–12%
mA
10%
Pre-charge current clamp (2s-4s)
CELL = Float or High, BAT below 0x3E(), in LDO
mode
384
mA
Pre-charge current clamp (1s only)
CELL = LOW, BAT below BATLOWV threshold
384
mA
Fast charge current clamp (1s only)
CELL = LOW, BAT above BATLOWV threshold,
but below 0x3E()
2
A
PRECHARGE CURRENT REGULATION IN LDO MODE
ChargeCurrent() = 0x0180H
ChargeCurrent() = 0x0100H
I(PRECHRG_REG_ACC)
Precharge current regulation accuracy,
VBAT > V(SYSMIN) (0°C - 85°C)
ChargeCurrent() = 0x00C0H
ChargeCurrent() = 0x0080H
I(LEAK_SRP_SRN)
SRP, SRN leakage current mismatch
384
–15%
mA
15%
256
–20%
mA
20%
192
–25%
mA
25%
128
mA
–30%
30%
–21
21
µA
LDO MODE TO FAST CHARGE COMPARATOR
V(BAT_SYSMIN)
LDO mode to fast charge mode threshold,
VBAT rising
as percentage of 0x3E()
V(BAT_SYSMIN_HYST)
Fast charge mode to LDO mode threshold
hysteresis
as percentage of 0x3E()
94%
96%
99%
4%
INPUT CURRENT REGULATION
V(IREG_DPM_RNG)
Input current regulation differential voltage
range
V(IREG_DPM) = V(ACP) – V(ACN)
ChargeCurrent() = 0x1000H
ChargeCurrent() = 0x0800H
I(DPM_REG_ACC)
Input current regulation accuracy
ChargeCurrent() = 0x0400H
ChargeCurrent() = 0x0200H
0
81.28
4096
–2
mA
2%
2048
–3
mA
3%
1024
–5
mA
5%
512
–10
mA
10%
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Electrical Characteristics (continued)
4.5V ≤ V(VCC) ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
I(LEAK_ACP_
ACN)
TEST CONDITION
MIN
ACP, ACN leakage current mismatch
TYP
––11
MAX
UNIT
20
µA
24
V
INPUT CURRENT SENSE AMPLIFIER
V(ACP/N_OP)
Input common mode range
V(IADP_CLAMP)
IADP output clamp voltage
I(IADP)
IADP output current
A(IADP)
Input current sense gain
V(IADP_ACC)
C(IADP_MAX)
Voltage on ACP/ACN
4.5
3.1
3.2
3.3
1
Input current monitor accuracy
V(IADP)/V(ACP-ACN), ChargeOption0[4]=0, (770/773)
40
V(IADP)/V(ACP-ACN), ChargeOption0[4]=1, (770/773)
80
V/V
V(ACP-ACN) = 40.96 mV
–2%
2%
V(ACP-ACN) = 20.48 mV
–3%
4%
V(ACP-ACN) = 10.24 mV
–6%
7%
V(ACP-ACN) = 5.12 mV
–10%
18%
Maximum output load capacitance
V
mA
100
pF
18
V
CHARGE CURRENT AND DISCHARGE CURRENT SENSE AMPLIFIER
V(SRP/N_OP)
Battery common mode range
V(IBAT_CLAMP)
IBAT output clamp voltage
I(IBAT)
IBAT output current
A(IBAT_DCHG)
Discharge current sensing gain on IBAT
pin
I(IBAT_DCHG_ACC)
A(IBAT_CHG)
I(IBAT_CHG_ACC)
C(IBAT_MAX)
Voltage on SRP/SRN
2.8
3.1
3.2
3.3
1
Discharge current monitor accuracy on
IBAT pin
Charge current sensing gain on IBAT pin
Charge current monitor accuracy on IBAT
pin (0°C - 85°C)
V(IBAT)/V(SRN-SRP), ChargeOption0[3]=0
8
V(IBAT)/V(SRN-SRP), ChargeOption0[3]=1
16
V/V
V(SRN-SRP) = 40.96 mV
–2%
2%
V(SRN-SRP) = 20.48 mV
–3%
3%
V(SRN-SRP) = 10.24 mV
–5%
5%
V(SRN-SRP) = 5.12 mV
–10%
10%
V(IBAT)/V(SRN-SRP)
20
V/V
V(SRN-SRP) = 40.96 mV
–2%
2%
V(SRN-SRP) = 20.48 mV
–3%
4%
V(SRN-SRP) = 10.24 mV
–5%
7%
V(SRN-SRP) = 5.12 mV
–10%
15%
Maximum output load capacitance
V
mA
100
pF
SYSTEM POWER SENSE AMPLIFIER
V(ACP/N_OP)
Input common mode range
Voltage on ACP/ACN
4.5
24
V
V(SRP/N_OP)
Battery common mode range
Voltage on SRP/SRN
2.8
18
V
V(PMON)
Power buffer output voltage
3.3
V
V(PMON_CLAMP)
Power buffer clamp voltage
I(PMON)
Power buffer output current
A(PMON)
System power sense gain,
V(PMON)/(V(ACP-ACN) x V(ACN) + V(SRN-SRP) x
V(SRP))
V(PMON_ACC)
PMON output accuracy
3
3.2
3.3
V
105
µA
ChargeOption1[9]=0
0.25
µA/V
ChargeOption1[9]=1
1
µA/V
Input 19.5 V, 65W, 1 µA/W
–5%
5%
Battery 11 V, 44W, 1 µA/W
–6%
6%
REGN REGULATOR
V(REGN_REG)
REGN Regulator voltage (0 mA - 40 mA)
V(VCC) > 10 V, V(ACDET) > 0.6 V (0 - 50 mA load)
5
5.5
6
V
V(DROPOUT)
REGN Voltage in drop out mode
V(VCC) = 5 V, I(LOAD) = 20 mA
4.4
4.6
4.7
V
REGN Current Limit when converter is
disabled or in T(SHUT) (no charging)
V(REGN) = 4 V, V(ACP) > V(UVLO), 0.6 V < ACDET <
2.4 V
6.5
REGN Current Limit when converter is
enabled (charging)
V(REGN) = 4 V, V(ACP) > V(UVLO)
50
REGN Output Capacitor Required for
Stability
ILOAD = 100 µA to 50 mA
I(REGN_LIM)
C(REGN)
mA
65
mA
1
µF
QUIESCENT CURRENT
I(BAT_BATFET_OFF)
8
Standby mode. System powered by
battery. BATFET off (0°C - 85°C).
I(SRN) + I(SRN) + I(SRP)+ I(PHASE) + I(BTST) +
I(ACP) + I(ACN) + IBAT + I(CMSRC) + I(VCC)
VBAT = 16.8 V
V(VCC) < V(UVLO), ACDET < 0.6 V
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20
27
µA
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Electrical Characteristics (continued)
4.5V ≤ V(VCC) ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
I(BAT_BATFET_ON)
I(STANDBY)
I(AC_SWLIGHT)
I(AC_SW)
TEST CONDITION
Standby mode. System powered by
battery. BATFET on (0°C - 85°C).
I(SRN) + I(SRP) + I(PHASE) + I(BTST) + I(ACP) +
I(ACN) + IBAT + I(CMSRC) + I(VCC)
Adapter standby quiescent current,
I(VCC) + I(ACP) + I(ACN) + I(CMSRC) + I(SRP) +
I(SRN) + I(PHASE) + I(BTST)
Adapter current,
I(VCC) + I(ACP) + I(ACN) + I(CMSRC) + I(SRP) +
I(SRN) + I(PHASE) + I(BTST)
Adapter current,
I(VCC) + I(ACP) + I(ACN) + I(CMSRC) + I(SRP) +
I(SRN) + I(PHASE) + I(BTST)
TYP
MAX
VBAT = 16.8 V
V(VCC) > V(UVLO), ACDET < 0.6 V, 0x12[15]=1,
low power mode enabled
MIN
UNIT
22
30
µA
VBAT = 16.8 V
V(VCC) > V(UVLO), ACDET < 0.6 V, 0x12[15]=0,
0x3B[2]=0,
IBAT Enabled, REGN = 0
114
150
µA
VBAT = 16.8 V
V(VCC) >V(UVLO), ACDET < 0.6 V, 0x12[15]=0,
0x3B[2]=0,
IBAT enabled, REGN = 5.5V
650
775
µA
ACN = ACP = CMSRC = VCC = 20 V,
VBAT = 12.6V, V(ACDET) > 2.4V,
CELL pul up, TJ = 0°C - 85°C
650
815
µA
I(STANDBY) plus supply current in PFM,
200mW output;
Reg0x12[10]=0;MOSFET Qg=4 nF;
1.5
2
mA
I(STANDBY) plus supply current in PFM,
200mW output,
Reg0x12[10]=1; limit 40kHz, MOSFET Qg=4 nF;
3
5
mA
V(ULVO) < V(VCC) < V(ACOVP), VBAT = 16.8 V,
V(ACDET) >2.4 V,
charge enabled, 800k Hz switching,
MOSFET Qg=4 nF
8
mA
ACOK COMPARATOR
V(ACOK_RISE)
ACOK rising threshold
V(VCC) > V(UVLO), ACDET rising
2.37
2.4
2.43
V(ACOK_FALL)
ACOK falling threshold
V(VCC) > V(UVLO)
2.32
2.35
2.38
V(ACOK_RISE_DEG)
ACOK rising deglitch to turn on ACFET
V(VCC) > V(UVLO)
V(ACOK_FALL_DEG)
ACOK falling deglitch to turn off ACFET
V(VCC) > V(UVLO)
V(WAKEUP_RISE)
WAKEUP detect rising threshold
ACDET rising
V(WAKEUP_FALL)
WAKEUP detect falling threshold
2
0.3
0.5
V
ms
2
0.56
V
µs
0.8
V
V
UNDER VOLTAGE LOCKOUT COMPARATOR (UVLO)
V(UVLOZ)
VCC undervoltage rising threshold
VCC rising
2.5
2.7
2.9
V
V(UVLO)
VCC undervoltage falling threshold
VCC falling
2.3
2.5
2.7
V
–25
55
135
mV
174
275
370
mV
SLEEP COMPARATOR (VCC_BAT)
V(VCC-BAT_FALL)
VCC-BAT falling threshold
V(VCC-BAT_RISE)
VCC-BAT rising threshold
tVCC_BAT_RDEG
VCC to BAT rising deglitch
VCC rising above SRN deglitch to turn on ACDRV
tVCC_SRN_FDEG
VCC to BATfalling deglitch
VCC falls below SRN deglitch to turn off ACDRV
Input connected to VCC via schottky diode
4
ms
100
µs
INPUT OVERVOLTAGE COMPARATOR (ACOVP)
V(ACOV_RISE)
VCC overvoltage rising threshold
VCC rising
24
26
28
V(ACOV_FALL)
VCC overvoltage falling threshold
VCC falling
22
24.5
27.5
V(ACOV_RISE_DEG)
VCC overvoltage rising deglitch
VCC rising to turn off ACDRV
V(ACOV_FALL_DEG)
VCC overvoltage falling deglitch
VCC falling falling to turn on ACDRV
V
V
100
µs
3
ms
INPUT OVERCURRENT COMPARATOR (ACOC)
V(ACOC)
ACP to ACN rising threshold,
respect to inputcurrent(), peak
Voltage across input sense resistor rising,
Reg0x12[7]=1
V(ACOC_FLOOR)
Measure between ACP and ACN
Set IDPM to min
44
50
55
mV
V(ACOC_CEILING)
Measure between ACP and ACN
Set IDPM to max
174
180
185
mV
tRELAX
Falling deglitch time
Relax Time, No Latchoff
270%
300%
330%
300
ms
SYSTEM OVERVOLTAGE COMPARATOR (SYS_OVP)
V(SYSOVP_RISE)
CELL = Low
System Overvoltage rising threshold to turn
CELL = Float
off ACFET
CELL = High
4.9
5
5.2
V
11.9
12
12.3
V
18.4
18.5
19
V
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Electrical Characteristics (continued)
4.5V ≤ V(VCC) ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
V(SYSOVP_FALL)
TEST CONDITION
System Overvoltage falling threshold
IOVP
Discharge current when the OVP stop
switching was triggered
tSYSOVP
Deglitch time to latch off ACFET
MIN
TYP
MAX
CELL = Low
4.6
4.7
4.9
V
CELL = Float
10.9
11.1
11.3
V
CELL = High
17.4
17.7
17.9
V
On SRP and SRN
UNIT
19
mA
25
µs
BAT OVERVOLTAGE COMPARATOR (BAT_OVP)
V(OVP_RISE)
Overvoltage rising threshold as percentage
of V(BAT_REG)
BAT rising
101%
102%
103%
V(OVP_FALL)
Overvoltage falling threshold as
percentage of V(BAT_REG)
BAT falling
100%
101%
102%
IOVP
Discharge current during OVP
On SRP and SRN
tOVP_RISE
Overvoltage rising deglitch to turn off
BATDRV to disable charge
19
mA
20
ms
CONVERTER CYCLE-BY-CYCLE COMPARATOR (ILIM_HI)
V(OCP_limit)
V(OCP_limit_SYSSHORT
Converter over current limit (PH-GND)
System Short or SRN < 2.5 V
)
Reg0x12 [6]=1
249
290
333
mV
Reg0x12 [6]=0
142
170
202
mV
Reg0x12 [6]=1
41
66
87
mV
Reg0x12 [6]=0
7
31
53
mV
0.4
mV
CONVERTER CYCLE-BY-CYCLE UNDER-CURRENT COMPARATOR (UCP)
V(UCP_FALL)
Charge Undercurrent falling threshold
PH voltage when LSFET is on
–2.8
CELL = Low
2.64
2.85
3.06
V
CELL = Float or High
5.71
5.92
6.12
V
CELL = Low
2.89
3.10
3.31
V
CELL = Float or High
5.96
6.17
6.37
V
BATTERY LOWV COMPARATOR
V(BATLV_FALL)
V(BATLV_RHYST)
BATLOWV falling threshold
BATLOWV rising threshold
LIGHT LOAD COMPARATOR (LIGHT_LOAD)
VLL(FALL)
Light load falling threshold detected on
ACP-ACN
0
0.5
1.1
mV
VLL(RISE)
Light load rising threshold detected on
ACP-ACN
0.7
1.4
2.1
mV
THERMAL SHUTDOWN COMPARATOR
T(SHUT)
Thermal shutdown rising temperature
T(SHUT_HYS)
Thermal shutdown hysteresis, falling
Temperature increasing
155
°C
20
°C
tSHUT_RDEG
Thermal shutdown rising deglitch
100
µs
tSHUT_FHYS
Thermal shutdown falling deglitch
10
ms
VSYS PROCHOT COMPARATOR
Reg0x3C [7:6]=00
V(SYS_PRO)
tSYS_PRO_RISE_DEG
Reg0x3C [7:6]=01
V(SYS) threshold falling threshold
5.75
5.9
6
V
6.15
V
Reg0x3C [7:6]=10
6.25
Reg0x3C [7:6]=11
6.5
V
20
µs
V(SYS) Rising Deglitch for throttling
V
ICRIT PROCHOT COMPARATOR
V(ICRIT_PRO)
IADP rising threshold for throttling above
IDPM
Reg0x3C [15:11]=01001
145%
150%
155%
106%
110%
114%
INOM PROCHOT COMPARATOR
V(INOM_PRO)
INOM rising threshold as percentage of
IDPM
IDCHG PROCHOT COMPARATOR
V(IDCHG_PRO)
10
IDCHG threshold for throttling for IDSCHG
of 6 A
Reg0x3D [15:10]=001100
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98%
mA
104%
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SLUSC03C – AUGUST 2014 – REVISED DECEMBER 2016
Electrical Characteristics (continued)
4.5V ≤ V(VCC) ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Reg0x3B [7]=1, CMPIN rising
1.17
1.2
1.23
V
Reg0x3B [7]=0, CMPIN rising
2.27
2.3
2.33
INDEPENDENT COMPARATOR
V(INDEP_CMP)
Independent comparator threshold
V(INDEP_CMP_HYS)
Independent comparator hysteresis
Reg0x3B [6]=0, CMPIN falling
100
V
mV
PWM OSCILLATOR
FSW
PWM Switching frequency
Reg0x12 [9:8]=00
510
600
Reg0x12 [9:8]=01
680
800
690
920
Reg0x12 [9:8]=10
850
1000
1150
Reg0x12 [9:8]=11
1020
1200
1380
8.5
9.5
10.5
V
3
3.5
4
kΩ
1.5
2
2.5
kΩ
kHz
BATFET GATE DRIVER (BATDRV)
V(BATDRV_ON)
Gate Drive Voltage on BATFET
R(BATDRV_ON)
Measured by sourcing 10 µA current to
BATDRV
V(SRN) - V(BATDRV) when BAT = 16 V
R(BATDRV_OFF)
Measured by sinking 100 µA current from
BATDRV
ACFET GATE DRIVER (ACDRV)
I(ACFET)
ACDRV charge pump current limit
V(ACDRV) – V(CMSRC)= 5 V
40
60
V(ACDRV_ON)
Gate drive voltage on ACFET
V(ACDRV) – V(CMSRC)when V(VCC) > V(UVLO)
5.5
6.2
R(ACDRV_OFF)
ACDRV turn-off resistance
I = 30μA
5
6.2
R(ACDRV_LOAD)
Minimum load between gate and source
µA
V
7.4
500
kΩ
kΩ
PWM HIGH SIDE DRIVER (HIDRV)
RDS(HI_ON)
High side driver(HSD) turn-on resistance
V(BTST) – V(PH) = 5 V
4
RDS(HI_OFF)
High side driver turn-off resistance
V(BTST) – V(PH) = 5 V
0.65
1.3
Ω
V(BTST_REFRESH)
Bootstrap refresh comparator falling
threshold voltage
V(BTST) – V(PH) when low side refresh pulse is
requested
3.8
4.1
V
3.5
Ω
PWM LOW SIDE DRIVER (LODRV)
RDS(LO_ON)
Low side driver (LSD) turn-on resistance
V(BTST) – V(PH) = .55 V
5.5
RDS(LO_OFF)
Low side driver turn-off resistance
V(BTST) – V(PH) = 5.5 V
1
Ω
1.45
Ω
INTERNAL SOFT START
I(CHG_DAC)
Soft start step size
64
mA
Soft start step time
30
µs
INTEGRATED BTST DIODE
VF
Forward bias voltage
IF = 20 mA at 25°C
VR
Reverse breakdown voltage
IR = 2 µA at 25°C
0.8
V
20
V
PWM DRIVERS TIMING
tDEADTIME_RISE
Driver dead time from low side to high side
20
ns
tDEADTIME_FALL
Driver dead time from high side to low side
20
ns
LOGIC INPUT (SDA, SCL)
V(IN_ LO)
V(IN_ HI)
Input low threshold
Input high threshold
I2C (bq24773)
0.4
V
SMBus (bq24770)
0.8
V
I2C (bq24773)
1.3
V
SMBus (bq24770)
2.1
V
LOGIC OUTPUT OPEN DRAIN (ACOK, SDA,CMPOUT)
V(OUT_ LO)
Output saturation voltage
5 mA drain current
V(OUT_
Leakage current (ACOK, SDA, SCL)
V=7V
LEAK)
–1
0.4
V
1
µA
300
mV
1
µA
LOGIC OUTPUT OPEN DRAIN (PROCHOT)
V(OUT_ LO)
Output saturation voltage
50 Ω pull up to 1.05 V/ 5mA load
V(OUT_
Leakage current
V = 5.5 V
–1
LEAK)
ANALOG INPUT (CELL)
V(CELL_HIGH)
3S/4S
REGN = 5.4 V
1.9
V(CELL_FLOAT)
2S
REGN = 5.4 V
1.2
V
1.8
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Electrical Characteristics (continued)
4.5V ≤ V(VCC) ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
REGN = 5.4 V
MAX
1.1
UNIT
V(CELL_LOW)
1S
R(CELL_UP)
Internal resistor between CELL and REGN
405
kΩ
V
R(CELL_DN)
Internal resistor between CELL and GND
141
kΩ
ANALOG INPUT (/BATPRES)
V(BATPRES_RISE)
BATPRES pin rising threshold
BATPRES rising
2.1
2.2
2.3
V
V(BATPRES_FALL)
BATPRES pin falling threshold
BATPRES falling
2
2.05
2.1
V
7.6 Timing Requirements
MIN
TYP MAX
UNIT
SMBus TIMING CHARACTERISTICS
tr
SCLK/SDATA rise time
tf
SCLK/SDATA fall time
1
µs
300
tW(H)
SCLK pulse width high
4
ns
50
µs
tW(L)
SCLK Pulse Width Low
4.7
µs
tSU(STA)
Setup time for START condition
4.7
µs
tH(STA)
START condition hold time after which first clock pulse is generated
4
µs
tSU(DAT)
Data setup time
250
µs
tH(DTA)
Data hold time
300
µs
tSU(STOP)
Setup time for STOP condition
4
µs
t(BUF)
Bus free time between START and STOP condition
4.7
FS(CL)
Clock Frequency
10
100
KHz
35
ms
µs
HOST COMMUNICATION FAILURE
ttimeout
SMBus bus release timeout (1)
25
tBOOT
Deglitch for watchdog reset signal
10
Watchdog timeout period, ChargeOption() bit [14:13] = 01 (2)
35
44
53
s
Watchdog timeout period, ChargeOption() bit [14:13] = 10 (2)
70
88
105
s
140
175
210
s
tWDI
Watchdog timeout period, ChargeOption() bit [14:13] = 11
(1)
(2)
12
(2)
(default)
ms
Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35 ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25
ms).
User can adjust threshold via SMBus ChargeOption() REG0x12.
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7.7 Typical Characteristics
100
100
VIN = 12V, VSYS = 4.4V
VIN = 12V, VSYS = 9.0V
VIN = 5V, VSYS = 4.4V
99
98
96
Efficiency (%)
97
Efficiency (%)
VSYS = 4.4V
VSYS = 9.0V
VSYS = 13.5V
98
96
95
94
93
94
92
90
92
88
91
86
90
0
1
2
3
4
5
6
System Load Current (A)
7
8
0
9
1
VIN = 12V/5V
3
4
5
6
System Load Current (A)
7
8
9
D002
VIN = 19V
Figure 1. Heavy Load Efficiency
Figure 2. Heavy Load Efficiency
100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
2
D001
80
75
70
80
75
70
65
65
60
60
VIN = 12V, VSYS = 4.4V
VIN = 12V, VSYS = 9.0V
VIN = 5V, VSYS = 4.4V
55
VSYS = 4.4V
VSYS = 9.0V
VSYS = 13.5V
55
50
50
0
0.02
0.04
0.06
0.08
0.1
System Load Current (A)
0.12
VIN = 12V/5V
0.14
0
0.02
0.04
0.06
0.08
0.1
System Load Current (A)
D004
0.12
0.14
D005
VIN = 19V
Figure 3. Light Load Efficiency
Figure 4. Light Load Efficiency
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8 Detailed Description
8.1 Overview
The bq2477x is a 1-4 cell battery charge controller with power selection for space-constrained, multi-chemistry
portable applications such as notebook and detachable ultrabook. It supports wide input range of input sources
from 4.5V to 24V, and 1-4 cell battery for a versatile solution.
The bq2477x supports automatic system power source selection with separate drivers for n-channel MOSFETs
on the adapter side, and p-channel MOSFETs on the battery side.
The bq2477x features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter
overloading. During battery charging, as the system power increases, the charging current will reduce to maintain
total input current below adapter rating. If system power demand is temporarily exceeds adapter rating, the
bq2477x supports NVDC architecture to allow battery discharge energy to supplement system power. For details,
refer to the System Voltage Regulation with Narrow VDC Architecture section.
The bq2477x closely monitors system power (PMON), input current (IADP) and battery current (IBAT) with highly
accurate current sense amplifiers. If current is too high, adapter or battery is removed, a PROCHOT signal is
asserted to CPU so that the CPU optimizes its performance to the power available to the system.
The SMBus/I2C controls input current, charge current and charge voltage registers with high resolution, high
accuracy regulation limits. It also sets the PROCHOT timing and threshold profile to meet system requirements.
14
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8.2 Functional Block Diagram
3.2V
UVLO*
VCC
28
ACDRV
CHARGE
PUMP
ACDRV
EN_REGN
ACDRV_CMSRC
CMSRC+5.9V
ACDET
6
ACGOOD
0.6V
ACOK_DRV
ACDRV
3
CMSRC
18
BATDRV
25
BTST
26
HIDRV
27
PHASE
24
REGN
23
LODRV
22
GND
15
/BATPRES
10
/PROCHOT
SYSOVP
ACOVP
26V
SELECTOR
LOGIC
ACOC
ACGOOD
SRN
EN_CHRG
VCC_SRN
EN_PRECHRG
2.4V
ACOK
4
WAKEUP*
SRN-10V
EN_FASTCHRG
5
ACOK_DRV
EN_SUPPLEMENT
2ms Rising
Deglitch
VREF_IAC
ACP
FBO
2
40X**
ACN
1
IADP
7
1X*
IBAT
TYPE III
COMPENSATION
EAI
VCC
EN_LEARN
20
SRN
19
BAT
EN_SUPPLEMENT
200mV
VREF_ICHG
RAMP
Frequency**
EN_CHRG
17
EN_FASTCHRG
EN_AUDIOFREQ
16X**
BATOVP or
SYSOVP
EN_PRECHRG
PWM
IDCHG
SRP
EN_CHRG
DAC_VALID
EAO
IADP
BAT
9
WATCHDOG
TIMER 175s**
CHARGE_INHIBIT
8
+1X or -1X*
PMON
WD_TIMEOUT
EN_DPM
SRP
Tj
VREF_SYSMIN
155C
TSHUT
GND_PHASE
ILIM_HI
350mV**
VREF_VREG
WAKEUP
GND
10uA
ILIM_LOW
PHASE
SDA
SCL
ILIM
CELL
SMBUS
(bq24770)
I2C
(bq24773)
12
11
21
16
EN_REGN
0.5mV
DAC_VALID
ACP_ACN
ACOC
VREF_VREG
3xVREF_IAC**
VREF_ICHG
3.8
REFRESH
VREF_IAC
BTST_PH
VREF_SYSMIN
VFB
EN_WAKEUP
EN_DPM
BATOVP
104%VREF_VREG
EN_AUDIOFREQ
TRI-STAT
BUFFER
CMPOUT
14
CELL_HIGH
CELL_FLOAT
CELL_LOW
2.8V
BATLOWV
SRN
CELL_HIGH
CELL_FLOAT
CELL_LOW
IADPT
VCC
VCC_SRN*
SRN+275mV
IDCHG
VSYS
SRP
SYSOVP
13
REGN
LDO
ACP_ACN
IREF_CMP**
CMPIN
PWM
CHARGE_INHIBIT
EN_LEARN
ChargeOption0()
ChargeOption1()
ChargeOption2()
ProchotOption0()
ProchotOption1()
ChargeCurrent()
ChargeVoltage()
InputCurrent()
MinsysVoltage()
ManufactureID()
DeviceID()
LIGHT_LOAD
PROC
HOT
detect
ACOK
VSYSOVP
bq24770/773
* Power from VCC
** Threshold is adjustable through SMBus/I2C
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8.3 Feature Description
8.3.1 Battery Only
Battery is connected to VCC via diode. When VCC voltage is above UVLO, bq2477x powers up to turn on
BATFET and starts SMBus/I2C communication. By default, bq2477x stays in low power mode (0x12[15] = 1) with
lowest quiescent current.
When 0x12[15] is set to 0, the device enters performance mode. The user can enable IBAT buffer through
SMBus/I2C. In order to enable PMON, PROCHOT or independent comparator, the bq2477x enables REGN LDO
for accurate reference.
8.3.2 Adapter Detect and ACOK Output
An external resistor divider attenuates the adapter voltage before it goes to ACDET. The adapter detect
threshold should typically be programmed to a value greater than the maximum battery voltage, but lower than
the maximum allowed adapter voltage. When ACDET is above 0.6V, REGN LDO and bias circuits are enabled.
The open drain ACOK output can be pulled to external rail under the following conditions:
• V(UVLO) < V(VCC) < V(ACOVP)
• V(ACDET) > 2.4 V
• V(VCC) – V(SRN) > V(VCC_SRN_RISE)
8.3.2.1 Adapter Overvoltage (ACOVP)
When the VCC pin voltage is higher than 26 V, it is considered adapter over voltage. ACOK is pulled low, and
charge is disabled. ACFET/RBFET are turned off to disconnect the high voltage adapter to system during
ACOVP. BATFET is turned on if turn-on conditions are valid. When VCC voltage falls below 22 V, it is
considered as adapter voltage returns back to normal voltage. ACOK is pulled high by an external pullup resistor.
BATFET is turned off and ACFET and RBFET is turned on to power the system from the adapter.
8.3.3 System Power Selection
The bq2477x device automatically switches adapter or battery power to system.
The ACDRV drives a pair of common-source (CMSRC) N-channel power MOSFETs (ACFET and RBFET)
between adapter and ACP (see Figure 21 for details). The ACFET separates adapter from system and battery,
and provides a limited di/dt when plugging in adapter by controlling the ACFET turn-on time. The RBFET
provides negative input voltage protection and battery discharge protection when adapter is shorted to ground,
and minimizes system power dissipation with its low RDS(on) compared to a Schottky diode.
When the adapter is not present, ACDRV is pulled to CMSRC to keep ACFET and RBFET off, disconnecting the
adapter from the system. BATDRV stays as low as VSRN – 10 V to connect battery to system if all of the
following conditions are valid:
• V(VCC) > V(UVLO)
• V(SRN) – V(SRP) > 2.56 mV
After the adapter plugs in, the system power source switches from battery to adapter if ACOK is HIGH. The gate
drive voltage on ACFET and RBFET is V(CMSRC) + 6 V. If ACDRV-CMSRC voltage drops at least 100 mV from its
normal voltage, the converter stops.
To limit the adapter inrush current during ACFET turn-on, the Cgs and Cgd external capacitor of ACFET must be
carefully selected following the guidelines below:
• Minimize total capacitance on system
• Cgs should be 40× or higher than Cgd to avoid ACFET false turn on during adapter hot plug-in
• Check with MOSFET vendor on peak current rating
• Place 4 kΩ resistor in series with ACDRV and CMSRC pins to limit MOSFET turn on/off time.
16
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Feature Description (continued)
8.3.4 System Power Up
After the ACFET is turned on, the converter is enabled and the HSFET and LSFET start switching. Every time
the buck converter is started, the IC automatically applies soft-start (no soft-start when exit LEARN) on buck
output current to avoid any overshoot or stress on the output capacitors or the power converter. No external
components are needed for this function.
When power up, the converter output voltage is a default value set by CELL pin configuration.
Table 1. Cell Pin Configuration
CELL PIN
DEFAULT BATTERY
CONFIGURATION
DEFAULT
MaxChargevoltage()
DEFAULT
MinSystemVoltage()
SYSOVP
THRESHOLD
Low
1s
4400mV
3568mV
5V
Float
2s
9008mV
6144mV
12 V
9008mV
18.5 V when
MaxChargeVoltage() < 15 V
High
3s/4s
13504mV
8.3.4.1 Dynamic Power Management (IDPM) and Supplement Mode
When the input current exceeds the input current setting, the bq2477x decreases the charge current to provide
priority to system load. As the system current rises, the available charge current drops accordingly toward zero. If
the system load keeps increasing after charge current drops down to zero, the system voltage starts to drop. As
the system voltage drops below battery voltage, the device enters supplement mode, the battery starts
discharge, and the total system power equals to input supply power and battery discharge power.
8.3.4.2 Minimum System Voltage Regulation and LDO Mode
The BATDRV drives a p-channel BATFET between converter output and battery to provide a charge and
discharge path for battery. The system is always above the MinSystemVoltage() even with depleted battery or
without battery.
When battery voltage is below the minimum system voltage setting, this BATFET works in linear mode (LDO
mode) during battery charging. The precharge current is set by ChargeCurrent() and clamped below 384mA. If
battery voltage reaches the minimum system voltage, BATFET fully turns on.
The minimum BATDRV voltage is 1.1 V. For 1s application, the BATFET has to fully turn on when the gate
voltage is 1.1 V or higher. Otherwise, BATFET may not operate properly.
8.3.5 Current and Power Monitor
8.3.5.1 High Accuracy Current Sense Amplifier (IADP and IBAT)
As an industry standard, a high-accuracy current sense amplifier (CSA) is used to monitor the input current
(IADP) and the charge/discharge current (IBAT). IADP voltage is 40X or 80X the differential voltage across ACP
and ACN. IBAT voltage is 20X (during charging), or 8X/16X (during discharging) of the differential across SRP
and SRN. After VCC is above V(UVLO) and ACDET is above 0.6 V, IADP output becomes valid. To lower the
voltage on current monitoring, a resistor divider from CSA output to GND can be used and accuracy over
temperature can still be achieved.
A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An
additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional
response delay. The CSA output voltage is clamped at 3.3 V.
8.3.5.2 High Accuracey Power Sense Amplifier (PMON)
The bq2477x device monitors total available power from adapter and battery together. The ratio of PMON current
and total power K(PMON) can be programmed in ChargeOption1() bit[8] with default 1µA/W. The bq2477x device
allows input sense resistor 2× of charge sense resistor by setting ChargeOption1() bit[12] to 1.
I = K(PMON)(VIN × IIN + VBAT × IBAT ) (IBAT > 0 during battery discharging, IBAT < 0 during battery charging) )
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A maximum PMON output current is 100µA. The user picks output resistor based on peak system power rating.
The PMON output voltage is clamped below 3.3V.
8.3.6 Processor Hot Indication for CPU Throttling
When CPU is running turbo mode, the peak power may exceed total available power from adapter and battery.
The adapter current and battery discharge overshoot, or system voltage drop indicates the system power may be
too high. When the adapter or battery is removed, the remaining power source may not support the peak power
in turbo mode. The processor hot function in bq2477x monitors these events, and PROCHOT pulse is asserted.
The PROCHOT triggering events include:
• ICRIT: adapter peak current
• INOM: adapter average current (110% of input current limit)
• IDCHG: battery discharge current
• VSYS: system voltage on SRN for 2s - 4s battery
• ACOK: upon adapter removal (ACOK pin HIGH to LOW)
• BATPRES: upon battery removal (BATPRES pin LOW to HIGH)
• CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW)
The threshold of ICRIT, IDCHG or VSYS, and the deglitch time of ICRIT, INOM, IDCHG or CMPOUT are
programmable through SMBus. Each triggering event can be individually enabled in REG0x3D[6:0].
ICRIT
IADP
Adjustable
Deglitch
1.05 V
INOM
IDCHG
50Ω
PROCHOT
Ref_DCHG
10 ms
Debounce
Ref
≥10 ms
VSRP
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