BQ29209TDRBTQ1

BQ29209-Q1 BQ29209-Q1 SLUSC62D – JUNE 2015 – REVISED SEPTEMBER 2020 SLUSC62D – JUNE 2015 – REVISED SEPTEMBER 2020 www.ti.com BQ29209-Q1 Voltage Protection with Automatic Cell Balance for 2-Series Cell Li-Ion Batteries 1 Features 3 Description • • The BQ29209-Q1 device is a secondary overvoltage protection IC for 2-series cell lithium-ion battery packs that incorporates a high-accuracy precision overvoltage detection circuit and automatic cell imbalance correction. • • • • • • • • • • 2-series cell secondary protection Automatic cell imbalance correction with external enable control – ±30-mV enable, 0-mV disable thresholds typical External capacitor-controlled delay timer External resistor-controlled cell balance current Low power consumption ICC < 3 µA typical (VCELL(ALL) < VPROTECT) Internal cell balancing handles current up to 15 mA External cell balancing mode supported High-accuracy overvoltage protection: – ±25 mV with TA = 0°C to 60°C Fixed overvoltage protection threshold: 4.30 V Small 8L DRB package Functional Safety-Capable – Documentation available to aid functional safety system design Automotive-qualified AEC Q100 grade two 2 Applications • 2nd level protection in li-ion battery packs – Emergency call (eCall) – Netbook computers – Power tools – Portable equipment and instrumentation – Battery backup systems The voltage of each cell in a 2-series cell battery pack is compared to a factory programmed internal reference voltage. If either cell reaches an overvoltage condition, the OUT pin changes from low to high state. The BQ29209-Q1 can perform automatic voltagebased cell imbalance correction. Balancing can start when the cell voltages are different by nominally 30 mV or more and stops when the difference is nominally 0 mV. Cell balancing is enabled and disabled by the CB_EN pin. Device Information PART NUMBER (1) BQ29209-Q1 (1) PACKAGE BODY SIZE (NOM) VSON (8) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. PACK+ RIN2 CELL2 CIN RIN1 CIN 1 VC2 OUT 8 2 VC1 VDD 7 3 VC1_CB CELL1 RCBext 4 CD RVD CB_EN 6 GND 5 CVD PWR PAD CCD PACK- Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: BQ29209-Q1 1 BQ29209-Q1 www.ti.com SLUSC62D – JUNE 2015 – REVISED SEPTEMBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Options................................................................ 3 6 Pin Configuration and Functions...................................3 Pin Functions.................................................................... 3 7 Specifications.................................................................. 3 7.1 Absolute Maximum Ratings........................................ 3 7.2 ESD Ratings............................................................... 4 7.3 Recommended Operating Conditions.........................4 7.4 Thermal Information....................................................4 7.5 Electrical Characteristics.............................................4 7.6 Recommended Cell Balancing Configurations........... 6 7.7 Typical Characteristics................................................ 6 8 Detailed Description........................................................7 8.1 Overview..................................................................... 7 8.2 Functional Block Diagram........................................... 7 8.3 Feature Description.....................................................7 8.4 Device Functional Modes..........................................11 9 Application and Implementation.................................. 11 9.1 Application Information..............................................11 9.2 Typical Applications.................................................. 12 9.3 System Example....................................................... 13 10 Power Supply Recommendations..............................14 11 Layout........................................................................... 14 11.1 Layout Guidelines................................................... 14 11.2 Layout Example...................................................... 14 12 Device and Documentation Support..........................15 12.1 Documentation Support.......................................... 15 12.2 Receiving Notification of Documentation Updates..15 12.3 Support Resources................................................. 15 12.4 Trademarks............................................................. 15 12.5 Electrostatic Discharge Caution..............................15 12.6 Glossary..................................................................15 13 Mechanical, Packaging, and Orderable Information.................................................................... 15 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (December 2018) to Revision D (September 2020) Page • Added the functional safety capable information................................................................................................ 1 Changes from Revision B (November 2018) to Revision C (December 2018) Page • Added a clarification regarding operation if GND is not connected first in sequence......................................... 8 Changes from Revision A (March 2016) to Revision B (November 2018) Page • Changed component names in the Simplified Schematic ................................................................................. 1 • Changed a component name in Recommended Operating Conditions ............................................................ 4 • Added the value of internal cell balancing switch resistances to Electrical Characteristics ...............................4 • Changed resistor names ....................................................................................................................................6 • Added Figure 8-2 to clarify the cell balancing description; updated the equations ............................................9 • Changed values and component names in Figure 9-1 .................................................................................... 12 • Changed component names and values used in the design example ............................................................ 12 • Changed external cell balancing figure, equations, and description.................................................................13 Changes from Revision * (June 2015) to Revision A (March 2016) Page • Changed resistor RVD location, added PACK+ and PACK– in the Simplified Schematic .................................. 1 • Deleted the Lead Temperature (soldering) from the Section 7.1 table .............................................................. 3 • Changed resistor RVD location in Figure 9-1 ................................................................................................... 12 • Added title to Table 9-1 .................................................................................................................................... 12 • Changed resistor RVD location, added PACK+ and PACK– in Figure 9-3 ....................................................... 13 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: BQ29209-Q1 BQ29209-Q1 www.ti.com SLUSC62D – JUNE 2015 – REVISED SEPTEMBER 2020 5 Device Options TA PART NUMBER OVP –40°C to +105°C BQ29209-Q1 4.3 V 6 Pin Configuration and Functions VC2 1 VC1 2 8 OUT 7 VDD PWR PAD VC1_CB 3 6 CB_EN CD 4 5 GND Figure 6-1. DRB Package 8-Pin VSON Top View Pin Functions PIN DESCRIPTION NAME NO. CB_EN 6 Cell balance enable CD 4 Connection to external capacitor for programmable delay time GND 5 Ground pin OUT 8 Output Thermal Pad PWR PAD VC1 2 Sense voltage input for bottom cell VC1_CB 3 Cell balance input for bottom cell VC2 1 Sense voltage input for top cell VDD 7 Power supply GND pin to be connected to the PWRPAD on the printed circuit board for proper operation 7 Specifications 7.1 Absolute Maximum Ratings Over-operating free-air temperature range (unless otherwise noted)(1) MIN Supply voltage range, VMAX Input voltage range, VIN Output voltage range, VOUT UNIT VDD–GND –0.3 16 V VC2–GND, VC1–GND –0.3 16 V VC2–VC1, CD–GND –0.3 8 V CB_EN–GND –0.3 16 V OUT–GND –0.3 16 V Continuous total power dissipation, PTOT See Section 7.4. Storage temperature , Tstg (1) MAX –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: BQ29209-Q1 3 BQ29209-Q1 www.ti.com SLUSC62D – JUNE 2015 – REVISED SEPTEMBER 2020 7.2 ESD Ratings VALUE Human-body model (HBM), per AEC V(ESD) (1) Electrostatic discharge Q100-002(1) Charged-device model (CDM), per AEC Q100-011 UNIT ±2000 All pins ±500 Corner pins (VC2, CD, OUT, and GND) ±750 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions MIN Supply voltage, VDD NOM 10 V 0 5 V VC2–VC1, VC1–GND Delay time capacitance, td(CD) CCD (See Figure 9-1.) Voltage monitor filter resistance RIN (See Figure 9-1.) 100 Voltage monitor filter capacitance CIN (See Figure 9-1.) 0.01 Supply voltage filter resistance RVD (See Figure 9-1.) 0.1 µF 1K Ω 0.1 100 Supply voltage filter capacitance CVD (See Figure 9-1.) RCBext (See Figure 9-1 and Section 8.3.1.) µF 1K 0.1 Operating ambient temperature range, TA UNIT 4 Input voltage range Cell balance resistance MAX Ω µF 100 4.7K Ω –40 105 °C 7.4 Thermal Information BQ29209-Q1 THERMAL METRIC(1) DRB UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 50.5 °C/W RθJC(top) Junction-to-case(top) thermal resistance 25.1 °C/W RθJB Junction-to-board thermal resistance 19.3 °C/W ψJT Junction-to-top characterization parameter 0.7 °C/W ψJB Junction-to-board characterization parameter 18.9 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance 5.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics Typical values stated where TA = 25°C and VDD = 7.2 V. Minimum and maximum values stated where TA = – 40°C to 105°C and VDD = 4 V to 10 V (unless otherwise noted). PARAMETER 4 VPROTECT Overvoltage detection voltage VHYS Overvoltage detection hysteresis VOA Overvoltage detection accuracy VOA_DRIFT Overvoltage threshold temperature drift XDELAY Overvoltage delay time scale factor TEST CONDITIONS MIN TYP MAX 4.3 200 300 V 400 mV mV TA = 25°C –10 10 TA = 0°C to 60°C –0.4 0.4 TA = –40°C to 110°C –0.6 0.6 TA = 0°C to 60°C Note: Does not include external capacitor variation. 6 9 12 TA = –40°C to 110°C Note: Does not include external capacitor variation. 5.5 9 13.5 Submit Document Feedback UNIT mV°/C s/µF Copyright © 2020 Texas Instruments Incorporated Product Folder Links: BQ29209-Q1 BQ29209-Q1 www.ti.com SLUSC62D – JUNE 2015 – REVISED SEPTEMBER 2020 Typical values stated where TA = 25°C and VDD = 7.2 V. Minimum and maximum values stated where TA = – 40°C to 105°C and VDD = 4 V to 10 V (unless otherwise noted). PARAMETER TYP MAX UNIT XDELAY_CTM (1) Overvoltage delay time scale factor in Customer Test Mode TEST CONDITIONS 0.08 s/µF ICD(CHG) Overvoltage detection charging current 150 nA ICD(DSG) Overvoltage detection discharging current 60 µA VCD Overvoltage detection external capacitor comparator threshold 1.2 V ICC Supply current (VC2–VC1) = (VC1–GND) = 3.5 V (See Figure 8-5.) (VC2–VC1) or (VC1–GND) > VPROTECT, VDD = 10 V, IOH = 0 (VC2–VC1) or (VC1–GND) = VPROTECT, VDD = VPROTECT, IOH = –100 µA, TA = 0°C to 60°C VOUT OUT pin drive voltage MIN 3 6 µA 6 8.25 9.5 V 1.75 2.5 (VC2–VC1) and (VC1–GND) < VPROTECT , IOL = 100 µA, TA = 25°C (VC2–VC1) and (VC1–GND) < VPROTECT , IOL = 0 µA, TA = 25°C 0 VC2 = VC1 = VDD = 4 V, IOL = 100 µA IOH High-level output current OUT = 1.75 V, (VC2–VC1) or (VC1–GND) = VPROTECT, VDD = VPROTECT to 10 V, TA = 0°C to 60°C –100 IOL Low-level output current OUT = 0.05 V, (VC2–VC1) or (VC1–GND) < VPROTECT, VDD = VPROTECT to 10 V, TA = 0°C to 60°C 30 IOH_ZV High-level short-circuit output current OUT = 0 V, (VC2–VC1) = (VC1–GND) = VPROTECT VDD = 4 to 10 V IIN Input current at VCx pins Measured at VC1, (VC2–VC1) = (VC1–GND) = 3.5 V, TA = 0°C to 60°C (See Figure 8-5.) V 200 mV 10 mV 200 mV µA –0.2 Measured at VC2, (VC2–VC1) = (VC1–GND) = 3.5 V, TA = 0°C to 60°C (See Figure 8-5.) 85 µA –8 mA 0.2 µA 2.5 µA VMM_DET_ON Cell mismatch detection threshold for turning ON (VC2–VC1) versus (VC1–GND) and vice-versa when cell balancing is enabled. VC2 = VDD = 7.6 V 17 30 45 mV VMM_DET_OFF Cell mismatch detection threshold for turning OFF Delta between (VC2–VC1) and (VC1–GND) when cell balancing is disabled. VC2 = VDD = 7.6 V –9 0 9 mV VCB_EN_ON Cell balance enable ON threshold Active LOW pin at CB_EN 1 V VCB_EN_OFF Cell balance enable OFF threshold Active HIGH at CB_EN ICB_EN Cell balance enable ON input current CB_EN = GND (See Figure 8-6.) RCB1int Internal cell balance switch resistance CB_EN = GND 300 Ω RCB2int Internal cell balance switch resistance CB_EN = GND 235 Ω (1) 2.2 V 0.2 µA Specified by design. Not 100% tested in production. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: BQ29209-Q1 5 BQ29209-Q1 www.ti.com SLUSC62D – JUNE 2015 – REVISED SEPTEMBER 2020 7.6 Recommended Cell Balancing Configurations Typical values stated where TA = 25°C and (VC2–VC1), (VC1–GND) = 3.8 V. Minimum and maximum values stated where TA = –40°C to 105°C, VDD = 4 V to 10 V, and (VC2–VC1), (VC1–GND) = 3 V to 4.2 V. All values assume recommended supply voltage filter resistance RVD of 100 Ω and 5% accurate or better cell balance resistor RCBext. MIN NOM MAX ICB RCBext = 4700 Ω 0.5 0.75 1 RCBext = 2200 Ω 1 1.5 2 RCBext = 910 Ω 2 3 4 Cell balance input current RCBext = 560 Ω 3 4.5 6 RCBext = 360 Ω 3.5 6 8.5 RCBext = 240 Ω 4 7.5 11 RCBext = 120 Ω 5 10 15 UNIT mA 7.7 Typical Characteristics Figure 7-1. ICD Charge Current Figure 7-2. ICD Discharge Current 3.3 3.2 ICC (uA) 3.1 3.0 2.9 2.8 2.7 2.6 2.5 -40 0 25 60 Operating Temperature (ƒC) 110 C002 Figure 7-3. Average ICC During Normal Operation Across Operational Temperature 6 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: BQ29209-Q1 BQ29209-Q1 www.ti.com SLUSC62D – JUNE 2015 – REVISED SEPTEMBER 2020 8 Detailed Description 8.1 Overview The BQ29209-Q1 provides overvoltage protection and cell balancing for 2-series cell lithium-ion battery packs. 8.1.1 Voltage Protection Each cell voltage is continuously compared to a factory configured internal reference threshold. If either cell reaches an overvoltage condition, the BQ29209-Q1 device starts a timer that provides a delay proportional to the capacitance on the CD pin. Upon expiration of the internal timer, the OUT pin changes from a low to high state. 8.1.2 Cell Balancing If enabled, the BQ29209-Q1 performs automatic cell-balance correction where the two cells are automatically corrected for voltage imbalance by loading the cell with the higher voltage with a small balancing current. When the cells are measured to be equal within nominally 0 mV, the load current is removed. It will be re-applied if the imbalance exceeds nominally 30 mV. The cell mismatch correction circuitry is enabled by pulling the CB_EN pin low, and disabled when CB_EN is pulled to greater than 2.2 V, for example, VDD. If the internal cell balancing current of up to 15 mA is insufficient, the BQ29209-Q1 may be configured via external circuitry to support much higher external cell balancing current. 8.2 Functional Block Diagram VDD 5-V LDO and POR VC2 CTRL + CB2_EN CB1 _EN CB Logic Hys. ICD = 150 nA – VC1 VC1_CB + OUT – GND CB_EN CD 0.1 µF 8.3 Feature Description 8.3.1 Protection (OUT) Timing Sizing the external capacitor is based on the desired delay time as follows: CCD = td XDELAY Where td is the desired delay time and XDELAY is the overvoltage delay time scale factor, expressed in seconds per microfarad. XDELAY is nominally 9 s/µF. For example, if a nominal delay of 3 seconds is desired, use a CCD capacitor that is 3 s / 9 s/µF = 0.33 µF. The delay time is calculated as follows: t d = CCD ´ XDELAY Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: BQ29209-Q1 7 BQ29209-Q1 www.ti.com SLUSC62D – JUNE 2015 – REVISED SEPTEMBER 2020 If the cell overvoltage condition is removed before the external capacitor reaches the reference voltage, the internal current source is disabled and an internal discharge block is employed to discharge the external capacitor down to 0 V. In this instance, the OUT pin remains in a low state. 8.3.2 Cell Voltage > VPROTECT When one or both of the cell voltages rises above VPROTECT, the internal comparator is tripped, and the delay begins to count to td. If the input remains above VPROTECT for the duration of td, the BQ29209-Q1 output changes from a low to a high state, by means of an internal pull-up network, to a regulated voltage of no more than 9.5 V when IOH = 0 mA. The external delay capacitor should charge up to no more than the internal LDO voltage (approximately 5 V typically), and will fully discharge in approximately under 100 ms when the overvoltage condition is removed. VPROTECT VPROTECT - VHYS Cell Voltage VC2-VC1, VC1-GND td L H OUT Figure 8-1. Timing for Overvoltage Sensing 8.3.3 Cell Connection Sequence Note Before connecting the cells, populate the overvoltage delay timing capacitor, CCD. The recommended cell connection sequence begins from the bottom of the stack, as follows: 1. GND 2. VC1 3. VC2 While not advised, connecting the cells in a sequence other than that described above does not result in errant activity on the OUT pin. For example: 1. GND 2. VC2 or VC1 3. Remaining VCx pin Note Using any cell connection sequence that does not connect GND first may result in increased leakage current drawn by the VDD pin. 8.3.4 Cell Balance Enable Control To avoid prematurely discharging the cells, it is recommended to turn off (pull high) the active-low Cell Balance Enable Control pin at lower state-of-charge (SOC) levels. 8 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: BQ29209-Q1 BQ29209-Q1 www.ti.com SLUSC62D – JUNE 2015 – REVISED SEPTEMBER 2020 8.3.5 Cell Balance Configuration The following cell balancing details relate to Figure 8-2. PACK+ RIN2 + CIN2 VCELL2 - RIN1 + VCELL1 - CIN1 1 VC2 RCB2int 2 VC1 3 VC1_CB VDD RVDD 7 CB_EN 6 RCB1int GND 5 4 CD RCBext OUT 8 CVDD PWR PAD CCD PACK- Figure 8-2. Simplified Schematic for Cell Balancing Description The cell balancing current may be calculated as follows: For Cell 1 balancing current, ICB1: VCELL1 ICB1 = RCBext + RCB1int (1) For Cell 2 balancing current, ICB2: VCELL2 ICB2 = RCBext + RCB2int + RVDD (2) Where: RCBext = resistor connected between the top of Cell 1 and the VC1_CB pin RIN1 = resistor connected between the top of Cell 1 and the VC1 pin RIN2 = resistor connected between the top of Cell 2 and the VC2 pin RVDD = resistor connected between the top of Cell 2 and the VDD pin 8.3.6 Cell Imbalance Auto-Detection (Via Cell Voltage) The VMM_DET_ON and VMM_DET_OFF specifications are calibrated where VDD = VC2 = 7.6 V and VC1 = 3.8 V. The recommended range of cell balancing is VC2 and VDD between 6.0 V and 8.4 V, and VC1 between 3 V and 4.2 V. Below VDD = 6 V, it is recommended to pull CB_EN high to disable the cell balancing function. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: BQ29209-Q1 9 BQ29209-Q1 www.ti.com SLUSC62D – JUNE 2015 – REVISED SEPTEMBER 2020 111% 100% 79% VC2 8.4 V 7.6 V 6V Figure 8-3. VMM_DET_ON and VMM_DET_OFF Threshold 8.3.7 Customer Test Mode Customer Test Mode (CTM) helps to greatly reduce the overvoltage detection delay time and enable quicker customer production testing. This mode is intended for quick-pass board-level verification tests, and, as such, individual cell overvoltage levels may deviate slightly from the specifications (VPROTECT, VOA). If accurate overvoltage thresholds are to be tested, use the standard delay settings that are intended for normal use. To enter CTM, VDD should be set to approximately 9.5 V higher than VC2. When CTM is entered, the device switches from the normal overvoltage delay time scale factor, XDELAY, to a significantly reduced factor of approximately 0.08, thereby reducing the delay time during an overvoltage condition. CAUTION Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part into CTM. Also, avoid exceeding absolute maximum voltages for the individual cell voltages (VC1–GND) and (VC2– VC1). Stressing the pins beyond the rated limits may cause permanent damage to the device. To exit CTM, power off the device and then power it back on. 15 V VDD Test Mode Entered VC2 > 10 ms 4.5 V (VC2–VC1) or (VC1–GND) VPROTECT VPROTECT –VHYST 4V OUT