BQ29209DRBR

Order Now Product Folder Tools & Software Technical Documents Support & Community bq29200, bq29209 ZHCSDT5C – SEPTEMBER 2010 – REVISED MARCH 2016 bq2920x 用于 2 节串联锂离子电池且具有自动电量平衡功能的电压保护 1 特性 • • 1 • • • • • • • • 3 说明 2 节串联电池二级保护 带外部使能控制的自动电量失衡校正 – ±30mV 使能阈值，0mV 禁用阈值（典型值） 外部电容控制的延迟定时器 外部电阻控制的电量平衡电流 低功耗 ICC < 3µA（典型值）（VCELL（总电压） < VPROTECT） 内部电量平衡功能可处理 高达 15mA 的电流 支持外部电量平衡模式 高精度过压保护： – ±25mV（TA = 0°C 至 60°C） 固定过压保护阈值： 4.30V，4.35V 小型 8 引脚 DRB 封装 bq2920x 器件是一款用于 2 节串联锂离子电池组的二 级过压保护集成电路 (IC)，集成有高精度精密过压检测 电路和自动电量失衡校正功能。 该 IC 将 2 节串联电池组中每节电池的电压与出厂设定 的内部参考电压进行比较。如果任一电池达到过压状 态，OUT 引脚由低电平转换为高电平状态。 bq2920x 可执行基于电压的自动电量失衡校正。当电 池电压与内部参考电压相差 30mV（标称值）或以上 时，启动电量平衡；当电池电压与内部参考电压相差 0mV（标称值）时，停止电量平衡。电量平衡功能由 CB_EN 引脚使能和禁用。 器件信息(1) 器件型号 bq29200 2 应用 • bq29209 封装 VSON (8) 封装尺寸（标称值） 3.00mm × 3.00mm (1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。 锂离子电池组二级保护 – 笔记本电脑 – 电动工具 – 便携式设备和仪器 – 备用电池系统 简化电路原理图 PACK+ RCB2 CELL2 CIN RCB1 1 VC2 OUT 8 2 VC1 VDD 7 CIN 3 VC1_CB CELL1 RCB RVD 4 CD CB_EN 6 GND 5 CVD PWR PAD CCD PACK- 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. English Data Sheet: SLUSA52 bq29200, bq29209 ZHCSDT5C – SEPTEMBER 2010 – REVISED MARCH 2016 www.ti.com.cn 目录 1 2 3 4 5 6 7 8 特性 .......................................................................... 应用 .......................................................................... 说明 .......................................................................... 修订历史记录 ........................................................... Device Options....................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 4 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 4 5 5 5 5 7 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Recommended Cell Balancing Configurations ......... Typical Characteristics .............................................. Detailed Description .............................................. 8 8.1 Overview ................................................................... 8 8.2 Functional Block Diagram ......................................... 8 8.3 Feature Description................................................... 8 8.4 Device Functional Modes........................................ 12 9 Application and Implementation ........................ 13 9.1 Application Information............................................ 13 9.2 Typical Applications ................................................ 13 9.3 System Example ..................................................... 14 10 Power Supply Recommendations ..................... 14 11 Layout................................................................... 15 11.1 Layout Guidelines ................................................. 15 11.2 Layout Example .................................................... 15 12 器件和文档支持 ..................................................... 16 12.1 12.2 12.3 12.4 12.5 相关链接................................................................ 社区资源................................................................ 商标 ....................................................................... 静电放电警告......................................................... Glossary ................................................................ 16 16 16 16 16 13 机械、封装和可订购信息 ....................................... 17 4 修订历史记录 Changes from Revision B (December 2014) to Revision C Page • 已更改 典型应用标题至简化原理图 ........................................................................................................................................ 1 • 已更改 电阻器 RVD 的位置，在简化原理图图形中添加了 PACK+ 和 PACK-.......................................................................... 1 • Deleted the Lead Temperature (soldering) from the Absolute Maximum Ratings table ....................................................... 4 • Deleted table notes 2 through 7 from the Thermal Information.............................................................................................. 5 • Changed resistor RVD location in Figure 9 ........................................................................................................................... 13 • Added title to Table 1............................................................................................................................................................ 13 • Changed resistor RVD location, added PACK+ and PACK- in Figure 11 ............................................................................ 14 Changes from Revision A (September 2010) to Revision B • Page 已添加 ESD 额定值表，特性 描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文 档支持部分以及机械、封装和可订购信息部分 ........................................................................................................................ 1 Changes from Original (June 2010) to Revision A Page • Changed values in XDELAY and XDELAY_CTM electrical characteristics....................................................................................... 5 • Changed specifications for VOUT ............................................................................................................................................. 6 • Changed test conditions for VOUT, IOH, and IOL ....................................................................................................................... 6 • Added VMM_DET_ON: VC2 = VDD = 7.6 V ................................................................................................................................. 6 • Changed VMM_DET_OFF: From VDD – VC2 – 7.6 V to VC2 = VDD = 7.6 V.............................................................................. 6 • Changed content in Recommended Cell Balancing Configurations section .......................................................................... 7 • Added ICD Charge Current figure ............................................................................................................................................ 7 • Added ICD Discharge Current figure ....................................................................................................................................... 7 • Changed XDELAY from nominally 8.0 s/µF to nominally 9.0 s/µF............................................................................................. 8 • Changed Timing for Overvoltage Sensing figure ................................................................................................................... 9 • Added Cell Imbalance Auto-Detection (Via Cell Voltage) section ........................................................................................ 10 • Changed VDD value in Customer Test Mode from 8.5 V to 9.5 V....................................................................................... 10 2 Copyright © 2010–2016, Texas Instruments Incorporated bq29200, bq29209 www.ti.com.cn ZHCSDT5C – SEPTEMBER 2010 – REVISED MARCH 2016 • Changed the Voltage Test Limits figure ............................................................................................................................... 11 • Added External Cell Balancing section................................................................................................................................. 14 Copyright © 2010–2016, Texas Instruments Incorporated 3 bq29200, bq29209 ZHCSDT5C – SEPTEMBER 2010 – REVISED MARCH 2016 www.ti.com.cn 5 Device Options TA PART NUMBER OVP BQ29200 4.35 V BQ29209 4.30 V –40°C to +110°C 6 Pin Configuration and Functions DRB Package 8-Pin VSON Top View VC2 1 VC1 2 8 OUT 7 VDD PWR PAD VC1_CB 3 6 CB_EN CD 4 5 GND Pin Functions PIN DESCRIPTION NAME NO. CB_EN 6 Cell balance enable CD 4 Connection to external capacitor for programmable delay time GND 5 Ground pin OUT 8 Output Thermal Pad PWR PAD VC1 2 Sense voltage input for bottom cell VC1_CB 3 Cell balance input for bottom cell VC2 1 Sense voltage input for top cell VDD 7 Power supply GND pin to be connected to the PWRPAD on the printed circuit board for proper operation 7 Specifications 7.1 Absolute Maximum Ratings Over-operating free-air temperature range (unless otherwise noted) (1) Supply voltage range, VMAX Input voltage range, VIN Output voltage range, VOUT MIN MAX UNIT VDD–GND –0.3 16 V VC2–GND, VC1–GND –0.3 16 V VC2–VC1, CD–GND –0.3 8 V CB_EN–GND –0.3 16 V OUT–GND –0.3 16 V Continuous total power dissipation, PTOT Storage temperature range, Tstg (1) 4 See Thermal Information. –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Copyright © 2010–2016, Texas Instruments Incorporated bq29200, bq29209 www.ti.com.cn ZHCSDT5C – SEPTEMBER 2010 – REVISED MARCH 2016 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. 7.3 Recommended Operating Conditions MIN Supply voltage, VDD NOM MAX 4 10 0 5 UNIT V Input voltage range VC2–VC1, VC1–GND Delay time capacitance, td(CD) CCD (See Figure 9.) Voltage monitor filter resistance RIN (See Figure 9.) 100 1K Ω Voltage monitor filter capacitance CIN (See Figure 9.) 0.01 0.1 µF Supply voltage filter resistance RVD (See Figure 9.) 100 Supply voltage filter capacitance CVD (See Figure 9.) 0.1 Cell balance resistance RCB (See Figure 9 and Protection (OUT) Timing.) 0.1 Operating ambient temperature range, TA V µF 1K Ω µF 100 4.7K Ω –40 110 °C 7.4 Thermal Information bq2920x THERMAL METRIC (1) DRB UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 50.5 °C/W RθJC(top) Junction-to-case(top) thermal resistance 25.1 °C/W RθJB Junction-to-board thermal resistance 19.3 °C/W ψJT Junction-to-top characterization parameter 0.7 °C/W ψJB Junction-to-board characterization parameter 18.9 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance 5.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics Typical values stated where TA = 25°C and VDD = 7.2 V. Minimum and maximum values stated where TA = –40°C to 110°C and VDD = 4 V to 10 V (unless otherwise noted). PARAMETER VPROTECT Overvoltage bq29209 detection bq29200 voltage VHYS Overvoltage detection hysteresis VOA Overvoltage detection accuracy VOA_DRIFT Overvoltage threshold temperature drift XDELAY Overvoltage delay time scale factor TEST CONDITIONS MIN TYP MAX UNIT 4.3 V 4.35 200 300 400 mV mV TA = 25°C –10 10 TA = 0°C to 60°C –0.4 0.4 TA = –40°C to 110°C –0.6 0.6 TA = 0°C to 60°C Note: Does not include external capacitor variation. 6 9 12 TA = –40°C to 110°C Note: Does not include external capacitor variation. 5.5 9 13.5 Copyright © 2010–2016, Texas Instruments Incorporated mV°/C s/µF 5 bq29200, bq29209 ZHCSDT5C – SEPTEMBER 2010 – REVISED MARCH 2016 www.ti.com.cn Electrical Characteristics (continued) Typical values stated where TA = 25°C and VDD = 7.2 V. Minimum and maximum values stated where TA = –40°C to 110°C and VDD = 4 V to 10 V (unless otherwise noted). PARAMETER TYP MAX UNIT XDELAY_CTM (1) Overvoltage delay time scale factor in Customer Test Mode TEST CONDITIONS MIN 0.08 s/µF ICD(CHG) Overvoltage detection charging current 150 nA ICD(DSG) Overvoltage detection discharging current 60 µA VCD Overvoltage detection external capacitor comparator threshold 1.2 V ICC Supply current (VC2–VC1) = (VC1–GND) = 3.5 V (See Figure 7.) (VC2–VC1) or (VC1–GND) > VPROTECT, VDD = 10 V, IOH = 0 (VC2–VC1) or (VC1–GND) = VPROTECT, VDD = VPROTECT, IOH = –100 µA, TA = 0°C to 60°C VOUT OUT pin drive voltage 3 6 µA 6 8.25 9.5 V 1.75 2.5 (VC2–VC1) and (VC1–GND) < VPROTECT , IOL = 100 µA, TA = 25°C (VC2–VC1) and (VC1–GND) < VPROTECT , IOL = 0 µA, TA = 25°C 0 VC2 = VC1 = VDD = 4 V, IOL = 100 µA IOH High-level output current OUT = 1.75 V, (VC2–VC1) or (VC1–GND) = VPROTECT, VDD = VPROTECT to 10 V, TA = 0°C to 60°C IOL Low-level output current OUT = 0.05 V, (VC2–VC1) or (VC1–GND) < VPROTECT, VDD = VPROTECT to 10 V, TA = 0°C to 60°C IOH_ZV High-level short-circuit output current OUT = 0 V, (VC2–VC1) = (VC1–GND) = VPROTECT VDD = 4 to 10 V IIN Input current at VCx pins Measured at VC1, (VC2–VC1) = (VC1–GND) = 3.5 V, TA = 0°C to 60°C (See Figure 7.) –100 30 V 200 mV 10 mV 200 mV µA –0.2 Measured at VC2, (VC2–VC1) = (VC1–GND) = 3.5 V, TA = 0°C to 60°C (See Figure 7.) 85 µA –8 mA 0.2 µA 2.5 µA VMM_DET_ON Cell mismatch detection threshold for turning ON (VC2–VC1) versus (VC1–GND) and vice-versa when cell balancing is enabled. VC2 = VDD = 7.6 V 17 30 45 mV VMM_DET_OFF Cell mismatch detection threshold for turning OFF Delta between (VC2–VC1) and (VC1–GND) when cell balancing is disabled. VC2 = VDD = 7.6 V –9 0 9 mV VCB_EN_ON Cell balance enable ON threshold Active LOW pin at CB_EN 1 V VCB_EN_OFF Cell balance enable OFF threshold Active HIGH at CB_EN ICB_EN Cell balance enable ON input current CB_EN = GND (See Figure 8.) RCB1 Internal cell balance switch resistance CB_EN = GND Ω RCB2 Internal cell balance switch resistance CB_EN = GND Ω (1) 6 2.2 V 0.2 µA Specified by design. Not 100% tested in production. Copyright © 2010–2016, Texas Instruments Incorporated bq29200, bq29209 www.ti.com.cn ZHCSDT5C – SEPTEMBER 2010 – REVISED MARCH 2016 7.6 Recommended Cell Balancing Configurations Typical values stated where TA = 25°C and (VC2–VC1), (VC1–GND) = 3.8 V. Minimum and maximum values stated where TA = –40°C to 110°C, VDD = 4 V to 10 V, and (VC2–VC1), (VC1–GND) = 3 V to 4.2 V. All values assume recommended supply voltage filter resistance RVD of 100 Ω and 5% accurate or better cell balance resistor RCB. MIN NOM MAX ICB Cell balance input current RCB = 4700 Ω 0.5 0.75 1 RCB = 2200 Ω 1 1.5 2 RCB = 910 Ω 2 3 4 RCB = 560 Ω 3 4.5 6 RCB = 360 Ω 3.5 6 8.5 RCB = 240 Ω 4 7.5 11 RCB = 120 Ω 5 10 15 UNIT mA -80 80 -90 75 -100 ICD Discharge Current (PA) ICD Charge Current (nA) 7.7 Typical Characteristics -110 -120 -130 -140 -150 -160 65 60 55 50 45 -170 -180 -40 70 -20 0 20 40 60 Temperature (qC) 80 40 -40 100 -20 0 D001 Figure 1. ICD Charge Current 20 40 60 Temperature (qC) 80 100 D002 Figure 2. ICD Discharge Current 3.3 3.2 ICC (uA) 3.1 3.0 2.9 2.8 2.7 2.6 2.5 -40 0 25 60 Operating Temperature (ƒC) 110 C002 Figure 3. Average ICC During Normal Operation Across Operational Temperature Copyright © 2010–2016, Texas Instruments Incorporated 7 bq29200, bq29209 ZHCSDT5C – SEPTEMBER 2010 – REVISED MARCH 2016 www.ti.com.cn 8 Detailed Description 8.1 Overview The bq2920x provides overvoltage protection and cell balancing for 2-series cell lithium-ion battery packs. 8.1.1 Voltage Protection Each cell voltage is continuously compared to a factory configured internal reference threshold. If either cell reaches an overvoltage condition, the bq2920x device starts a timer that provides a delay proportional to the capacitance on the CD pin. Upon expiration of the internal timer, the OUT pin changes from a low to high state. 8.1.2 Cell Balancing If enabled, the bq2920x performs automatic cell-balance correction where the two cells are automatically corrected for voltage imbalance by loading the cell with the higher voltage with a small balancing current. When the cells are measured to be equal within nominally 0 mV, the load current is removed. It will be re-applied if the imbalance exceeds nominally 30 mV. The cell mismatch correction circuitry is enabled by pulling the CB_EN pin low, and disabled when CB_EN is pulled to greater than 2.2 V, for example, VDD. If the internal cell balancing current of up to 15 mA is insufficient, the bq2920x may be configured via external circuitry to support much higher external cell balancing current. 8.2 Functional Block Diagram VDD 5-V LDO and POR VC2 CTRL + CB2_EN CB1 _EN CB Logic Hys. ICD = 150 nA – VC1 VC1_CB + OUT – GND CB_EN CD 0.1 µF 8.3 Feature Description 8.3.1 Protection (OUT) Timing Sizing the external capacitor is based on the desired delay time as follows: CCD = td XDELAY Where td is the desired delay time and XDELAY is the overvoltage delay time scale factor, expressed in seconds per microFarad. XDELAY is nominally 9 s/µF. For example, if a nominal delay of 3 seconds is desired, use a CCD capacitor that is 3 s / 9 s/µF = 0.33 µF. The delay time is calculated as follows: t d = CCD ´ XDELAY 8 Copyright © 2010–2016, Texas Instruments Incorporated bq29200, bq29209 www.ti.com.cn ZHCSDT5C – SEPTEMBER 2010 – REVISED MARCH 2016 Feature Description (continued) If the cell overvoltage condition is removed before the external capacitor reaches the reference voltage, the internal current source is disabled and an internal discharge block is employed to discharge the external capacitor down to 0 V. In this instance, the OUT pin remains in a low state. 8.3.2 Cell Voltage > VPROTECT When one or both of the cell voltages rises above VPROTECT, the internal comparator is tripped, and the delay begins to count to td. If the input remains above VPROTECT for the duration of td, the bq2920x output changes from a low to a high state, by means of an internal pull-up network, to a regulated voltage of no more than 9.5 V when IOH = 0 mA. The external delay capacitor should charge up to no more than the internal LDO voltage (approximately 5 V typically), and will fully discharge in approximately under 100 ms when the overvoltage condition is removed. VPROTECT VPROTECT - VHYS Cell Voltage VC2-VC1, VC1-GND td L H OUT Figure 4. Timing for Overvoltage Sensing 8.3.3 Cell Connection Sequence NOTE Before connecting the cells, populate the overvoltage delay timing capacitor, CCD. The recommended cell connection sequence begins from the bottom of the stack, as follows: 1. GND 2. VC1 3. VC2 While not advised, connecting the cells in a sequence other than that described above does not result in errant activity on the OUT pin. For example: 1. GND 2. VC2 or VC1 3. Remaining VCx pin 8.3.4 Cell Balance Enable Control To avoid prematurely discharging the cells, it is recommended to turn off (pull high) the active-low Cell Balance Enable Control pin at lower State of Charge (SOC) levels. Copyright © 2010–2016, Texas Instruments Incorporated 9 bq29200, bq29209 ZHCSDT5C – SEPTEMBER 2010 – REVISED MARCH 2016 www.ti.com.cn Feature Description (continued) 8.3.5 Cell Balance Configuration The cell balancing current may be calculated as follows: For Cell 1 (VC1–GND) balancing current, ICB1: ICB1 = VC1 RCB + RCB1 (1) For Cell 2 (VC2–VC1) balancing current, ICB2: ICB2 = (VC2 - VC1) (RCB + R VD )+ RCB2 (2) Where: RCB = resistor connected between the top of Cell 1 and the VC1_CB RCB1 = resistor connected between the top of Cell 1 and the VC1 RCB2 = resistor connected between the top of Cell 2 and the VC2 RVD = resistor connected between the top of Cell 2 and the VDD 8.3.6 Cell Imbalance Auto-Detection (Via Cell Voltage) The VMM_DET_ON and VMM_DET_OFF specifications are calibrated where VDD = VC2 = 7.6 V and VC1 = 3.8 V. The recommended range of cell balancing is VC2 and VDD between 6.0 V and 8.4 V, and VC1 between 3 V and 4.2 V. Below VDD = 6 V, it is recommended to pull CB_EN high to disable the cell balancing function. 111% 100% 79% VC2 6V 7.6 V 8.4 V Figure 5. VMM_DET_ON and VMM_DET_OFF Threshold 8.3.7 Customer Test Mode Customer Test Mode (CTM) helps to greatly reduce the overvoltage detection delay time and enable quicker customer production testing. This mode is intended for quick-pass board-level verification tests, and, as such, individual cell overvoltage levels may deviate slightly from the specifications (VPROTECT, VOA). If accurate overvoltage thresholds are to be tested, use the standard delay settings that are intended for normal use. To enter CTM, VDD should be set to approximately 9.5 V higher than VC2. When CTM is entered, the device switches from the normal overvoltage delay time scale factor, XDELAY, to a significantly reduced factor of approximately 0.08, thereby reducing the delay time during an overvoltage condition. 10 Copyright © 2010–2016, Texas Instruments Incorporated bq29200, bq29209 www.ti.com.cn ZHCSDT5C – SEPTEMBER 2010 – REVISED MARCH 2016 Feature Description (continued) CAUTION Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part into CTM. Also, avoid exceeding absolute maximum voltages for the individual cell voltages (VC1–GND) and (VC2–VC1). Stressing the pins beyond the rated limits may cause permanent damage to the device. To exit CTM, power off the device and then power it back on. 15 V VDD Test Mode Entered VC2 > 10 ms 4.5 V (VC2–VC1) or (VC1–GND) VPROTECT VPROTECT –VHYST 4V