CC3220R, CC3220S, CC3220SF
SWAS035C – SEPTEMBER 2016 – REVISED MAY 2021
CC3220R, CC3220S, and CC3220SF SimpleLink™ Wi-Fi®
Single-Chip Wireless MCU Solutions
1 Features
•
•
•
•
•
•
Dual-Core Architecture:
– User-Dedicated Application MCU Subsystem
– Highly-Integrated Wi-Fi Network Processor
Rich Set of IoT Security Features:
– Enhanced IoT Networking Security
– Asymmetric Keys and Unique Device Identity
– Software IP Protection and Secure Storage
(CC3220S/CC3220SF)
Advanced Low-Power Modes for Battery Powered
Applications
Built-In Power Management Subsystem
Industrial Temperature: –40°C to 85°C
Chip-Level Wi-Fi Alliance® Wi-Fi CERTIFIED™
Extended Features List:
•
•
Applications Microcontroller Subsystem:
– Arm® Cortex®-M4 Core at 80 MHz
– Embedded Memory:
• 256KB of RAM
• Optional 1MB of Executable Flash
• External Serial Flash
– Peripherals:
• McASP Supports Two I2S Channels
• SD, SPI, I2C, UART
• 8-Bit Synchronous Imager Interface
• 4-Channel 12-Bit ADCs
• 4 General-Purpose Timers (GPT) With 16Bit PWM Mode
• Watchdog Timer
• Up to 27 GPIO Pins
• Debug Interfaces: JTAG, cJTAG, SWD
Wi-Fi Network Processor (NWP) Subsystem:
– Wi-Fi Modes:
• 802.11b/g/n Station
• 802.11b/g Access Point (AP) Supports up to
Four Stations
• Wi-Fi Direct® Client and Group Owner
– WPA2 Personal and Enterprise Security:
WEP, WPA™/ WPA2™ PSK, WPA2 Enterprise
(802.1x), WPA3™ Personal, WPA3™ Enterprise
– IPv4 and IPv6 TCP/IP Stack
– Industry-Standard BSD Socket Application
Programming Interfaces (APIs):
• 16 Simultaneous TCP or UDP Sockets
• 6 Simultaneous TLS and SSL Sockets
– IP Addressing: Static IP, LLA, DHCPv4,
DHCPv6 With Duplicate Address Detection
(DAD)
– SimpleLink Connection Manager for
Autonomous and Fast Wi-Fi Connections
– Flexible Wi-Fi Provisioning With SmartConfig™
Technology, AP Mode, and WPS2 Options
– RESTful API Support Using the Internal HTTP
Server
– Wide Set of Security Features:
• Hardware Features:
– Separate Execution Environments
– Device Identity
– Hardware Crypto Engine for Advanced
Fast Security, Including: AES, DES,
3DES, SHA2, MD5, CRC, and
Checksum
– Initial Secure Programming:
• Debug Security
• JTAG and Debug Ports are Locked
– Personal and Enterprise Wi-Fi Security
– Secure Sockets (SSLv3, TLS1.0,
TLS1.1, TLS1.2)
• Networking Security:
– Personal and Enterprise Wi-Fi Security
– Secure Sockets (SSLv3, TLS1.0,
TLS1.1, TLS1.2)
– HTTPS Server
– Trusted Root-Certificate Catalog
– TI Root-of-Trust Public Key
• Software IP Protection:
– Secure Key Storage
– File System Security
– Software Tamper Detection
– Cloning Protection
– Secure Boot: Validate the Integrity and
Authenticity of the Runtime Binary During
Boot
– Embedded Network Applications Running on
the Dedicated Network Processor:
• HTTP/HTTPS Web Server With Dynamic
User Callbacks
• mDNS, DNS-SD, DHCP Server
• Ping
– Recovery Mechanism—Can Recover to Factory
Defaults or to a Complete Factory Image
– Wi-Fi TX Power:
• 18.0 dBm at 1 DSSS
• 14.5 dBm at 54 OFDM
– Wi-Fi RX Sensitivity:
• –96 dBm at 1 DSSS
• –74.5 dBm at 54 OFDM
– Application Throughput:
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC3220R, CC3220S, CC3220SF
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SWAS035C – SEPTEMBER 2016 – REVISED MAY 2021
•
• UDP: 16 Mbps
• TCP: 13 Mbps
• Peak: 72 Mbps
Power-Management Subsystem:
– Integrated DC/DC Converters Support a Wide
Range of Supply Voltage:
• VBAT Wide-Voltage Mode: 2.1 V to 3.6 V
• VIO is Always Tied With VBAT
• Preregulated 1.85-V Mode
– Advanced Low-Power Modes:
• Shutdown: 1 µA
• Hibernate: 4.5 µA
• Low-Power Deep Sleep (LPDS): 135 µA
(Measured on CC3220R, CC3220S, and
CC3220SF With 256KB RAM Retention)
• RX Traffic (MCU Active): 59 mA (Measured
on CC3220R and CC3220S; CC3220SF
Consumes an Additional 10 mA) at
54 OFDM
• TX Traffic (MCU Active): 223 mA (Measured
on CC3220R and CC3220S; CC3220SF
Consumes an Additional 15 mA) at
54 OFDM, Maximum Power
• Idle Connected (MCU in LPDS): 710 µA
(Measured on CC3220R and CC3220S With
256KB RAM Retention) at DTIM = 1
•
•
•
•
Clock Source:
– 40.0-MHz Crystal With Internal Oscillator
– 32.768-kHz Crystal or External RTC
RGK Package
– 64-Pin, 9-mm × 9-mm Very Thin Quad Flat
Nonleaded (VQFN) Package, 0.5-mm Pitch
Operating Temperature
– Ambient Temperature Range: –40°C to +85°C
Device Supports SimpleLink™ MCU Platform
Developer's Ecosystem
2 Applications
•
For Internet of Things applications, such as:
– Building and Home Automation:
• HVAC Systems & Thermostat
• Video Surveillance, Video Doorbells, and
Low-Power Camera
• Building Security Systems & E-locks
– Appliances
– Asset Tracking
– Factory Automation
– Medical and Healthcare
– Grid Infrastructure
3 Description
The SoC Wireless MCU CC3220x device comes in three variants: CC3220R, CC3220S, and C3220SF.
• CC3220R features 256KB of RAM, IoT networking security and device identity/keys.
• CC3220S builds on the CC3220R and MCU level security such as file system encryption, user IP (MCU
image) encryption, secure boot and debug security.
• CC3220SF builds on the CC3220S and integrates a user-dedicated 1MB of executable Flash, in addition to
the 256KB of RAM.
Start your internet-of-things (IoT) design with a Wi-Fi CERTIFIED™ Wireless Microcontroller. The SimpleLink™
Wi-Fi® CC3220x device family is a system-on-chip (SoC) solution, that integrates two processors within a
single-chip:
•
•
The application processor is an Arm® Cortex®-M4 MCU with a user-dedicated 256KB of RAM and an optional
1MB of serial flash.
The network processor MCU runs all Wi-Fi® and internet logical layers. This ROM-based subsystem includes
an 802.11b/g/n radio, baseband, and MAC with a powerful crypto engine.
These devices introduce new features and capabilities that further simplify the connectivity of things to the
internet. The main new features include the following:
• Optimized low-power management
• Enhanced networking security
• Device identity and Asymmetric keys
• Enhanced file system security (supported only by the CC3220S and CC3220SF variants)
• IPv6 TCP/IP Stack
• AP mode with support of four stations
• Up to 16 concurrent BSD sockets, of which 6 are secure
• HTTPS support
• RESTful API support
2
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The CC3220x device family is part of the SimpleLink™ MCU platform, a common, easy-to-use development
environment based on a single core software development kit (SDK), rich tool set, reference designs and E2E™
community that supports Wi-Fi®, Bluetooth® low energy, Sub-1 GHz and host MCUs. For more information, visit
the SimpleLink™ MCU Platform.
Device Information
PART NUMBER (1)
PACKAGE
BODY SIZE (NOM)
CC3220RM2ARGKR/T
VQFN (64)
9.00 mm × 9.00 mm
CC3220SM2ARGKR/T
VQFN (64)
9.00 mm × 9.00 mm
CC3220SF12ARGKR/T
VQFN (64)
9.00 mm × 9.00 mm
(1)
For all available packages, see the orderable addendum at the end of the data sheet.
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4 Functional Block Diagrams
Figure 4-1 shows the functional block diagram of the CC3220x SimpleLink Wi-Fi solution.
Figure 4-1. Functional Block Diagram
4
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Figure 4-2 shows the CC3220x hardware overview.
CC32xx ± Single-Chip Wireless MCU
1MB flash (optional)
256KB RAM
Arm® Cortex®-M4
Processor
80 MHz
ROM
1× SPI
2× UART
1× I2S/PCM
DMA
System
Timers
1× SD/MMC
Peripherals
1× I2C
8-bit Camera
GPIOs
4× ADC
Network Processor
Application
Protocols
Wi-Fi® Driver
TCP/IP Stack
Oscillators
(Arm® Cortex®
Processor)
DC/DC
ROM
Baseband
MAC
Processor
Radio
Synthesizer
RTC
Crypto Engine
RAM
Power
Management
Figure 4-2. CC3220x Hardware Overview
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Figure 4-3 shows an overview of the CC3220x embedded software.
Customer Application
NetApp
BSD Socket
Wi-Fi®
6LPSOH/LQNΠ'ULYHU $3,V
Host Interface
Network Apps
WLAN Security
and
Management
TCP/IP Stack
WLAN MAC and PHY
Figure 4-3. CC3220x Embedded Software Overview
6
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 2
3 Description.......................................................................2
4 Functional Block Diagrams............................................ 4
5 Revision History.............................................................. 7
6 Device Comparison......................................................... 8
6.1 Related Products........................................................ 9
7 Terminal Configuration and Functions........................10
7.1 Pin Diagram.............................................................. 10
7.2 Pin Attributes and Pin Multiplexing............................11
7.3 Signal Descriptions................................................... 19
7.4 Pin Multiplexing.........................................................24
7.5 Drive Strength and Reset States for Analog and
Digital Multiplexed Pins............................................... 26
7.6 Pad State After Application of Power to Chip But
Before Reset Release................................................. 26
7.7 Connections for Unused Pins................................... 27
8 Specifications................................................................ 28
8.1 Absolute Maximum Ratings...................................... 28
8.2 ESD Ratings............................................................. 28
8.3 Power-On Hours (POH)............................................ 28
8.4 Recommended Operating Conditions.......................29
8.5 Current Consumption Summary (CC3220R,
CC3220S) ...................................................................29
8.6 Current Consumption Summary (CC3220SF).......... 31
8.7 TX Power and IBAT versus TX Power Level
Settings....................................................................... 32
8.8 Brownout and Blackout Conditions........................... 34
8.9 Electrical Characteristics (3.3 V, 25°C)..................... 35
8.10 WLAN Receiver Characteristics..............................37
8.11 WLAN Transmitter Characteristics.......................... 37
8.12 WLAN Filter Requirements..................................... 38
8.13 Thermal Resistance Characteristics....................... 38
8.14 Timing and Switching Characteristics..................... 38
9 Detailed Description......................................................56
9.1 Arm® Cortex®-M4 Processor Core Subsystem.........56
9.2 Wi-Fi Network Processor Subsystem....................... 57
9.3 Security..................................................................... 59
9.4 Power-Management Subsystem...............................61
9.5 Low-Power Operating Mode..................................... 62
9.6 Memory..................................................................... 64
9.7 Restoring Factory Default Configuration...................67
9.8 Boot Modes...............................................................67
10 Applications, Implementation, and Layout............... 68
10.1 Application Information........................................... 68
10.2 PCB Layout Guidelines...........................................73
11 Device and Documentation Support..........................76
11.1 Development Tools and Software........................... 76
11.2 Firmware Updates...................................................77
11.3 Device Nomenclature..............................................77
11.4 Documentation Support.......................................... 78
11.5 Support Resources................................................. 80
11.6 Trademarks............................................................. 80
11.7 Electrostatic Discharge Caution.............................. 80
11.8 Export Control Notice.............................................. 80
11.9 Glossary.................................................................. 81
12 Mechanical, Packaging, and Orderable
Information.................................................................... 82
12.1 Packaging Information............................................ 82
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from November 29, 2018 to May 13, 2021 (from Revision B (November 2018) to
Revision C (May 2021))
Page
• Updated formatting and organization to reflect current TI standards..............................................................0
• Added WPA3 Personal and WPA3 Enterprise to Section 1 ............................................................................... 1
• Added WPA3 personal and enterprise to Section 9.2 ......................................................................................57
• Added WPA3 personal and enterprise to Section 9.2.1 ...................................................................................57
• Added WPA3 personal and enterprise to Table 9-1 .........................................................................................57
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6 Device Comparison
Table 6-1 shows the features supported across different CC3220 devices.
Table 6-1. Device Features Comparison
DEVICE
FEATURE
CC3220R
CC3220S
CC3220SF
On-Chip Application Memory
RAM
256KB
256KB
256KB
Flash
–
–
1MB
Enhanced Application Level
Security
–
File system security
Secure key storage
Software tamper detection
Cloning protection
Initial secure programming
File system security
Secure key storage
Software tamper detection
Cloning protection
Initial secure programming
Hardware Acceleration
Hardware Crypto Engines
Hardware Crypto Engines
Hardware Crypto Engines
Additional Networking Security
Unique Device Identity
Trusted Root-Certificate Catalog
TI Root-of-Trust Public key
Unique Device Identity
Trusted Root-Certificate Catalog
TI Root-of-Trust Public key
Unique Device Identity
Trusted Root-Certificate Catalog
TI Root-of-Trust Public key
Secure Boot
No
Yes
Yes
Security Features
Additional Features
Standard
TCP/IP Stack
8
802.11 b/g/n
IPv4, IPv6
Package
9 mm × 9 mm VQFN
Sockets
16
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6.1 Related Products
For information about other devices in this family of products or related products, see the following links:
SimpleLink™ MCU
Portfolio
This portfolio offers a single development environment that delivers flexible hardware,
software and tool options for customers developing wired and wireless applications.
With 100 percent code reuse across host MCUs, Wi-Fi™, Bluetooth® low energy,
Sub-1 GHz devices and more, choose the MCU or connectivity standard that fits your
design. A one-time investment with the SimpleLink software development kit (SDK)
allows you to reuse often, opening the door to create unlimited applications.
SimpleLink™ Wi-Fi®
Family
This device platform offers several Internet-on-a chip™ solutions, which address the
need of battery operated, security enabled products. Texas instruments offers a single
chip wireless microcontroller and a wireless network processor which can be paired
with any MCU, to allow developers to design new wi-fi products, or upgrade existing
products with wi-fi capabilities.
BoosterPack™ Plug-In
Modules
The BoosterPack Plug-in modules extend the functionality of TI LaunchPad
Development Kit. Application-specific BoosterPack Plug-in modules allow you to
explore a broad range of applications, including capacitive touch, wireless sensing,
LED Lighting control, and more. Stack multiple BoosterPack modules onto a single
LaunchPad kit to further enhance the functionality of your design.
Reference Designs for
CC3200 and CC3220
Devices
TI Designs Reference Design Library is a robust reference design library spanning
analog, embedded processor and connectivity. Created by TI experts to help you
jump start your system design, all TI Designs include schematic or block diagrams,
BOMs and design files to speed your time to market. Search and download designs at
ti.com/tidesigns.
SimpleLink™ Wi-Fi®
CC3220 SDK
This SDK contains drivers for the CC3220 programmable MCU, sample applications,
and documentation required to start development with CC3220 solutions.
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7 Terminal Configuration and Functions
7.1 Pin Diagram
37
VDD_PA_IN
38
SOP1
39
LDO_IN1
40
SOP0
41
VIN_DCDC_ANA
42
VIN_DCDC_PA
43
DCDC_ANA_SW
44
DCDC_PA_SW_P
45
DCDC_PA_OUT
DCDC_DIG_SW
46
DCDC_PA_SW_N
VIN_DCDC_DIG
47
DCDC_ANA2_SW_N
VDD_ANA2
48
DCDC_ANA2_SW_P
VDD_ANA1
VQFN 64-Pin Assignments Top View shows pin assignments for the 64-pin VQFN package.
36
35
34
33
VDD_RAM
49
32
nRESET
GPIO0
50
31
RF_BG
ANTSEL2
RTC_XTAL_P
51
30
RTC_XTAL_N
52
29
ANTSEL1
GPIO30
53
28
NC
VIN_IO2
54
27
NC
GPIO1
55
26
NC
VDD_DIG2
56
25
LDO_IN2
GPIO2
57
24
VDD_PLL
GPIO3
58
23
WLAN_XTAL_P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GPIO22
TDI
TDO
FLASH_SPI_CS
GPIO28
17
FLASH_SPI_DIN
18
64
FLASH_SPI_DOUT
63
GPIO9
VIN_IO1
GPIO8
FLASH_SPI_CLK
TCK
VDD_DIG1
TMS
19
GPIO17
20
62
GPIO16
61
GPIO7
GPIO15
GPIO6
GPIO14
SOP2
GPIO12
WLAN_XTAL_N
21
GPIO13
22
60
GPIO10
59
GPIO11
GPIO4
GPIO5
NC = No internal connection
Figure 7-1. VQFN 64-Pin Assignments Top View
10
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7.2 Pin Attributes and Pin Multiplexing
The device makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in
the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of
hardware configuration (at device reset) and register control.
Note
TI highly recommends using Pin Mux Tool to obtain the desired pinout.
The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does
not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used.
Section 7.2.1 and Table 7-1 list the pin descriptions and attributes. Section 7.3.1 lists the signal descriptions.
Table 7-2 presents an overall view of pin multiplexing. All pin multiplexing options are configurable using the pin
mux registers.
The following special considerations apply:
•
•
•
•
•
All I/Os support drive strengths of 2, 4, and 6 mA. The drive strength is individually configurable for each pin.
All I/Os support 10-µA pullup and pulldown resistors.
The VIO and VBAT supply must be tied together at all times.
By default, all I/Os float in the Hibernate state. However, the default state can be changed by SW.
All digital I/Os are nonfail-safe.
Note
If an external device drives a positive voltage to the signal pads and the CC3220x device is not
powered, DC is drawn from the other device. If the drive strength of the external device is adequate,
an unintentional wakeup and boot of the CC3220x device can occur. To prevent current draw, TI
recommends any one of the following conditions:
• All devices interfaced to the CC3220x device must be powered from the same power rail as the
chip.
• Use level shifters between the device and any external devices fed from other independent rails.
• The nRESET pin of the CC3220x device must be held low until the VBAT supply to the device is
driven and stable.
• All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the
TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other pins are left in the Hi-Z state.
7.2.1 Pin Descriptions
PINS
NO.
NAME
TYPE
DESCRIPTION
SELECT AS
WAKEUP
SOURCE
CONFIGURE
ADDITIONAL
ANALOG MUX
MUXED
WITH JTAG
1
GPIO10
I/O
General-purpose input or output
No
No
No
2
GPIO11
I/O
General-purpose input or output
Yes
No
No
3
GPIO12
I/O
General-purpose input or output
No
No
No
4
GPIO13
I/O
General-purpose input or output
Yes
No
No
5
GPIO14
I/O
General-purpose input or output
No
No
No
6
GPIO15
I/O
General-purpose input or output
No
No
No
7
GPIO16
I/O
General-purpose input or output
No
No
No
8
GPIO17
I/O
General-purpose input or output
Yes
No
No
9
VDD_DIG1
Power
Internal digital core voltage
N/A
N/A
N/A
Power
I/O power supply (same as
battery voltage)
N/A
N/A
N/A
Serial flash interface: SPI clock
N/A
N/A
N/A
10
VIN_IO1
11
FLASH_SPI_CLK
O
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PINS
NO.
NAME
TYPE
DESCRIPTION
SELECT AS
WAKEUP
SOURCE
CONFIGURE
ADDITIONAL
ANALOG MUX
MUXED
WITH JTAG
12
FLASH_SPI_DOUT
O
Serial flash interface: SPI data
out
N/A
N/A
N/A
13
FLASH_SPI_DIN
I
Serial flash interface: SPI data in
N/A
N/A
N/A
N/A
N/A
N/A
14
FLASH_SPI_CS
O
Serial flash interface: SPI chip
select
15
GPIO22
I/O
General-purpose input or output
No
No
No
16
TDI
I/O
JTAG interface: data input
No
No
Muxed with
JTAG TDI
17
TDO
I/O
JTAG interface: data output
Yes
No
Muxed with
JTAG TDO
18
GPIO28
I/O
General-purpose input or output
No
No
No
19
TCK
I/O
JTAG/SWD interface: clock
No
No
Muxed with
JTAG/
SWD-TCK
20
TMS
I/O
JTAG/SWD interface: mode
select or SWDIO
No
No
Muxed with
JTAG/
SWD-TMSC
21(2)
SOP2
I
Configuration sense-on-power 2
No
No
No
N/A
N/A
N/A
22
WLAN_XTAL_N
Analog
40-MHz crystal. Pulldown if
external TCXO is used.
23
WLAN_XTAL_P
Analog
40-MHz crystal or TCXO clock
input
N/A
N/A
N/A
24
VDD_PLL
Power
Internal analog voltage
N/A
N/A
N/A
Power
Internal analog RF supply from
analog DC/DC output
N/A
N/A
N/A
25
LDO_IN2
26
NC
—
No connect
N/A
N/A
N/A
27
NC
—
Reserved
N/A
N/A
N/A
28
NC
—
Reserved
N/A
N/A
N/A
29(1)
ANTSEL1
O
Antenna selection control
No
User configuration
not required (3)
No
30(1)
ANTSEL2
O
Antenna selection control
No
User configuration
not required (3)
No
31
RF_BG
RF
RF BG band: 2.4-GHz TX, RX
N/A
N/A
N/A
I
Master chip reset input. Active
low input.
N/A
N/A
N/A
Power
Internal RF power amplifier (PA)
input from PA DC/DC output
N/A
N/A
N/A
32
nRESET
33
VDD_PA_IN
34
SOP1
I
Configuration sense-on-power 1
N/A
N/A
N/A
35
SOP0
I
Configuration sense-on-power 0
N/A
N/A
N/A
36
LDO_IN1
Power
Internal Analog RF supply from
analog DC/DC output
N/A
N/A
N/A
37
VIN_DCDC_ANA
Analog DC/DC supply input
(same as battery voltage [VBAT])
N/A
N/A
N/A
38
DCDC_ANA_SW
Power
Internal Analog DC/DC converter
switching node
N/A
N/A
N/A
39
VIN_DCDC_PA
Power
PA DC/DC converter input
supply (same as battery voltage
[VBAT])
N/A
N/A
N/A
40
DCDC_PA_SW_P
Power
Internal PA DC/DC converter
+ve switching node
N/A
N/A
N/A
41
DCDC_PA_SW_N
Power
Internal PA DC/DC converter
–ve switching node
N/A
N/A
N/A
12
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PINS
NO.
NAME
TYPE
DESCRIPTION
SELECT AS
WAKEUP
SOURCE
CONFIGURE
ADDITIONAL
ANALOG MUX
MUXED
WITH JTAG
42
DCDC_PA_OUT
Power
Internal PA buck DC/DC
converter output
N/A
N/A
N/A
43
DCDC_DIG_SW
Power
Internal Digital DC/DC converter
switching node
N/A
N/A
N/A
44
VIN_DCDC_DIG
Power
Digital DC/DC converter supply
input (same as battery voltage
[VBAT])
N/A
N/A
N/A
45(4)
DCDC_ANA2_SW_P
I/O
Analog2 DC/DC converter
+ve switching node
No
User configuration
not required (3)
No
46
DCDC_ANA2_SW_N
Power
Internal Analog2 DC/DC
converter –ve switching node
N/A
N/A
N/A
47
VDD_ANA2
Power
Internal Analog2 DC/DC output
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
No
48
VDD_ANA1
Power
Internal Analog1 power supply
fed by analog2 DC/DC converter
output
49
VDD_RAM
Power
Internal SRAM LDO output
I/O
General-purpose input or output
No
User configuration
not required (3)
RTC_XTAL_P
Analog
32.768-kHz XTAL_P or external
CMOS level clock input
N/A
N/A
N/A
52(5)
RTC_XTAL_N
Analog
32.768-kHz XTAL_N
N/A
User configuration
not required (3) (7)
No
53
GPIO30
I/O
General-purpose input or output
No
User configuration
not required (3)
No
54
VIN_IO2
Power
device supply voltage (VBAT)
N/A
N/A
N/A
55
GPIO1
General-purpose input or output
No
No
No
56
VDD_DIG2
internal digital core voltage
N/A
N/A
N/A
Yes
See (8)
No
50
GPIO0
51
I/O
Power
57(6)
GPIO2
I/O
Analog input (up to 1.5-V ) or
general-purpose input or output
58(6)
GPIO3
I/O
Analog input (up to 1.5-V ) or
general-purpose input or output
No
See (8)
No
59(6)
GPIO4
I/O
Analog input (up to 1.5-V ) or
general-purpose input or output
Yes
See (8)
No
60(6)
GPIO5
I/O
Analog input (up to 1.5 V) or
general-purpose input or output
No
See (8)
No
61
GPIO6
I/O
General-purpose input or output
No
No
No
62
GPIO7
I/O
General-purpose input or output
No
No
No
63
GPIO8
I/O
General-purpose input or output
No
No
No
64
GPIO9
I/O
General-purpose input or output
No
No
No
—
Thermal pad and electrical
ground
N/A
N/A
N/A
GND_TAB
(1)
(2)
(3)
(4)
(5)
This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device
between two antennas. These pins must not be used for other functionalities.
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
Device firmware automatically enables the digital path during ROM boot.
Pin 45 is used by an internal DC/DC converter (ANA2_DCDC). This pin will be available automatically if the serial flash is forced in the
CC3220SF device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level
configuration is required to use pin 52 as a digital pad. Pin 52 is used for the RTC crystal in most applications. However, in some
applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available,
the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the device to
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automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent
false detection, TI recommends using pin 52 for output-only functions.
This pin is shared by the ADC inputs and digital I/O pad cells.
To use the digital functions, RTC_XTAL_N must be pulled high to the supply voltage using a 100-kΩ resistor.
Requires user configuration to enable the analog switch of the ADC channel (the switch is off by default.) The digital I/O is always
connected and must be made Hi-Z before enabling the ADC switch.
(6)
(7)
(8)
Table 7-1. Pin Attributes
PIN
NO.
1
2
3
SIGNAL NAME(1)
SIGNAL
TYPE(2)
5
6
14
PAD STATES
SIGNAL
DIRECTION
LPDS(3)
Hib(4)
nRESET = 0
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
GPIO10 (PN)
0
I/O
Hi-Z, Pull, Drive
I2C_SCL
1
I/O (open drain)
Hi-Z, Pull, Drive
3
O
Hi-Z, Pull, Drive
7
O
1
SDCARD_CLK
6
O
0
GT_CCP01
12
I
Hi-Z, Pull, Drive
GT_PWM06
UART1_TX
I/O
GPIO11 (PN)
0
I/O
Hi-Z, Pull, Drive
I2C_SDA
1
I/O (open drain)
Hi-Z, Pull, Drive
GT_PWM07
3
O
Hi-Z, Pull, Drive
pXCLK (XVCLK)
4
O
0
6
I/O (open drain)
Hi-Z, Pull, Drive
UART1_RX
7
I
Hi-Z, Pull, Drive
GT_CCP02
12
I
Hi-Z, Pull, Drive
McAFSX
13
O
Hi-Z, Pull, Drive
GPIO12 (PN)
0
I/O
Hi-Z, Pull, Drive
McACLK
3
O
Hi-Z, Pull, Drive
pVS (VSYNC)
4
I
Hi-Z, Pull, Drive
5
I/O (open drain)
Hi-Z, Pull, Drive
UART0_TX
7
O
1
GT_CCP03
12
I
Hi-Z, Pull, Drive
GPIO13 (PN)
0
I/O
5
I/O (open drain)
4
I
UART0_RX
7
I
GT_CCP04
12
I
SDCARD_CMD
I2C_SCL
I/O
I/O
I2C_SDA
4
PIN MUX
ENCODING
pHS (HSYNC)
I/O
GPIO14 (PN)
0
I/O
I2C_SCL
5
I/O (open drain)
7
I/O
pDATA8 (CAM_D4)
4
I
GT_CCP05
12
I
GPIO15 (PN)
0
I/O
I2C_SDA
5
I/O (open drain)
GSPI_MISO
7
I/O
4
I
GT_CCP06
13
I
SDCARD_DATA0
8
I/O
GSPI_CLK
pDATA9 (CAM_D5)
I/O
I/O
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Table 7-1. Pin Attributes (continued)
PIN
NO.
7
8
PAD STATES
PIN MUX
ENCODING
SIGNAL
DIRECTION
LPDS(3)
GPIO16 (PN)
0
I/O
Hi-Z, Pull, Drive
GSPI_MOSI
7
I/O
Hi-Z, Pull, Drive
4
I
Hi-Z, Pull, Drive
5
O
1
SIGNAL NAME(1)
pDATA10 (CAM_D6)
UART1_TX
SIGNAL
TYPE(2)
I/O
Hib(4)
nRESET = 0
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
N/A
N/A
N/A
GT_CCP07
13
I
Hi-Z, Pull, Drive
SDCARD_CLK
8
O
0
GPIO17 (PN)
0
I/O
UART1_RX
5
I
7
I/O
4
I
GSPI_CS
I/O
pDATA11 (CAM_D7)
8
I/O
9
SDCARD_CMD
VDD_DIG1 (PN)
—
N/A
N/A
10
VIN_IO1
—
N/A
N/A
N/A
N/A
N/A
Hi-Z, Pull,
Drive
Hi-Z
11
FLASH_SPI_CLK
O
N/A
O
Hi-Z, Pull,
Drive(5)
12
FLASH_SPI_DOUT
O
N/A
O
Hi-Z, Pull,
Drive(5)
Hi-Z, Pull,
Drive
Hi-Z
13
FLASH_SPI_DIN
I
N/A
I
Hi-Z, Pull,
Drive(5)
Hi-Z
Hi-Z
14
FLASH_SPI_CS
O
N/A
O
1
Hi-Z, Pull,
Drive
Hi-Z
GPIO22 (PN)
I/O
0
I/O
McAFSX
O
7
O
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
GT_CCP04
I
5
I
1
I
0
I/O
2
O
1
Hi-Z, Pull,
Drive
Hi-Z
I2C_SCL
9
I/O (open drain)
Hi-Z, Pull, Drive
TDO (PN)
1
O
GPIO24
0
I/O
PWM0
5
O
Hi-Z, Pull, Drive
Driven high
in SWD;
driven low in
4-wire JTAG
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
15
TDI (PN)
16
17
18
19
20
GPIO23
UART1_TX
UART1_RX
I/O
I/O
2
I
I2C_SDA
9
I/O (open drain)
GT_CCP06
4
I
McAFSX
6
O
0
I/O
1
I
8
O
GPIO28
TCK (PN)
GT_PWM03
TMS (PN)
GPIO29
I/O
I/O
I/O
1
0
I/O
Hi-Z, Pull, Drive
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Table 7-1. Pin Attributes (continued)
PIN
NO.
21(6)
PAD STATES
PIN MUX
ENCODING
SIGNAL
DIRECTION
LPDS(3)
GPIO25
0
O
Hi-Z, Pull, Drive
GT_PWM02
9
O
Hi-Z, Pull, Drive
SIGNAL NAME(1)
SIGNAL
TYPE(2)
McAFSX
2
O
Hi-Z, Pull, Drive
TCXO_EN
N/A
(see (8))
O
0
SOP2 (PN)
N/A
(see (9))
I
Hi-Z, Pull, Drive
O
Hib(4)
nRESET = 0
Driven low
Hi-Z
22
WLAN_XTAL_N
—
N/A
(see (8))
N/A
N/A
N/A
N/A
23
WLAN_XTAL_P
—
N/A
N/A
N/A
N/A
N/A
24
VDD_PLL
—
N/A
N/A
N/A
N/A
N/A
25
LDO_IN2
—
N/A
N/A
N/A
N/A
N/A
26
NC
—
N/A
N/A
N/A
N/A
N/A
27
NC
—
N/A
N/A
N/A
N/A
N/A
28
NC
—
N/A
N/A
N/A
N/A
N/A
29(10)
ANTSEL1
O
0
O
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
30(10)
ANTSEL2
O
0
O
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
31
RF_BG
—
N/A
N/A
N/A
N/A
N/A
32
nRESET
—
N/A
N/A
N/A
N/A
N/A
33
VDD_PA_IN
—
N/A
N/A
N/A
N/A
N/A
34
SOP1
—
N/A
N/A
N/A
N/A
N/A
35
SOP0
—
N/A
N/A
N/A
N/A
N/A
36
LDO_IN1
—
N/A
N/A
N/A
N/A
N/A
37
VIN_DCDC_ANA
—
N/A
N/A
N/A
N/A
N/A
38
DCDC_ANA_SW
—
N/A
N/A
N/A
N/A
N/A
39
VIN_DCDC_PA
—
N/A
N/A
N/A
N/A
N/A
40
DCDC_PA_SW_P
—
N/A
N/A
N/A
N/A
N/A
41
DCDC_PA_SW_N
—
N/A
N/A
N/A
N/A
N/A
42
DCDC_PA_OUT
—
N/A
N/A
N/A
N/A
N/A
43
DCDC_DIG_SW
—
N/A
N/A
N/A
N/A
N/A
44
VIN_DCDC_DIG
—
N/A
N/A
N/A
N/A
N/A
0
I/O
Hi-Z
Hi-Z
Hi-Z
GPIO31
45(7)
UART0_RX
9
I
McAFSX
12
O
2
I
6
I/O
UART1_RX
I/O
McAXR0
GSPI_CLK
16
7
I/O
—
N/A
(see (8))
N/A
N/A
N/A
N/A
DCDC_ANA2_SW_N
—
N/A
N/A
N/A
N/A
N/A
47
VDD_ANA2
—
N/A
N/A
N/A
N/A
N/A
48
VDD_ANA1
—
N/A
N/A
N/A
N/A
N/A
49
VDD_RAM
—
N/A
N/A
N/A
N/A
N/A
DCDC_ANA2_SW_P
(PN)
46
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Table 7-1. Pin Attributes (continued)
PIN
NO.
50
51
SIGNAL
DIRECTION
LPDS(3)
GPIO0 (PN)
0
I/O
Hi-Z, Pull, Drive
UART0_CTS
12
I
Hi-Z, Pull, Drive
McAXR1
6
I/O
Hi-Z, Pull, Drive
GT_CCP00
7
I
Hi-Z, Pull, Drive
9
I/O
Hi-Z, Pull, Drive
UART1_RTS
10
O
1
UART0_RTS
3
O
1
McAXR0
4
I/O
Hi-Z, Pull, Drive
N/A
N/A
N/A
N/A
N/A
N/A
GPIO32
0
O
McACLK
2
O
4
O
UART0_RTS
6
O
1
GSPI_MOSI
8
O
Hi-Z, Pull, Drive
GPIO30 (PN)
0
I/O
Hi-Z, Pull, Drive
UART0_TX
9
O
1
McACLK
2
O
3
O
4
I
GSPI_CS
RTC_XTAL_P
I/O
—
RTC_XTAL_N (PN)
52(11)
53
McAXR0
McAFSX
O
I/O
GT_CCP05
GSPI_MISO
54
55
I/O
N/A
N/A
GPIO1 (PN)
0
I/O
Hi-Z, Pull, Drive
UART0_TX
3
O
1
4
I
Hi-Z, Pull, Drive
6
O
1
pCLK (PIXCLK)
I/O
Hi-Z, Pull,
Drive
Hi-Z
N/A
N/A
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull,
Drive
Hi-Z
N/A
N/A
Hi-Z, Pull,
Drive
Hi-Z
7
I
Hi-Z, Pull, Drive
N/A
N/A
N/A
N/A
N/A
(see (8))
I
0
I/O
3
I
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
6
I
GT_CCP02
7
I
ADC_CH1
N/A
(see (8))
I
0
I/O
Hi-Z
6
O
1
Hi-Z, Pull,
Drive
4
I
Hi-Z, Pull, Drive
N/A
(see (8))
I
0
I/O
Hi-Z
6
I
Hi-Z, Pull,
Drive
4
I
—
GPIO2 (PN)
UART0_RX
Analog input
(up to 1.5 V)
or digital I/O
UART1_RX
GPIO3 (PN)
UART1_TX
Analog input
(up to 1.5 V)
or digital I/O
pDATA7 (CAM_D3)
ADC_CH2
59(12)
nRESET = 0
N/A
VDD_DIG2
ADC_CH0
58(12)
Hib(4)
Hi-Z, Pull, Drive
7
—
GT_CCP01
57(12)
Hi-Z, Pull, Drive
N/A
VIN_IO2
UART1_TX
56
PAD STATES
PIN MUX
ENCODING
SIGNAL NAME(1)
SIGNAL
TYPE(2)
GPIO4 (PN)
UART1_RX
Analog input
(up to 1.5 V)
or digital I/O
pDATA6 (CAM_D2)
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
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SWAS035C – SEPTEMBER 2016 – REVISED MAY 2021
Table 7-1. Pin Attributes (continued)
PIN
NO.
SIGNAL
DIRECTION
N/A
(see (8))
I
0
I/O
4
I
McAXR1
6
I/O
GT_CCP05
7
I
GPIO6 (PN)
0
I/O
Hi-Z, Pull, Drive
UART0_RTS
5
O
1
4
I
3
I
UART0_CTS
6
I
GT_CCP06
7
I
GPIO7 (PN)
0
I/O
McACLKX
13
O
3
O
UART0_RTS
10
O
UART0_TX
11
O
GPIO8 (PN)
0
I/O
ADC_CH3
60(12)
61
62
63
64
PAD STATES
PIN MUX
ENCODING
SIGNAL NAME(1)
SIGNAL
TYPE(2)
GPIO5 (PN)
pDATA5 (CAM_D1)
pDATA4 (CAM_D0)
UART1_CTS
UART1_RTS
SDCARD_IRQ
McAFSX
Analog input
(up to 1.5 V)
or digital I/O
I/O
I/O
I/O
6
I
7
O
GT_CCP06
12
I
GPIO9 (PN)
0
I/O
GT_PWM05
3
O
6
I/O
7
I/O
SDCARD_DATA0
I/O
McAXR0
GT_CCP00
GND_TAB
—
12
I
N/A
N/A
LPDS(3)
Hib(4)
nRESET = 0
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
Hi-Z
N/A
N/A
N/A
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
1
(1)
(2)
(3)
Signals names with (PN) denote the default pin name.
Signal Types: I = Input, O = Output, I/O = Input or Output.
LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin
configuration), according to the need.
(4) Hibernate mode: The I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin
configuration), according to the need.
(5) To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak
pulldown resistors on the FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.
(6) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(7) Pin 45 is used by an internal DC/DC (ANA2_DCDC). This pin will be available automatically if serial flash is forced in the CC3220SF
device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
(8) For details on proper use, see Section 7.5.
(9) This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the device hardware power-up mode.
For this reason, the pin must be output only when used for digital functions.
(10) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device
between two antennas. These pins must not be used for other functionalities.
(11) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level
configuration is required to use pin 52 as a digital pad. Pin 52 is used for RTC crystal in most applications. However, in some
applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available,
the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to
automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent
false detection, TI recommends using pin 52 for output-only functions.
(12) This pin is shared by the ADC inputs and digital I/O pad cells.
18
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Note
The ADC inputs are tolerant up to 1.8 V (see Section 8.14.6.6.1 for more details about the usable
range of the ADC). On the other hand, the digital pads can tolerate up to 3.6 V. Hence, take care to
prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the
digital I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter
disabling the respective pass switches (S7 [Pin 57], S8 [Pin 58], S9 [Pin 59], and S10 [Pin 60]). For
more information about drive strength and reset states for analog-digital multiplexed pins, see Section
7.5.
7.3 Signal Descriptions
7.3.1 Signal Descriptions
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
ADC_CH0
57
I/O
I
ADC channel 0 input (maximum of 1.5 V)
ADC_CH1
58
I/O
I
ADC channel 1 input (maximum of 1.5 V)
ADC_CH2
59
I/O
I
ADC channel 2 input (maximum of 1.5 V)
ADC_CH3
60
I/O
I
ADC channel 3 input (maximum of 1.5 V)
ANTSEL1
29
O
O
Antenna selection control 1
ANTSEL2
30
O
O
Antenna selection control 2
TCX0_EN
21
O
O
Enable to optional external 40-MHz TCXO
WLAN_XTAL_N
22
—
—
40-MHz crystal; pull down if external TCXO is used
WLAN_XTAL_P
23
—
—
40-MHz crystal or TCXO clock input
RTC_XTAL_P
51
—
—
Connect 32.768-kHz crystal or force external CMOS
level clock
RTC_XTAL_N
52
—
—
Connect 32.768-kHz crystal or connect 100-kΩ resistor
to supply voltage
TDI
16
I/O
I
JTAG TDI. Reset default pinout.
TDO
17
I/O
O
JTAG TDO. Reset default pinout.
TCK
19
I/O
I
JTAG/SWD TCK. Reset default pinout.
TMS
20
I/O
I/O
JTAG/SWD TMS. Reset default pinout.
I/O
I/O (open drain)
I2C clock data
I/O
I/O (open drain)
I2C data
FUNCTION
ADC
Antenna
selection
SIGNAL NAME
Clock
JTAG / SWD
DESCRIPTION
1
I2C_SCL
3
5
16
I2C
2
I2C_SDA
4
6
17
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FUNCTION
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
GT_PWM06
1
I/O
O
Pulse-width modulated O/P
GT_CCP01
1
I/O
I
Timer capture port
GT_PWM07
2
I/O
O
Pulse-width modulated O/P
GT_CCP02
2
I/O
I
GT_CCP03
3
I/O
I
4
I/O
I
15
I/O
I
5
I/O
I
6
I/O
I
17
I/O
I
61
I/O
I
63
I/O
I
GT_CCP07
7
I/O
I
PWM0
17
I/O
O
GT_PWM03
19
I/O
O
GT_PWM02
21
O
O
SIGNAL NAME
GT_CCP04
GT_CCP05
GT_CCP06
Timers
50
I/O
I
64
I/O
I
GT_CCP05
53
I/O
I
GT_CCP01
55
I/O
I
GT_CCP02
57
I/O
I
GT_CCP05
60
I
I
GT_PWM05
64
I/O
O
GT_CCP00
20
DESCRIPTION
Timer capture port
Pulse-width modulated output
Timer capture port
Pulse-width modulated output
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FUNCTION
GPIO
SWAS035C – SEPTEMBER 2016 – REVISED MAY 2021
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
GPIO10
1
I/O
I/O
GPIO11
2
I/O
I/O
GPIO12
3
I/O
I/O
GPIO13
4
I/O
I/O
GPIO14
5
I/O
I/O
GPIO15
6
I/O
I/O
GPIO16
7
I/O
I/O
GPIO17
8
I/O
I/O
GPIO22
15
I/O
I/O
GPIO23
16
I/O
I/O
GPIO24
17
I/O
I/O
GPIO28
18
I/O
I/O
GPIO29
20
I/O
I/O
GPIO25
21
O
O
GPIO31
45
I/O
I/O
GPIO0
50
I/O
I/O
SIGNAL NAME
GPIO32
52
I/O
O
GPIO30
53
I/O
I/O
GPIO1
55
I/O
I/O
GPIO2
57
I/O
I/O
GPIO3
58
I/O
I/O
GPIO4
59
I/O
I/O
GPIO5
60
I/O
I/O
GPIO6
61
I/O
I/O
GPIO7
62
I/O
I/O
GPIO8
63
I/O
I/O
GPIO9
64
I/O
I/O
I/O
O
3
I/O
O
52
O
O
53
I/O
O
DESCRIPTION
General-purpose input or output
General-purpose output only
General-purpose input or output
General-purpose output only
General-purpose input or output
2
15
17
McAFSX
21
I2S audio port frame sync
45
53
63
McASP
I2S or PCM
McACLK
McAXR1
McAXR0
McACLKX
50
I/O
I/O
60
I
I/O
I2S audio port clock output
I2S audio port data 1 (RX and TX)
45
I/O
I/O
50
I/O
I/O
52
O
O
I2S audio port data (only output mode is supported on
pin 52)
64
I/O
I/O
I2S audio port data (RX and TX)
62
I/O
O
I2S audio port clock
I2S audio port data 0 (RX and TX)
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SWAS035C – SEPTEMBER 2016 – REVISED MAY 2021
FUNCTION
SIGNAL NAME
SDCARD_CLK
Multimedia card
(MMC or SD)
SDCARD_CMD
SDCARD_DATA0
22
PIN
TYPE
SIGNAL
DIRECTION
I/O
O
2
I/O
I/O (open drain)
8
I/O
I/O
I/O
I/O
1
7
6
64
DESCRIPTION
SD card clock data
SD card command line
SD card data
SDCARD_IRQ
63
I/O
I
Interrupt from SD card (future support)
pXCLK (XVCLK)
2
I/O
O
Free clock to parallel camera
pVS (VSYNC)
3
I/O
I
Parallel camera vertical sync
pHS (HSYNC)
4
I/O
I
Parallel camera horizontal sync
pDATA8 (CAM_D4)
5
I/O
I
Parallel camera data bit 4
pDATA9 (CAM_D5)
6
I/O
I
Parallel camera data bit 5
7
I/O
I
Parallel camera data bit 6
8
I/O
I
Parallel camera data bit 7
pCLK (PIXCLK)
55
I/O
I
Pixel clock from parallel camera sensor
pDATA7 (CAM_D3)
58
I/O
I
Parallel camera data bit 3
pDATA6 (CAM_D2)
59
I/O
I
Parallel camera data bit 2
pDATA5 (CAM_D1)
60
I
I
Parallel camera data bit 1
pDATA4 (CAM_D0)
61
I/O
I
Parallel camera data bit 0
VDD_DIG1
9
—
—
Internal digital core voltage
VIN_IO1
10
—
—
Device supply voltage (VBAT)
VDD_PLL
24
—
—
Internal analog voltage
LDO_IN2
25
—
—
Internal analog RF supply from analog DC/DC output
VDD_PA_IN
33
—
—
Internal PA supply voltage from PA DC/DC output
LDO_IN1
36
—
—
Internal analog RF supply from analog DC/DC output
VIN_DCDC_ANA
37
—
—
Analog DC/DC input (connected to device input supply
[VBAT])
DCDC_ANA_SW
38
—
—
Internal analog DC/DC switching node
VIN_DCDC_PA
39
—
—
PA DC/DC input (connected to device input supply
[VBAT])
DCDC_PA_SW_P
40
—
—
DCDC_PA_SW_N
41
—
—
DCDC_PA_OUT
42
—
—
Internal PA buck converter output
DCDC_DIG_SW
43
—
—
Internal digital DC/DC switching node
VIN_DCDC_DIG
44
—
—
Digital DC/DC input (connected to device input supply
[VBAT])
DCDC_ANA2_SW_P
45
—
—
Analog to DC/DC converter +ve switching node
DCDC_ANA2_SW_N
46
—
—
Internal analog to DC/DC converter –ve switching node
VDD_ANA2
47
—
—
Internal analog to DC/DC output
VDD_ANA1
48
—
—
Internal analog supply fed by ANA2 DC/DC output
VDD_RAM
49
—
—
Internal SRAM LDO output
VIN_IO2
54
—
—
Device supply voltage (VBAT)
VDD_DIG2
56
—
—
Internal digital core voltage
Parallel interface pDATA10 (CAM_D6)
(8-bit π)
pDATA11 (CAM_D7)
Power
PIN
NO.
Internal PA DC/DC switching node
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FUNCTION
SWAS035C – SEPTEMBER 2016 – REVISED MAY 2021
SIGNAL NAME
GSPI_CLK
GSPI_MISO
SPI
GSPI_CS
GSPI_MOSI
FLASH SPI
PIN
TYPE
SIGNAL
DIRECTION
5
I/O
I/O
45
I/O
I/O
6
I/O
I/O
53
I/O
I/O
8
I/O
I/O
50
I/O
I/O
7
I/O
I/O
52
O
O
DESCRIPTION
General SPI clock
General SPI MISO
General SPI chip select
General SPI MOSI
FLASH_SPI_CLK
11
O
O
Clock to SPI serial flash (fixed default)
FLASH_SPI_DOUT
12
O
O
Data to SPI serial flash (fixed default)
FLASH_SPI_DIN
13
I
I
Data from SPI serial flash (fixed default)
FLASH_SPI_CS
14
O
O
Device select to SPI serial flash (fixed default)
1
I/O
O
7
I/O
O
16
I/O
O
55
I/O
O
58
I/O
O
2
I/O
I
8
I/O
I
17
I/O
I
45
I/O
I
57
I/O
I
59
I/O
I
UART1_TX
UART1_RX
UART1_RTS
UART
PIN
NO.
UART1_CTS
UART0_TX
UART0_RX
UART0_CTS
UART0_RTS
50
I/O
O
62
I/O
O
61
I/O
I
3
I/O
O
53
I/O
O
55
I/O
O
62
I/O
O
4
I/O
I
45
I/O
I
57
I/O
I
50
I/O
I
61
I/O
I
50
I/O
O
52
O
O
61
I/O
O
62
I/O
O
UART1 TX data
UART1 RX data
UART1 request-to-send (active low)
UART1 clear-to-send (active low)
UART0 TX data
UART0 RX data
UART0 clear-to-send input (active low)
UART0 request-to-send (active low)
21(1)
O
I
Sense-on-Power SOP1
34
—
—
Configuration sense-on-power 1
SOP0
35
—
—
Configuration sense-on-power 0
nRESET
32
—
—
Global master device reset (active low)
SOP2
Reset
Sense-on-power 2
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SWAS035C – SEPTEMBER 2016 – REVISED MAY 2021
FUNCTION
RF
(1)
SIGNAL NAME
RF_BG
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
31
—
—
DESCRIPTION
WLAN analog RF 802.11 b/g bands
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
7.4 Pin Multiplexing
Table 7-2. Pin Multiplexing
REGIST
ER
ADDRE
SS
REGISTER NAME
PIN
ANALO
G OR
SPECIA
L
FUNCTI
ON
JTAG
DIGITAL FUNCTION (XXX FIELD ENCODING)(1)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
—
—
—
—
GT_CC
P01
—
0x4402
E0C8
GPIO_PAD_CONFI
G_10
1
—
GPIO10
I2C_S
CL
—
GT_PW
M06
—
—
SDCA
UART1_
RD_C
TX
LK
0x4402
E0CC
GPIO_PAD_CONFI
G_11
2
—
GPIO11
I2C_S
DA
—
GT_PW
M07
pXCL
K
(XVCL
K)
—
SDCA
UART1_
RD_C
RX
MD
—
—
—
—
GT_CC
P02
MCAFS
X
0x4402
E0D0
GPIO_PAD_CONFI
G_12
3
—
GPIO12
—
—
pVS
I2C_SC
McACLK (VSYN
L
C)
—
UART0_
TX
—
—
—
—
GT_CC
P03
—
0x4402
E0D4
GPIO_PAD_CONFI
G_13
4
—
GPIO13
—
—
—
pHS
I2C_SD
(HSYN
A
C)
—
UART0_
RX
—
—
—
—
GT_CC
P04
—
0x4402
E0D8
GPIO_PAD_CONFI
G_14
5
—
GPIO14
—
—
—
pDATA
8
I2C_SC
(CAM_
L
D4)
—
GSPI_C
LK
—
—
—
—
GT_CC
P05
—
0x4402
E0DC
GPIO_PAD_CONFI
G_15
6
—
GPIO15
—
—
—
pDATA
9
I2C_SD
(CAM_
A
D5)
—
GSPI_
MISO
SDCA
RD_D
ATA0
—
—
—
—
GT_CC
P06
0x4402
E0E0
GPIO_PAD_CONFI
G_16
7
—
GPIO16
—
—
—
pDATA
10
UART1
(CAM_
_TX
D6)
—
GSPI_
MOSI
SDCA
RD_C
LK
—
—
—
—
GT_CC
P07
0x4402
E0E4
GPIO_PAD_CONFI
G_17
8
—
GPIO17
—
—
—
pDATA
11
UART1
(CAM_
_RX
D7)
—
GSPI_C
S
SDCA
RD_C
MD
—
—
—
—
—
0x4402
E0F8
GPIO_PAD_CONFI
G_22
15
—
GPIO22
—
—
—
—
GT_CC
P04
—
McAFS
X
—
—
—
—
—
—
0x4402
E0FC
GPIO_PAD_CONFI
G_23
16
Muxed
with
JTAG
GPIO23
TDI
UART1
_TX
—
—
—
—
—
—
I2C_S
CL
—
—
—
—
0x4402
E100
GPIO_PAD_CONFI
G_24
17
Muxed
with
JTAG
TDO
GPIO24
TDO
UART1
_RX
—
GT_C
CP06
PWM0
McAF
SX
—
—
I2C_S
DA
—
—
—
—
0x4402
E140
GPIO_PAD_CONFI
G_40
18
—
GPIO28
—
—
—
—
—
—
—
—
—
—
—
—
—
19
Muxed
with
JTAG or
SWD
and TCK
—
TCK
—
—
—
—
—
—
GT_
PWM0
3
—
—
—
—
—
GPIO29
TMS
—
—
—
—
—
—
—
—
—
—
—
—
GPIO25
—
McAFS
X
—
—
—
—
—
—
GT_
PWM0
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x4402
E110
GPIO_PAD_CONFI
G_28
0x4402
E114
GPIO_PAD_CONFI
G_29
20
Muxed
with
JTAG or
SWD
and
TMSC
0x4402
E104
GPIO_PAD_CONFI
G_25
21(2)
—
0x4402
E108
GPIO_PAD_CONFI
G_26
29
—
0x4402
E10C
GPIO_PAD_CONFI
G_27
30
—
24
ANTSEL1
(3)
ANTSEL2
(3)
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Table 7-2. Pin Multiplexing (continued)
ANALO
G OR
SPECIA
L
FUNCTI
ON
REGIST
ER
ADDRE
SS
REGISTER NAME
0x4402
E11C
GPIO_PAD_CONFI
G_31
45
—
0x4402
E0A0
GPIO_PAD_CONFI
G_0
50
0x4402
E120
GPIO_PAD_CONFI
G_32
0x4402
E118
PIN
DIGITAL FUNCTION (XXX FIELD ENCODING)(1)
JTAG
1
2
GPIO31
—
UART1
_RX
5
6
7
8
9
—
—
McAX
R0
GSPI_C
LK
—
UART0
_RX
—
—
GPIO0
—
—
UART0_
RTS
McAX
R0
—
McAX
R1
GT_CC
P00
—
52
—
GPIO32
—
McACL
K
—
McAX
R0
—
UART
0_
RTS
—
GPIO_PAD_CONFI
G_30
53
-—
GPIO30
—
McACL
McAFSX
K
GT_C
CP05
—
—
0x4402
E0A4
GPIO_PAD_CONFI
G_1
55
—
GPIO1
—
—
UART0_
TX
pCLK
(PIXC
LK)
—
0x4402
E0A8
GPIO_PAD_CONFI
G_2
57
—
GPIO2
—
—
UART0_
RX
—
0x4402
E0AC
GPIO_PAD_CONFI
G_3
58
—
GPIO3
—
—
—
0x4402
E0B0
GPIO_PAD_CONFI
G_4
59
—
GPIO4
—
—
0x4402
E0B4
GPIO_PAD_CONFI
G_5
60
—
GPIO5
—
—
0x4402
E0B8
GPIO_PAD_CONFI
G_6
61
—
GPIO6
—
—
pDATA
UART0
UART1_
4
_
CTS
(CAM_
RTS
D0)
0x4402
E0BC
GPIO_PAD_CONFI
G_7
62
—
GPIO7
—
—
UART1_
RTS
—
0x4402
E0C0
GPIO_PAD_CONFI
G_8
63
—
GPIO8
—
—
—
0x4402
E0C4
GPIO_PAD_CONFI
G_9
64
-—
GPIO9
—
—
GT_PW
M05
(1)
(2)
0
3
4
10
11
12
13
—
—
McAFS
X
—
GSPI_
CS
UART1
_
RTS
—
UART0
_
CTS
—
GSPI_
MOSI
—
—
—
—
—
GSPI_
MISO
—
UART0
_TX
—
—
—
—
UART
1_TX
GT_CC
P01
—
—
—
—
—
—
—
UART
1_RX
GT_CC
P02
—
—
—
—
—
—
pDATA
7
(CAM_
D3)
—
UART
1_TX
—
—
—
—
—
—
—
—
pDATA
6
(CAM_
D2)
—
UART
1_RX
—
—
—
—
—
—
—
—
pDATA
5
(CAM_
D1)
—
McAX
R1
GT_CC
P05
—
—
—
—
—
—
UART
0_
CTS
GT_CC
P06
—
—
—
—
—
—
—
—
—
—
—
UART0
_
RTS
UART
0_TX
—
McACL
KX
—
—
SDCA
RD_
IRQ
McAFS
X
—
—
—
—
GT_CC
P06
—
—
—
SDCA
McAXR
RD_
0
DATA0
—
—
—
—
GT_CC
P00
—
Pin mux encodings with (RD) denote the default encoding after reset release.
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
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7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
Table 7-3 describes the use, drive strength, and default state of analog and digital multiplexed pins at first-time
power up and reset (nRESET pulled low).
Table 7-3. Drive Strength and Reset States for Analog and Digital Multiplexed Pins
Pin
BOARD-LEVEL CONFIGURATION AND
USE
DEFAULT STATE AT FIRST
POWER UP OR FORCED
RESET
STATE AFTER
CONFIGURATION OF
ANALOG SWITCHES
(ACTIVE, LPDS, AND HIB
POWER MODES)
MAXIMUM
EFFECTIVE
DRIVE
STRENGTH
(mA)
29
Connected to the enable pin of the
RF switch (ANTSEL1). Other use is not
recommended.
Analog is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as
are other digital I/Os.
4
30
Connected to the enable pin of the
RF switch (ANTSEL2). Other use is not
recommended.
Analog is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as
are other digital I/Os.
4
45
VDD_ANA2 (pin 47) must be shorted to the
Analog is isolated. The digital I/O
input supply rail. Otherwise, the pin is driven
cell is also isolated.
by the ANA2 DC/DC.
Determined by the I/O state, as
are other digital I/Os.
4
50
Generic I/O
Analog is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as
are other digital I/Os.
4
52
The pin must have an external pullup of 100
Analog is isolated. The digital I/O
kΩ to the supply rail and must be used in
cell is also isolated.
output signals only.
Determined by the I/O state, as
are other digital I/Os.
4
53
Generic I/O
Analog is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as
are other digital I/Os.
4
57
Analog signal (1.8-V absolute, 1.46-V full
scale)
ADC is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as
are other digital I/Os.
4
58
Analog signal (1.8-V absolute, 1.46-V full
scale)
ADC is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as
are other digital I/Os.
4
59
Analog signal (1.8-V absolute, 1.46-V full
scale)
ADC is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as
are other digital I/Os.
4
60
Analog signal (1.8-V absolute, 1.46-V full
scale)
ADC is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as
are other digital I/Os.
4
7.6 Pad State After Application of Power to Chip But Before Reset Release
When a stable power is applied to the CC3220x chip for the first time or when supply voltage is restored to the
proper value following a period with supply voltage less than 1.5 V, the level of each digital pad is undefined
in the period starting from the release of nRESET and until DIG_DCDC powers up. This period is less than
approximately 10 ms. During this period, pads can be internally pulled weakly in either direction. If a certain set
of pins is required to have a definite value during this prereset period, an appropriate pullup or pulldown resistor
must be used at the board level. The recommended value of this external pull is 2.7 kΩ.
26
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7.7 Connections for Unused Pins
All unused pins must be left as no connect (NC) pins. Table 7-4 provides a list of NC pins.
Table 7-4. Connections for Unused Pins
PIN
DEFAULT FUNCTION
STATE AT RESET
AND HIBERNATE
I/O TYPE
26
NC
WLAN analog
—
Unused; leave unconnected.
27
NC
WLAN analog
—
Unused; leave unconnected.
28
NC
WLAN analog
—
Unused; leave unconnected.
DESCRIPTION
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8 Specifications
All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over
process and voltage, unless otherwise indicated.
8.1 Absolute Maximum Ratings
All measurements are referenced at the device pins unless otherwise indicated. All specifications are over process, voltage,
and operating free-air temperature range (unless otherwise noted) (1) (2)
VBAT and VIO
Pins: 37, 39, 44
VIO – VBAT (differential)
Pins: 10, 54
Digital inputs
RF pins
Analog pins, crystal
Pins: 22, 23, 51, 52
MIN
MAX
–0.5
3.8
UNIT
V
VBAT and VIO should be
tied together
V
–0.5
VIO + 0.5
V
–0.5
2.1
V
–0.5
2.1
V
Operating temperature, TA
–40
85
°C
Storage temperature, Tstg
–55
125
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
8.2 ESD Ratings
VALUE
VESD
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Power-On Hours (POH)
This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's
standard terms and conditions for TI semiconductor products.
OPERATING CONDITION
TA up to 85°C(1)
(1)
28
POWER-ON HOURS [POH]
(hours)
87,600
The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the remaining 90% of the time, the device
can be in any other state.
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8.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) (2)
VBAT, VIO
(shorted to VBAT)
Pins: 10, 37, 39,
44, 54
Direct battery
connection(3)
(3)
(4)
(5)
(6)
TYP
MAX
2.1(6)
3.3
3.6
Preregulated 1.85 V(4) (5)
Ambient thermal slew
(1)
(2)
MIN
–20
20
UNIT
V
°C/minute
Operating temperature is limited by crystal frequency variation.
When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect
feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the
transmission.
To ensure WLAN performance, ripple on the supply must be less than ±300 mV.
To ensure WLAN performance, ripple on the 1.85-V supply must be less than 2% (±40 mV).
TI recommends keeping VBAT above 1.85 V. For lower voltages, use a boost converter.
The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also 2.1
V, and care must be taken when operating at the minimum specified voltage.
8.5 Current Consumption Summary (CC3220R, CC3220S)
TA = 25°C, VBAT = 3.6 V
TEST CONDITIONS(1) (5)
PARAMETER
1 DSSS
TX
MCU ACTIVE
6 OFDM
NWP ACTIVE
54 OFDM
RX
NWP idle
272
TX power level = 4
190
TX power level = 0
248
TX power level = 4
182
TX power level = 0
223
TX power level = 4
160
1 DSSS
59
54 OFDM
59
6 OFDM
NWP ACTIVE
54 OFDM
RX
TX power level = 0
269
TX power level = 4
187
TX power level = 0
245
TX power level = 4
179
TX power level = 0
220
TX power level = 4
157
1 DSSS
54 OFDM
6 OFDM
NWP ACTIVE
54 OFDM
RX
56
TX power level = 0
266
TX power level = 4
184
TX power level = 0
242
TX power level = 4
176
TX power level = 0
217
TX power level = 4
154
1 DSSS
53
54 OFDM
53
120 µA at 64KB
135 µA at 256KB
NWP LPDS(2)
mA
12.2
1 DSSS
MCU LPDS
mA
56
NWP idle connected(3)
TX
MAX UNIT
15.3
1 DSSS
MCU SLEEP
TYP
TX power level = 0
connected(3)
TX
MIN
NWP idle connected(3)
mA
135
µA
710
µA
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TA = 25°C, VBAT = 3.6 V
TEST CONDITIONS(1) (5)
PARAMETER
MCU SHUTDOWN
MCU shutdown
MCU HIBERNATE
MCU hibernate
Peak calibration current(4)
(1)
(2)
(3)
(4)
(5)
30
MIN
TYP
MAX UNIT
1
µA
4.5
µA
VBAT = 3.6 V
420
VBAT = 3.3 V
450
VBAT = 2.1 V
670
VBAT = 1.85 V
700
mA
TX power level = 0 implies maximum power (see Figure 8-1, Figure 8-2, and Figure 8-3). TX power level = 4 implies output power
backed off approximately 4 dB.
LPDS current does not include the external serial Flash. The LPDS number of reported is with retention of 256KB of MCU SRAM.
The CC3220x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU
retained SRAM increases LPDS current by 4 µA.
DTIM = 1
The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is
performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C.
There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further
details, see CC3120, CC3220 SimpleLink™ Wi-Fi® and IoT Network Processor Programmer's Guide.
The CC3220x system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
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8.6 Current Consumption Summary (CC3220SF)
TA = 25°C, VBAT = 3.6 V
TEST CONDITIONS(1) (5)
PARAMETER
1 DSSS
TX
MCU ACTIVE
6 OFDM
NWP ACTIVE
54 OFDM
RX
NWP idle
TX power level = maximum
286
TX power level = maximum – 4
202
TX power level = maximum
255
TX power level = maximum – 4
192
TX power level = maximum
232
TX power level = maximum – 4
174
74
54 OFDM
74
connected(3)
6 OFDM
NWP ACTIVE
54 OFDM
RX
TX power level = maximum
282
TX power level = maximum – 4
198
TX power level = maximum
251
TX power level = maximum – 4
188
TX power level = maximum
228
TX power level = maximum – 4
170
1 DSSS
70
54 OFDM
70
connected(3)
6 OFDM
TX
NWP active
54 OFDM
MCU LPDS
RX
TX power level = 0
266
TX power level = 4
184
TX power level = 0
242
TX power level = 4
176
TX power level = 0
217
TX power level = 4
154
1 DSSS
53
54 OFDM
53
120 µA at 64KB
135 µA at 256KB
NWP LPDS(2)
NWP idle connected(3)
1
MCU
HIBERNATE
MCU hibernate
4.5
(3)
(4)
mA
710
MCU shutdown
(2)
mA
135
MCU
SHUTDOWN
(1)
mA
21.2
1 DSSS
Peak calibration current(4)
MAX UNIT
25.2
TX
NWP idle
TYP
1 DSSS
1 DSSS
MCU SLEEP
MIN
VBAT = 3.6 V
420
VBAT = 3.3 V
450
VBAT = 2.1 V
670
VBAT = 1.85 V
700
µA
mA
TX power level = 0 implies maximum power (see Figure 8-1, Figure 8-2, and Figure 8-3). TX power level = 4 implies output power
backed off approximately 4 dB.
LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The
CC3220x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU
retained SRAM increases LPDS current by 4 µA.
DTIM = 1
The complete calibration can take up to 17 mJ of energy from the battery over a period of 24 ms. Calibration is performed sparingly,
typically when coming out of HIBERNATE and only if temperature has changed by more than 20°C. The calibration event can be
controlled by a configuration file in the serial Flash..
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8.7 TX Power and IBAT versus TX Power Level Settings
Figure 8-1, Figure 8-2, and Figure 8-3 show TX Power and IBAT versus TX power level settings for the
CC3220R and CC3220S devices at modulations of 1 DSSS, 6 OFDM, and 54 OFDM, respectively. For the
CC3220SF device, the IBAT current has an increase of approximately 10 mA to 15 mA depending on the
transmitted rate. The TX power level will remain the same.
In Figure 8-1, the area enclosed in the circle represents a significant reduction in current during transition from
TX power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI recommends
using TX power level 4 to reduce the current.
1 DSSS
19.00
280.00
Color by
17.00
264.40
TX Power (dBm)
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
TX Power (dBm)
15.00
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 8-1. TX Power and IBAT vs TX Power Level Settings (1 DSSS)
6 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 8-2. TX Power and IBAT vs TX Power Level Settings (6 OFDM)
32
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54 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
15
Figure 8-3. TX Power and IBAT vs TX Power Level Settings (54 OFDM)
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8.8 Brownout and Blackout Conditions
The device enters a brownout condition when the input voltage drops below Vbrownout (see Figure 8-4 and Figure
8-5). This condition must be considered during design of the power supply routing, especially when operating
from a battery. High-current operations, such as a TX packet or any external activity (not necessarily related
directly to networking) can cause a drop in the supply voltage, potentially triggering a brownout condition. The
resistance includes the internal resistance of the battery, the contact resistance of the battery holder (four
contacts for 2× AA batteries), and the wiring and PCB routing resistance.
Note
When the device is in HIBERNATE state, brownout is not detected. Only blackout is in effect during
HIBERNATE state.
Figure 8-4. Brownout and Blackout Levels (1 of 2)
Figure 8-5. Brownout and Blackout Levels (2 of 2)
34
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In the brownout condition, all sections of the device (including the 32-kHz RTC) shut down except for the
Hibernate module, which remains on. The current in this state can reach approximately 400 µA. The blackout
condition is equivalent to a hardware reset event in which all states within the device are lost.
Table 8-1 lists the brownout and blackout voltage levels.
Table 8-1. Brownout and Blackout Voltage Levels
CONDITION
VOLTAGE LEVEL
UNIT
Vbrownout
2.1
V
Vblackout
1.67
V
8.9 Electrical Characteristics (3.3 V, 25°C)
GPIO Pins Except 29, 30, 50, 52, and 53 (25°C)(1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
Pin capacitance
VIH
High-level input voltage
0.65 × VDD
VDD + 0.5 V
V
VIL
Low-level input voltage
–0.5
0.35 × VDD
V
IIH
High-level input current
5
nA
IIL
Low-level input current
5
nA
VOH
VOL
IOH
IOL
4
UNIT
CIN
High-level output voltage
Low-level output voltage
High-level
source current
Low-level
sink current
pF
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.8
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.75
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.25
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
VDD × 0.35
2-mA drive
2
4-mA drive
4
6-mA drive
6
2-mA drive
2
4-mA drive
4
6-mA drive
6
V
V
mA
mA
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GPIO Pins Except 29, 30, 50, 52, and 53 (25°C)(1)
PARAMETER
GPIO Pins 29, 30, 50, 52, and 53
TEST CONDITIONS
MIN
NOM
MAX
UNIT
(25°C)(1)
CIN
Pin capacitance
VIH
High-level input voltage
0.65 × VDD
VDD + 0.5 V
V
VIL
Low-level input voltage
–0.5
0.35 × VDD
V
IIH
High-level input current
50
nA
IIL
Low-level input current
50
nA
VOH
VOL
IOH
IOL
VIL
7
High-level output voltage
Low-level output voltage
High-level
source current,
VOH = 2.4
Low-level
sink current
pF
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.8
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.75
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.25
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
VDD × 0.35
2-mA drive
1.5
4-mA drive
2.5
6-mA drive
3.5
2-mA drive
1.5
4-mA drive
2.5
6-mA drive
3.5
nRESET(2)
V
V
mA
mA
0.6
V
Pin Internal Pullup and Pulldown (25°C)(1)
IOH
Pullup current, VOH = 2.4
(VDD = 3.0 V)
5
IOL
Pulldown current, VOL = 0.4
(VDD = 3.0 V)
5
(1)
(2)
36
10
µA
µA
TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk
of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength
setting is 6 mA.
The nRESET pin must be held below 0.6 V for the device to register a reset.
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8.10 WLAN Receiver Characteristics
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters are measured at the SoC pin on channel 6 (2437 MHz).
PARAMETER
TEST CONDITIONS (Mbps)
Sensitivity
(8% PER for 11b rates, 10% PER for 11g/11n
rates) (10% PER)(3)
TYP(1)
1 DSSS
–96.0
2 DSSS
–94.0
11 CCK
–88.0
6 OFDM
–90.5
9 OFDM
–90.0
18 OFDM
–86.5
36 OFDM
–80.5
54 OFDM
–74.5
(GF)(2)
–71.5
MCS7 (MM)(2)
–70.5
802.11b
–4.0
802.11g
–10.0
MCS7
Maximum input level
(10% PER)
(1)
(2)
(3)
MIN
MAX
UNIT
dBm
dBm
In preregulated 1.85-V mode, RX sensitivity is 0.25- to 1-dB lower.
Sensitivity for mixed mode is 1-dB worse.
Sensitivity is 1-dB worse on channel 13 (2472 MHz).
8.11 WLAN Transmitter Characteristics
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters measured at SoC pin on channel 6 (2437 MHz).(1) (2) (3)
TEST CONDITIONS(3)
PARAMETER
Maximum RMS output power measured at 1
dB from IEEE spectral mask or EVM
MIN
1 DSSS
18.0
2 DSSS
18.0
11 CCK
18.3
6 OFDM
17.3
9 OFDM
17.3
18 OFDM
17.0
36 OFDM
16.0
54 OFDM
14.5
MCS7 (MM)
Transmit center frequency accuracy
(1)
(2)
(3)
TYP
MAX
UNIT
dBm
13.0
–25
25
ppm
The edge channels (2412 and 2472 MHz) have reduced TX power to meet FCC emission limits.
Power of 802.11b rates are reduced to meet ETSI requirements.
In preregulated 1.85-V mode, maximum TX power is 0.25- to 0.75-dB lower for modulations higher than 18 OFDM.
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8.12 WLAN Filter Requirements
The device requires an external band-pass filter to meet the various emission standards, including FCC. Section
8.12.1 presents the attenuation requirements for the band-pass filter. TI recommends using the same filter used
in the reference design to ease the process of certification.
8.12.1 WLAN Filter Requirements
PARAMETER
FREQUENCY (MHz)
Return loss
Insertion
2412 to 2484
loss(1)
TYP
Reference impendence
UNIT
dB
1
800 to 830
30
45
1600 to 1670
20
25
3200 to 3300
30
48
4000 to 4150
45
50
4800 to 5000
20
25
5600 to 5800
20
25
6400 to 6600
20
35
7200 to 7500
35
45
7500 to 10000
20
25
2412 to 2484
Filter type
MAX
10
2412 to 2484
Attenuation
(1)
MIN
1.5
dB
dB
50
Ω
Bandpass
Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation
requirements.
8.13 Thermal Resistance Characteristics
8.13.1 Thermal Resistance Characteristics for RGK Package
AIR FLOW
PARAMETER
0 lfm (C/W)
150 lfm (C/W)
250 lfm (C/W)
500 lfm (C/W)
θja
23
14.6
12.4
10.8
Ψjt
0.2
0.2
0.3
0.1
Ψjb
2.3
2.3
2.2
2.4
θjc
6.3
θjb
2.4
8.14 Timing and Switching Characteristics
8.14.1 Power Supply Sequencing
For proper operation of the CC3220x device, perform the recommended power-up sequencing as follows:
1. Tie VBAT (pins 37, 39, 44) and VIO (pins 54 and 10) together on the board.
2. Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit (100 K
||, 1 µF, RC = 100 ms).
3. For an external RTC, ensure that the clock is stable before RESET is deasserted (high).
For timing diagrams, see Section 8.14.3.
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8.14.2 Device Reset
When a device restart is required, the user may issue a negative pulse to the nRESET pin. The user must follow
one of the two alternatives to ensure the reset is properly applied:
•
•
A negative reset pulse (on pin 32) of at least 200-ms duration
If the above cannot be guaranteed, a pull-down resistor of 2 MΩ should be connected to pin 52
(RTC_XTAL_N). If implemented, a shorter pulse of at least 100 µs can be used.
To ensure a proper reset sequence, the user has to call the sl_stop function prior to toggling the reset. It is
preferable to use software reset instead of an external trigger when a reset is required.
8.14.3 Reset Timing
8.14.3.1 nRESET (32-kHz Crystal)
First-Time Power-Up and Reset Removal Timing Diagram (32-kHz Crystal) shows the reset timing diagram for
the 32-kHz crystal first-time power-up and reset removal.
T1
T2
T3
T4
HW INIT
FW INIT
APP CODE
LOAD
VBAT
VIO
nRESET
STATE
POWER
RESET
OFF
APP CODE
EXECUTION
32-kHz
RTC CLK
T1 should be ≥200 ms without a pulldown resistor on the XTAL_N pin or T1 should be ≥100 µs if there is 2-MΩ pulldown resistor on the
XTAL_N pin.
Figure 8-6. First-Time Power-Up and Reset Removal Timing Diagram (32-kHz Crystal)
Section 8.14.3.2 describes the timing requirements for the 32-kHz clock crystal first-time power-up and reset
removal.
8.14.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
ITEM
NAME
T1
Supply settling time
T2
Hardware wake-up time
T3
Time taken by ROM
firmware to initialize
hardware
T4
App code load time for
CC3220R and CC3220S
App code integrity check
time for CC3220SF
DESCRIPTION
MIN
Depends on application board
power supply, decoupling capacitor,
and so on
Includes 32.768-kHz XOSC settling
time
TYP
MAX
UNIT
3
ms
25
ms
1.1
s
CC3220R
Image size (KB) × 0.75 ms
CC3220S
Image size (KB) × 1.7 ms
CC3220SF
Image size (KB) × 0.06 ms
8.14.3.3 nRESET (External 32-kHz)
Figure 8-7 shows the reset timing diagram for the external 32-kHz first-time power-up and reset removal.
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T1
T2
T3
T4
RESET
HW INIT
FW INIT
APP CODE
LOAD
VBAT
VIO
nRESET
STATE
POWER
OFF
APP CODE
EXECUTION
32-kHz
RTC CLK
Figure 8-7. First-Time Power-Up and Reset Removal Timing Diagram (External 32-kHz)
Section 8.14.3.3.1 describes the timing requirements for the external 32-kHz clock first-time power-up and reset
removal.
8.14.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz)
ITEM
NAME
T1
Supply settling time
T2
Hardware wake-up time
T3
Time taken by ROM
firmware to initialize
hardware
T4
App code load time for
CC3220R and CC3220S
App code integrity check
time for CC3220SF
40
DESCRIPTION
MIN
Depends on application board power
supply, decoupling capacitor, and so
on
TYP
UNIT
3
ms
25
ms
CC3220R
5
CC3220S
10.3
CC3220SF
17.3
CC3220R
Image size (KB) × 0.75 ms
CC3220S
Image size (KB) × 1.7 ms
CC3220SF
Image size (KB) × 0.06 ms
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8.14.4 Wakeup From HIBERNATE Mode
Figure 8-8 shows the timing diagram for wakeup from HIBERNATE mode.
Application software requests
entry to HIBERNATE mode
THIB_MIN
T2
T3
T4
FW INIT
APP CODE
LOAD
VBAT
VIO
nRESET
STATE
ACTIVE
HIBERNATE
HW WAKEUP
EXECUTION
32-kHz
RTC CLK
Figure 8-8. Wakeup From HIBERNATE Timing Diagram
Note
The 32.768-kHz crystal is kept enabled by default when the chip goes into HIBERNATE mode .
8.14.5 Clock Specifications
The CC3220x device requires two separate clocks for its operation:
•
•
A slow clock running at 32.768 kHz is used for the RTC.
A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN subsystem.
The device features internal oscillators that enable the use of less-expensive crystals rather than dedicated
TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system
and to reduce overall cost.
8.14.5.1 Slow Clock Using Internal Oscillator
The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock
frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P
(pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance to meet the ppm requirement.
Figure 8-9 shows the crystal connections for the slow clock.
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51
RTC_XTAL_P
10 pF
GND
32.768 kHz
RTC_XTAL_N
52
10 pF
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 8-9. RTC Crystal Connections
Section 8.14.5.1.1 lists the RTC crystal requirements.
8.14.5.1.1 RTC Crystal Requirements
CHARACTERISTICS
TEST CONDITIONS
MIN
Frequency
TYP
MAX
UNIT
±150
ppm
32.768
Frequency accuracy
Initial plus temperature plus aging
Crystal ESR
32.768 kHz
kHz
70
kΩ
8.14.5.2 Slow Clock Using an External Clock
When an RTC oscillator is present in the system, the CC3220x device can accept this clock directly as an
input. The clock is fed on the RTC_XTAL_P line, and the RTC_XTAL_N line is held to VIO. The clock must be a
CMOS-level clock compatible with VIO fed to the device.
Figure 8-10 shows the external RTC input connection.
RTC_XTAL_P
32.768 kHz
VIO
Host system
100 KΩ
RTC_XTAL_N
Copyright © 2017, Texas Instruments Incorporated
Figure 8-10. External RTC Input
Section 8.14.5.2.1 lists the external RTC digital clock requirements.
8.14.5.2.1 External RTC Digital Clock Requirements
CHARACTERISTICS
TEST CONDITIONS
MIN
Frequency
Frequency accuracy
(Initial plus temperature plus aging)
tr, tf
42
Input transition time tr, tf (10% to 90%)
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TYP
MAX
UNIT
32768
Hz
±150
ppm
100
ns
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CHARACTERISTICS
TEST CONDITIONS
Frequency input duty cycle
Vih
Slow clock input voltage limits
Vil
Square wave, DC coupled
MIN
TYP
MAX
20%
50%
80%
0.65 × VIO
VIO
0
0.35 × VIO
1
Input impedance
UNIT
V
Vpeak
MΩ
5
pF
8.14.5.3 Fast Clock (Fref) Using an External Crystal
The CC3220x device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The
crystal is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading
capacitors.
Figure 8-11 shows the crystal connections for the fast clock.
23
WLAN_XTAL_P
6.2 pF
GND
40 MHz
WLAN_XTAL_N
22
6.2 pF
GND
SWAS031-030
A.
The crystal capacitance must be tuned to ensure that the PPM requirement is met. See CC31xx & CC32xx Frequency Tuning for
information on frequency tuning.
Figure 8-11. Fast Clock Crystal Connections
Section 8.14.5.3.1 lists the WLAN fast-clock crystal requirements.
8.14.5.3.1 WLAN Fast-Clock Crystal Requirements
CHARACTERISTICS
TEST CONDITIONS
Frequency
MIN
TYP
MAX
40
Frequency accuracy
Initial plus temperature plus aging
Crystal ESR
40 MHz
UNIT
MHz
±25
ppm
60
Ω
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8.14.5.4 Fast Clock (Fref) Using an External Oscillator
The CC3220x device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the
clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external
TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the
system.
If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the
LDO improves noise on the TCXO power supply.
Figure 8-12 shows the connection.
Vcc
XO (40 MHz)
CC3220x
TCXO_EN
EN
82 pF
WLAN_XTAL_P
OUT
WLAN_XTAL_N
Copyright © 2017, Texas Instruments Incorporated
Figure 8-12. External TCXO Input
Section 8.14.5.4.1 lists the external Fref clock requirements.
8.14.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
CHARACTERISTICS
TEST CONDITIONS
MIN
Frequency
TYP
40.00
Frequency accuracy (Initial plus temperature plus
aging)
45%
Sine or clipped sine wave, AC
coupled
Clock voltage limits
0.7
at 1 kHz
Phase noise at 40 MHz
at 10 kHz
44
Resistance
Capacitance
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ppm
55%
1.2
Vpp
–125
–138.5 dBc/Hz
at 100 kHz
Input impedance
50%
UNIT
MHz
±25
Frequency input duty cycle
Vpp
MAX
–143
12
kΩ
7
pF
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8.14.6 Peripherals Timing
This section describes the peripherals that are supported by the CC3220x device:
•
•
•
•
•
•
•
•
•
•
SPI
I2S
GPIOs
I2C
IEEE 1149.1 JTAG
ADC
Camera parallel port
UART
SD Host
Timers
8.14.6.1 SPI
8.14.6.1.1 SPI Master
The CC3220x microcontroller includes one SPI module, which can be configured as a master or slave device.
The SPI includes a serial clock with programmable frequency, polarity, and phase; a programmable timing
control between chip select and external clock generation; and a programmable delay before the first SPI word is
transmitted. Slave mode does not include a dead cycle between two successive words.
Figure 8-13 shows the timing diagram for the SPI master.
T2
CLK
T6
T7
MISO
T9
T8
MOSI
Figure 8-13. SPI Master Timing Diagram
Section 8.14.6.1.1.1 lists the timing parameters for the SPI master.
8.14.6.1.1.1 SPI Master Timing Parameters
PARAMETER
NUMBER
MIN
F(1)
T2
(1)
Tclk
Clock frequency
(1)
Clock period
MAX
UNIT
20
MHz
50
ns
D(1)
Duty cycle
T6
tIS (1)
RX data setup time
1
ns
T7
tIH (1)
RX data hold time
2
ns
(1)
T8
tOD
T9
tOH (1)
TX data output delay
TX data hold time
45%
55%
8.5
ns
8
ns
Timing parameter assumes a maximum load of 20 pF.
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8.14.6.1.2 SPI Slave
Figure 8-14 shows the timing diagram for the SPI slave.
T2
CLK
T6
T7
MISO
T9
T8
MOSI
Figure 8-14. SPI Slave Timing Diagram
Section 8.14.6.1.2.1 lists the timing parameters for the SPI slave.
8.14.6.1.2.1 SPI Slave Timing Parameters
PARAMETER
NUMBER
MIN
F(1)
46
Clock frequency at VBAT = 3.3 V
20
Clock frequency at VBAT ≤ 2.1 V
12
UNIT
MHz
Tclk (1)
Clock period
D(1)
Duty cycle
T6
tIS (1)
RX data setup time
4
ns
T7
tIH (1)
RX data hold time
4
ns
T2
(1)
MAX
(1)
T8
tOD
T9
tOH (1)
50
45%
ns
55%
TX data output delay
20
ns
TX data hold time
24
ns
Timing parameter assumes a maximum load of 20 pF at 3.3 V.
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8.14.6.2 I2S
The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio
applications and supports transfer of two stereo channels over two data pins. The McASP consists of transmit
and receive sections that operate synchronously and have programmable clock and frame-sync polarity. A
fractional divider is available for bit-clock generation.
8.14.6.2.1 I2S Transmit Mode
Figure 8-15 shows the timing diagram for the I2S transmit mode.
T2
T1
T3
McACLKX
T4
T4
McAFSX
McAXR0/1
Figure 8-15. I2S Transmit Mode Timing Diagram
Section 8.14.6.2.1.1 lists the timing parameters for the I2S transmit mode.
8.14.6.2.1.1 I2S Transmit Mode Timing Parameters
PARAMETER
NUMBER
(1)
MIN
MAX
UNIT
MHz
T1
fclk (1)
Clock frequency
9.216
T2
tLP (1)
Clock low period
1/2 fclk
ns
T3
tHT
(1)
Clock high period
1/2 fclk
ns
T4
tOH (1)
TX data hold time
22
ns
Timing parameter assumes a maximum load of 20 pF.
8.14.6.2.2 I2S Receive Mode
Figure 8-16 shows the timing diagram for the I2S receive mode.
T2
T1
T3
McACLKX
T5
T4
McAFSX
McAXR0/1
Figure 8-16. I2S Receive Mode Timing Diagram
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Section 8.14.6.2.2.1 lists the timing parameters for the I2S receive mode.
8.14.6.2.2.1 I2S Receive Mode Timing Parameters
PARAMETER
NUMBER
(1)
MIN
MAX
UNIT
T1
fclk (1)
Clock frequency
9.216
MHz
T2
tLP (1)
Clock low period
1/2 fclk
ns
T3
tHT (1)
Clock high period
1/2 fclk
ns
T4
tOH
(1)
RX data hold time
0
ns
T5
tOS (1)
RX data setup time
15
ns
Timing parameter assumes a maximum load of 20 pF.
8.14.6.3 GPIOs
All digital pins of the device can be used as general-purpose input/output (GPIO) pins. The GPIO module
consists of four GPIO blocks, each of which provides eight GPIOs. The GPIO module supports 24
programmable GPIO pins, depending on the peripheral used. Each GPIO has configurable pullup and pulldown
strength (weak 10 µA), configurable drive strength (2, 4, and 6 mA), and open-drain enable.
Figure 8-17 shows the GPIO timing diagram.
VDD
80%
20%
tGPIOF
tGPIOR
SWAS031-067
Figure 8-17. GPIO Timing Diagram
8.14.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
Section 8.14.6.3.1.1 lists the GPIO output transition times for Vsupply = 3.3 V.
8.14.6.3.1.1 GPIO Output Transition Times (Vsupply = 3.3 V)(1) (2)
DRIVE
STRENGTH (mA)
2
4
6
(1)
(2)
48
DRIVE STRENGTH
CONTROL BITS
2MA_EN=1
4MA_EN=0
2MA_EN=0
4MA_EN=1
2MA_EN=1
4MA_EN=1
tr
tf
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
8.0
9.3
10.7
8.2
9.5
11.0
ns
6.6
7.1
7.6
4.7
5.2
5.8
ns
3.2
3.5
3.7
2.3
2.6
2.9
ns
Vsupply = 3.3 V, T = 25°C, total pin load = 30 pF
The transition data applies to the pins except the multiplexed analog-digital pins 29, 30, 45, 50, 52, and 53.
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8.14.6.3.2 GPIO Output Transition Time Parameters (Vsupply = 1.85 V)
Section 8.14.6.3.2.1 lists the GPIO output transition times for Vsupply = 1.8 V.
8.14.6.3.2.1 GPIO Output Transition Times (Vsupply = 1.85 V)(1) (2)
DRIVE
STRENGTH (mA)
2
4
6
(1)
(2)
DRIVE STRENGTH
CONTROL BITS
2MA_EN=1
4MA_EN=0
2MA_EN=0
4MA_EN=1
tr
tf
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
11.7
13.9
16.3
11.5
13.9
16.7
ns
13.7
15.6
18.0
9.9
11.6
13.6
ns
5.5
6.4
7.4
3.8
4.7
5.8
ns
2MA_EN=1
4MA_EN=1
Vsupply = 1.8 V, T = 25°C, total pin load = 30 pF
The transition data applies to the pins other than the multiplexed analog-digital pins 29, 30, 45, 50, 52, and 53.
8.14.6.3.3 GPIO Input Transition Time Parameters
Section 8.14.6.3.3.1 lists the input transition time parameters.
8.14.6.3.3.1 GPIO Input Transition Time Parameters'
tr
tf
Input transition time (tr, tf), 10% to 90%
MIN
MAX
UNIT
1
3
ns
1
3
ns
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8.14.6.4 I2C
The CC3220x microcontroller includes one I2C module operating with standard (100 kbps) or fast
(400 kbps) transmission speeds.
Figure 8-18 shows the I2C timing diagram.
T2
T6
T5
I2CSCL
T1
T4
T7
T8
T3
T9
I2CSDA
Figure 8-18. I2C Timing Diagram
Section 8.14.6.4.1 lists the I2C timing parameters.
8.14.6.4.1 I2C Timing Parameters(3)
PARAMETER
NUMBER
T2
(1)
(2)
(3)
50
MIN
tLP
Clock low period
MAX
See (1)
UNIT
System clock
See
(2)
T3
tSRT
SCL/SDA rise time
T4
tDH
Data hold time
ns
T5
tSFT
SCL/SDA fall time
T6
tHT
Clock high time
See (1)
System clock
T7
tDS
Data setup time
tLP/2
System clock
T8
tSCSR
Start condition setup time
36
System clock
T9
tSCS
Stop condition setup time
24
System clock
NA
3
ns
This value depends on the value programmed in the clock period register of I2C. Maximum output frequency is the result of the minimal
value programmed in this register.
Because I2C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of external pullup. Rise time depends on
the value of the external signal capacitance and external pullup register.
All timing is with 6-mA drive and 20-pF load.
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8.14.6.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits and provides a standardized serial interface to control
the associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the
IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture.
Figure 8-19 shows the JTAG timing diagram.
T2
T3
T4
TCK
T7
TMS
T8
TMS Input Valid
T9
TDI
T8
T7
TMS Input Valid
T10
T9
TDI Input Valid
T10
TDI Input Valid
T1
T11
TDO
TDO Output Valid
TDO Output Valid
Figure 8-19. JTAG Timing Diagram
Section 8.14.6.5.1 lists the JTAG timing parameters.
8.14.6.5.1 JTAG Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
15
MHz
T1
fTCK
Clock frequency
T2
tTCK
Clock period
1 / fTCK
ns
T3
tCL
Clock low period
tTCK / 2
ns
T4
tCH
Clock high period
tTCK / 2
ns
T7
tTMS_SU
TMS setup time
1
ns
T8
tTMS_HO
TMS hold time
16
ns
T9
tTDI_SU
TDI setup time
1
ns
T10
tTDI_HO
TDI hold time
16
ns
T11
tTDO_HO
TDO hold time
15
ns
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8.14.6.6 ADC
Figure 8-20 shows the ADC clock timing diagram.
Repeats Every 16 µs
Internal Ch
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
ADC CLOCK
= 10 MHz
Sampling
4 cycles
SAR Conversion
16 cycles
Sampling
4 cycles
EXT CHANNEL 0
SAR Conversion
16 cycles
INTERNAL CHANNEL
Sampling
4 cycles
SAR Conversion
16 cycles
Sampling
4 cycles
EXT CHANNEL 1
SAR Conversion
16 cycles
INTERNAL CHANNEL
Figure 8-20. ADC Clock Timing Diagram
Section 8.14.6.6.1 lists the ADC electrical specifications. See CC32xx ADC Appnote for further information on
using the ADC and for application-specific examples.
8.14.6.6.1 ADC Electrical Specifications
PARAMETER
DESCRIPTION
TEST CONDITIONS AND
ASSUMPTIONS
MIN
TYP
MAX
12
UNIT
Nbits
Number of bits
INL
Integral nonlinearity
Worst-case deviation from
histogram method over full scale
(not including first and last three
LSB levels)
–2.5
2.5
LSB
DNL
Differential nonlinearity
Worst-case deviation of any step
from ideal
–1
4
LSB
0
1.4
V
100
Ω
Input range
Driving source
impedance
FCLK
Successive approximation input
clock rate
Clock rate
Input capacitance
Input impedance
MHz
12
pF
2.15
ADC Pin 58
0.7
ADC Pin 59
2.12
ADC Pin 60
1.17
kΩ
4
Fsample
Sampling rate of each pin
F_input_max
Maximum input signal frequency
62.5
SINAD
Signal-to-noise and distortion
I_active
Active supply current
Average for analog-to-digital
during conversion without
reference current
I_PD
Power-down supply current for
core supply
Total for analog-to-digital when
not active (this must be the SoC
level test)
Absolute offset error
KSPS
31
Input frequency DC to 300 Hz
and 1.4 Vpp sine wave input
FCLK = 10 MHz
Gain error
52
10
ADC Pin 57
Number of channels
Bits
55
kHz
60
dB
1.5
mA
1
µA
±2
mV
±2%
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PARAMETER
Vref
TEST CONDITIONS AND
ASSUMPTIONS
DESCRIPTION
MIN
TYP
ADC reference voltage
MAX
1.467
UNIT
V
8.14.6.7 Camera Parallel Port
The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in a
FIFO, and generates DMA requests. The camera parallel port supports 8 bits.
Figure 8-21 shows the timing diagram for the camera parallel port.
T3
T2
T4
pCLK
T6
T7
pVS, pHS
pDATA
Figure 8-21. Camera Parallel Port Timing Diagram
Section 8.14.6.7.1 lists the timing parameters for the camera parallel port.
8.14.6.7.1 Camera Parallel Port Timing Parameters
PARAMETER NUMBER
MIN
MAX
UNIT
2
MHz
pCLK
Clock frequency
T2
Tclk
Clock period
1/pCLK
ns
T3
tLP
Clock low period
Tclk/2
ns
T4
tHT
Clock high period
Tclk/2
ns
T6
tIS
RX data setup time
2
ns
T7
tIH
RX data hold time
2
ns
D
Duty cycle
45%
55%
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8.14.6.8 UART
The CC3220x device includes two UARTs with the following features:
•
•
•
•
•
•
•
•
•
•
•
Programmable baud-rate generator allowing speeds up to 3 Mbps
Separate 16-bit × 8-bit TX and RX FIFOs to reduce CPU interrupt service loading
Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered
interface
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
Standard asynchronous communication bits for start, stop, and parity
Generation and detection of line-breaks
Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Generation and detection of even, odd, stick, or no-parity bits
– Generation of 1 or 2 stop-bits
RTS and CTS hardware flow support
Standard FIFO-level and end-of-transmission interrupts
Efficient transfers using µDMA:
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO
level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed
FIFO level
System clock is used to generate the baud clock.
8.14.6.9 SD Host
CC3220x provides an interface between a local host (LH), such as an MCU and an SD memory card, and
handles SD transactions with minimal LH intervention.
The SD host does the following:
•
•
•
•
•
•
Provides SD card access in 1-bit mode
Deals with SD protocol at the transmission level
Handles data packing
Adds cyclic redundancy checks (CRC)
Start and end bit
Checks for syntactical correctness
The application interface sends every SD command and either polls for the status of the adapter or waits for
an interrupt request. The result is then sent back to the application interface in case of exceptions or to warn
of end-of-operation. The controller can be configured to generate DMA requests and work with minimum CPU
intervention. Given the nature of integration of this peripheral on the CC3220x platform, TI recommends that
developers use peripheral library APIs to control and operate the block. This section emphasizes understanding
the SD host APIs provided in the peripheral library of the CC3220x Software Development Kit (SDK).
The SD Host features are as follows:
•
•
•
•
•
•
•
54
Full compliance with SD command and response sets, as defined in the SD memory card
– Specifications, v2.0
– Includes high-capacity (size >2 GB) cards HC SD
Flexible architecture, allowing support for new command structure.
1-bit transfer mode specifications for SD cards
Built-in 1024-byte buffer for read or write
– 512-byte buffer for both transmit and receive
– Each buffer is 32-bits wide by 128-words deep
32-bit-wide access bus to maximize bus throughput
Single interrupt line for multiple interrupt source events
Two slave DMA channels (1 for TX, 1 for RX)
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•
•
•
•
•
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Programmable clock generation
Integrates an internal transceiver that allows a direct connection to the SD card without external transceiver
Supports configurable busy and response timeout
Support for a wide range of card clock frequency with odd and even clock ratio
Maximum frequency supported is 24 MHz
8.14.6.10 Timers
Programmable timers can be used to count or time external events that drive the timer input pins. The CC3220x
general-purpose timer module (GPTM) contains 16- or 32-bit GPTM blocks. Each 16- or 32-bit GPTM block
provides two 16-bit timers or counters (referred to as Timer A and Timer B) that can be configured to operate
independently as timers or event counters, or they can be concatenated to operate as one 32-bit timer. Timers
can also be used to trigger µDMA transfers.
The GPTM contains four 16- or 32-bit GPTM blocks with the following functional options:
•
•
•
•
•
•
•
Operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal
Counts up or counts down
Sixteen 16- or 32-bit capture compare pins (CCP)
User-enabled stalling when the microcontroller asserts CPU Halt flag during debug
Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt
service routine
Efficient transfers using micro direct memory access controller (µDMA):
– Dedicated channel for each timer
– Burst request generated on timer interrupt
Runs from system clock (80 MHz)
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9 Detailed Description
The CC3220x wireless MCU family has a rich set of peripherals for diverse application requirements. This
section briefly highlights the internal details of the CC3220x devices and offers suggestions for application
configurations.
9.1 Arm® Cortex®-M4 Processor Core Subsystem
The high-performance Cortex-M4 processor provides a low-cost platform that meets the needs of minimal
memory implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
•
•
•
•
56
The Cortex-M4 core has low-latency interrupt processing with the following features:
– A 32-bit Arm® Thumb® instruction set optimized for embedded applications
– Handler and thread modes
– Low-latency interrupt handling by automatic processor state saving and restoration during entry and exit
– Support for ARMv6 unaligned accesses
Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low-latency
interrupt processing. The NVIC includes the following features:
– Bits of priority configurable from 3 to 8
– Dynamic reprioritization of interrupts
– Priority grouping that enables selection of preempting interrupt levels and nonpreempting interrupt levels
– Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt processing
without the overhead of state saving and restoration between interrupts
– Processor state automatically saved on interrupt entry and restored on interrupt exit with no instruction
overhead
– Wake-up interrupt controller (WIC) providing ultra-low-power sleep mode support
Bus interfaces:
– Advanced high-performance bus (AHB-Lite) interfaces: system bus interfaces
– Bit-band support for memory and select peripheral that includes atomic bit-band write and read operations
Low-cost debug solution featuring:
– Debug access to all memory and registers in the system, including access to memory-mapped devices,
access to internal core registers when the core is halted, and access to debug control registers even while
SYSRESETn is asserted
– Serial wire debug port (SW-DP) or serial wire JTAG debug port (SWJ-DP) debug access
– Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches
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9.2 Wi-Fi Network Processor Subsystem
The Wi-Fi network processor subsystem includes a dedicated Arm MCU to completely offload the host MCU
along with an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast, secure WLAN
and Internet connections with 256-bit encryption. The CC3220x devices support station, AP, and Wi-Fi Direct
modes. The device also supports WPA2 personal and enterprise security, WPS 2.0, WPA3 personal and
enterprise. The Wi-Fi network processor includes an embedded IPv6, IPv4 TCP/IP stack.
9.2.1 WLAN
The WLAN features are as follows:
•
802.11b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station, AP,
Wi-Fi Direct client and group owner with CCK and OFDM rates in the 2.4-GHz ISM band, channels 1 to 13.
Note
802.11n is supported only in Wi-Fi station, Wi-Fi direct, and P2P client modes.
•
•
•
•
•
Autocalibrated radio with a single-ended 50-Ω interface enables easy connection to the antenna without
requiring expertise in radio circuit design.
Advanced connection manager with multiple user-configurable profiles stored in serial Flash allows automatic
fast connection to an access point without user or host intervention.
Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security
accelerators, including: WEP, WPA/WPA2 PSK, WPA2 Enterprise (802.1x), WPA3 Personal, and WPA3
Enterprise.
Smart provisioning options deeply integrated within the device providing a comprehensive end-to-end
solution. With elaborate events notification to the host, enabling the application to control the provisioning
decision flow. The wide variety of Wi-Fi provisioning methods include:
– Access Point using HTTPS
– SmartConfig Technology: a 1-step, 1-time process to connect a CC3220-enabled device to the home
wireless network, removing dependency on the I/O capabilities of the host MCU; thus, it is usable by
deeply embedded applications
802.11 transceiver mode allows transmitting and receiving of proprietary data through a socket without
adding MAC or PHY headers. The 802.11 transceiver mode provides the option to select the working
channel, rate, and transmitted power. The receiver mode works with the filtering options.
9.2.2 Network Stack
The Network Stack features are as follows:
•
Integrated IPv4, IPv6 TCP/IP stack with BSD (BSD adjacent) socket APIs for simple Internet connectivity with
any MCU, microprocessor, or ASIC
Note
Not all APIs are 100% BSD compliant. Not all BSD APIs are supported.
•
•
•
•
Support of 16 simultaneous TCP, UDP, or RAW sockets
Support of 6 simultaneous SSL\TLS sockets
Built-in network protocols:
– Static IP, LLA, DHCPv4, DHCPv6 with DAD and stateless autoconfiguration
– ARP, ICMPv4, IGMP, ICMPv6, MLD, ND
– DNS client for easy connection to the local network and the Internet
Built-in network application and utilities:
– HTTP/HTTPS
• Web page content stored on serial Flash
• RESTful APIs for setting and configuring application content
• Dynamic user callbacks
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– Service discovery: Multicast DNS service discovery lets a client advertise its service without a centralized
server. After connecting to the access point, the CC3220x device provides critical information, such as
device name, IP, vendor, and port number.
– DHCP server
– Ping
Table 9-1 describes the NWP features.
Table 9-1. NWP Features
Feature
Description
802.11b/g/n station
Wi-Fi standards
802.11b/g AP supporting up to four stations
Wi-Fi Direct client and group owner
Wi-Fi channels
1 to 13
Wi-Fi security
WEP, WPA/WPA2 PSK, WPA2 enterprise (802.1x), WPA3 personal and enterprise
Wi-Fi provisioning
SmartConfig technology, Wi-Fi protected setup (WPS2), AP mode with internal HTTP web server
IP protocols
IPv4/IPv6
IP addressing
Static IP, LLA, DHCPv4, DHCPv6 with DAD
Cross layer
ARP, ICMPv4, IGMP, ICMPv6, MLD, NDP
UDP, TCP
Transport
SSLv3.0/TLSv1.0/TLSv1.1/TLSv1.2
RAW
Ping
Network applications and
utilities
HTTP/HTTPS web server
mDNS
DNS-SD
DHCP server
Host interface
UART/SPI
Device identity
Trusted root-certificate catalog
TI root-of-trust public key
The CC3220S and CC3220SF variants also support:
Security
Power management
Other
58
•
Secure key storage
•
•
•
•
•
•
•
•
File system security
Software tamper detection
Cloning protection
Secure boot
Validate the integrity and authenticity of the run-time binary during boot
Initial secure programming
Debug security
JTAG and debug
Enhanced power policy management uses 802.11 power save and deep-sleep power modes
Transceiver
Programmable RX filters with event-trigger mechanism
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9.3 Security
The SimpleLink™ Wi-Fi® CC3220x Internet-on-a-Chip device enhances the security capabilities available for
development of IoT devices, while completely offloading these activities from the MCU to the networking
subsystem. The security capabilities include the following key features:
Wi-Fi and Internet Security:
•
•
•
•
Personal and enterprise Wi-Fi security
– Personal standards
• AES (WPA2-PSK)
• TKIP (WPA-PSK)
• WEP
– Enterprise standards
• EAP Fast
• EAP PEAPv0/1
• EAP PEAPv0 TLS
• EAP PEAPv1 TLS EAP LS
• EAP TLS
• EAP TTLS TLS
• EAP TTLS MSCHAPv2
Secure sockets
– Protocol versions: SSL v3, TLS 1.0, TLS 1.1, TLS 1.2
– Powerful crypto engine for fast, secure Wi-Fi and internet connections with 256-bit AES encryption for TLS
and SSL connections
– Ciphers suites
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
– Server authentication
– Client authentication
– Domain name verification
– Runtime socket upgrade to secure socket – STARTTLS
Secure HTTP server (HTTPS)
Trusted root-certificate catalog—Verifies that the CA used by the application is trusted and known secure
content delivery
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•
•
TI root-of-trust public key—Hardware-based mechanism that allows authenticating TI as the genuine origin of
a given content using asymmetric keys
Secure content delivery—Allows encrypted file transfer to the system using asymmetric keys created by the
device
Code and Data Security:
•
•
•
•
•
•
•
•
•
Network passwords and certificates are encrypted and signed.
Cloning protection—Application and data files are encrypted by a unique key per device.
Access control—Access to application and data files only by using a token provided in file creation time. If an
unauthorized access is detected, a tamper protection lockdown mechanism takes effect.
Encrypted and Authenticated file system (not supported in CC3220R)
Secured boot—Authentication of the application image on every boot
Code and data encryption (not supported in CC3220R)—User application and data files are encrypted in
serial flash.
Code and data authentication (not supported in CC3220R)—User Application and data files are authenticated
with a public key certificate.
Offloaded crypto library for asymmetric keys, including the ability to create key-pair, sign and verify data
buffer.
Recovery mechanism
Device Security:
•
•
•
•
Separate execution environments—Application processor and network processor run on separate Arm cores
Initial secure programming (not supported in CC3220R)—Allows for keeping the content confidential on the
production line
Debug security (not supported in CC3220R)
– JTAG lock
– Debug ports lock
True random number generator
Figure 9-1 shows the high-level structure of the CC3220R device. The network information files (passwords and
certificates) are encrypted using a device-specific key.
CC3220R
Network Processor + MCU
MCU
Peripherals
SPI and I2C
GPIO
Network Processor
Arm® Cortex®-M4
Processor
PWM
-
Wi-Fi®
HTTPS
MAC
TLS/SSL
Baseband
TCP/IP
Radio
Internet
UART
ADC
Internet
256KB RAM
OEM
Application
Serial Flash
OEM
Application
Data Files
Network Information
Figure 9-1. CC3220R High-Level Structure
60
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Figure 9-2 shows the high-level structure of the CC3220S and CC3220SF devices. The application image, user
data, and network information files (passwords, certificates) are encrypted using a device-specific key.
CC3220S and CC3220SF
Network Processor + MCU
MCU
Peripherals
SPI and I2C
GPIO
UART
®
Network Processor
®
Arm Cortex -M4
Processor
256KB RAM /
1MB Flash (CC3220SF)
PWM
ADC
OEM
Application
-
Internet
Wi-Fi®
HTTPS
MAC
TLS/SSL
Baseband
TCP/IP
Radio
Internet
Serial Flash
OEM
Application
Data Files
Network Information
Figure 9-2. CC3220S and CC3220SF High-Level Structure
9.4 Power-Management Subsystem
The CC3220x power-management subsystem contains DC/DC converters to accommodate the different voltage
or current requirements of the system.
•
•
•
•
Digital DC/DC (Pin 44)
– Input: VBAT wide voltage (2.1 to 3.6 V) or preregulated 1.85 V
ANA1 DC/DC (Pin 37)
– Input: VBAT wide voltage (2.1 to 3.6 V)
– In preregulated 1.85-V mode, the ANA1 DC/DC converter is bypassed.
PA DC/DC (Pin 39)
– Input: VBAT wide voltage (2.1 to 3.6 V)
– In preregulated 1.85-V mode, the PA DC/DC converter is bypassed.
ANA2 DC/DC (Pin 47)
– Input: VBAT wide voltage (2.1 to 3.6 V) or preregulated 1.85 V
The CC3220x device is a single-chip WLAN radio solution used on an embedded system with a wide-voltage
supply range. The internal power management, including DC/DC converters and LDOs, generates all of the
voltages required for the device to operate from a wide variety of input sources. For maximum flexibility, the
device can operate in the modes described in Section 9.4.1 and Section 9.4.2.
9.4.1 VBAT Wide-Voltage Connection
In the wide-voltage battery connection, the device is powered directly by the battery or preregulated 3.3-V
supply. All other voltages required to operate the device are generated internally by the DC/DC converters. This
scheme supports wide-voltage operation from 2.1 to 3.6 V and is thus the most common mode for the device.
9.4.2 Preregulated 1.85-V Connection
The preregulated 1.85-V mode of operation applies an external regulated 1.85 V directly at pins 10, 25, 33, 36,
37, 39, 44, 48, and 54 of the device. The VBAT and the VIO are also connected to the 1.85-V supply. This mode
provides the lowest BOM count version in which inductors used for PA DC/DC and ANA1 DC/DC (2.2 and 1 µH)
and a capacitor (22 µF) can be avoided.
In the preregulated 1.85-V mode, the regulator providing the 1.85 V must have the following characteristics:
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•
•
Load current capacity ≥900 mA
Line and load regulation with
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