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CD4013B
SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
CD4013B CMOS Dual D-Type Flip-Flop
1 Features
3 Description
•
•
•
The CD4013B device consists of two identical,
independent data-type flip-flops. Each flip-flop has
independent data, set, reset, and clock inputs and Q
and Q outputs. These devices can be used for shift
register applications, and, by connecting Q output to
the data input, for counter and toggle applications.
The logic level present at the D input is transferred to
the Q output during the positive-going transition of the
clock pulse. Setting or resetting is independent of the
clock and is accomplished by a high level on the set
or reset line, respectively.
1
•
•
•
Asynchronous Set-Reset Capability
Static Flip-Flop Operation
Medium-Speed Operation: 16 MHz (Typical) Clock
Toggle Rate at 10-V Supply
Standardized Symmetrical Output Characteristics
Maximum Input Current Of 1-µA at 18 V Over Full
Package Temperature Range:
– 100 nA at 18 V and 25°C
Noise Margin (Over Full Package Temperature
Range):
– 1 V at VDD = 5 V
– 2 V at VDD = 10 V
– 2.5 V at VDD = 15 V
The CD4013B types are supplied in 14-pin dual-inline plastic packages (E suffix), 14-pin small-outline
packages (M, MT, M96, and NSR suffixes), and
14-pin thin shrink small-outline packages (PW and
PWR suffixes).
2 Applications
•
•
•
•
•
•
•
Device Information(1)
PART NUMBER
Power Delivery
Grid Infrastructure
Medical, Healthcare, and Fitness
Body Electronics and Lighting
Building Automation
Telecom Infrastructure
Test and Measurement
PACKAGE
BODY SIZE (NOM)
CD4013BE
PDIP (14)
19.30 mm x 6.35 mm
CD4013BF
CDIP (14)
19.50 mm x 6.92 mm
CD4013BM
SOIC (14)
8.65 mm x 3.90 mm
CD4013BNS
SO (14)
10.20 mm x 5.30 mm
CD4013BPW
TSSOP (14)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram
4 (10)
RESET
MASTER SECTION
CL
All inputs are protected by
CMOS protection network
SLAVE SECTION
CL
VDD
p
5 (9)
DATA
p
TG
TG
n
n
CL
CL
CL
p
CL
p
TG
TG
n
n
CL
VSS
CL
6 (8)
SET
Q
1 (13)
CL
CL
Buffered Outputs
3 (11)
CL
Q
2 (12)
VDD = Pin 14
VSS = Pin 7
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD4013B
SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: Static................................
Electrical Characteristics: Dynamic...........................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................ 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description ................................................ 10
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application .................................................. 11
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................ 12
10.2 Layout Example .................................................... 12
11 Device and Documentation Support ................. 14
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
14
12 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
Changes from Revision D (March 2005) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added Thermal Information table ........................................................................................................................................... 5
2
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SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
5 Pin Configuration and Functions
D, J, N, NS, PW Package
14-Pin SOIC, CDIP, PDIP, SO, TSSOP
Top View
Q1
1
14
VDD
Q1
2
13
Q2
CLOCK1
3
12
Q2
RESET1
4
11
CLOCK2
D1
5
10
RESET2
SET1
6
9
D2
VSS
7
8
SET2
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
Q1
O
Channel 1 output
2
Q1
O
Inverted channel 1 output
3
CLOCK1
I
Channel 1 clock input
4
RESET1
I
Channel 1 reset
5
D1
I
Channel 1 data input
6
SET1
I
Channel 1 set
7
VSS
—
8
SET2
I
Channel 2 set
9
D2
I
Channel 2 data input
10
RESET2
I
Channel 2 reset
11
CLOCK2
I
Channel 2 clock input
12
Q2
O
Inverted channel 2 output
13
Q2
O
Channel 2 output
14
VDD
—
Power supply
Ground
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CD4013B
SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
DC supply voltage, VDD (2)
–0.5
20
V
Input voltage, all inputs
–0.5
VDD + 0.5
V
10
mA
DC input current, any one input
TA = –55°C to 100°C
Power dissipation, PD
TA = 100°C to 125°C
500
(3)
mW
200
Device dissipation per output transistor
100
mW
Operating temperature, TA
–55
125
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltages reference to VSS terminal
Derate linearity at 12 mW/°C
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
tS
Data setup time
tW
Clock pulse width
fCL
Clock input frequency
trCL (1)
tfCL
tW
(1)
4
Clock rise or fall time
Set or reset pulse width
TYP
3
VDD = 5
40
VDD = 10
20
VDD = 15
15
VDD = 5
140
VDD = 10
60
MAX
18
ns
40
VDD = 5
3.5
7
VDD = 10
8
16
VDD = 15
12
24
MHz
VDD = 5
15
VDD = 10
10
VDD = 15
5
180
VDD = 10
80
VDD = 15
50
V
ns
VDD = 15
VDD = 5
UNIT
µs
ns
If more than one unit is cascaded in a parallel clocked operation, trCL must be made less than or equal to the sum of the fixed
propagation delay time at 15 pF and the transistion time of the output driving stage for the estimated capacitive load.
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6.4 Thermal Information
CD4013B
THERMAL METRIC (1)
N (PDIP)
D (SOIC)
NS (SO)
PW (TSSOP)
14 PINS
14 PINS
14 PINS
14 PINS
47.1
92.5
89.3
121
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
34.5
54
47.1
49.6
°C/W
RθJB
Junction-to-board thermal resistance
27.1
46.8
48
62.7
°C/W
ψJT
Junction-to-top characterization parameter
19.4
19
17
5.9
°C/W
ψJB
Junction-to-board characterization parameter
27
46.5
47.7
62.1
°C/W
RθJA
(1)
Junction-to-ambient thermal resistance
UNIT
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics: Static
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
TA = –55°C
VIN = 0 or 10, VDD = 10
IDDmax
Quiescent device current
TA = 25°C
1
0.02
30
TA = 125°C
30
TA = –55°C
2
TA = –40°C
2
0.02
VIN = 0 or 20, VDD = 20
2
TA = 85°C
60
TA = 125°C
60
TA = –55°C
4
TA = –40°C
VIN = 0 or 15, VDD = 15
1
TA = 85°C
TA = 25°C
TA = 25°C
4
120
TA = 125°C
120
TA = –55°C
20
TA = –40°C
20
0.04
20
TA = 85°C
600
TA = 125°C
600
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µA
4
0.02
TA = 85°C
TA = 25°C
UNIT
1
TA = –40°C
VIN = 0 or 5, VDD = 5
MAX
5
CD4013B
SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
www.ti.com
Electrical Characteristics: Static (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VO = 0.4, VIN = 0 or 5,
VDD = 5
IOLmin
Output low (sink) current
VO = 0.5, VIN = 0 or 10,
VDD = 10
MIN
TA = –55°C
0.64
TA = –40°C
0.61
TA = 25°C
0.51
TA = 85°C
0.42
TA = 125°C
0.36
TA = –55°C
1.6
TA = –40°C
1.5
TA = 25°C
1.3
TA = 85°C
1.1
TA = 125°C
0.9
TA = –55°C
4.2
TA = –40°C
VO = 1.5, VIN = 0 or 15,
VDD = 15
VO = 4.6, VIN = 0 or 5,
VDD = 5
VO = 2.5, VIN = 0 or 5,
VDD = 5
Output high (source)
current
IOHmin
VO = 9.5, VIN = 0 or 10,
VDD = 10
3.4
TA = 85°C
2.8
TA = 125°C
2.4
TA = –55°C
–0.64
TA = –40°C
–0.61
TA = 25°C
–0.51
TA = 85°C
–0.42
TA = 125°C
–0.36
TA = –55°C
–2
TA = –40°C
–1.8
TA = 25°C
–1.6
TA = 85°C
–1.3
TA = 125°C
–1.15
TA = –55°C
–1.6
TA = –40°C
–1.5
TA = 25°C
–1.3
TA = 85°C
–1.1
TA = 125°C
–0.9
TA = –55°C
–4.2
–3.4
6
High-level output voltage
1
2.6
mA
6.8
–1
–3.2
mA
–2.6
–6.8
–2.8
TA = 125°C
VOHmin
–2.4
VIN = 0 or 5, VDD = 5
TA = –55°C, –40°C,
25°C, 85°C, and 125°C
0
0.05
VIN = 0 or 10, VDD = 10
TA = –55°C, –40°C,
25°C, 85°C, and 125°C
0
0.05
VIN = 0 or 15, VDD = 15
TA = –55°C, –40°C,
25°C, 85°C, and 125°C
0
0.05
VIN = 0 or 5, VDD = 5
TA = –55°C, –40°C,
25°C, 85°C, and 125°C
4.95
5
VIN = 0 or 10, VDD = 10
TA = –55°C, –40°C,
25°C, 85°C, and 125°C
9.95
10
VIN = 0 or 15, VDD = 15
TA = –55°C, –40°C,
25°C, 85°C, and 125°C
14.95
15
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UNIT
–4
VO = 13.5, VIN = 0 or 15,
TA = 25°C
VDD = 15
TA = 85°C
Low-level output voltage
MAX
4
TA = 25°C
TA = –40°C
VOLmax
TYP
V
V
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Electrical Characteristics: Static (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VILmax
VIHmin
Input low voltage
Input high voltage
TEST CONDITIONS
MIN
TYP
VO = 0.5 or 4.5, VDD = 5
TA = –55°C, –40°C,
25°C, 85°C, and 125°C
1.5
VO = 1 or 9, VDD = 10
TA = –55°C, –40°C,
25°C, 85°C, and 125°C
3
VO = 1.5 or 13.5,
VDD = 15
TA = –55°C, –40°C,
25°C, 85°C, and 125°C
4
VO = 0.5 or 4.5, VDD = 5
TA = –55°C, –40°C,
25°C, 85°C, and 125°C
3.5
VO = 1 or 9, VDD = 10
TA = –55°C, –40°C,
25°C, 85°C, and 125°C
7
VO = 1.5 or 13.5,
VDD = 15
TA = –55°C, –40°C,
25°C, 85°C, and 125°C
11
VIN = 0 or 18, VDD = 18
V
±0.1
TA = –40°C
Input current
UNIT
V
TA = –55°C
IINmax
MAX
±0.1
–5
TA = 25°C
±10
±0.1
TA = 85°C
±1
TA = 125°C
±1
µA
6.6 Electrical Characteristics: Dynamic
at TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, RL = 20 kΩ (unless otherwise noted)
PARAMETER
tPHL,
tPLH
tPLH
Propagation delay time,
clock to Q or Q outputs
Set to Q or reset to Q
tPHL
Set to Q or reset to Q
tTHL,
tTLH
Transition time
TYP
MAX
VDD = 5
TEST CONDITIONS
150
300
VDD = 10
65
130
VDD = 15
45
90
VDD = 5
150
300
VDD = 10
65
130
VDD = 15
45
90
VDD = 5
200
400
VDD = 10
85
170
VDD = 15
60
120
VDD = 5
100
200
VDD = 10
50
100
VDD = 15
40
80
VDD = 5
fCL
Maximum clock input frequency (1)
Minimum clock pulse width
tW
Minimum set or reset pulse width
tS
tH
(1)
Minimum data setup time
Minimum data hold time
MIN
3.5
7
VDD = 10
8
16
VDD = 15
12
24
UNIT
ns
ns
ns
ns
MHz
VDD = 5
70
140
VDD = 10
30
60
VDD = 15
20
40
VDD = 5
90
180
VDD = 10
40
80
VDD = 15
25
50
VDD = 5
20
40
VDD = 10
10
20
VDD = 15
7
15
VDD = 5, 10, 15
2
5
ns
ns
ns
ns
Input tr, tf = 5 ns
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CD4013B
SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
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Electrical Characteristics: Dynamic (continued)
at TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, RL = 20 kΩ (unless otherwise noted)
PARAMETER
trCL,
tfCL
TEST CONDITIONS
Clock input rise or fall time
CIN
Input capacitance
MIN
TYP
MAX
VDD = 5
15
VDD = 10
10
VDD = 15
5
Any input
5
UNIT
7.5
µs
pF
6.7 Typical Characteristics
20
Gate-to-Source Voltage = 5 V
Gate-to-Source Voltage = 10 V
Gate-to-Source Voltage = 15 V
35
Output Low (Sink) Current (mA)
Output Low (Sink) Current (mA)
40
30
25
20
15
10
5
Gate-to-Source Voltage = 5 V
Gate-to-Source Voltage = 10 V
Gate-to-Source Voltage = 15 V
17.5
15
12.5
10
7.5
5
2.5
0
0
0
5
10
15
Drain-to-Source Voltage (V)
20
0
25
Figure 1. Typical Output Low (Sink) Current
Output High (Source) Current (mA)
Output High (Source) Current (mA)
-15
-20
-25
-30
-35
-20
-15
-10
Drain-to-Source Voltage (V)
-5
0
25
D002
Gate-to-Source Voltage = -5 V
Gate-to-Source Voltage = -10 V
Gate-to-Source Voltage = -15 V
-5
-10
-15
-20
-25
D003
Figure 3. Typical Output High (Source) Current
8
20
0
Gate-to-Source Voltage = -5 V
Gate-to-Source Voltage = -10 V
Gate-to-Source Voltage = -15 V
-10
-40
-25
10
15
Drain-to-Source Voltage (V)
Figure 2. Minimum Output Low (Sink) Current
0
-5
5
D001
-20
-15
-10
Drain-to-Source Voltage (V)
-5
0
D004
Figure 4. Minimum Output High (Source) Current
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Typical Characteristics (continued)
300
Supply Voltage = 5 V
Supply Voltage = 10 V
Supply Voltage = 15 V
250
Propagation Delay Time (ns)
Propagation Delay Time (ns)
300
200
150
100
50
250
200
150
100
50
0
0
0
20
40
60
Load Capacitance (pF)
80
100
0
20
D023
CLOCK or SET to Q, CLOCK or RESET to Q
Figure 5. Typical Propagation Delay Time
vs Load Capacitance
40
60
Load Capacitance (pF)
80
100
D024
SET to Q or RESET to Q
Figure 6. Typical Propagation Delay Time
vs Load Capacitance
10k
35
30
25
20
15
10
5
0
0
5
10
15
Supply Voltage (V)
20
25
1k
e
Power Dissipation Per Device (PW)
40
Clock Frequency (MHz)
Supply Voltage = 5 V
Supply Voltage = 10 V
Supply Voltage = 15 V
100
10
Supply Voltage = 5 V
Supply Voltage = 10 V (CL = 15 pF)
Supply Voltage = 10 V (CL = 50 pF)
Supply Voltage = 15 V
1
100
D025
Figure 7. Typical Maximum Clock Frequency
vs Supply Voltage
1k
10k
100k
Input Clock Frequency (kHz)
1M
10M
D026
Figure 8. Typical Power Dissipation vs Frequency
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CD4013B
SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
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7 Detailed Description
7.1 Overview
The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent
data, set, reset, and clock inputs and Q and Q outputs. These devices are ideal for data and memory hold
functions, including shift register applications, or by connecting Q output to the data input, this device is used for
counter and toggle applications. The CD4013B is a positive-edge triggered device, meaning that the logic level
present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting
or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively.
7.2 Functional Block Diagram
VDD
6
SET1
5
D1
3
CLOCK1
F/F2
13
Q1
Q1
8
SET2
9
D2
RESET2
1
4
RESET1
CLOCK2
2
F/F1
11
12
Q2
Q2
10
VSS
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7.3 Feature Description
CD4013B has standardized symmetrical output characteristics and a wide operating voltage range from 3 V to
18 V with quiescent current tested at 20 V. This has a medium operation speed –tPHL, tPLH = 30 ns (typical) at 10
V. The operating temperature is from –55°C to 125°C.
7.4 Device Functional Modes
Table 1 lists the functional modes of the CD4013B.
Table 1. Function Table
INPUTS
10
OUTPUT (Q)
INVERTED OUTPUT (Q)
0
0
1
1
1
0
0
X
Q0
Q
0
1
X
0
1
1
0
X
1
0
1
1
X
1
1
CLOCK
SET
RESET
D
↑
0
0
↑
0
0
↓
0
X
X
X
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A high level at the SET or RESET inputs sets or resets the outputs, regardless of the levels of the other inputs.
When SET and RESET are inactive (low), data at the data (D) input meeting the setup time requirements is
transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level
and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input
can be changed without affecting the levels at the outputs. The resistor and capacitor at the RESET pin are
optional. If they are not used, the RESET and SET pin must be connected directly to ground to be inactive.
8.2 Typical Application
3V
3V
3V
NC
VCC
A
GND
Y
SN74LVC1G17
CLK
VCC
D
SET
Q RESET
GND
Q
TO MCU
CD4013B
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Figure 9. Power Button Circuit
8.2.1 Design Requirements
Input signals must be designed and implemented so that they do not exceed the voltage level of the power
supply.
8.2.2 Detailed Design Procedure
The recommended input conditions for this application example includes rise time and fall time specifications
(see Δt/ΔV in Recommended Operating Conditions) and specified high and low levels (see VIH and VIL in
Recommended Operating Conditions). Inputs are not overvoltage tolerant and must be below VCC level because
of the presence of input clamp diodes to VCC. The recommended output condition for the CD4013B application
includes specific load currents. Load currents must be limited so as to not exceed the total power (continuous
current through VCC or GND) for the device. These limits are located in Absolute Maximum Ratings. Outputs
must not be pulled above VCC.
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SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
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Typical Application (continued)
8.2.3 Application Curve
140
CL = 15 pF
CL = 50 pF
Propagation Delay Time (ns)
120
100
80
60
40
20
0
0
5
10
15
Supply Voltage (V)
20
25
D037
Figure 10. Typical Transition Time vs Load Capacitance
9 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions. Each VCC pin must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor. If there are multiple VCC pins,
then TI recommends a 0.01-μF or 0.022-μF capacitor for each power pin. It is acceptable to parallel multiple
bypass capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in
parallel. The bypass capacitor must be installed as close to the power pin as possible for best results.
10 Layout
10.1 Layout Guidelines
When using multiple bit logic devices, inputs must never float.
In many cases, digital logic device functions or parts of these functions are unused (for example, when only two
inputs of a triple-input and gate are used, or only 3 of the 4 buffer gates are used). Such input pins must not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. This rule must be observed under all circumstances specified in the next paragraph.
All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating.
See application note, Implications of Slow or Floating CMOS Inputs (SCBA004), for more information on the
effects of floating inputs. The logic level must apply to any particular unused input depending on the function of
the device. Generally, they are tied to GND or VCC (whichever is convenient).
10.2 Layout Example
VCC
Unused Input
Input
Output
Output
Unused Input
Input
Figure 11. Layout Example for CD4013B
12
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CD4013B
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SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016
Layout Example (continued)
Figure 12. Dimensions and Pad Layout for CD4013B
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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Product Folder Links: CD4013B
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
(1)
CD4013BE
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD4013BE
CD4013BEE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD4013BE
CD4013BF
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD4013BF
CD4013BF3A
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD4013BF3A
CD4013BM
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4013BM
CD4013BM96
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4013BM
CD4013BM96E4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4013BM
CD4013BM96G4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4013BM
CD4013BME4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4013BM
CD4013BMG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4013BM
CD4013BMT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4013BM
CD4013BNSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4013B
CD4013BPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM013B
CD4013BPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM013B
CD4013BPWRE4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM013B
CD4013BPWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM013B
JM38510/05151BCA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
05151BCA
M38510/05151BCA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
05151BCA
The marketing status values are defined as follows:
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2021
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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