CD74FCT843AM96G4

CD74FCT843A BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS727 – JULY 2000 D D D D D D D D D M PACKAGE (TOP VIEW) BiCMOS Technology With Low Quiescent Power Buffered Inputs Noninverted Outputs Input/Output Isolation From VCC Controlled Output Edge Rates 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V SCR Latch-Up-Resistant BiCMOS Process and Circuit Design Packaged in Plastic Small-Outline Package OE 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND description 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q PRE LE The CD74FCT843A is a 9-bit, bus-interface, D-type latch with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA. The CD74FCT843A outputs are transparent to the inputs when the latch-enable (LE) input is high. The latches are transparent D-type latches. When LE goes low, the data is latched. The output-enable (OE) input controls the 3-state outputs. When OE is high, the outputs are in the high-impedance state. The latch operation is independent of the state of the output enable. This device, having preset (PRE) and clear (CLR), are ideal for parity-bus interfacing. When PRE is low, the outputs are high if OE is low. PRE overrides CLR. When CLR is low, the outputs are low if OE is low. When CLR is high, data can be entered into the latch. The device provides noninverted outputs. OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. The CD74FCT843A is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each latch) INPUTS PRE CLR OE LE D OUTPUT Q L X L X X H H L L X X L H H L H L L H H L H H H H H L L X Q0 X X H X X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD74FCT843A BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS727 – JULY 2000 logic symbol† OE 1 EN 14 PRE 11 CLR LE 1D 2D 3D 4D 5D 6D 7D 8D 9D 13 2 S2 R C1 2 1D 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE PRE CLR LE 1 14 11 13 S2 C1 1D 2 1D R To Eight Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 1Q CD74FCT843A BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS727 – JULY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† DC supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V DC input clamp current, IIK (VI < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA DC output clamp current, IOK (VO < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA DC output sink current per output pin, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA DC output source current per output pin, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA Continuous current through VCC, (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 mA Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 mA Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 2) MIN MAX UNIT 4.75 5.25 V VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL ∆t/∆v High-level input voltage 2 V 0.8 V VCC VCC V High-level output current –15 mA Low-level output current 48 mA 10 ns/V Input transition rise or fall rate 0 V TA Operating free-air temperature 0 70 °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C MIN MAX MIN UNIT –1.2 V VIK VOH II = –18 mA IOH = –15 mA 4.75 V VOL II IOL = 48 mA VI = VCC or GND 4.75 V 0.55 0.55 V 5.25 V ±0.1 ±1 mA IOZ IOS‡ VO = VCC or GND VI = VCC or GND, 5.25 V ±0.5 ±10 mA ICC ∆ICC§ Ci Co 4.75 V VO = 0 VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND 5.25 V –1.2 MAX 2.4 2.4 –75 V –75 mA 5.25 V 8 80 mA 5.25 V 1.6 1.6 mA 10 10 pF 15 15 pF VI = VCC or GND VO = VCC or GND ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms. § This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CD74FCT843A BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS727 – JULY 2000 timing requirements over recommended operating temperature conditions (unless otherwise noted) (see Figure 1) MIN tw tsu th trec Pulse duration Setup time CLR low 8 PRE low 8 LE low 4 Data before LE↓ 2.5 MAX UNIT ns ns PRE inactive 1.4 CLR inactive 1.4 Hold time Data before LE↓ 2.5 ns Recovery time PRE, CLR 14 ns switching characteristics over recommended operating temperature conditions (unless otherwise noted) (see Figure 1) PARAMETER tpd d 4 FROM (INPUT) TO (OUTPUT) D LE Q TA = 25°C TYP MIN MAX 6.8 1.5 9 9 1.5 12 9 1.5 12 ns UNIT ns tPLH PRE Q tPHL CLR Q 9.8 1.5 13 ns 1.5 14 ns 1.5 8 ns ten OE Q 10.5 tdis OE Q 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD74FCT843A BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS727 – JULY 2000 PARAMETER MEASUREMENT INFORMATION 7V CL = 50 pF (see Note A) 500 Ω From Output Under Test Test Point From Output Under Test Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 S1 Open 7V Open 7V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω Open Drain LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 90% 1.5 V 10% 3V 1.5 V 10% 0 V 90% tr tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V 1.5 V Input th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 1.5 V Input 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ ≈3.5 V 1.5 V tPZH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V V VOH – 0.3 V OH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr and tf = 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) CD74FCT843AM ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74FCT843AM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of