CD74HCT652M96E4

CD74HC652, CD74HCT652 Data sheet acquired from Harris Semiconductor SCHS194A High-Speed CMOS Logic Octal-Bus Transceiver/Registers, Three-State February 1998 - Revised May 2003 Features Description • CD74HC652, CD74HCT652 . . . . . . . . . . . Non-Inverting The CD74HC652 and CD74HCT652 three-state, octal-bus transceiver/registers use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. The CD74HC652 and CD74HCT652 have non-inverting outputs. These devices consists of bus transceiver circuits, D-type flipflops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output Enables OEAB and OEBA are provided to control the transceiver functions. SAB and SBA control pins are provided to select whether real-time or stored data is transferred. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A LOW input level selects real-time data, and a HIGH selects stored data. The following examples demonstrates the four fundamentals bus-management functions that can be performed with the octal-bus transceivers and registers. •[ /Title Independent Registers for A and B Buses (CD74HC652, CD74HCT652) (High-Speed •/Subject Three-State Outputs CMOS Logic Octal-Bus Transceiver/Registers, • Drives 15 LSTTL Loads Three-State) /Author () • Typical Propagation Delay = 12ns at VCC = 5V, CL = 15pF /Keywords () • Fanout (Over /Creator () Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads /DOCINFO pdfmark - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads o oC Wide Operating Temperature Range . . . -55 C to 125 [• /PageMode /UseOutlines • Balanced Propagation /DOCVIEW pdfmark Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • Alternate Source is Philips Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (CAB or CBA) regardless of the select of the control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Ordering Information PART NUMBER Pinout CD74HC652 (PDIP) CD74HCT652 ( SOIC) TOP VIEW TEMP. RANGE (oC) CD74HC652EN -55 to 125 24 Ld PDIP CD74HCT652M -55 to 125 24 Ld SOIC CD74HCT652M96 -55 to 125 24 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. CAB 1 24 VCC SAB 2 23 CBA OEAB 3 22 SBA A0 4 21 OEBA A1 5 20 B0 A2 6 19 B1 A3 7 18 B2 A4 8 17 B3 A5 9 16 B4 A6 10 15 B5 A7 11 14 B6 GND 12 13 B7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated PACKAGE 1 CD74HC652, CD74HCT652 Functional Diagram A0 A1 A2 A DATA PORT A3 A4 A5 A6 A7 4 20 5 19 6 18 7 17 8 16 9 15 10 14 11 13 21 OEBA OEAB CAB CLOCK FLIP-FLOP CLOCKS DATA SOURCE SELECTION INPUTS CBA CLOCK SAB SOURCE SBA SOURCE B0 B1 B2 B3 B4 B DATA PORT B5 B6 B7 GND = PIN 12 VCC = PIN 24 3 1 23 2 22 FUNCTION TABLE INPUTS DATA I/O OPERATION OR FUNCTION OEAB OEBA CAB CBA SAB SBA A0 THRU A7 B0 THRU B7 651 652 L H H or L H or L X X Input Input Isolation (Note 1) Isolation (Note 1) L H ↑ ↑ X X Store A and B Data Store A and B Data X H ↑ H or L X X Input Unspecified (Note 2) Store A, Hold B Store A, Hold B H H ↑ ↑ X (Note 3) X Input Output Store A in Both Registers Store A in Both Registers L X H or L ↑ X X Unspecified (Note 2) Input Hold A, Store B Hold A, Store B L L ↑ ↑ X X (Note 3) Output Input Store B in Both Registers Store B in Both Registers L L X X X L Output Input L L X H or L X H H H X X L X H H H or L X H X H L H or L H or L H H Real-Time B Data to Real-Time B Data to A Bus A Bus Stored B Data to A Bus Input Output Output Output Stored B Data to A Bus Real-Time A Data to Real-Time A Data to B Bus B Bus Stored A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored A Data to B Bus Stored B Data to A Bus Stored B Data to A Bus NOTES: 1. To prevent excess currents in the High-Z (isolation) modes, all I/O terminals should be terminated with 10kΩ to 1MΩ resistors. 2. The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs. 3. Select Control = L: Clocks can occur simultaneously. Select Control = H: Clocks must be staggered in order to load both registers. 2 OEBA 21 VCC OEAB 3 SAB 2 TO CHANNELS 2 THRU 8 CD74HC652, CD74HCT652 SBA 3 FIGURE 1. LOGIC BLOCK DIAGRAM 22 CAB 1 CBA 23 VCC † P CK D F/F A Q 4, (5, 6, 7, 8, 9, 10, 11) N VCC GND P † B N GND P N 24 VCC 12 GND P N P N F/F P N † Inverter not included in HC/HCT651 ONE OF EIGHT IDENTICAL CHANNELS 20, (19, 18, 17, 16, 15, 14, 13) CD74HC652, CD74HCT652 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC (Voltages Referenced to Ground) . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical) θJA (oC/W) EN (PDIP) Package (Note 4) . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package (Note 5). . . . . . . . . . . . . . . . . . . 46 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 4. The package thermal impedance is calculated in accordance with JESD 51-3. 5. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) VIS (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS VIH - - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.3 - 0.3 - 0.3 V 4.5 - - 0.9 - 0.9 - 0.9 V 6 - - 1.2 - 1.2 - 1.2 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -6 4.5 3.98 - - 3.84 - 3.7 - V -7.8 6 5.48 - - 5.34 - 5.2 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads VOL VIH or VIL - 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 6 4.5 - - 0.26 - 0.33 - 0.4 V 7.8 6 - - 0.26 - 0.33 - 0.4 V 4 CD74HC652, CD74HCT652 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) VIS (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA VIL or VIH VO = VCC or GND - 6 - - ±0.5 - ±5.0 - ±10 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -6 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA PARAMETER Input Leakage Current Quiescent Device Current Three- State Leakage Current HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current II VCC and GND 0 5.5 - ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Three- State Leakage Current VIL or VIH VO = VCC or GND - 5.5 - - ±0.5 - ±5.0 - ±10 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load ∆ICC (Note 6) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Quiescent Device Current NOTE: 6. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS OEBA 1.3 OEAB 0.75 Clock A to B, B to A 0.6 Select A, Select B 0.45 Inputs A0-A7, B0-B7 0.3 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 5 CD74HC652, CD74HCT652 Prerequisite for Switching Specifications 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS fMAX 2 6 - - 5 - - 4 - - MHz 4.5 30 - - 25 - - 20 - - MHz 6 35 - - 29 - - 23 - - MHz 2 60 - - 75 - - 90 - - ns 4.5 12 - - 15 - - 18 - - ns 6 10 - - 13 - - 15 - - ns 2 35 - - 45 - - 55 - - ns 4.5 7 - - 9 - - 11 - - ns 6 6 - - 8 - - 9 - - ns 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns fMAX 4.5 25 - - 20 - - 17 - - MHz Setup Time Data to Clock tSU 4.5 12 - - 15 - - 18 - - ns Hold Time Data to Clock tH 4.5 5 - - 5 - - 5 - - ns Clock Pulse Width tW 4.5 25 - - 31 - - 38 - - ns HC TYPES Maximum Clock Frequency Setup Time Data to Clock Hold Time Data to Clock Clock Pulse Width tSU tH tW HCT TYPES Maximum Clock Frequency Switching Specifications Input tr, tf = 6ns PARAMETER SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF VCC (V) 25oC MIN -40oC TO 85oC -55oC TO 125oC TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay, Store A Data to B Bus Store B Data to A Bus Propagation Delay, A Data to B Bus B Data to A Bus tPLH, tPHL 2 - - 220 - 275 - 300 ns 4.5 - - 44 - 55 - 66 ns 6 - - 37 - 47 - 5.6 ns CL = 15pF 5 - 18 - - - - - ns CL = 50pF 2 - - 135 - 170 - 205 ns 4.5 - - 27 - 34 - 41 ns 6 - - 23 - 29 - 35 ns 5 - 12 - - - - - ns CL = 15pF Propagation Delay, Select to Data tPLH, tPHL CL = 50pF CL = 15pF 2 - - 170 - 215 - 255 ns 4.5 - - 34 - 43 - 51 ns 6 - - 29 - 37 - 43 ns 5 - 14 - - - - - ns 6 CD74HC652, CD74HCT652 Switching Specifications Input tr, tf = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS Three-State Disabling Time Bus to Output or Register to Output tPLZ, tPHZ CL = 50pF Three-State Enabling Time Bus to Output or Register to Output Output Transition Time tPZL, tPZH tTLH, tTHL 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns 6 - - 30 - 37 - 45 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns 6 - - 30 - 37 - 45 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 2 - - 60 - 75 - 90 ns 4.5 - - 12 - 15 - 18 ns 6 - - 10 - 13 - 15 ns Three-State Output Capacitance CO - - - - 20 - 20 - 20 pF Input Capacitance CI - - - - 10 - 10 - 10 pF Maximum Frequency fMAX CL = 15pF 5 - 60 - - - - - MHz Power Dissipation Capacitance (Notes 7, 8) CPD - 5 - 52 - - - - - pF Propagation Delay, Store A Data to B Bus Store B Data to A Bus tPLH, tPHL CL = 50pF 4.5 - - 44 - 55 - 66 ns CL = 15pF 5 - 18 - - - - - ns Propagation Delay, A Data to B Bus B Data to A Bus tPLH, tPHL CL = 50pF 4.5 - - 37 - 46 - 56 ns CL = 15pF 5 - 15 - - - - - ns Propagation Delay, Select to Data tPLH, tPHL CL = 50pF 4.5 - - 46 - 58 - 69 ns CL = 15pF 5 - 19 - - - - - ns Three-State Disabling Time Bus to Output or Register to Output tPLZ, tPHZ CL = 50pF 4.5 - - 35 - 44 - 53 ns Three-State Enabling Time Bus to Output or Register to Output tPZL, tPZH Output Transition Time HCT TYPES CL = 15pF 5 - 14 - - - - - ns CL = 50pF 4.5 - - 45 - 56 - 68 ns CL = 15pF 5 - 19 - - - - - ns tTLH, tTHL CL = 50pF 4.5 - - 12 - 15 - 18 ns Three-State Output Capacitance CO - - - - 20 - 20 - 20 pF Input Capacitance CI - - - - 10 - 10 - 10 pF Maximum Frequency fMAX CL = 15pF 5 - 45 - - - - - MHz Power Dissipation Capacitance (Notes 7, 8) CPD - 5 - 52 - - - - - pF NOTES: 7. CPD is used to determine the dynamic power consumption, per package. 8. PD = VCC2 CPD fi + Σ VCC2 CL fo where fi = input frequency, fo = output frequency, CL = output load capacitance, CS = switch capacitance, VCC = supply voltage. 7 CD74HC652, CD74HCT652 Test Circuits and Waveforms tfCL trCL CLOCK tWL + tWH = 90% 10% I fCL CLOCK 50% 50% tfCL = 6ns 2.7V 1.3V 0.3V 0.3V GND 1.3V 1.3V GND tWH tWL tWH tWL I fCL 3V VCC 50% 10% tWL + tWH = trCL = 6ns NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tr = 6ns tf = 6ns VCC 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 4. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 8 CD74HC652, CD74HCT652 Test Circuits and Waveforms (Continued) trCL tfCL trCL VCC 90% CLOCK INPUT GND tH(H) 3V 2.7V CLOCK INPUT 50% 10% tfCL 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT 3V DATA INPUT 50% tH(L) 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH tTHL 90% 50% 10% 90% OUTPUT tREM VCC SET, RESET OR PRESET tTLH OUTPUT tREM 3V SET, RESET OR PRESET GND 6ns tr VCC 10% OUTPUTS ENABLED OUTPUT LOW TO OFF FIGURE 8. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% OUTPUT HIGH TO OFF 50% 3V tPZL tPHZ tPZH 90% OUTPUTS DISABLED 6ns 2.7 1.3 tPLZ 10% tPHZ tf GND 50% OUTPUT HIGH TO OFF 6ns OUTPUT DISABLE tPZL tPLZ CL 50pF FIGURE 7. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6ns OUTPUT LOW TO OFF GND IC 90% 50% tPHL 1.3V CL 50pF FIGURE 6. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS OUTPUT DISABLE 1.3V 10% tPLH 50% IC tTHL 90% 90% 1.3V tPHL tPLH GND tSU(L) 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 9. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 10. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 9 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty CD74HCT652M ACTIVE SOIC DW 24 25 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 Device Marking (4/5) CD74HCT652M96 OBSOLETE SOIC DW 24 TBD Call TI Call TI -55 to 125 CD74HCT652M96E4 OBSOLETE SOIC DW 24 TBD Call TI Call TI -55 to 125 CD74HCT652M96G4 OBSOLETE SOIC DW 24 TBD Call TI Call TI -55 to 125 HCT652M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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