CDCE421
www.ti.com..................................................................................................................................................... SCAS842B – APRIL 2007 – REVISED JANUARY 2009
Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator
•
FEATURES
1
• Single 3.3-V Supply
• High-Performance Clock Generator
Incorporating Crystal-Oscillator Circuitry With
Integrated Frequency Synthesizer
• Low-Output Jitter: As Low as 380 fs (rms
Integrated Between 10 kHz–20 MHz)
• Low Phase Noise at High Frequency: at 708
MHz it is less than –109 dBc/Hz at 10-kHz and
–146 dBc/Hz at 10-MHz Offset from the Carrier
• Supports Crystal Frequencies Between
27.35 MHz to 38.33 MHz
• Output Frequency Ranges from 10.9 MHz up to
766.7 MHz and from 875.2 MHz up to 1175 MHz
• Low-Voltage Differential Signaling (LVDS)
Output, 100-Ω Differential Off-Chip
Termination, 10.9-MHz to 400-MHz Frequency
Range
2
•
•
•
•
•
•
•
•
•
Differential Low-Voltage Positive
Emitter-Coupled Logic (LVPECL) Output,
10.9-MHz to 1.175-GHz Frequency Range
Two Fully Integrated Voltage-Controlled
Oscillators (VCOs) Support Wide Output
Frequency Range
Fully Integrated Programmable Loop Filter
Typical Power Consumption: 274 mW in LVDS
Mode and 250 mW in LVPECL Mode
Chip-Enable Control Pin
Simple Serial Interface Allows Programming
After Manufacturing
Integrated On-Chip Nonvolatile Memory
(EEPROM) to Store Settings Without the Need
to Apply High Voltage to the Device
QFN24 Package
ESD Protection Exceeds 2 kV HBM
Industrial Temperature Range: –40°C to +85°C
APPLICATIONS
•
CE
Low-Cost, High-Frequency Crystal Oscillator
SDATA
Output Enable/Programming Interface and EEPROM for Configuration Settings
LVPECL or LVDS
Feedback
Divider
VCO 1
Output Divider
X-tal
Prescaler
Crystal
Oscillator
Input
PFD/Charge Pump
Loop Filter
CLK
NCLK
VCO 2
B0216-01
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
CDCE421
SCAS842B – APRIL 2007 – REVISED JANUARY 2009..................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The CDCE421 is a high-performance, low-phase-noise clock generator. It has two fully integrated, low-noise,
LC-based voltage controlled oscillators (VCOs) that operate in the 1.750-GHz to 2.350-GHz frequency range. It
has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a
stable frequency reference for the PLL-based frequency synthesizer.
The output frequency (fout) is proportional to the frequency of the input crystal (fxtal). The prescaler divider,
feedback divider, output divider, and VCO selection are what set (fout) with respect to (fxtal). For a desired
frequency (fout), look in Table 1 and find the corresponding settings in the same row. Use Equation 1 to calculate
the exact crystal oscillator frequency needed for the desired output.
f xtal +
OutputDivider
ǒFeedbackDivider
Ǔ
(1)
Output divider
f out
(1)
= 1, 2, 4, 8, 16, or 32
Feedback divider(2) = 12, 16, 20, or 32
(1)
Output divider and feedback divider should be from the same row in Table 1.
(2)
Feedback divider is set automatically with respect to the prescaler setting in Table 1.
A high-level block diagram of the CDCE421 is shown in Figure 1.
The CDCE421 supports one differential LVDS clock output or one differential LVPECL output.
All device settings are programmable through a Texas Instruments proprietary simple serial interface.
The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to +85°C.
The CDCE421 is available in a QFN-24 package.
XIN 1
XIN 2
Crystal
Oscillator
Loop Filter
PFD/
Charge Pump
VCO 1
1890
VCO 2
2200
Feedback
Divider
12, 16, 20 and 32
LVPCL
Prescaler
2, 3, 4 and 5
CE
1-Pin
Interface
and
Control
LVDS
EEPROM
Output
Divider
1, 2, 4, 8, 16 and 32
SDATA
B0217-01
Figure 1. High-Level Block Diagram of the CDCE421
In the CDCE421, the feedback divider is set automatically with respect to the prescaler setting. The product of
the prescaler and the feedback divider will be either 60 or 64, as shown in Table 1, to keep the control loop
stable.
2
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DEVICE SETUP AND CONFIGURATION
Table 1. Crystal Frequency Selection and Device Settings
DESIRED OUTPUT
FREQUENCY (MHz)
VCO
SELECTION
OUTPUT
DIVIDER
PRESCALER
SETTING
FEEDBACK
DIVIDER (1)
From
To
From
To
1020.0
1175.0
31.875
36.719
VCO 2
1
2
32
1020.0
27.351
31.875
VCO 1
1
2
32
875.2
(2)
650.0
(1)
(2)
REQUIRED INPUT
CRYSTAL
FREQUENCY (MHz)
766.7
(2)
32.500
38.333
VCO 2
1
3
20
583.5
650.0
29.174
32.500
VCO 1
1
3
20
510.0
587.5
31.875
36.719
VCO 2
1
4
16
437.6
510.0
27.351
31.875
VCO 1
1
4
16
408.0
460.0
34.000
38.333
VCO 2
1
5
12
350.1
408.0
29.174
34.000
VCO 1
1
5
12
340.0
383.3
34.000
38.333
VCO 2
2
3
20
291.7
340.0
29.174
34.000
VCO 1
2
3
20
255.0
293.8
31.875
36.719
VCO 2
2
4
16
218.8
255.0
27.351
31.875
VCO 1
2
4
16
204.0
230.0
34.000
38.333
VCO 2
2
5
12
175.0
204.0
29.174
34.000
VCO 1
2
5
12
170.0
191.7
34.000
38.333
VCO 2
4
3
20
145.9
170.0
29.174
34.000
VCO 1
4
3
20
127.5
146.9
31.875
36.719
VCO 2
4
4
16
109.4
127.5
27.351
31.875
VCO 1
4
4
16
102.0
115.0
34.000
38.333
VCO 2
4
5
12
87.5
102.0
29.174
34.000
VCO 1
4
5
12
85.0
95.8
34.000
38.333
VCO 2
8
3
20
72.9
85.0
29.174
34.000
VCO 1
8
3
20
63.8
73.4
31.875
36.719
VCO 2
8
4
16
54.7
63.8
27.351
31.875
VCO 1
8
4
16
51.0
57.5
34.000
38.333
VCO 2
8
5
12
43.8
51.0
29.174
34.000
VCO 1
8
5
12
42.5
47.9
34.000
38.333
VCO 2
16
3
20
36.5
42.5
29.174
34.000
VCO 1
16
3
20
31.9
36.7
31.875
36.719
VCO 2
16
4
16
27.4
31.9
27.351
31.875
VCO 1
16
4
16
25.5
28.8
34.000
38.333
VCO 2
16
5
12
21.9
25.5
29.174
34.000
VCO 1
16
5
12
21.3
24.0
34.000
38.333
VCO 2
32
3
20
18.2
21.3
29.174
34.000
VCO 1
32
3
20
15.9
18.4
31.875
36.719
VCO 2
32
4
16
13.7
15.9
27.351
31.875
VCO 1
32
4
16
12.8
14.4
34.000
38.333
VCO 2
32
5
12
10.9
12.8
29.174
34.000
VCO 1
32
5
12
The feedback divider is set automatically with respect to the prescaler setting.
Discontinuity in frequency range.
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DEVICE SETUP EXAMPLE
The following example illustrates the procedure to calculate the required AT-cut crystal frequency needed to
generate a desired output frequency.
Assuming the requirement to generate an output frequency of 622.08 MHz, Table 1 shows that the desired
output frequency lies between 583.5 MHz and 680 MHz.
DESIRED OUTPUT
FREQUENCY (MHz)
(1)
REQUIRED INPUT
CRYSTAL
FREQUENCY (MHz)
VCO
SELECTION
OUTPUT
DIVIDER
PRESCALER
SETTING
FEEDBACK
DIVIDER (1)
From
To
From
To
650.0
766.7
32.500
38.333
VCO 2
1
3
20
583.5
650.0
29.174
32.500
VCO 1
1
3
20
510.0
587.5
31.875
36.719
VCO 2
1
4
16
The feedback divider is set automatically with respect to the prescaler setting.
So this means that the device must be configured with:
VCO = VCO 1
Output divider = 1
Prescaler setting = 3
To determine the correct crystal frequency needed to get 622.08 MHz with these settings, substitute values into
Equation 1.
f xtal +
OutputDivider
ǒFeedbackDivider
Ǔ
f out
f xtal +
ǒ201 Ǔ
622.08 + 31.154 MHz
(2)
The AT-cut frequency should be 31.154 MHz (between 29.174 MHz and 32.500 MHz, as shown in Table 1) .
SERIAL INTERFACE AND CONTROL
The CDCE421 uses a unique Texas Instruments proprietary interface protocol that can be configured and
programmed via a single input pin to the device. The architecture enables only writing to the device from this
input pin. Reading the content of a register can be achieved by sending a read command on the input pin and
monitoring the output pins (LVDS or LVPECL). In cases where the output pins cannot be used to read the
content, the software controlling the interface must account for what is written to the EEPROM and when it is
programmed. Monitoring the outputs verifies the programming modes, and cycling power on the device verifies
that the EEPROM is holding the proper configuration.
The CDCE421 can be configured and programmed via the SDATA input pin. For this purpose, a square-wave
programming sequence must be written to the device as described in the following section. During the EEPROM
programming phase, the device requires a stable VCC of 3 V to 3.6 V for secure writing of the EEPROM cells.
After each Write to WordX, the written data are latched, made effective, and offer look-ahead before the actual
data are stored into the EEPROM.
The following table summarizes all valid programming commands.
SDATA
FUNCTION
00 1100
Enter Programming Mode (State 1 → State 2); bits must be sent in the specified order with the specified timing.
Otherwise, a time-out occurs.
11 1011
Enter Register Read Back Mode; bits must be sent in the specified order with the specified timing. Otherwise, a
time-out occurs.
000 xxxx xxxx
Write to Word0 (State 2) (1)
(2) (3)
(1) (2) (3)
100 xxxx xxxx
Write to Word1 (State 2)
010 xxxx xxxx
Write to Word2 (State 2)(1) (2) (3)
110 xxxx xxxx
Write to Word3 (State 2)(1) (2) (3)
(1)
(2)
(3)
4
Each rising edge causes a bit to be latched.
Between the bits, some longer time delays can occur, but this has no effect on the data.
A Write to WordX is expected to be 10 bits long. After the 10th bit, the respective word is latched and its effect can be observed as
look-ahead function.
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SDATA
FUNCTION
(1) (2) (3)
001 xxxx xxxx
Write to Word4 (State 2)
101 xxxx xxxx
Write to Word5 (State 2)(1) (2) (3)
111 xxxx xxxx
State machine jump: All other patterns not defined as follows cause an exit to normal mode.
111 1111 0000
Jump: Enter EEPROM programming without EEPROM lock (State 2 → State 3)
111 0101 0101
Jump: Enter EEPROM programming with EEPROM lock (State 2 → State 4)
111 0000 0000
Jump: Exit EEPROM programming (State 3 or State 4 → State 1)
Power Up:
Read
EEPROM &
Configure
Write
WORD 0
11 Bit
Written
th
11 Bit
Written
Write
WORD 2
Power Up Reset
Completed
th
Write
WORD 1
SDATA =
100 xxxx xxxx
SDATA =
000 xxxx xxxx
State 1: IDLE
Normal
Operation
SDATA = 111011
SDATA =
111 1111 1111
SDATA =
010 xxxx xxxx
th
60 Clock Applied
State 5:
Read Back
Mode
th
11 Bit
Written
State 2:
Programming
Mode
SDATA =
110 xxxx xxxx
Write
WORD 3
SDATA = 001100
th
11 Bit
Written
SDATA =
001 xxxx xxxx
th
SDATA =
101 xxxx xxxx
11 Bit
Written
SDATA =
111 1111 0000
SDATA =
111 0101 0101
Write
WORD 4
th
11 Bit
Written
Write
WORD 5
SDATA =
111 0000 0000
SDATA =
111 0000 0000
State 4:
Programming
EEPROM
Locking
State 3:
Programming
EEPROM
No Locking
F0016-02
NOTE: In States 2, 3, 4, and 5, the signal pin CE is disregarded and has no influence on power down.
Figure 2. State Flow-Diagram of Single-Pin Interface
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Enter Programming Mode
Figure 3 shows the timing behavior of data to be written into SDATA. The sequence shown is 00 1100. If the high
period is as short as t1, this is interpreted as 0. If the high period is as long as t3, this is interpreted as a 1. This
behavior is achieved by shifting the incoming signal SDATA by time t5 into signal SDATA_DELAYED. As can be
seen in Figure 3, SDATA_DELAYED can be used to latch (or strobe) SDATA. The timing specifications for t1–t7,
tr, and tf are shown in Figure 3.
t7
CE
t2
t1
t4
tf
tr
t3
SDATA
t5
SDATA
DELAYED
0
DATA
0
1
1
0
0
T0042-05
MIN
TYP
MAX
UNIT
60
70
80
kHz
fSDATACLK
Repeat frequency of programming
t1
LOW signal: high-pulse duration
0.2 t
ms
t2
LOW signal: low-pulse duration while entering programming sequence
0.8 t
ms
t2
LOW signal: low-pulse duration while programming bits
0.8 t
ms
t3
HIGH signal: high-pulse duration
0.8 t
ms
t4
HIGH signal: low-pulse duration while entering programming sequence
0.2 t
ms
t4
HIGH signal: low-pulse duration while programming bits
0.2 t
ms
t6
Time-out during Entering Programming Mode and Enter Read Back Mode.
High-pulse or low-pulse duration each must be less than this time; otherwise,
time-out will result.
16
t7
CE-high time before first SDATA can be clocked in
3t
tr and tf
Rise Time and Fall Time
µs
ms
2
ns
t = 1 / fSDATACLK
Figure 3. SDATA/CE Timing
EEPROM PROGRAMMING
Load all the registers in RAM by writing Word0 through Word5, and after going back to State 2, then going to
State 3 (programming EEPROM, no locking) or State 4 (programming EEPROM with locking), the contents of
Word0–Word5 are saved in the EEPROM. Wait 10 ms in State 3 or State 4 when programming the EEPROM
before moving to State 2 (the idle state).
NOTE:
When writing to the device for functionality testing and verification via the serial bus,
only the RAM is being accessed.
6
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EXAMPLE: Programming Cycle of Six Words and Programming Into EEPROM
The following sequence shows how to enter programming mode and how the different words can be written. The
addressing of Word0 … Word5 is shown in bold. After the word address, the payload for the respective word is
clocked in. In this example, this is followed by a jump from State 2 → State 3 into enter EEPROM programming
with EEPROM lock. In the EEPROM-programming state, it is necessary to wait at least 10 ms for safe
programming. The last command is a jump from State 3 into State 1 (normal operation). Cycle power and verify
that the device functions as programmed.
Enter Programming Sequence
Word0
Payload
After 8 bits, the payload
data is transferred to
the RAM and is active.
Word1
·
·
·
·
·
·
Payload
Word5
Payload
Wait for at least
10 ms before
exiting EEPROM
write phase, for
safe operation.
State
Machine
Jump
State 2 ® State 3
State
Machine
Jump
State 3 ® State 1
T0043-03
Figure 4. Programming Cycle of Six Words and Programming Into EEPROM
Enter Register Readback Mode and Related Timing Diagram
Similar to the enter programming mode sequence, the enter register read back mode is written into SDATA. After
the command has been issued, the SDATA input is reconfigured as clock input. By applying one clock, the
EEPROM content is read into shift registers. Now, by further applying clocks at SDATA, the EEPROM content
can be clocked out and observed at OUTP/OUTN. There are 59 bits to be clocked out. With the 61st rising clock
edge, the OUTP/OUTN pins are reconfigured back into normal operation.
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SDATA
1
1
1
0
1
1
Output Oscillation
FOUT
Enter Register
Read-Back Mode
0
Fetch
EEPROM
Content With
st
1 CLK
1
56
2
57
Output Oscillation
58
60th Falling Edge
Switches Back Into
Normal Operation
EEPROM Content
st
1 Bit Available After
st
1 Falling Edge
T0044-03
In the following table, the content of the output bit stream is summarized. Important to notice: bit 0 is clocked out
first. The default values in register 0 to register 5 are programmed in the EEPROM.
OUTPUT BIT STREAM
FUNCTION
Bits[0:2]
Revision identifier (MSB first)
Bits[3:8]
VCO calibration word
Bit[9]
EEPROM status:
0 = EEPROM has never been written
1 = EEPROM has been programmed before
Bit[10]
EEPROM lock:
0 = EEPROM can be rewritten
1 = EEPROM is locked, rewriting to the EEPROM is not possible any more
Bits[11:18]
Storage value, Word5 (MSB first)
Bits[19:26]
Storage value, Word4 (MSB first)
Bits[27:34]
Storage value, Word3 (MSB first)
Bits[35:42]
Storage value, Word2 (MSB first)
Bits[43:50]
Storage value, Word1 (MSB first)
Bits[51:58]
Storage value, Word0 (MSB first)
REGISTER DESCRIPTIONS
Word 0:
BIT
NAME
DESCRIPTION/FUNCTION
TYPE
DEFAULT
VALUE
0
C0
Register selection
W
0
1
C1
Register selection
W
0
2
C2
Register selection
W
0
3
SELVCO
VCO select, 0 = VCO1, 1 = VCO2
W
0
4
SELPRESC
Prescaler setting, bit 0
W
0
5
SELPRESC
Prescaler setting, bit 1
W
1
6
OUTSEL
Output divider select, bit 0
W
1
7
OUTSEL
Output divider select, bit1
W
1
8
OUTSEL
Output divider select, bit 2
W
0
9
DRVSEL
Driver select, 0 = LVDS, 1 = PECL
W
1
10
TITEST0
Reserved
W
1
4
5
6
7
Divide by value (SELPRESC 1, SELPRESC 0)
Divide by 5 = (00), 3 = (01), 4 = (10), 2 = (11)
Output divider (OUTSEL2, OUTSEL1, OUTSEL0)
Divide by 1 = (000), 2 = (001), 4 = (010), 8 = (011), 16 = (100), 32 = (101)
8
8
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Word 1:
BIT
NAME
DESCRIPTION/FUNCTION
TYPE
DEFAULT
VALUE
0
C0
Register selection
W
1
1
C1
Register selection
W
0
2
C2
Register selection
W
0
3
LFRCSEL
Loop filter control settings, bit 0
W
1
4
LFRCSEL
Loop filter control settings, bit 1
W
1
5
LFRCSEL
Loop filter control settings, bit 2
W
1
6
LFRCSEL
Loop filter control settings, bit 3
W
1
7
LFRCSEL
Loop filter control settings, bit 4
W
1
8
LFRCSEL
Loop filter control settings, bit 5
W
0
9
LFRCSEL
Loop filter control settings, bit 6
W
1
10
LFRCSEL
Loop filter control settings, bit 7
W
0
TYPE
DEFAULT
VALUE
Word 2:
BIT
NAME
DESCRIPTION/FUNCTION
0
C0
Register selection
W
0
1
C1
Register selection
W
1
2
C2
Register selection
W
0
3
LFRCSEL
Loop filter control settings, bit 8
W
1
4
LFRCSEL
Loop filter control settings, bit 9
W
1
5
LFRCSEL
Loop filter control settings, bit 10
W
0
6
LFRCSEL
Loop filter control settings, bit 11
W
0
7
LFRCSEL
Loop filter control settings, bit 12
W
0
8
LFRCSEL
Loop filter control settings, bit 13
W
0
9
LFRCSEL
Loop filter control settings, bit 14
W
0
10
LFRCSEL
Loop filter control settings, bit 15
W
0
TYPE
DEFAULT
VALUE
Word 3:
BIT
NAME
DESCRIPTION/FUNCTION
0
C0
Register selection
W
1
1
C1
Register selection
W
1
2
C2
Register selection
W
0
3
LFRCSEL
Loop filter control settings, bit 16
W
0
4
LFRCSEL
Loop filter control settings, bit 17
W
0
5
LFRCSEL
Loop filter control settings, bit 18
W
0
6
ICPSEL
Charge pump current sel, bit 0
W
1
7
ICPSEL
Charge pump current sel, bit 1
W
1
8
ICPSEL
Charge pump current sel, bit 2
W
1
9
ICPSEL
Charge pump current sel, bit 3
W
1
10
TITEST1
Reserved
W
0
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Word 4:
BIT
NAME
DESCRIPTION/FUNCTION
TYPE
DEFAULT
VALUE
0
C0
Register selection
W
0
1
C1
Register selection
W
0
2
C2
Register selection
W
1
3
CALWRD
VCO calibration word, bit 0
W
0
4
CALWRD
VCO calibration word, bit 1
W
0
5
CALWRD
VCO calibration word, bit 2
W
0
6
CALWRD
VCO calibration word, bit 3
W
0
7
CALWRD
VCO calibration word, bit 4
W
0
8
CALWRD
VCO calibration word, bit 5
W
0
9
CALOVR
VCO calibration override
W
0
10
ENCAL
Enable VCO calibration
W
1
TYPE
DEFAULT
VALUE
Word 5:
BIT
10
NAME
DESCRIPTION/FUNCTION
0
C0
Register selection
W
1
1
C1
Register selection
W
0
2
C2
Register selection
W
1
3
TITSTCFG
TI test use, bit 0
W
0
4
TITSTCFG
TI test use, bit 1
W
0
5
TITSTCFG
TI test use, bit 2
W
0
6
TITSTCFG
TI test use, bit 3
W
0
7
Not used
W
0
8
Not used
W
0
9
Not used
W
0
10
Not used
W
0
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Product Folder Link(s): CDCE421
CDCE421
www.ti.com..................................................................................................................................................... SCAS842B – APRIL 2007 – REVISED JANUARY 2009
PACKAGE (QFN24)
The CDCE421 is available in a QFN 24-pin package. The QFN package footprint is illustrated in Figure 5, as well
as the pad locations and numbers.
NC
NC
XIN 2
XIN 1
NC
NC
24
23
22
21
20
19
RGE PACKAGE
(TOP VIEW)
CE
1
18
NC
NC
2
17
VCC
SDATA
3
16
VCC
CDCE421
12
NC
NC
13
11
6
NC
NC
10
NC
OUTP
14
9
5
GND
NC
8
NC
GND
15
7
4
OUTN
NC
P0024-05
Figure 5. Pinout of the CDCE421 QFN-24 Package
PIN DESCRIPTIONS
Table 2 shows the pin descriptions for the CDCE421 QFN-24 package.
Table 2. CDCE421 Pin Descriptions
TERMINAL
NAME
CE
GND
No connect
TERMINAL
NO.
TYPE
ESD
PROTECTION
1
I
Y
Chip enable
CE = 1: enable the device and the outputs.
CE = 0: disable all current sources; in LVDS mode, LVDSP = LVDSN = Hi-Z;
in LVPECL mode, LVPECLP = LVPECLN = Hi-Z.
8, 9
GND
Y
Ground
2, 4–6,
11–15,
18–20, 23,24
DESCRIPTION
Do not connect these pins. Leave them floating.
OUTN
7
O
Y
High-speed negative differential LVPECL or LVDS outputs. (Outputs are
enabled by CE and selected by the EEPROM configuration registers.)
OUTP
10
O
Y
High-speed positive differential LVPECL or LVDS outputs. (Outputs are
enabled by CE and selected by the EEPROM configuration registers.)
SDATA
3
I
Y
Programming pin using TI proprietary interface protocol
VCC
16, 17
Power
Y
3.3-V power supply
XIN 1
XIN 2
21
22
I
GND/NC
Y
N
In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the
other end of the crystal. In LVCMOS input single-ended driven mode, XIN1
(pin 21) acts as an input reference, and XIN2 should connect to GND or it can
be left unconnected.
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CDCE421
SCAS842B – APRIL 2007 – REVISED JANUARY 2009..................................................................................................................................................... www.ti.com
OUTPUTS (LVPECL OR LVDS)
The CDCE421 device has two sets of output drivers, LVPECL and LVDS, where the outputs are wire-ORed
together. Only one output can be selected at a time; the other goes to the high-impedance state (Hi-Z).
If the device is configured for an LVPECL, the output buffers go to Hi-Z and the termination resistors determine
the state of the output (LVPECLP = LVPECLN = Hi-Z) in the device disable mode (CE = L). If the device is
configured in LVDS mode, the outputs go to Hi-Z if the device is disabled (CE = L).
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
VCC
Supply voltage (2)
VI
Voltage range for all other input pins (2)
IO
Output current for LVPECL
Electrostatic discharge (HBM)
TA
Characterized free-air temperature range (no airflow)
TJ
Maximum junction temperature
Tstg
Storage temperature range
(1)
(2)
VALUE
UNIT
–0.5 to 4.6
V
–0.5 to VCC + 0.5
V
–50
mA
2
kV
–40 to +85
°C
+125
°C
–65 to +150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
VCC
Supply voltage
TA
Ambient temperature (no airflow, no heat sink)
12
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MIN
TYP
MAX
3
3.3
3.6
V
+85
°C
–40
UNIT
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): CDCE421
CDCE421
www.ti.com..................................................................................................................................................... SCAS842B – APRIL 2007 – REVISED JANUARY 2009
ELECTRICAL CHARACTERISTICS
Using the recommended operating conditions for the CDCE421 device.
PARAMETER
VCC
Supply voltage
IVCC(LVDS)
Total current
IVCC(LVPECL)
Total current
TEST CONDITIONS
MIN
TYP
MAX
3
3.3
3.6
UNIT
V
LVDS mode
83
103
mA
LVPECL mode
91
110
mA
10.9
400
MHz
247
454
mV
50
mV
1.3
V
50
mV
LVDS OUTPUT MODE (see Figure 8)
fCLK
Output frequency
|VOD|
LDVS differential output voltage
ΔVOD
LVDS VOD magnitude change
VOS
Offset voltage
ΔVOS
VOS magnitude change
tr
Output rise time
20% to 80% of VOUTpp
230
tf
Output fall time
80% to 20% of VOUTpp
230
IOS
Short-circuit output current
RL = 100 Ω
–40°C to 85°C
Short Vout+ to ground
Short Vout– to ground
Duty cycle of the output waveform
TJ
Random jitter
1.1
45%
ps
ps
–30
mA
30
mA
55%
10kHz to 20MHz
1
ps, rms
LVPECL OUTPUT MODE (see Figure 9)
fCLK
Output frequency
10.9
1175
VOH
LVPECL high-level output voltage
VCC – 1.2
VCC – 0.81
VOL
LVPECL low-level output voltage
VCC – 2.17
VCC – 1.36
|VOD|
LVPECL differential output voltage
tr
Output rise time
20% to 80% of VOUTpp
230
ps
tf
Output fall time
80% to 20% of VOUTpp
230
ps
407
Duty cycle of the output waveform
TJ
Random jitter
45%
10kHz to 20MHz
MHz
V
V
mV
55%
1
ps, rms
LVCMOS INPUT
VIL,CMOS
Low-level CMOS input voltage
VCC = 3.3 V
VIH,CMOS
High-level CMOS input voltage
VCC = 3.3 V
IL,CMOS
Low- level CMOS input current
VCC = VCC max, VIL = 0 V
IH,CMOS
High-level CMOS input current
VCC = VCC min, VIH = 3.7 V
0.3 VCC
V
–200
µA
200
µA
0.7 VCC
V
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CDCE421
SCAS842B – APRIL 2007 – REVISED JANUARY 2009..................................................................................................................................................... www.ti.com
Jitter Characteristics in Input Clock Mode
If the CDCE421 is being referenced by an external and cleaner LVCMOS input of 35.42 MHz, Figure 6 shows
the SSB phase noise plot of the output at 708 MHz from 100 Hz to 40 MHz from the carrier. Note the
dependence of output jitter on the input reference jitter. See Figure 11 for test setup.
0
−20
Phase Noise − dBc/Hz
−40
−60
−80
−100
−120
−140
−160
10
100
1k
10k
100k
1M
10M
100M
f − Single-Sideband Frequency − Hz
G001
Figure 6. Phase Noise Plot for LVPECL Output at 708 MHz
Table 3. Phase Noise Parameters With LVCMOS Input of 35.4 MHz and LVPECL Output at 708 MHz
Phase noise specifications under following assumptions: input frequency f = 35.42 MHz (VCO = 2, prescaler = 3, output divider =
1), fout = 708 MHz (driver mode = LVPECL)
PARAMETER
phn100
Phase noise at 100 Hz
phn1k
MIN
TYP
MAX
UNIT
–95
dBc/Hz
Phase noise at 1 kHz
–105
dBc/Hz
phn10k
Phase noise at 10 kHz
–109
dBc/Hz
phn100k
Phase noise at 100 kHz
–114
dBc/Hz
phn1M
Phase noise at 1 MHz
–126
dBc/Hz
phn10M
Phase noise at 10 MHz
–146
dBc/Hz
phn20M
Phase noise at 20 MHz
–146
dBc/Hz
JRMS
RMS jitter integrated from 12 kHz to 20 MHz
438
fs
14
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CDCE421
www.ti.com..................................................................................................................................................... SCAS842B – APRIL 2007 – REVISED JANUARY 2009
If the CDCE421 is being referenced by a clean external LVCMOS input of 33.33 MHz, Figure 7 shows the SSB
phase noise plot of the output at 400 MHz from 100 Hz to 40 MHz from carrier. See Figure 10 for test setup.
0
−20
Phase Noise − dBc/Hz
−40
−60
−80
−100
−120
−140
−160
10
100
1k
10k
100k
1M
10M
100M
f − Single-Sideband Frequency − Hz
G002
Figure 7. Phase Noise Plot for LVDS Output at 400 MHz
Table 4. Phase Noise Parameters With LVCMOS Input of 33.33 MHz and LVDS Output at 400 MHz
Phase noise specifications under following assumptions: input frequency f = 33.33 MHz (VCO = 1, prescaler = 5, output divider =
1), fout = 400 MHz (driver mode = LVDS)
PARAMETER
phn100
Phase noise at 100 Hz
phn1k
MIN
TYP
MAX
UNIT
–99
dBc/Hz
Phase noise at 1 kHz
–109
dBc/Hz
phn10k
Phase noise at 10 kHz
–119
dBc/Hz
phn100k
Phase noise at 100 kHz
–121
dBc/Hz
phn1M
Phase noise at 1 MHz
–130
dBc/Hz
phn10M
Phase noise at 10 MHz
–147
dBc/Hz
phn20M
Phase noise at 20 MHz
–147
dBc/Hz
JRMS
RMS jitter integrated from 12 kHz to 20 MHz
409
fs
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15
CDCE421
SCAS842B – APRIL 2007 – REVISED JANUARY 2009..................................................................................................................................................... www.ti.com
APPENDIX A: TEST CONFIGURATIONS
Test setups are used to characterize the CDCE421 device in ac and dc terminations. Figure 8 through Figure 11
illustrate all four setups used to terminate the clock signal driven by the device under test.
100 W
LVDS
LVDS
S0248-01
Figure 8. LVDS DC Termination Test Configuration
LVPECL
LVPECL
50 W
50 W
VCC – 2V
S0249-01
Figure 9. LVPECL DC Termination Test Configuration
Phase Noise
Analyzer
LVDS
50 W
S0250-01
Figure 10. LVDS AC Termination Test Configuration
Phase Noise
Analyzer
LVPECL
150 W
150 W
50 W
S0251-01
Figure 11. LVPECL AC Termination Test Configuration
16
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CDCE421RGER
NRND
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCE
421
CDCE421RGERG4
NRND
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCE
421
CDCE421RGET
NRND
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCE
421
CDCE421RGETG4
NRND
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCE
421
CDCE421Y
NRND
DIESALE
Y
0
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCE421RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
CDCE421RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCE421RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
CDCE421RGET
VQFN
RGE
24
250
210.0
185.0
35.0
Pack Materials-Page 2
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