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CDCE813-Q1
SNAS705C – JANUARY 2017 – REVISED APRIL 2019
CDCE813-Q1 Programmable 1-PLL Clock Synthesizer and Jitter Cleaner
With 2.5-V and 3.3-V Outputs
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 2: –40°C to 105°C
ambient operating temperature range
– Device HBM ESD classification level H2
– Device CDM ESD classification level C6
In-system programmability and EEPROM
– Serial programmable volatile register
– Nonvolatile EEPROM to store customer
settings
Flexible input clocking concept
– External crystal: 8 MHz to 32 MHz
– Single-ended LVCMOS up to 160 MHz
Free selectable output frequency up to 230 MHz
Low-noise PLL core
– PLL loop filter components integrated
– Low period jitter (typical 50 ps)
1.8-V device power supply (core voltage)
Separate output supply pins: 3.3 V and 2.5 V
Flexible clock driver
– Three user-definable control inputs [S0, S1,
S2], for example, SSC selection, frequency
switching, output enable, or power down
– Generates highly accurate clocks for video,
audio, USB, IEEE1394, RFID, Bluetooth®,
WLAN, Ethernet, and GPS
– Generates common clock frequencies used
with TI-DaVinci™, OMAP™, DSPs
– Programmable SSC modulation
– Enables 0-PPM clock generation
Packaged in TSSOP
Development and programming kit for easy PLL
design and programming (TI ClockPro™
programming software)
Cluster
Head unit
Navigation systems
Advanced Driver Assistance Systems (ADAS)
3 Description
The CDCE813-Q1 device is a modular Phase-lockedloop-based (PLL), low-cost, high-performance,
programmable clock synthesizers. They generate up
to three output clocks from a single input frequency.
Each output can be programmed in-system for any
clock frequency up to 230 MHz, using the integrated
configurable PLL.
The CDCE813-Q1 has separate output supply pins,
VDDOUT, providing 2.5 V to 3.3 V.
The input accepts an external crystal or LVCMOS
clock signal. A selectable on-chip VCXO allows
synchronization of the output frequency to an external
control signal.
The PLL supports SSC (spread-spectrum clocking)
for better electromagnetic interference (EMI)
performance.
Device Information(1)
PART NUMBER
CDCE813-Q1
PACKAGE
BODY SIZE (NOM)
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Device Comparison
ORDERABLE
S0 CONTROL PIN DEFAULT FUNCTION
CDCE813R02-Q1
Y1 Output Enable (Active High)
CDCE813-Q1
Not Used (1)
Typical Application Schematic
PCLK
CDCE813-Q1
I2C
PCLK
SoC
To Display
Image Data
Serializer
Copyright © 2017, Texas Instruments Incorporated
1
(1)
Output must be enabled by I2C control.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCE813-Q1
SNAS705C – JANUARY 2017 – REVISED APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
6
6
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 11
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 15
9.5 Programming........................................................... 15
9.6 Register Maps ......................................................... 17
10 Application and Implementation........................ 21
10.1 Application Information.......................................... 21
10.2 Typical Application ................................................ 21
11 Power Supply Recommendations ..................... 25
12 Layout................................................................... 26
12.1 Layout Guidelines ................................................. 26
12.2 Layout Example .................................................... 26
13 Device and Documentation Support ................. 27
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
14 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2018) to Revision C
Page
•
Added CDCE813R02-Q1 orderable information to the data sheet ........................................................................................ 1
•
Added Device Comparison table ........................................................................................................................................... 1
•
Added default configuration information to the S0 pin description ......................................................................................... 4
•
Removed 'CDCE813-Q1' text from the VDDOUT pin description. The information applies to both CDCE813-Q1 and
CDCE813R02-Q1 orderables ................................................................................................................................................. 4
•
Added S0 pin information in the Overview section............................................................................................................... 11
•
Added S0 pin information to the Default Device Configuration section................................................................................ 13
•
Added CDCE813R02-Q1 Default Configuration graphic...................................................................................................... 14
•
Changed S0 pin information in the Factory Default Setting for Control Terminal Register tablenote.................................. 14
•
Added Y1_ST1 default settings for the CDCE813-Q1 and CDCE813R02-Q1 orderables .................................................. 18
•
Added Y1_1 default settings for the CDCE813-Q1 and CDCE813R02-Q1 orderables ....................................................... 18
Changes from Revision A (May 2018) to Revision B
Page
•
Changed the text in the Default Device Configuration section from: However the outputs are disabled by default and
need to be turned on through I2C or with the S0 pin to: However the outputs are disabled by default and need to be
turned on through I2C........................................................................................................................................................... 13
•
Changed the Factory Default Setting table and Default Configuration graphic text to show that the Y1 outputs as 3state when S0 = 1 or S0 = 0................................................................................................................................................. 14
•
Changed the default value of the SLAVE_ADR 1:0 bits from: 00b to: 01b in the Generic Configuration Register table .... 18
•
Changed the default value of the Y1_ST0 3:2 bits from: 11b to: 01b in the Generic Configuration Register table............. 18
•
Changed the default value of the BCOUNT 7:1 bits from: 20h to: 00h in the Generic Configuration Register table .......... 18
•
Changed the default value of the Y2Y3_1 bit from: 1b to: 0b in the PLL1 Configuration Register table ............................. 19
2
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Changes from Original (January 2017) to Revision A
•
Page
Changed the Factory Default Setting table and Default Configuration graphic text to show that S0 = 1 means Y1
outputs 3-state and S0 = 0 means Y1 is enabled ................................................................................................................ 14
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5 Description (continued)
The device supports nonvolatile EEPROM programming for easy customization of the device to the application.
All device settings are programmable through the I2C bus, a 2-wire serial interface.
The CDCE813-Q1 operates in a 1.8-V core environment as well as eliminating the need for additional,
independent XTAL oscillators which reduces component count and board size. It operates in a temperature
range of –40°C to 105°C.
6 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
Xin/CLK
1
14
Xout
S0
2
13
SDA/S1
VDD
3
12
SCL/S2
Vctr
4
11
Y1
GND
5
10
GND
VDDOUT
6
9
Y2
VDDOUT
7
8
Y3
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
GND
5, 10
G
Ground
SCL/S2
12
I
SCL: serial clock input LVCMOS (default configuration), 500-kΩ internal pullup; or
S2: user-programmable control input, LVCMOS input, 500-kΩ internal pullup
SDA/S1
13
I/O or I
SDA: bidirectional serial data input or output (default configuration), LVCMOS internal pullup; or
S1: user-programmable control input, LVCMOS input, 500-kΩ internal pullup
S0
2
I
User-programmable control input S0, LVCMOS input, 500-kΩ internal pullup
CDCE813-Q1 default:
S0 = 1: Y1 is 3-state,
S0 = 0: Y1 is 3-state
CDCE813R02-Q1 default:
S0 = 1: Y1 is enabled,
S0 = 0: Y1 is 3-state
Vctr
4
I
VCXO control voltage (leave open or pull up when not used)
VDD
3
P
1.8-V power supply for the device
VDDOUT
6, 7
P
3.3-V or 2.5-V supply for all outputs
Xin/CLK
1
I
Crystal oscillator input or LVCMOS clock input (selectable through the I2C bus)
Xout
14
O
Crystal oscillator output (leave open or pull up when not used)
Y1
11
O
LVCMOS output
Y2
9
O
LVCMOS output
Y3
8
O
LVCMOS output
(1)
4
G = Ground, I = Input, O = Output, P = Power
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.5
2.5
V
–0.5
3.6 + 0.5
V
–0.5
VDD + 0.5
V
–0.5
VDDOUT + 0.5
V
Input current (VI < 0, VI > VDD)
20
mA
Continuous output current
50
mA
TJ
Maximum junction temperature
125
Tstg
Storage temperature
VDD
Supply voltage
VDDOUT
Output clocks supply voltage
VI
Input voltage (2) (3)
VO
Output voltage (2)
II
IO
(1)
(2)
(3)
CDCE813-Q1
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
VDD
Device supply voltage
VO
Output Yx supply voltage, VDDOUT
VIL
Low-level input voltage, LVCMOS
VIH
High-level input voltage, LVCMOS
VI(thresh)
Input voltage threshold, LVCMOS
VI(S)
VI(CLK)
CDCE813-Q1
MIN
NOM
MAX
1.7
1.8
1.9
V
3.6
V
0.3 × VDD
V
2.3
0.7 × VDD
V
0.5 × VDD
V
Input voltage range, S0
0
1.9
Input voltage range S1, S2, SDA, SCL (VI(thresh) = 0.5 VDD)
0
3.6
Input voltage range CLK
0
IOH, IOL
Output current
CL
Output load, LVCMOS
TA
Operating ambient temperature
1.9
VDDOUT = 3.3 V
±12
VDDOUT = 2.5 V
±10
–40
Product Folder Links: CDCE813-Q1
V
V
mA
15
pF
105
°C
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UNIT
5
CDCE813-Q1
SNAS705C – JANUARY 2017 – REVISED APRIL 2019
www.ti.com
Recommended Operating Conditions (continued)
MIN
NOM
MAX
UNIT
8
27
32
MHz
±120
±150
CRYSTAL AND VCXO SPECIFICATIONS (1)
fXtal
Crystal input frequency range (fundamental mode)
ESR
Effective series resistance
fPR
Pulling range (0 V ≤ Vctr ≤ 1.8 V) (2)
Vctr
Frequency control voltage
C0 / C1
Pullability ratio
CL
On-chip load capacitance at Xin and Xout
(1)
(2)
Ω
100
ppm
0
VDD
V
220
0
20
pF
For more information about VCXO configuration, and crystal recommendation, see application report VCXO Application Guideline for
CDCE(L)9xx Family (SCAA085).
Pulling range depends on crystal type, on-chip crystal load capacitance, and PCB stray capacitance; pulling range of minimum ±120
ppm applies for crystal listed in the application report VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
7.4 Thermal Information
CDCE813-Q1
THERMAL METRIC (1) (2)
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
110.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
35.4
°C/W
RθJB
Junction-to-board thermal resistance
53.6
°C/W
ψJT
Junction-to-top characterization parameter
2.1
°C/W
ψJB
Junction-to-board characterization parameter
52.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-K board).
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
OVERALL PARAMETER
IDD
Supply current (see Figure 1)
All outputs off,
fCLK = 27 MHz,
fVCO = 135 MHz,
fOUT = 27 MHz
IDD(OUT)
Supply current (see Figure 2)
No load, all outputs on,
fOUT = 27 MHz
IDD(PD)
Power-down current. Every circuit
powered down except I2C
fIN = 0 MHz, VDD = 1.9 V
V(PUC)
Supply voltage VDD threshold for
power-up control circuit
fVCO
VCO frequency range of PLL
fOUT
LVCMOS output frequency
(1)
6
All PLLS on
11
Per PLL
VDDOUT = 3.3 V
VDDOUT = 3.3 V
mA
9
1.3
mA
30
μA
0.85
1.45
V
70
230
MHz
230
MHz
All typical values are at respective nominal VDD.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
LVCMOS PARAMETER
VIK
LVCMOS input voltage
VDD = 1.7 V, II = –18 mA
II
LVCMOS input current
VI = 0 V or VDD, VDD = 1.9 V
IIH
LVCMOS input current for S0, S1,
and S2
IIL
CI
–1.2
V
±5
μA
VI = VDD, VDD = 1.9 V
5
μA
LVCMOS input current for S0, S1,
and S2
VI = 0 V, VDD = 1.9 V
–4
μA
Input capacitance at Xin/CLK
VIClk = 0 V or VDD
6
Input capacitance at Xout
VIXout = 0 V or VDD
2
Input capacitance at S0, S1, and S2
VIS = 0 V or VDD
3
pF
CDCE813-Q1, LVCMOS PARAMETER FOR VDDOUT = 3.3-V MODE
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
VDDOUT = 3 V, IOH = –0.1 mA
2.9
VDDOUT = 3 V, IOH = –8 mA
2.4
VDDOUT = 3 V, IOH = –12 mA
2.2
VDDOUT = 3 V, IOL = 0.1 mA
0.1
VDDOUT = 3 V, IOL = 8 mA
0.5
VDDOUT = 3 V, IOL = 12 mA
0.8
PLL bypass
tPLH, tPHL
Propagation delay
tr, tf
Rise and fall time
PLL enabled (fCLK = fVCO), 70 MHz ≤ fVCO ≤
85 MHz
(2)
V
V
3.2
1.6
4.3
VDDOUT = 3.3 V (20%–80%)
0.6
ns
ns
tjit(cc)
Cycle-to-cycle jitter
1 PLL switching, Y2-to-Y3, 10,000 cycles
50
200
ps
tjit(per)
Peak-to-peak period jitter (2)
1 PLL switching, Y2-to-Y3
60
200
ps
tsk(o)
Output skew (see Table 2) (3)
fOUT = 50 MHz, Y1-to-Y3
440
ps
odc
(4)
Output duty cycle
fVCO = 100 MHz, Pdiv = 1
45%
55%
CDCE813-Q1, LVCMOS PARAMETER FOR VDDOUT = 2.5-V MODE
VOH
LVCMOS high-level output voltage
VDDOUT = 2.3 V, IOH = –0.1 mA
2.2
VDDOUT = 2.3 V, IOH = –6 mA
1.7
VDDOUT = 2.3 V, IOH = –10 mA
1.6
V
VDDOUT = 2.3 V, IOL = 0.1 mA
0.1
VDDOUT = 2.3 V, IOL = 6 mA
0.5
VOL
LVCMOS low-level output voltage
tPLH, tPHL
Propagation delay
PLL bypass
3.6
ns
tr, tf
Rise and fall time
VDDOUT = 2.5 V (20%–80%)
0.8
ns
VDDOUT = 2.3 V, IOL = 10 mA
(2)
V
0.7
tjit(cc)
Cycle-to-cycle jitter
1 PLL switching, Y2-to-Y3, 10,000 cycles
50
200
ps
tjit(per)
Peak-to-peak period jitter (2)
1 PLL switching, Y2-to-Y3
60
200
ps
tsk(o)
Output skew (see Table 2) (3)
fOUT = 50 MHz, Y1-to-Y3
440
ps
odc
(2)
(3)
(4)
Output duty cycle
(4)
fVCO = 100 MHz, Pdiv = 1
45%
55%
Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2).
The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.
odc depends on the output rise and fall time (tr and tf); data sampled on the rising edge (tr)
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
I2C PARAMETER
VIK
SCL and SDA input clamp voltage
VDD = 1.7 V, II = –18 mA
–1.2
V
IIH
SCL and SDA input current
VI = VDD, VDD = 1.9 V
±10
μA
VIH
I2C input high voltage (5)
0.7 × VDD
V
(5)
VIL
I2C input low voltage
VOL
SDA low-level output voltage
IOL = 3 mA, VDD = 1.7 V
CI
SCL-SDA input capacitance
VI = 0 V or VDD
0.3 ×
VDD
V
0.2 ×
VDD
V
10
pF
3
EEPROM SPECIFICATION
EEcyc
Programming cycles of EEPROM
EEret
Data retention
(5)
100
1000
cycles
10
years
SDA and SCL pins are 3.3-V tolerant.
7.6 Timing Requirements
over recommended ranges of supply voltage, load, and operating free-air temperature
MIN
NOM
MAX
UNIT
CLK_IN
fCLK
LVCMOS clock input frequency
tr and tf
Rise and fall time, CLK signal (20% to 80%)
PLL bypass mode
0
160
PLL mode
8
160
40%
60%
Standard mode
0
100
Fast mode
0
400
3
Duty cycle of CLK at VDD / 2
MHz
ns
I2C (SEE Figure 13)
fSCL
SCL clock frequency
tsu(START)
START setup time (SCL high before SDA low)
th(START)
START hold time (SCL low after SDA low)
tw(SCLL)
SCL low-pulse duration
tw(SCLH)
SCL high-pulse duration
th(SDA)
SDA hold time (SDA valid after SCL low)
tsu(SDA)
SDA setup time
tr
SCL-SDA input rise time
tf
SCL-SDA input fall time
4.7
Fast mode
0.6
Standard mode
0.6
Standard mode
4.7
Fast mode
1.3
Fast mode
μs
4
Fast mode
Standard mode
μs
μs
4
μs
0.6
Standard mode
0
3.45
Fast mode
0
0.9
Standard mode
250
Fast mode
100
Standard mode
300
300
Standard mode
STOP setup time
tBUS
Bus free time between a STOP and START condition
4
Fast mode
0.6
Standard mode
4.7
Fast mode
1.3
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μs
ns
1000
Fast mode
tsu(STOP)
8
Standard mode
kHz
ns
ns
μs
μs
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7.7 Typical Characteristics
16
30
VDD = 1.8 V
14
3 Outputs on
12
20
IDDOUT - mA
IDD - Supply Current - mA
25
VDD = 1.8 V,
VDDOUT = 3.3 V,
no load
1 PLL on
15
10
1 Output on
8
6
10
4
all PLL off
5
2
0
10
60
110
160
fVCO - Frequency - MHz
210
0
10
Figure 1. CDCE813-Q1 Supply Current
vs PLL Frequency
all Outputs off
30
50 70 90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 2. CDCE813-Q1 Output Current
vs Output Frequency
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8 Parameter Measurement Information
CDCE813-Q1
1 k:
LVCMOS
1 k:
10 pF
Copyright © 2017, Texas Instruments Incorporated
Figure 3. Test Load
CDCE813-Q1
LVCMOS
driver
impedance
~ 50 :
LVCMOS
series
termination
(optional)
line impedance
Zo = 50 :
Copyright © 2017, Texas Instruments Incorporated
Figure 4. Test Load for 50-Ω Board Environment
10
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9 Detailed Description
9.1 Overview
The CDCExxx-Q1 devices are modular PLL-based, low-cost, high-performance, programmable clock
synthesizers, multipliers, and dividers. They generate up to three output clocks from a single input frequency.
Each output can be programmed in-system for any clock frequency up to 230 MHz, using the integrated
configurable PLL.
The CDCExxx-Q1 devices have separate output supply pins, VDDOUT, with output of 2.5 V to 3.3 V.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF.
Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control
signal, that is, the PWM signal.
The deep M / N divider ratio allows the generation of zero-ppm audio-video, networking (WLAN, Bluetooth,
Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from, for example, a 27-MHz reference input
frequency.
The PLL supports spread-spectrum clocking (SSC). SSC can be center-spread or down-spread clocking, which
is a common technique to reduce electromagnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristics.
The device supports nonvolatile EEPROM programming for easy customization of the device to the application. It
is preset to a factory default configuration (see Default Device Configuration). It can be reprogrammed to a
different application configuration before PCB assembly, or reprogrammed by in-system programming. All device
settings are programmable through the SDA-SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1, and S2, can be used to select different frequencies, change SSC
setting for lowering EMI, or control other features like outputs disable to low, outputs in Hi-Z state, power down,
PLL bypass, and so forth). For CDCE813-Q1, the S0 pin is unused by default. For the CDCE813R02-Q1, the S0
control input pin provides output enable (OE) control for output Y1 only.
The CDCE813-Q1 core operates in a 1.8-V environment. It operates in a temperature range of –40°C to 105°C.
9.2 Functional Block Diagram
GND
VDD
VDDOUT
Input Clock
Pdiv1
10-Bit
LV
CMOS
Y1
M2
Xin/CLK
LV
CMOS
Y2
M3
M1
V ctr
LV
CMOS
Y3
VCXO
with SSC
Xout
EEPROM
S0
S1/SDA
PLL 1
MUX1
XO
LVCMOS
PLL Bypass
Pdiv2
7-Bit
Pdiv3
7-Bit
Programming
and I2C
Register
S2/SCL
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9.3 Feature Description
9.3.1 Control Terminal Configuration
The CDCE813-Q1 device has three user-definable control terminals (S0, S1, and S2), which allow external
control of device settings. They can be programmed to any of the following functions:
• Spread-spectrum clocking selection → spread type and spread amount selection
• Frequency selection → switching between any of two user-defined frequencies
• Output state selection → output configuration and power-down control
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.
Table 1. Control Terminal Definition
EXTERNAL CONTROL
BITS
PLL1 SETTING
PLL frequency
selection
Control function
SSC selection
Y1 SETTING
Output Y2 and Y3
selection
Table 2. PLL1 Setting
SSCx [3 BITS]
Output Y1 and power-down selection
(1)
CENTER
DOWN
SSC SELECTION (CENTER AND DOWN)
(1)
0
0
0
0% (off)
0% (off)
0
0
1
±0.25%
–0.25%
0
1
0
±0.5%
–0.5%
0
1
1
±0.75%
–0.75%
1
0
0
±1.0%
–1.0%
1
0
1
±1.25%
–1.25%
1
1
0
±1.5%
–1.5%
1
1
1
±2.0%
–2.0%
Center and down-spread, Frequency0, Frequency1, State0, and State1 are user-definable in PLL1
configuration register.
Table 3. PLL1 Setting, Frequency Selection
(1)
FSx
FUNCTION
0
Frequency 0
1
Frequency 1
(1)
Frequency0 and Frequency1 can be any frequency within the
specified fVCO range.
Table 4. PLL1 Setting, Output Selection (Y2, Y3)
(1)
12
Y2, Y3
FUNCTION
0
State 0
1
State 1
(1)
State0 or State1 selection is valid for both outputs of the
corresponding PLL module and can be power down, Hi-Z state, low,
or active.
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Table 5. Y1 Setting
(1)
(1)
Y1
FUNCTION
0
State 0
1
State 1
State0 and State1 are user definable in the generic configuration
register and can be power down, Hi-Z state, low, or active.
The S1/SDA and S2/SCL pins of the CDCE813-Q1 device are dual-function pins. In the default configuration,
they are defined as SDA and SCL for the serial programming interface. They can be programmed as control pins
(S1 and S2) by setting the appropriate bits in the EEPROM.
NOTE
Changes to the control register (Bit [6] of byte 02h) have no effect until they are written
into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is
forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA and SCL).
S0 is not a multi-use pin; it is a control pin only.
9.3.2 Default Device Configuration
The internal EEPROM of the CDCE813-Q1 device is pre-configured with a factory default configuration as shown
in Figure 5 (the input frequency is routed through PLL1 to the outputs as a default). This mode can be used to
clean the jitter of an incoming clock signal. For the CDCE813-Q1, the outputs are disabled by default and must
be turned on through I2C. For the CDCE813R02-Q1, output Y1 is enabled through the S0 control pin (active
high), while outputs Y2 and Y3 are either in a tri-state condition or disabled by the register default. Y1 is enabled
when S0 is floating because S0 has an internal pullup.
The default setting appears either after power is supplied or after a power-down – power-up sequence until it is
reprogrammed by the user to a different application configuration. A new register setting is programmed through
the serial I2C interface.
VDD
VDDOUT
GND
Y1 = 3-state
M2
M1
LV
CMOS
LV
CMOS
Y2 = 3-state
M3
Input Clock
Vctr
LV
CMOS
Y3 = 3-state
Pdiv1 = 1
1.8V LVCMOS
CLK input
LVCMOS
Pdiv2 = 0
MUX1
PLL 1 enabled
FIN = FVCO
(disabled)
Pdiv3 = 0
EEPROM
^1_ = outputs 3-State
S0
^0_ = outputs 3-State
Programming Bus
SDA
SCL
PLL Bypass
(disabled)
Programming
and
SDA/SCL Register
Figure 5. CDCE813-Q1 Default Configuration
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VDD
VDDOUT
GND
Input Clock
M1
Vctr
LV
CMOS
Pdiv1 = 1
Pdiv2 = 0
Pdiv3 = 0
S0
Y2 = 3-state
LV
CMOS
Y3 = 3-state
Programming
and
SDA/SCL Register
^0_ = Y1 output 3-state
SDA
Programming Bus
(disabled)
PLL Bypass
EEPROM
^1_ = Y1 output enable
LV
CMOS
(disabled)
MUX1
PLL 1 enabled
FIN = FVCO
M2
LVCMOS
Y1 = enable
through S0 pin
M3
1.8V LVCMOS
CLK input
SCL
Figure 6. CDCE813R02-Q1 Default Configuration
Table 6 shows the factory default setting for the Control Terminal Register.
NOTE
Even though eight different register settings are possible, in the default configuration, only
the first two settings (0 and 1) can be selected with S0, as S1 and S2 are configured as
programming pins in default mode.
Table 6. Factory Default Setting for Control Terminal Register
Y1
GPN
EXTERNAL CONTROL PINS
S2
S1
2
CDCE813-Q1
CDCE813R02Q1
(1)
2
(1)
PLL1 SETTINGS
OUTPUT
SELECTION
FREQUENCY
SELECTION
SSC
SELECTION
OUTPUT
SELECTION
S0
Y1
FS1
SSC1
Y2Y3
SCL (I C)
SDA (I C)
0
3-state
fVCO1_0
Off
3-state
SCL (I2C)
SDA (I2C)
1
3-state
fVCO1_0
Off
3-state
SCL (I2C)
SDA (I2C)
0
3-state
fVCO1_0
Off
3-state
SCL (I2C)
SDA (I2C)
1
Enabled
fVCO1_0
Off
3-state
In default mode or when programmed respectively, S1 and S2 act as serial programming interface, I2C. They do not have any controlpin function but they are internally interpreted as if S1 = 0 and S2 = 0. For the CDCE813-Q1, S0 is an unused control pin by default. For
the CDCE813R02-Q1, S0 provides output enable (OE) control output Y1 only.
9.3.3 I2C Serial Interface
The CDCE813-Q1 device operates as a slave device on the 2-wire serial I2C bus compatible with the popular
SMBus or I2C specification. It operates in the standard-mode transfer (up to 100 kbps) and fast-mode transfer
(up to 400 kbps) and supports 7-bit addressing.
The S1/SDA and S2/SCL pins of the CDCE813-Q1 device are dual-function pins. In the default configuration,
they are used as the I2C serial programming interface. They can be reprogrammed as general-purpose control
pins, S1 and S2, by changing the corresponding EEPROM setting, byte 02h, bit [6].
9.3.4 Data Protocol
The device supports Byte Write and Byte Read and Block Write and Block Read operations.
For Byte Write/Read operations, the system controller can individually access addressed bytes.
For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with
most-significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of
bytes read out are defined by Byte Count in the generic configuration register. At the Block Read instruction, all
bytes defined in Byte Count must be read out to finish the read cycle correctly.
14
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Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to
each transferred byte, regardless of whether this is a Byte Write or a Block Write sequence.
If the EEPROM write cycle is initiated, the internal SDA registers are written into the EEPROM. During this write
cycle, data is not accepted at the I2C bus until the write cycle is completed. However, data can be read out
during the programming sequence (Byte Read or Block Read). The programming status can be monitored by
EEPIP, byte 01h–bit 6.
The offset of the indexed byte is encoded in the command code, as described in Table 7.
Table 7. Slave Receiver Address (7 Bits)
A6
A5
A4
A3
A2
A1 (1)
A0 (1)
R/W
CDCE813-Q1
1
1
0
0
1
0
1
1/0
CDCEx925
1
1
0
0
1
0
0
1/0
CDCEx937
1
1
0
1
1
0
1
1/0
CDCEx949
1
1
0
1
1
0
0
1/0
DEVICE
(1)
Address bits A0 and A1 are programmable through the I2C bus (byte 01, bits [1:0]. This allows addressing up to 4 devices connected to
the same I2C bus. The least-significant bit of the address byte designates a write or read operation.
9.4 Device Functional Modes
9.4.1 SDA and SCL Hardware Interface
Figure 7 shows how the CDCE813-Q1 clock synthesizer is connected to the I2C serial interface bus. Multiple
devices can be connected to the bus, but it may be necessary to reduce the speed (400 kHz is the maximum) if
many devices are connected.
Note that the pullup resistors (RP) depend on the supply voltage, bus capacitance, and number of connected
devices. The recommended pullup value is 4.7 kΩ. The resistor must meet the minimum sink current of 3 mA at
VOLmax = 0.4 V for the output stages (for more details see the SMBus or I2C Bus specifications in the Timing
Requirements table).
CDCE813-Q1
Rp
Rp
Master
Slave
SDA
SCL
CBUS CBUS
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Figure 7. I2C Hardware Interface
9.5 Programming
Table 8. Command Code Definition
BIT
7
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
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Programming (continued)
Table 8. Command Code Definition (continued)
BIT
DESCRIPTION
(6:0)
Byte offset for Byte Read, Block Read, Byte Write, and Block Write operations
1
S
7
Slave Address
1
R/W
MSB
LSB
S
Start Condition
Sr
Repeated Start Condition
1
A
8
Data Byte
1
A
MSB
1
P
LSB
1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx
R/W
A
Acknowledge (ACK = 0 and NACK =1)
P
Stop Condition
Master-to-Slave Transmission
Slave-to-Master Transmission
Figure 8. Generic Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
CommandCode
1
A
8
Data Byte
1
A
1
P
7
Slave Address
1
Rd
1
A
1
A
1
P
Figure 9. Byte Write Protocol
1
S
7
Slave Address
1
Wr
1
A
8
Data Byte
1
A
1
P
8
CommandCode
1
A
1
Sr
Figure 10. Byte Read Protocol
1
S
(1)
7
Slave Address
1
Wr
8
Data Byte 0
1
A
1
A
8
CommandCode
8
Data Byte 1
1
A
1
A
8
Byte Count = N
8
Data Byte N-1
…
1
A
Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose
and should not be overwritten.
Figure 11. Block Write Protocol
1
S
7
Slave Address
1
Wr
8
Byte Count N
1
A
1
A
8
CommandCode
8
Data Byte 0
1
A
1
A
1
Sr
…
7
Slave Address
1
Rd
1
A
8
Data Byte N-1
1
A
1
P
Figure 12. Block Read Protocol
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P
S
tw(SCLL)
Bit 7 (MSB)
tw(SCLH)
Bit 6
tr
Bit 0 (LSB)
A
P
tf
VIH
SCL
VIL
tsu(START)
th(START)
tsu(SDA)
th(SDA)
t(BUS)
tsu(STOP)
tf
tr
VIH
SDA
VIL
Figure 13. Timing Diagram for I2C Serial Control Interface
9.6 Register Maps
9.6.1 I2C Configuration Registers
The clock input, control pins, PLLs, and output stages are user configurable. The following tables and
explanations describe the programmable functions of the CDCE813-Q1 device. All settings can be manually
written into the device through the I2C bus or easily programmed by using the TI ClockPro™ programming
software. The TI ClockPro™ programming software allows the user to make all settings quickly, and
automatically calculates the values for optimized performance at lowest jitter.
Table 9. I2C Registers
ADDRESS OFFSET
REGISTER DESCRIPTION
TABLE
00h
Generic configuration register
Table 11
10h
PLL1 configuration register
Table 12
The grey-highlighted bits, described in the configuration register tables in the following pages, belong to the
control terminal register. The user can predefine up to eight different control settings. These settings then can be
selected by the external control pins, S0, S1, and S2. See the Control Terminal Configuration section.
Table 10. Configuration Register, External Control Terminals
Y1
EXTERNAL
CONTROL PINS
OUTPUT SELECTION
FREQUENCY SELECTION
SSC SELECTION
OUTPUT
SELECTION
S2
S1
S0
Y1
FS1
SSC1
Y2Y3
0
0
0
0
Y1_0
FS1_0
SSC1_0
Y2Y3_0
1
0
0
1
Y1_1
FS1_1
SSC1_1
Y2Y3_1
2
0
1
0
Y1_2
FS1_2
SSC1_2
Y2Y3_2
3
0
1
1
Y1_3
FS1_3
SSC1_3
Y2Y3_3
4
1
0
0
Y1_4
FS1_4
SSC1_4
Y2Y3_4
5
1
0
1
Y1_5
FS1_5
SSC1_5
Y2Y3_5
6
1
1
0
Y1_6
FS1_6
SSC1_6
Y2Y3_6
7
1
1
1
Y1_7
FS1_7
SSC1_7
Y2Y3_7
04h
13h
10h–12h
15h
Address offset (1)
(1)
PLL1 SETTINGS
Address offset refers to the byte address in the configuration register in Table 11 and Table 12.
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Table 11. Generic Configuration Register
OFFSET
00h
01h
(1)
BIT
(2)
ACRONYM
DEFAULT
(3)
DESCRIPTION
7
E_EL
1b
Device identification (read-only): 1 is CDCE813-Q1 (3.3 Vout)
6:4
RID
Xb
Revision identification number (read-only)
3:0
VID
1h
Vendor identification number (read-only)
7
—
0b
Reserved – always write 0
6
EEPIP
0b
EEPROM programming Status: (4) (read-only)
0 – EEPROM programming is completed.
1 – EEPROM is in programming mode.
5
EELOCK
0b
Permanently lock EEPROM data (5)
0 – EEPROM is not locked.
1 – EEPROM is permanently locked.
4
PWDN
0b
Device power down (overwrites S0, S1, and S2 settings; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – Device active (PLL1 and all outputs are enabled)
1 – Device power down (PLL1 in power down and all outputs in Hi-Z state)
3:2
INCLK
10b
00 – Xtal
10 – LVCMOS
01 – VCXO
11 – Reserved
Input clock selection:
1:0
SLAVE_AD
R
01b
Address bits A0 and A1 of the slave receiver address
7
M1
1b
Clock source selection for output Y1:
0 – Input clock
1 – PLL1 clock
Operation mode selection for pins 12 and 13 (6)
02h
6
SPICON
0b
5:4
Y1_ST1
CDCE813-Q1: 01b
CDCE813R02-Q1:
11b
3:2
Y1_ST0
01b
1:0
Pdiv1 [9:8]
7:0
Pdiv1 [7:0]
7
Y1_7
0b
6
Y1_6
0b
5
Y1_5
0b
4
Y1_4
0b
3
Y1_3
0b
2
Y1_2
0b
1
Y1_1
CDCE813-Q1: 0b
CDCE813R02-Q1: 1b
0
Y1_0
0b
7:3
XCSEL
00h
001h
03h
04h
0 – Serial programming interface SDA (pin 13) and SCL (pin 12)
1 – Control pins S1 (pin 13) and S2 (pin 12)
Y1-State0/1 definition
00 – Device power down (all PLLs in power down and all
outputs in Hi-Z state)
01 – Y1 disabled to Hi-Z state
10-bit Y1-output-divider Pdiv1:
0 – Divider reset and stand-by
1 to 1023 – Divider value
Y1_x State selection (7)
0 – State0 (predefined by Y1_ST0)
1 – State1 (predefined by Y1_ST1)
Crystal load capacitor selection (8)
05h
2:0
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
18
0b
10 – Y1 disabled to low
11 – Y1 enabled
00h – 0 pF
01h – 1 pF
02h – 2 pF
:14h to 1Fh – 20 pF
Reserved – do not write other than 0
Writing data beyond 20h may affect device function.
All data transferred with the MSB first
Unless customer-specific setting
During EEPROM programming, no data is allowed to be sent to the device through the I2C bus until the programming sequence is
completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).
If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible.
Data, however can still be written through the I2C bus to the internal register to change device function on the fly, but new data can no
longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM.
Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no
longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporarily act as serial programming pins
(SDA-SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.
These are the bits of the control terminal register (see Table 10 ). The user can predefine up to eight different control settings. These
settings then can be selected by the external control pins, S0, S1, and S2.
The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors should be used only to
finely adjust CL by a few picofarads. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20
pF. For CL > 20 pF, use additional external capacitors. The device input capacitance value must be considered, which always adds 1.5
pF (6 pF//2 pF) to the selected CL. For more about VCXO configuring and crystal recommendation, see application report VCXO
Application Guideline for CDCE(L)9xx Family (SCAA085).
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Table 11. Generic Configuration Register (continued)
OFFSET
(1)
ACRONYM
DEFAULT (3)
7:1
BCOUNT
00h
7-bit byte count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes
must be read out to finish the read cycle correctly.
0
EEWRITE
0b
Initiate EEPROM write cycle
—
0h
Unused address range
BIT
(2)
DESCRIPTION
06h
07h-0Fh
(9)
(4) (9)
0– No EEPROM write cycle
1 – Start EEPROM write cycle (internal registers are saved to the EEPROM)
The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The
EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level-high does not trigger an EEPROM WRITE cycle. The
EEWRITE bit must be reset to low after the programming is completed. The programming status can be monitored by reading out
EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
Table 12. PLL1 Configuration Register
OFFSET
10h
11h
12h
13h
14h
15h
(1)
(2)
(3)
(4)
(1)
ACRONYM
DEFAULT (3)
7:5
SSC1_7 [2:0]
000b
4:2
SSC1_6 [2:0]
000b
1:0
SSC1_5 [2:1]
7
SSC1_5 [0]
6:4
SSC1_4 [2:0]
000b
3:1
SSC1_3 [2:0]
000b
0
SSC1_2 [2]
7:6
SSC1_2 [1:0]
5:3
SSC1_1 [2:0]
000b
2:0
SSC1_0 [2:0]
000b
7
FS1_7
0b
6
FS1_6
0b
5
FS1_5
0b
4
FS1_4
0b
3
FS1_3
0b
2
FS1_2
0b
1
FS1_1
0b
0
FS1_0
0b
7
MUX1
0b
PLL1 multiplexer:
0 – PLL1
1 – PLL1 bypass (PLL1 is in power down)
6
M2
1b
Output Y2 multiplexer:
0 – Pdiv1
1 – Pdiv2
5:4
M3
10b
Output Y3 Multiplexer:
00 –
01 –
10 –
11 –
3:2
Y2Y3_ST1
00b
00 – Y2 and Y3 disabled to Hi-Z state (PLL1 is in power down)
01 – Y2 and Y3 disabled to Hi-Z state
10–Y2 and Y3 disabled to low
11 – Y2 and Y3 enabled
BIT
(2)
000b
000b
DESCRIPTION
SSC1: PLL1 SSC selection (modulation amount).
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
(4)
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS1_x: PLL1 frequency selection (4)
0 – fVCO1_0 (predefined by PLL1_0 – multiplier/divider value)
1 – fVCO1_1 (predefined by PLL1_1 – multiplier/divider value)
1:0
Y2Y3_ST0
01b
Y2, Y3State0/1definition:
7
Y2Y3_7
0b
Y2Y3_x output state selection.
6
Y2Y3_6
0b
5
Y2Y3_5
0b
4
Y2Y3_4
0b
3
Y2Y3_3
0b
2
Y2Y3_2
0b
1
Y2Y3_1
0b
0
Y2Y3_0
0b
Pdiv1-divider
Pdiv2-divider
Pdiv3-divider
Reserved
(4)
0 – State0 (predefined by Y2Y3_ST0)
1 – State1 (predefined by Y2Y3_ST1)
Writing data beyond 20h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 12. PLL1 Configuration Register (continued)
OFFSET
(1)
BIT
(2)
ACRONYM
DEFAULT (3)
7
SSC1DC
0b
6:0
Pdiv2
00h
7-bit Y2-output-divider Pdiv2:
7
—
0b
Reserved – do not write other than 0
6:0
Pdiv3
00h
7-bit Y3-output-divider Pdiv3:
7:0
PLL1_0N [11:4]
7:4
PLL1_0N [3:0]
3:0
PLL1_0R [8:5]
7:3
PLL1_0R[4:0]
2:0
PLL1_0Q [5:3]
7:5
PLL1_0Q [2:0]
4:2
PLL1_0P [2:0]
100b
1:0
VCO1_0_RANGE
00b
7:0
PLL1_1N [11:4]
7:4
PLL1_1N [3:0]
3:0
PLL1_1R [8:5]
7:3
PLL1_1R[4:0]
2:0
PLL1_1Q [5:3]
7:5
PLL1_1Q [2:0]
4:2
PLL1_1P [2:0]
100b
1:0
VCO1_1_RANGE
00b
16h
17h
18h
19h
1Ah
DESCRIPTION
PLL1 SSC down or center
selection:
1Dh
1Eh
1Fh
(5)
20
0 – Reset and standby
1 to 127 – Divider value
0 – Reset and standby
1 to 127 – Divider value
1FFh
000h
PLL1_0 (5): 30-bit multiplier or divider value for frequency fVCO1_0
(for more information, see PLL Frequency Planning).
10h
1Bh
1Ch
0 – Down
1 – Center
fVCO1_0 range selection:
00 –
01 –
10 –
11 –
fVCO1_0 < 125 MHz
125 MHz ≤ fVCO1_0 < 150 MHz
150 MHz ≤ fVCO1_0 < 175 MHz
fVCO1_0 ≥ 175 MHz
1FFh
000h
PLL1_1 (5): 30-bit multiplier or divider value for frequency fVCO1_1
(for more information, see PLL Frequency Planning).
10h
fVCO1_1 range selection:
00 –
01 –
10 –
11 –
fVCO1_1 < 125 MHz
125 MHz ≤ fVCO1_1 < 150 MHz
150 MHz ≤ fVCO1_1 < 175 MHz
fVCO1_1 ≥ 175 MHz
PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The CDCE813-Q1 device is an easy-to-use, high-performance, programmable CMOS clock synthesizer which
can be used as a crystal buffer, clock synthesizer with separate output supply pin. The CDCE813-Q1 device
features an on-chip loop filter and spread-spectrum modulation. Programming can be done through the I2C
interface, or previously saved settings can be loaded from on-chip EEPROM. The pins S0, S1, and S2 can be
programmed as control pins to select various output settings. This section shows some examples of using the
CDCE813-Q1 device in various applications.
10.2 Typical Application
Figure 14 shows the application example of CDCE813-Q1 in combination with an SoC processor and an FPDLink3 serializer, serving as a PCLK jitter cleaner.
VDD_1p8
VDDO_3p3
L1
L2
120 Q
120 Q
C6
0.1µF
C1
0.1 …F
C2
0.01 …F
C4
1000pF
C3
1000 pF
3
R1
U1
GND
PCLK
4.7k
R3
860 Q
R4
4
1
14
U2
VDD
VDDOUT
VDDOUT
VCTRL
Y1
XIN/CLK
Y2
XOUT
1 lQ
GND
Y3
13
12
C5
0.01µF
S0
SDA
SCL
GND
GND
6
7
11
R2
9
18 Q
GND
8
U3
PCLK
5
10
CDCE813-Q1
SoC
GND
Serializer
To Display
Image Data
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Figure 14. PCLK Jitter Cleaner Reference Design
10.2.1 Design Requirements
The CDCE813-Q1 device supports spread-spectrum clocking (SSC) with multiple control parameters:
• Modulation amount (%)
• Modulation frequency (>20 kHz)
• Center spread or down spread (± or –)
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Typical Application (continued)
Figure 15. Modulation Frequency (fm) and Modulation Amount
10.2.2 Detailed Design Procedure
10.2.2.1 Spread-Spectrum Clock (SSC)
Spread-spectrum modulation is a method to spread emitted energy over a larger bandwidth. In clocking, spread
spectrum can reduce electromagnetic interference (EMI) by reducing the level of emission from clock distribution
network.
CDCS502 with a 25-MHz Crystal, FS = 1, fOUT = 100 MHz, and 0%, ±0.5, ±1%, and ±2% SSC
Figure 16. Comparison Between Typical Clock Power Spectrum and Spread-Spectrum Clock
Spread spectrum clocking can be used to help reduce EMI to meet design specifications. For example, a
specified EMI threshold of 55 dB/mV would require ±1% spread-spectrum clocking to meet this requirement.
22
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Typical Application (continued)
10.2.2.2 PLL Frequency Planning
At a given input frequency (fIN), the output frequency (fOUT) of the CDCE813-Q1 device is calculated with
Equation 1.
ƒ
N
ƒOUT = IN ´
Pdiv M
•
•
M (1 to 511) and N (1 to 4095) are the multiplier or divider values of the PLL,
and Pdiv (1 to 127) is the output divider.
The target VCO frequency (ƒVCO) of each PLL is calculated with Equation 2.
N
ƒ VCO = ƒIN ´
M
(1)
(2)
The PLL internally operates as fractional divider and needs the following multiplier or divider settings:
• N
• P = 4 – int(log2N / M); if P < 0 then P = 0
• Q = int(N' / M)
• R = N′ – M × Q
where
• int(X) = integer portion of X
• N′ = N × 2P
• N≥M
80 MHz ≤ ƒVCO ≤ 230 MHz
16 ≤ Q ≤ 63
0≤P≤4
0 ≤ R ≤ 51
Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2
for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2
→ fOUT = 54 MHz
→ fOUT = 74.25 MHz
→ fVCO = 108 MHz
→ fVCO = 148.50 MHz
→ P = 4 – int(log24) = 4 – 2 = 2
→ P = 4 – int(log25.5) = 4 – 2 = 2
2
→ N' = 4 × 2 = 16
→ N' = 11 × 22 = 44
→ Q = int(16) = 16
→ Q = int(22) = 22
→ R = 16 – 16 = 0
→ R = 44 – 44 = 0
The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.
10.2.2.3 Crystal Oscillator Start-Up
When the CDCE813-Q1 device can be used as a crystal buffer, the crystal oscillator start-up dominates the startup time compared to the internal PLL lock time. Figure 17 shows the oscillator start-up sequence for a 27-MHz
crystal input with an 8-pF load. The start-up time for the crystal is on the order of approximately 250 µs
compared to approximately 10 µs of lock time. In general, lock time is an order of magnitude less compared to
the crystal start-up time.
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Typical Application (continued)
Figure 17. Crystal Oscillator Start-Up vs PLL Lock Time
10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
The frequency for the CDCE813-Q1 device is adjusted for media and other applications with the VCXO control
input Vctr. If a PWM-modulated signal is used as a control signal for the VCXO, an external filter is needed.
LP
PWM
control
signal
CDCE813-Q1
Vctrl
Xin/CLK
Xout
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Figure 18. Frequency Adjustment Using PWM Input to the VCXO Control
10.2.2.5 Unused Inputs and Outputs
If VCXO-pulling functionality is not required, Vctr should be left floating. All other unused inputs should be set to
GND. Unused outputs should be left floating.
If one output block is not used, TI recommends disabling it. However, TI recommends providing a supply for all
output blocks, even if they are disabled.
10.2.2.6 Switching Between XO and VCXO Mode
When the CDCE813-Q1 device is in the crystal-oscillator or VCXO configuration, the internal capacitors require
different internal capacitance. The following steps are recommended to switch to VCXO mode when the
configuration for the on-chip capacitor is still set for XO mode. To center the output frequency to 0 ppm:
1. While in XO mode, put Vctr = VDD / 2
2. Switch from XO mode to VCXO mode
3. Program the internal capacitors to obtain 0 ppm at the output.
24
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Typical Application (continued)
10.2.3 Application Curves
Figure 19, Figure 20, Figure 21, and Figure 22 show CDCE813-Q1 measurements with the SSC feature enabled.
Device configuration: 27-MHz input, 27-MHz output.
Figure 19. fOUT = 27 MHz,
VCO frequency < 125 MHz, SSC (2% Center)
Figure 20. fOUT = 27 MHz,
VCO frequency > 175 MHz, SSC (1%, Center)
Figure 21. Output Spectrum With SSC Off
Figure 22. Output Spectrum With SSC On,
2% Center
11 Power Supply Recommendations
There is no restriction on the power-up sequence. In case VDDOUT is applied first, TI recommends grounding the
VDD. In case VDDOUT is powered while VDD is floating, there is a risk of high current flowing on the VDDOUT pins.
The device has a power-up control that is connected to the 1.8-V supply. This keeps the whole device disabled
until the 1.8-V supply reaches a sufficient voltage level. Then the device switches on all internal components,
including the outputs. If a 3.3-V VDDOUT is available before the 1.8-V, the outputs stay disabled until the 1.8-V
supply has reached a certain level.
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12 Layout
12.1 Layout Guidelines
When the CDCE813-Q1 device is used as a crystal buffer, any parasitic across the crystal affect the pulling
range of the VCXO. Therefore, take care in placing the crystal units on the board. Crystals must be placed as
close to the device as possible, ensuring that the routing lines from the crystal terminals to Xin and Xout have the
same length.
If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the
device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise
coupling.
Additional discrete capacitors can be required to meet the load capacitance specification of certain crystals. For
example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can
range from 0 pF to 20 pF with steps of 1 pF. The 0.7-pF capacitor therefore can be discretely added on top of an
internal 10-pF capacitor.
To minimize the inductive influence of the trace, TI recommends placing this small capacitor as close to the
device as possible and symmetrically with respect to Xin and Xout.
Figure 23 shows a conceptual layout detailing recommended placement of power-supply bypass capacitors. For
component-side mounting, use 0402 body-size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low-impedance connection to the ground plane.
12.2 Layout Example
1
4
3
2
1
Place crystal with associated load
capacitors close to the chip.
3
Place bypass capacitors close to the
device pins; ensure wide frequency range.
2
Place series termination resistors at
clock outputs to improve signal integrity.
4
Use ferrite beads to isolate the device
supply pins from board noise sources.
Figure 23. Annotated Layout
26
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• VCXO Application Guideline for CDCE(L)9xx Family (SCAA085)
• Practical Consideration on Choosing a Crystal for CDCE(L)9xx Family (SLEA071)
• General I2C/EEPROM Usage for the CDCE(L)9xx Family (SCAA104)
• Crystal Or Crystal Oscillator Replacement with Silicon Devices (SNAA217)
• Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)813 (SCAA105)
• Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency Word Clock (SCAA088)
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
DaVinci, OMAP, ClockPro, E2E are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCE813QPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
CE813Q
CDCE813R02TPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
E813Q02
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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