CDCE949-Q1
www.ti.com
SCAS891 – FEBRUARY 2010
PROGRAMMABLE 4-PLL VCXO CLOCK SYNTHESIZER
WITH 1.8-V, 2.5-,V and 3.3-V LVCMOS OUTPUTS
Check for Samples: CDCE949-Q1
FEATURES
1
•
•
•
•
Qualified for Automotive Applications
Member of Programmable Clock Generator
Family
– CDCE913/CDCEL913: 1 PLLs, 3 Outputs
– CDCE925/CDCEL925: 2 PLLs, 5 Outputs
– CDCE937/CDCEL937: 3 PLLs, 7 Outputs
– CDCE949: 4 PLLs, 9 Outputs
In-System Programmability and EEPROM
– Serial Programmable Volatile Register
– Non-Volatile EEPROM to Store Customer
Settings
Highly Flexible Clock Driver
– Three User-Definable Control Inputs
[S0/S1/S2]; e.g,. SSC-Selection, Frequency
Switching, Output Enable or Power Down
– Generates Highly-Accurate Clocks for
Video, Audio, USB, IEEE1394, RFID,
Generates Common Clock Frequencies
Used with TI DaVinci™, OMAP™, DSPs
– BlueTooth™, WLAN, Ethernet and GPS
– Programmable SSC Modulation
– Enables 0-PPM Clock Generation
VDD
•
•
•
•
•
•
•
•
•
Selectable Output Frequency up to 230 MHz
Flexible Input Clocking Concept
– External Crystal: 8 to 32 MHz
– On-Chip VCXO: Pull-Range ±150 ppm
– Single-Ended LVCMOS up to 160 MHz
Low-Noise PLL Core
– Integrated PLL Loop Filter Components
– Very Low Period Jitter (typ 60 ps)
Separate Output Supply Pins
– 3.3 V and 2.5 V
1.8 V Device Power Supply
Latch-Up Performace Meets 100 mA
Per JESD 78, Class I
Wide Temperature Range –40°C to 125°C
Packaged in TSSOP
Development and Programming Kit for Ease
PLL Design and Programming (TI-Pro Clock)
APPLICATIONS
•
•
D-TV, HD-TV, STB, IP-STB, DVD-Player,
DVD-Recorder, Printer
General Purpose Frequency Synthesizing
VDDOUT
GND
Crystal or
Clock Input
Vctr
VCXO
LV
CMOS
Y1
LV
CMOS
Y2
LV
CMOS
Y3
XO
LVCMOS
PLL1
3
S2/S1/S0 or
SDA/SCL
EEPROM
Programming
and
Control Register
with SSC
LV
CMOS
Y4
LV
CMOS
Y5
LV
CMOS
Y6
LV
CMOS
Y7
LV
CMOS
Y8
LV
CMOS
Y9
PLL2
with SSC
Divider
and
Output
Control
PLL3
with SSC
Xin/Clk
S0
Vdd
Vctr
GND
Vddout
Y4
Y5
GND
Vddout
Y8
Y9
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Xout
S1/SDA
S2/SCL
Y1
GND
Y2
Y3
Vddout
Y6
Y7
GND
Vdd
PLL4
with SSC
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CDCE949-Q1
SCAS891 – FEBRUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The CDCE949 is a modular PLL-based low-cost high-performance programmable clock synthesizer, multiplier,
and divider. It generates up to 9 output clocks from a single input frequency. Each output can be programmed
in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs.
The CDCE949 has separate output supply pins, VDDOUT, of 2.5 V to 3.3 V.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.
Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external
control signal, that is, a PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth™,
Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as
27 MHz.
All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This
is a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically
adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.
The device supports non-volatile EEPROM programming for easy customization of the device to the application.
It is preset to a factory-default configuration (see the Default Device Configuration section). It can be
reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system
programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including
frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing
between low level or 3-state for the output-disable function.
The CDCE949 operates in a 1.8 V environment. It operates within a temprateure range of –40°C to 125°C.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
2
TSSOP – PW
Reel of 2000
ORDERABLE PART NUMBER
CDCE949QPWRQ1
TOP-SIDE MARKING
CDCE949Q
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
NO.
21, 19, 18, 7, 8,
16, 15, 11, 12
Y1, Y2, ...Y9
O
LVCMOS outputs
Xin/CLK
1
I
Crystal oscillator input or LVCMOS clock input (selectable via SDA/SCL bus)
Xout
24
O
Crystal oscillator output (leave open or pull up when not used)
VCtrl
4
I
VCXO control voltage (leave open or pull up when not used)
VDD
3, 13
Power
1.8V power supply for the device
6, 10, 17
Power
3.3-V or 2.5-V supply for all outputs
5, 9, 14, 20
Ground
Ground
S0
2
I
SDA / S1
23
I/O / I
SDA: Bidirectional serial data input/output (default configuration), LVCMOS; internal
pullup 500 kΩ; or
S1: User-programmable control input; LVCMOS inputs; internal pullup 500 kΩ
SCL / S2
22
I
SCL: Serial clock input (default configuration), LVCMOS; internal pullup 500 kΩ; or
S2: User-programmable control input; LVCMOS inputs; internal pullup 500 kΩ
VDDOUT
GND
User-programmable control input S0; LVCMOS inputs; internal pullup 500 kΩ
FUNCTIONAL BLOCK DIAGRAM
VDD
VDDOUT
GND
LV
CMOS
Y1
M2
LV
CMOS
Y2
M3
LV
CMOS
Y3
M4
LV
CMOS
Y4
M5
LV
CMOS
Y5
M6
LV
CMOS
Y6
M7
LV
CMOS
Y7
M8
M1
Xin/CLK
LV
CMOS
Y8
M9
Input Clock
Vctr
LV
CMOS
Y9
Pdiv1
10-Bit
VCXO
XO
with SSC
Xout
Pdiv2
PLL 1
MUX1
LVCMOS
7-Bit
Pdiv3
S0
S1/SDA
S2/SCL
Programming
and
SDA/SCL
Register
PLL Bypass
7-Bit
Pdiv4
PLL 2
with SSC
MUX2
EEPROM
Pdiv6
MUX3
PLL 3
7-Bit
Pdiv7
7-Bit
PLL Bypass
Pdiv8
MUX4
PLL 4
with SSC
Pdiv5
7-Bit
PLL Bypass
with SSC
7-Bit
7-Bit
Pdiv9
PLL Bypass
7-Bit
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
–0.5 to 2.5
V
–0.5 to VDD + 0.5
V
–0.5 to VDDOUT + 0.5
V
Input current (VI < 0, VI > VDD)
20
mA
Continuous output current
50
mA
Storage temperature range
–65 to 150
°C
VDD
Supply voltage range
VI
Input voltage range (2)
VO
Output voltage range (2)
II
IO
Tstg
(1)
(2)
(3)
(1)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed.
SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table.
THERMAL RESISTANCE (1)
PARAMETER
Thermal resistance, junction to ambient
qJA
AIRFLOW
(lfm)
°C/W
0
91
150
75
200
74
250
73
500
65
27
qJC
Thermal resistance, junction to case
—
qJB
Thermal resistance, junction to board
—
52
RqJT
Thermal resistance, junction to top
—
0.5
RqJB
Thermal resistance, junction to bottom
—
50
(1)
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
VDD
Device supply voltage
1.7
1.8
1.9
V
VDD(OUT)
Output Yx supply voltage
2.3
3.6
V
VIL
Low level input voltage LVCMOS
0.3 × VDD
V
VIH
High level input voltage LVCMOS
VI(thresh)
Input voltage threshold LVCMOS
VIS
VICLK
IOH /IOL
Input voltage range S1, S2, SDA, SCL
VIthresh = 0.5 VDD
Input voltage range CLK
Output current
Output load LVCMOS
TJ
Operating junction temperature
V
0.5 × VDD
Input voltage range S0
CL
4
0.7 × VDD
V
0
1.9
0
3.6
0
UNIT
V
1.9
V
VDDout = 3.3 V
±12
mA
VDDout = 2.5 V
±10
mA
VDDout = 1.8 V
±8
mA
10
pF
125
°C
–40
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SCAS891 – FEBRUARY 2010
RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS (1)
fXtal
Crystal Input frequency range (fundamental mode)
ESR
Effective series resistance
(2)
fPR
Pulling range (0 V ≤ VCtrl ≤ 1.8 V)
V(Ctrl)
Frequency control voltage
C0/C1
Pullability ratio
CL
On-chip load capacitance at Xin and Xout
(1)
(2)
MIN
NOM
MAX
UNIT
8
27
32
MHz
100
Ω
±120
±150
ppm
0
VDD
V
220
0
20
pF
For more information about VCXO configuration and crystal recommendation see application report SCAA085.
Pulling range depends on crystal type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm
applies for crystal listed in the application report SCAA085.
EEPROM SPECIFICATION
MIN
EEcyc
EEcyc programming cycles of EEPROM
EEret
EEret data retention
TYP
MAX
UNIT
1000
cycles
10
years
CLK_IN TIMING REQUIREMENTS
over recommended ranges of supply voltage, load and operating free-air temperature
MIN
NOM
MAX
PLL Bypass Mode
0
160
PLL Mode
8
160
f(CLK)
LVCMOS clock input frequency
tr / tf
Rise and fall time CLK signal (20% to 80%)
dutyCLK
Duty cycle CLK at VDD / 2
UNIT
MHz
3
40%
ns
60%
SDA/SCL TIMING REQUIREMENTS
see Figure 11
STANDARD
MODE
FAST
MODE
UNIT
MIN
MAX
MIN
MAX
0
100
0
400
f(SCL)
SCL clock frequency
tsu(START)
START setup time (SCL high before SDA low)
th(START)
START hold time (SCL low after SDA low)
tw(SCLL)
SCL low-pulse duration
tw(SCLH)
SCL high-pulse duration
th(SDA)
SDA hold time (SDA valid after SCL low)
tsu(SDA)
SDA setup time
tr
SCL/SDA input rise time
tf
SCL/SDA input fall time
tsu(STOP)
STOP setup time
4.0
0.6
ms
tBUF
Bus free time between a STOP and START condition
4.7
1.3
ms
4.7
0.6
ms
4
0.6
ms
4.7
1.3
ms
4
0.6
ms
0
3.45
250
0
0.9
100
1000
300
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ns
300
300
Copyright © 2010, Texas Instruments Incorporated
kHz
ns
ns
5
CDCE949-Q1
SCAS891 – FEBRUARY 2010
www.ti.com
DEVICE CHARACTERISTICS
over recommended operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX
UNIT
OVERALL PARAMETER
All PLLs on
IDD
Supply current (see Figure 3)
All outputs off, fCLK = 27
MHz, fVCO= 135 MHz
IDD(OUT)
Supply current (see Figure 4)
No load, all outputs on, fout = 27 MHz,
VDDOUT = 3.3 V
IDD(PD)
Power down current. Every circuit
powered down except SDA/SCL.
fIN = 0 MHz, VDD = 1.9 V
V(PUC)
Supply voltage VDD threshold for power
up control circuit
fVCO
VCO frequency range of PLL
fOUT
LVCMOS output frequency
38
Per PLL
mA
9
4
mA
50
?A
0.85
1.45
V
80
230
MHz
230
MHz
LVCMOS PARAMETER
VIK
LVCMOS input voltage
VDD = 1.7 V; II = –18 mA
II
LVCMOS input current
VI = 0 V or VDD; VDD = 1.9 V
IIH
LVCMOS input current for S0/S1/S2
VI = VDD; VDD = 1.9 V
IIL
LVCMOS input current for S0/S1/S2
VI = 0 V; VDD = 1.9 V
Input capacitance at Xin/Clk
VICLK = 0 V or VDD
6
Input capacitance at Xout
VIXout = 0 V or VDD
2
Input capacitance at S0/S1/S2
VIS = 0 V or VDD
3
CI
–1.2
V
±5
?A
5
?A
–4
?A
pF
LVCMOS PARAMETER FOR VDDOUT = 3.3 V – MODE
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
VDDOUT = 3 V, IOH = –0.1 mA
2.9
VDDOUT = 3 V, IOH = –8 mA
2.4
VDDOUT = 3 V, IOH = –12 mA
2.2
V
VDDOUT = 3 V, IOL = 0.1 mA
0.1
VDDOUT = 3 V, IOL = 8 mA
0.5
VDDOUT = 3 V, IOL = 12 mA
0.8
tPLH,
tPHL
Propagation delay
PLL bypass
3.2
tr/tf
Rise and fall time
VDDOUT = 3.3 V (20%–80%)
0.6
1 PLL switching, Y2-to-Y3
60
90
4 PLLs switching, Y2-to-Y9
120
170
1 PLL switching, Y2-to-Y3
70
100
4 PLLs switching, Y2-to-Y9
130
180
tjit(cc)
Cycle-to-cycle jitter (2)
tjit(per)
Peak-to-peak period jitter
tsk(o)
Output skew (4)
odc
Output duty cycle (5)
(1)
(2)
(3)
(4)
(5)
6
(3)
(2) (3)
fOUT = 50 MHz; Y1-to-Y3
fVCO = 100 MHz; Pdiv = 1
ns
ns
60
fOUT = 50 MHz; Y2-to-Y5 or Y6-to-Y9
160
45
V
55
ps
ps
ps
%
All typical values are at respective nominal VDD.
10000 cycles.
Jitter depends on device configuration. Data is taken under the following conditions: 1-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (measured at
Y2), 4-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (manured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz, Y8/9 = 48 MHz.
The tsk(o) specification is only valid for equal loading of each bank of outputs and outputs are generated from the same divider; data
sampled on rising edge (tr).
odc depends on output rise- and fall-time (tr/tf).
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SCAS891 – FEBRUARY 2010
DEVICE CHARACTERISTICS (continued)
over recommended operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX
UNIT
LVCMOS PARAMETER FOR VDDOUT = 2.5 V – MODE
VOH
VOL
LVCMOS high-level output voltage
LVCMOS low-level output voltage
VDDOUT = 2.3 V, IOH = –0.1 mA
2.2
VDDOUT = 2.3 V, IOH = –6 mA
1.7
VDDOUT = 2.3 V, IOH = –10 mA
1.6
V
VDDOUT = 2.3 V, IOL = 0.1 mA
0.1
VDDOUT = 2.3 V, IOL = 6 mA
0.5
VDDOUT = 2.3 V, IOL = 10 mA
0.7
tPLH,
tPHL
Propagation delay
PLL bypass
3.4
tr/tf
Rise and fall time
VDDOUT = 2.5 V (20%–80%)
0.8
1 PLL switching, Y2-to-Y3
60
90
4 PLLs switching, Y2-to-Y9
120
170
1 PLL switching, Y2-to-Y3
70
100
4 PLLs switching, Y2-to-Y9
130
180
tjit(cc)
Cycle-to-cycle jitter
(6) (7)
tjit(per)
Peak-to-peak period jitter
tsk(o)
Output skew (8)
odc
Output duty cycle (9)
(6) (7)
fOUT = 50 MHz; Y1-to-Y3
fVCO = 100 MHz; Pdiv = 1
ns
ns
60
fOUT = 50 MHz; Y2-to-Y5 or Y6-to-Y9
160
45
V
55
ps
ps
ps
%
SDA/SCL PARAMETER
VIK
SCL and SDA input clamp voltage
VDD = 1.7 V; II = –18 mA
–1.2
V
IIH
SCL and SDA input current
VI = VDD; VDD = 1.9 V
±10
?A
VIH
SDA/SCL input high voltage (10)
VIL
SDA/SCL input low voltage (10)
VOL
SDA low-level output voltage
IOL = 3 mA, VDD = 1.7 V
CI
SCL/SDA input capacitance
VI = 0 V or VDD
0.7 VDD
V
3
0.3
VDD
V
0.2
VDD
V
10
pF
(6)
(7)
10000 cycles.
Jitter depends on device configuration. Data is taken under the following conditions: 1-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (measured at
Y2), 4-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (manured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz, Y8/9 = 48 MHz.
(8) The tsk(o) specification is only valid for equal loading of each bank of outputs and outputs are generated from the same divider; data
sampled on rising edge (tr).
(9) odc depends on output rise- and fall-time (tr/tf).
(10) SDA and SCL pins are 3.3-V tolerant.
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PARAMETER MEASUREMENT INFORMATION
CDCE949
CDCEL949
1 kW
LVCMOS
1 kW
10 pF
Figure 1. Test Load
CDCE949
CDCEL949
LVCMOS
Typical Driver
Impedance
~ 32 W
LVCMOS
Series
Termination
~ 18 W
Line Impedance
Zo = 50 W
Figure 2. Test Load for 50 Ω Board Environment
8
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
PLL FREQUENCY
OUTPUT CURRENT
vs
OUTPUT FREQUENCY
100
90
35
VDD = 1.8 V
4 PLL on
70
25
3 PLL on
60
3 outputs on
IDDOUT - mA
IDD - Supply Current - mA
30
80
2 PLL on
1 PLL on
50
all PLL off
40
VDD = 1.8 V,
VDDOUT = 3.3 V,
9 outputs on
7 outputs on
No Load
5 outputs on
30
20
15
1 output on
all outputs off
10
20
5
10
0
10
60
110
160
PLL - Frequency - MHz
210
0
10
30
Figure 3.
50 70 90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 4.
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APPLICATION INFORMATION
Control Terminal Configuration
The CDCE949 has three user-definable control terminals (S0, S1 and S2) which allow external control of device
settings. They can be programmed to perform any of the following functions:
• Spread-Spectrum Clocking selection: Spread-type and spread-amount selection
• Frequency selection: Switching between any of two user-defined frequencies
• Output-State selection: Output configuration and power-down control
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.
Table 1. Control Terminal Definition
Output Y1 and Power Down Selection
Y1 Setting
Output Y8/Y9 Selection
SSC Selection
PLL Frequency Selection
PLL4 Setting
Output Y6/Y7 Selection
SSC Selection
PLL Frequency Selection
PLL3 Setting
Output Y4/Y5 Selection
SSC Selection
Output Y2/Y3 Selection
SSC Selection
Control Function
PLL2 Setting
PLL Frequency Selection
PLL1 Setting
PLL Frequency Selection
External Control-Bits
Table 2. PLLx Setting (can be selected for each PLL individual) (1)
SSC Selection (Center/Down)
SSCx [3-bits]
Center
Down
0
0
0
0% (off)
0% (off)
0
0
1
±0.25%
–0.25%
0
1
0
±0.5%
–0.5%
0
1
1
±0.75%
–0.75%
1
0
0
±1.0%
–1.0%
1
0
1
±1.25%
–1.25%
1
1
0
±1.5%
–1.5%
1
1
1
±2.0%
–2.0%
FREQUENCY SELECTION
(2)
FSx
FUNCTION
0
Frequency0
1
Frequency1
OUTPUT SELECTION (3) (Y2 ... Y9)
(1)
(2)
(3)
10
YxYx
FUNCTION
0
State0
1
State1
Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register;
Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,
3-state, low or active
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Table 3. Y1 Setting (1)
Y1 SELECTION
(1)
Y1
FUNCTION
0
State 0
1
State 1
State0 and State1 are user-definable in Generic Configuration
Register and can be power down, 3-state, low or active.
The S1/SDA and S2/SCL pins of the CDCE949 are dual-function pins. In the default configuration they are
defined as SDA/SCL for the serial interface. They can be programmed as control pins (S1/S2) by setting the
appropriate bits in the EEPROM. Note that changes to the Control register (Bit [6] of Byte 02) have no effect until
they are written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is
forced to GND, the two control-pins, S1 and S2, temporarily act as serial programming pins (SDA/SCL).
S0 is not a multi-use pin, it is a control pin only.
DEFAULT DEVICE SETTING
The internal EEPROM of CDCE949 is preconfigured as shown in Figure 5. (The input frequency is passed
through to the output as a default.) This allows the device to operate in default mode without the extra production
step of programming it. The default setting appears after power is supplied or after a power-down/up sequence
until it is reprogrammed by the user to a different application configuration. A new register setting is programmed
via the serial SDA/SCL Interface.
VDD
VDDOUT
GND
PLL 2
Pdiv4 = 1
Pdiv5 = 1
PLL Bypass
PLL 3
Pdiv6 = 1
Pdiv7 = 1
PLL Bypass
PLL 4
Y4 = 27 MHz
LV
CMOS
Y5 = 27 MHz
LV
CMOS
Y6 = 27 MHz
LV
CMOS
Y7 = 27 MHz
Pdiv8 = 1
LV
CMOS
Y8 = 27 MHz
LV
CMOS
Y9 = 27 MHz
MUX4
power down
LV
CMOS
MUX3
power down
M2
Pdiv3 = 1
PLL Bypass
power down
M3
SCL
M4
Programming Bus
Programming
and
SDA/SCL
Register
Y3 = 27 MHz
M5
S0
SDA
LV
CMOS
M6
“0” = outputs 3-State
Y2 = 27 MHz
MUX2
EEPROM
“1” = outputs enabled
Pdiv2 = 1
MUX1
Xout
M7
PLL 1
LV
CMOS
Pdiv1 =1
X-tal
power down
Y1 = 27MHz
M8
27 MHz
Crystal
LV
CMOS
M9
M1
Input Clock
Xin
PLL Bypass
Pdiv9 = 1
Figure 5. Default Configuration
Table 4 shows the default setting for the Control Terminal Register (external control pins). In normal operation, all
8 register settings are available, but in the default configuration only the first two settings (0 and 1) can be
selected with S0, as S1 and S2 are configured as programming pins in default mode.
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Table 4. Factory Default Setting for Control Terminal Register
Y1
EXTERNAL
CONTROL-PINS (1)
S2
S1
2
S0
2
PLL1 SETTING
PLL2 SETTING
PLL3 SETTING
PLL4 SETTING
Output
Select
Freq.
Select
SSC
Sel.
Output
Select
Freq.
Select
SSC
Sel.
Output
Select
Freq.
Select
SSC
Sel.
Output
Select
Freq.
Select
SSC
Sel.
Output
Select
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
FS3
SSC3
Y6Y7
FS4
SSC4
Y8Y9
SCL (I C)
SDA (I C)
0
3-State
fVCO1_0
off
3-State
fVCO2_0
off
3-State
fVCO3_0
off
3-State
fVCO4_0
off
3-State
SCL (I2C)
SDA (I2C)
1
enabled
fVCO1_0
off
enabled
fVCO2_0
off
enabled
fVCO3_0
off
enabled
fVCO4_0
off
enabled
(1)
In default mode or when programmed respectively, S1 and S2 act as a serial programming interface, SDA/SCL. In this mode, they have
no control-pin function, but are internally interpreted as if S1=0 and S2=0. S0, however, is a control-pin which in the default mode
switches all outputs ON or OFF (as pre-defined above).
SDA/SCL SERIAL INTERFACE
The CDCE949 operates as a slave device on the 2-wire serial SDA/SCL bus, compatible with the popular SMBus
or I2C™ specification. It operates in the standard-mode transfer (up to 100 kbps) and fast-mode transfer (up to
400 kbps) and supports 7-bit addressing.
The S1/SDA and S2/SCL pins of the CDC9xx are dual-function pins. In the default configuration they are used as
SDA/SCL serial programming interface. They can be reprogrammed as general purpose control pins, S1 and S2,
by changing the corresponding EEPROM setting, Byte 02, Bit [6].
DATA PROTOCOL
The device supports Byte Write and Byte Read and Block Write and Block Read operations.
For Byte Write/Read operations, the system controller can individually access addressed bytes.
For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with
most significant bit first) with the ability to stop after any complete byte has been transferred. The number of
bytes read out is defined by the Byte Count field in the Generic Configuration Register. During a Block Read
instruction, the entire number of bytes defined in Byte Count must be read out to correctly finish the read cycle.
When a byte is sent to the device, it is written into the internal register and immediately takes effect. This applies
to each transferred byte, whether in a Byte Write or a Block Write sequence.
If the EEPROM Write Cycle is initiated, the internal SDA register contents are written into the EEPROM. During
this write cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can
be read during the programming sequence (Byte Read or Block Read). The programming status can be
monitored by reading EEPIP, Byte 01–Bit [6].
The offset of the indexed byte is encoded in the command code, as described in Table 6.
Table 5. Slave Receiver Address (7 bits)
(1)
12
Device
A6
A5
A4
A3
A2
A1 (1)
A0 (1)
R/W
CDCE913/CDCEL913
1
1
0
0
1
0
1
1/0
CDCE925/CDCEL925
1
1
0
0
1
0
0
1/0
CDCE937/CDCEL937
1
1
0
1
1
0
1
1/0
CDCE949
1
1
0
1
1
0
0
1/0
Address bits A0 and A1 are programmable via the SDA/SCL bus (Byte 01, Bit [1:0]). This allows addressing up to 4 devices connected
to the same SDA/SCL bus. The least significant bit of the address byte designates a write or read operation.
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Table 6. Command Code Definition
BIT
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
7
(6:0)
Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation.
Generic Programming Sequence
1
S
7
Slave Address
1
1
R/W A
LSB
MSB
MSB
S
Start Condition
Sr
Repeated Start Condition
8
Data Byte
1
A
1
P
LSB
R/W 1 = Read (Rd) from CDCE9xx device; 0 = Write (Wr) to the CDCE9xxx
A
Acknowledg (ACK = 0 and NACK =1)
P
Stop Condition
Master to Slave Transmission
Slave to Master Transmission
Figure 6. Generic Programming Sequence
Byte Write Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
CommandCode
1
A
8
Data Byte
1
A
1
P
7
Slave Address
1
Rd
1
A
1
A
1
P
Figure 7. Byte Write Protocol
Byte Read Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
Data Byte
1
A
1
P
8
CommandCode
1
A
1
S
Figure 8. Byte Read Protocol
Block Write Programming Sequence
1
S
7
Slave Address
1
Wr
8
Data Byte 0
1
A
1
A
1
A
8
CommandCode
8
Data Byte 1
1
A
8
Byte Count = N
…
8
Data Byte N-1
1
A
NOTE: Data Byte 0 Bits [7:0] is reserved for Revision Code and Vendor Identification. Also it is used for internal test purpose
and should not be overwritten.
Figure 9. Block Write Programming
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Block Read Programming Sequence
1
S
7
Slave Address
1
Wr
8
Byte Count N
1
A
1
A
8
CommandCode
8
Data Byte 0
1
A
1
A
1
Sr
…
7
Slave Address
1
Rd
1
A
8
Data Byte N-1
1
A
1
P
Figure 10. Block Read Protocol
Timing Diagram for the SDA/SCL Serial Control Interface
P
Bit 7 (MSB)
S
tw(SCLL)
Bit 6
tw(SCLH)
tr
Bit 0 (LSB)
A
P
tf
VIH
SCL
VIL
tSU(START)
t(BUS)
th(START)
t
SU(SDA)
t
tSU(STOP)
h(SDA)
tr
tf
VIH
SDA
VIL
Figure 11. Timing Diagram for the SDA/SCL Serial Control Interface
SDA/SCL Hardware Interface
Figure 12 shows how the CDCE949 clock synthesizer is connected to the SDA/SCL serial interface bus. Multiple
devices can be connected to the bus but the speed may need to be reduced (400 kHz is the maximum) if many
devices are connected.
Note that the pullup resistor value (RP) depends on the supply voltage, bus capacitance and number of
connected devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at
VOLmax = 0.4 V for the output stages (for more details see the SMBus or I2C Bus specification).
CDCE949
CDCEL949
RP
RP
Master
Slave
SDA
SCL
CBUS
CBUS
Figure 12. SDA/SCL Hardware Interface
14
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SDA/SCL CONFIGURATION REGISTERS
The clock input, control pins, PLLs and output stages are user configurable. The following tables and
explanations describe the programmable functions of the CDCE949. All settings can be manually written to the
device via the SDA/SCL bus, or are easily programmable by using the TI Pro Clock software. TI Pro Clock
software allows the user to quickly make all settings and automatically calculates the values for optimized
performance at lowest jitter.
Table 7. SDA/SCL Registers
ADDRESS OFFSET
REGISTER DESCRIPTION
TABLE
00h
Generic Configuration Register
Table 9
10h
PLL1 Configuration Register
Table 10
20h
PLL2 Configuration Register
Table 11
30h
PLL3 Configuration Register
Table 12
40h
PLL4 Configuration Register
Table 13
The grey-highlighted Bits described in the Configuration Registers tables on the following pages, belong to the
Control Terminal Register. The user can predefine up to eight different control settings. These settings can then
be selected by the external control pins, S0, S1, and S2 (See the Control Terminal Configuration section).
Table 8. Configuration Register, External Control Terminals
EXTERNAL
CONTROL
PINS
S2 S1 S0
Y1
Output
Select
PLL1 SETTING
Freq.
Select
SSC
Select
PLL2 SETTING
Output
Select
Freq.
Select
SSC
Select
PLL3 SETTING
Output
Select
Freq.
Select
SSC
Select
PLL4 SETTING
Output
Select
Freq.
Select
SSC
Select
Output
Select
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
FS3
SSC3
Y6Y7
FS4
SSC4
Y8Y9
0
0
0
Y1_0
FS1_0
SSC1_0
Y2Y3_0
FS2_0
SSC2_0
Y4Y5_0
FS3_0
SSC3_0
Y6Y7_0
FS4_0
SSC4_0
Y8Y9_0
0
0
1
Y1_1
FS1_1
SSC1_1
Y2Y3_1
FS2_1
SSC2_1
Y4Y5_1
FS3_1
SSC3_1
Y6Y7_1
FS4_1
SSC4_1
Y8Y9_1
0
1
0
Y1_2
FS1_2
SSC1_2
Y2Y3_2
FS2_2
SSC2_2
Y4Y5_2
FS3_2
SSC3_2
Y6Y7_2
FS4_2
SSC4_2
Y8Y9_2
0
1
1
Y1_3
FS1_3
SSC1_3
Y2Y3_3
FS2_3
SSC2_3
Y4Y5_3
FS3_3
SSC3_3
Y6Y7_3
FS4_3
SSC4_3
Y8Y9_3
1
0
0
Y1_4
FS1_4
SSC1_4
Y2Y3_4
FS2_4
SSC2_4
Y4Y5_4
FS3_4
SSC3_4
Y6Y7_4
FS4_4
SSC4_4
Y8Y9_4
1
0
1
Y1_5
FS1_5
SSC1_5
Y2Y3_5
FS2_5
SSC2_5
Y4Y5_5
FS3_5
SSC3_5
Y6Y7_5
FS4_5
SSC4_5
Y8Y9_5
1
1
0
Y1_6
FS1_6
SSC1_6
Y2Y3_6
FS2_6
SSC2_6
Y4Y5_6
FS3_6
SSC3_6
Y6Y7_6
FS4_6
SSC4_6
Y8Y9_6
1
1
1
Y1_7
FS1_7
SSC1_7
Y2Y3_7
FS2_7
SSC2_7
Y4Y5_7
FS3_7
SSC3_7
Y6Y7_7
FS4_7
SSC4_7
Y8Y9_7
04h
13h
10h-12h
15h
23h
20h-22h
25h
33h
30h-32h
35h
43h
40h-42h
45h
Addr.
Offset (1)
(1)
Address Offset refers to the byte address in the Configuration Register on following pages.
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Table 9. Generic Configuration Register
OFFSET (1)
Bit (2)
Acronym
Default (3)
00h
7
E_EL
xb
Device Identification (read only): 1 is CDCE949 (3.3 V), 0 is CDCEL949 (1.8 V)
6:4
RID
Xb
Revision Identification Number (read only)
3:0
VID
1h
Vendor Identification Number (read only)
7
–
0b
Reserved - always write 0
6
EEPIP
0b
EEPROM Programming
Status (4): (read only)
0 – EEPROM programming is completed
1 – EEPROM is in programming mode
5
EELOCK
0b
Permanently Lock EEPROM
Data (5):
0 – EEPROM is not locked
1 – EEPROM will be permanently locked
4
PWDN
0b
3:2
INCLK
00b
1:0
SLAVE_ADR
00b
7
M1
1b
6
SPICON
0b
5:4
Y1_ST1
11b
3:2
Y1_ST0
01b
01h
02h
DESCRIPTION
Device power down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – device active (all PLLs and all outputs are enabled)
1 – device power down (all PLLs in power down and all outputs in 3-State)
Input clock selection:
00 – X-tal
01 – VCXO
10 – LVCMOS
11 – reserved
Programmable Address Bits A0 and A1 of the Slave Receiver Address
Clock source selection for output Y1:
0 – input clock
1 – PLL1 clock
Operation mode selection for pin 22/23 (6)
1:0
Pdiv1 [9:8]
03h
7:0
Pdiv1 [7:0]
04h
7
Y1_7
0b
6
Y1_6
0b
5
Y1_5
0b
4
Y1_4
0b
3
Y1_3
0b
2
Y1_2
0b
1
Y1_1
1b
0
Y1_0
0b
001h
05h
0 – serial programming interface SDA (pin 23) and SCL (pin 22)
1 – control pins S1 (pin 23) and S2 (pin 22)
Y1-State0/1 Definition (applies to Y1_ST1 and Y1_ST0)
00 –
01 –
10 –
11 –
device power down (all PLLs in power down and all outputs in 3-state)
Y1 disabled to 3-state
Y1 disabled to low
Y1 enabled (normal operation)
10-Bit Y1-Output-Divider Pdiv1:
Y1_x State Selection (7)
0 – State0 (predefined by Y1-State0 Definition [Y1_ST0])
1 – State1 (predefined by Y1-State1 Definition [Y1_ST1])
Crystal load capacitor
selection (8):
7:3
XCSEL
0Ah
0 – divider reset and stand-by
1-to-1023 – divider value
00h → 0 pF
01h → 1 pF
02h → 2 pF
14h-to-1Fh → 20 pF
Vctr
Xin
20pF
i.e.
XCSEL = 10pF
XO
Xout
2:0
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
16
—
0b
VCXO
20pF
Reserved - do not write others than 0
Writing data beyond ‘50h’ may adversely affect device function.
All data is transferred MSB-first.
Unless custom setting is used.
During EEPROM programming, no data is allowed to be sent to the device via the SDA/SCL bus until the programming sequence is
completed. Data, however, can be read during the programming sequence (Byte Read or Block Read).
If this bit is set high in the EEPROM, the actual data in the EEPROM is permanently locked, and no further programming is possible.
Data, however can still be written via SDA/SCL bus to the internal register to change device function on the fly. But new data can no
longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM
Selection of control-pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are
no longer available. However, if VDDOUT is forced to GND, the two control-pins, S1 and S2, temporally act as serial programming pins
(SDA/SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.
These are the bits of the Control Terminal Register. The user can pre-define up to eight different control settings. These settings can
then be selected by the external control pins, S0, S1, and S2.
The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors should be used only to do
a fine adjustment of CL by few pF. The value of CL can be programmed with a resolution of 1 pF for a total crystal load range of 0 pF to
20 pF. For CL > 20 pF use additional external capacitors. Also, the device input capacitance must be considered; this adds 1.5 pF
(6pF//2pF) to the selected CL. For more information about VCXO configuration and crystal recommendations, see application report
SCAA085
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Table 9. Generic Configuration Register (continued)
OFFSET (1)
06h
Bit (2)
Acronym
Default (3)
DESCRIPTION
7-Bit Byte Count (Defines the number of Bytes which will be sent from this device at the next Block Read
transfer; all bytes must be read out to correctly finish the read cycle.)
7:1
BCOUNT
50h
0
EEWRITE
0b
0 – no EEPROM write cycle
1 – start EEPROM write cycle (internal configuration register is saved to the EEPROM)
—
—
0h
Reserved – do not write others than 0
Initiate EEPROM Write Cycle(4)
07h-0Fh
(9)
(9)
NOTE: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are written into the EEPROM.
The EEWRITE cycle is initiated by the rising edge of the EEWRITE-Bit. A static level high does not trigger an EEPROM WRITE cycle.
The EEWRITE-Bit must be reset low after the programming is completed. The programming status can be monitored by readout EEPIP.
If EELOCK is set high, no EEPROM programming will be possible.
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Table 10. PLL1 Configuration Register
OFFSET (1)
Bit (2)
Acronym
Default (3)
10h
7:5
SSC1_7 [2:0]
000b
4:2
SSC1_6 [2:0]
000b
1:0
SSC1_5 [2:1]
7
SSC1_5 [0]
6:4
SSC1_4 [2:0]
000b
3:1
SSC1_3 [2:0]
000b
0
SSC1_2 [2]
7:6
SSC1_2 [1:0]
5:3
SSC1_1 [2:0]
000b
2:0
SSC1_0 [2:0]
000b
7
FS1_7
0b
6
FS1_6
0b
5
FS1_5
0b
4
FS1_4
0b
3
FS1_3
0b
2
FS1_2
0b
1
FS1_1
0b
0
FS1_0
0b
7
MUX1
1b
6
M2
1b
5:4
M3
10b
3:2
Y2Y3_ST1
11b
1:0
Y2Y3_ST0
01b
7
Y2Y3_7
0b
6
Y2Y3_6
0b
5
Y2Y3_5
0b
4
Y2Y3_4
0b
3
Y2Y3_3
0b
2
Y2Y3_2
0b
1
Y2Y3_1
1b
0
Y2Y3_0
0b
7
SSC1DC
0b
6:0
Pdiv2
01h
7
—
0b
6:0
Pdiv3
01h
11h
12h
13h
14h
15h
16h
17h
(1)
(2)
(3)
(4)
18
000b
000b
DESCRIPTION
SSC1: PLL1 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS1_x: PLL1 Frequency Selection(4)
0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)
PLL1 Multiplexer:
0 – PLL1
1 – PLL1 Bypass (PLL1 is in power down)
Output Y2 Multiplexer:
0 – Pdiv1
1 – Pdiv2
Output Y3 Multiplexer:
00 –
01 –
10 –
11 –
Pdiv1-Divider
Pdiv2-Divider
Pdiv3-Divider
reserved
Y2, Y3-State0/1definition: 00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State (PLL1 on)
10–Y2/Y3 disabled to low (PLL1 on)
11 – Y2/Y3 enabled (normal operation, PLL1 on)
Y2Y3_x Output State Selection(4)
0 – state0 (predefined by Y2Y3_ST0)
1 – state1 (predefined by Y2Y3_ST1)
PLL1 SSC down/center selection:
0 – down
1 – center
7-Bit Y2-Output-Divider Pdiv2:
0 – reset and stand-by
1-to-127 – divider value
Reserved – do not write others than 0
7-Bit Y3-Output-Divider Pdiv3:
0 – reset and stand-by
1-to-127 – divider value
Writing data beyond 50h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can pre-define up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 10. PLL1 Configuration Register (continued)
OFFSET (1)
Bit (2)
Acronym
18h
7:0
PLL1_0N [11:4
19h
7:4
PLL1_0N [3:0]
3:0
PLL1_0R [8:5]
7:3
PLL1_0R[4:0]
2:0
PLL1_0Q [5:3]
7:5
PLL1_0Q [2:0]
4:2
PLL1_0P [2:0]
010b
1:0
VCO1_0_RANGE
00b
1Ch
7:0
PLL1_1N [11:4]
1Dh
7:4
PLL1_1N [3:0]
3:0
PLL1_1R [8:5]
7:3
PLL1_1R[4:0]
2:0
PLL1_1Q [5:3]
7:5
PLL1_1Q [2:0]
4:2
PLL1_1P [2:0]
010b
1:0
VCO1_1_RANGE
00b
1Ah
1Bh
Default (3)
004h
DESCRIPTION
PLL1_0: 30-Bit Multiplier/Divider value for frequency fVCO1_0
(for more information see PLL Multiplier/Divider Definition )
000h
10h
fVCO1_0 range selection:
1Eh
1Fh
004h
00 –
01 –
10 –
11 –
fVCO1_0 < 125 MHz
125 MHz ≤ fVCO1_0 < 150 MHz
150 MHz ≤ fVCO1_0 < 175 MHz
fVCO1_0 ≥ 175 MHz
PLL1_1: 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information see paragraph PLL Multiplier/Divider Definition)
000h
10h
fVCO1_1 range selection:
00 –
01 –
10 –
11 –
fVCO1_1 < 125 MHz
125 MHz ≤ fVCO1_1 < 150 MHz
150 MHz ≤ fVCO1_1 < 175 MHz
fVCO1_1 ≥ 175 MHz
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Table 11. PLL2 Configuration Register
OFFSET (1)
Bit (2)
Acronym
Default (3)
20h
7:5
SSC2_7 [2:0]
000b
4:2
SSC2_6 [2:0]
000b
1:0
SSC2_5 [2:1]
7
SSC2_5 [0]
6:4
SSC2_4 [2:0]
000b
3:1
SSC2_3 [2:0]
000b
0
SSC2_2 [2]
7:6
SSC2_2 [1:0]
5:3
SSC2_1 [2:0]
000b
2:0
SSC2_0 [2:0]
000b
7
FS2_7
0b
6
FS2_6
0b
5
FS2_5
0b
4
FS2_4
0b
3
FS2_3
0b
2
FS2_2
0b
1
FS2_1
0b
0
FS2_0
0b
7
MUX2
1b
6
M4
1b
5:4
M5
10b
3:2
Y4Y5_ST1
11b
1:0
Y4Y5_ST0
01b
7
Y4Y5_7
0b
6
Y4Y5_6
0b
5
Y4Y5_5
0b
4
Y4Y5_4
0b
3
Y4Y5_3
0b
2
Y4Y5_2
0b
1
Y4Y5_1
1b
0
Y4Y5_0
0b
7
SSC2DC
0b
6:0
Pdiv4
01h
7
—
0b
6:0
Pdiv5
01h
21h
22h
23h
24h
25h
26h
27h
(1)
(2)
(3)
(4)
20
000b
000b
DESCRIPTION
SSC2: PLL2 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS2_x: PLL2 Frequency Selection(4)
0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value)
1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value)
PLL2 Multiplexer:
0 – PLL2
1 – PLL2 Bypass (PLL2 is in power down)
Output Y4 Multiplexer:
0 – Pdiv2
1 – Pdiv4
Output Y5 Multiplexer:
00 –
01 –
10 –
11 –
Y4,
Y5-State0/1definition:
00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)
01 – Y4/Y5 disabled to 3-State (PLL2 on)
10–Y4/Y5 disabled to low (PLL2 on)
11 – Y4/Y5 enabled (normal operation, PLL2 on)
Pdiv2-Divider
Pdiv4-Divider
Pdiv5-Divider
reserved
Y4Y5_x Output State Selection(4)
0 – state0 (predefined by Y4Y5_ST0)
1 – state1 (predefined by Y4Y5_ST1)
PLL2 SSC down/center selection:
0 – down
1 – center
7-Bit Y4-Output-Divider Pdiv4:
0 – reset and stand-by
1-to-127 – divider value
Reserved – do not write others than 0
7-Bit Y5-Output-Divider Pdiv5:
0 – reset and stand-by
1-to-127 – divider value
Writing data beyond 50h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can pre-define up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 11. PLL2 Configuration Register (continued)
OFFSET (1)
Bit (2)
Acronym
28h
7:0
PLL2_0N [11:4
29h
7:4
PLL2_0N [3:0]
3:0
PLL2_0R [8:5]
7:3
PLL2_0R[4:0]
2:0
PLL2_0Q [5:3]
7:5
PLL2_0Q [2:0]
4:2
PLL2_0P [2:0]
010b
1:0
VCO2_0_RANGE
00b
2Ch
7:0
PLL2_1N [11:4]
2Dh
7:4
PLL2_1N [3:0]
3:0
PLL2_1R [8:5]
7:3
PLL2_1R[4:0]
2:0
PLL2_1Q [5:3]
7:5
PLL2_1Q [2:0]
4:2
PLL2_1P [2:0]
010b
1:0
VCO2_1_RANGE
00b
2Ah
2Bh
Default (3)
004h
DESCRIPTION
PLL2_0: 30-Bit Multiplier/Divider value for frequency fVCO2_0
(for more information see paragraph PLL Multiplier/Divider Definition)
000h
10h
fVCO2_0 range selection:
2Eh
2Fh
004h
00 –
01 –
10 –
11 –
fVCO2_0 < 125 MHz
125 MHz ≤ fVCO2_0 < 150 MHz
150 MHz ≤ fVCO2_0 < 175 MHz
fVCO2_0 ≥ 175 MHz
PLL2_1: 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information see paragraph PLL Multiplier/Divider Definition)
000h
10h
fVCO2_1 range selection:
00 –
01 –
10 –
11 –
fVCO2_1 < 125 MHz
125 MHz ≤ fVCO2_1 < 150 MHz
150 MHz ≤ fVCO2_1 < 175 MHz
fVCO2_1 ≥ 175 MHz
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Table 12. PLL3 Configuration Register
OFFSET (1)
Bit (2)
Acronym
Default (3)
30h
7:5
SSC3_7 [2:0]
000b
4:2
SSC3_6 [2:0]
000b
1:0
SSC3_5 [2:1]
7
SSC3_5 [0]
6:4
SSC3_4 [2:0]
000b
3:1
SSC3_3 [2:0]
000b
0
SSC3_2 [2]
7:6
SSC3_2 [1:0]
5:3
SSC3_1 [2:0]
000b
2:0
SSC3_0 [2:0]
000b
7
FS3_7
0b
6
FS3_6
0b
5
FS3_5
0b
4
FS3_4
0b
3
FS3_3
0b
2
FS3_2
0b
1
FS3_1
0b
0
FS3_0
0b
7
MUX3
1b
6
M6
1b
5:4
M7
10b
3:2
Y6Y7_ST1
11b
1:0
Y6Y7_ST0
01b
7
Y6Y7_7
0b
6
Y6Y7_6
0b
5
Y6Y7_5
0b
4
Y6Y7_4
0b
3
Y6Y7_3
0b
2
Y6Y7_2
0b
1
Y6Y7_1
1b
0
Y6Y7_0
0b
7
SSC3DC
0b
6:0
Pdiv6
01h
7
—
0b
6:0
Pdiv7
01h
31h
32h
33h
34h
35h
36h
37h
(1)
(2)
(3)
(4)
22
000b
000b
DESCRIPTION
SSC3: PLL3 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS3_x: PLL3 Frequency Selection(4)
0 – fVCO3_0 (predefined by PLL3_0 – Multiplier/Divider value)
1 – fVCO3_1 (predefined by PLL3_1 – Multiplier/Divider value)
PLL3 Multiplexer:
0 – PLL3
1 – PLL3 Bypass (PLL3 is in power down)
Output Y6 Multiplexer:
0 – Pdiv4
1 – Pdiv6
Output Y7 Multiplexer:
00 –
01 –
10 –
11 –
Y6,
Y7-State0/1definition:
00 – Y6/Y7 disabled to 3-State (PLL3 is in power down)
01 – Y6/Y7 disabled to 3-State (PLL3 on)
10 –Y6/Y7 disabled to low (PLL3 on)
11 – Y6/Y7 enabled (normal operation, PLL3 on)
Pdiv4-Divider
Pdiv6-Divider
Pdiv7-Divider
reserved
Y6Y7_x Output State Selection(4)
0 – state0 (predefined by Y6Y7_ST0)
1 – state1 (predefined by Y6Y7_ST1)
PLL3 SSC down/center selection:
0 – down
1 – center
7-Bit Y6-Output-Divider Pdiv6:
0 – reset and stand-by
1-to-127 – divider value
Reserved – do not write others than 0
7-Bit Y7-Output-Divider Pdiv7:
0 – reset and stand-by
1-to-127 – divider value
Writing data beyond 50h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can pre-define up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 12. PLL3 Configuration Register (continued)
OFFSET (1)
Bit (2)
Acronym
38h
7:0
PLL3_0N [11:4
39h
7:4
PLL3_0N [3:0]
3:0
PLL3_0R [8:5]
7:3
PLL3_0R[4:0]
2:0
PLL3_0Q [5:3]
7:5
PLL3_0Q [2:0]
4:2
PLL3_0P [2:0]
010b
1:0
VCO3_0_RANGE
00b
3Ch
7:0
PLL3_1N [11:4]
3Dh
7:4
PLL3_1N [3:0]
3:0
PLL3_1R [8:5]
7:3
PLL3_1R[4:0]
2:0
PLL3_1Q [5:3]
7:5
PLL3_1Q [2:0]
4:2
PLL3_1P [2:0]
010b
1:0
VCO3_1_RANGE
00b
3Ah
3Bh
Default (3)
004h
DESCRIPTION
PLL3_0: 30-Bit Multiplier/Divider value for frequency fVCO3_0
(for more information see paragraph PLL Multiplier/Divider Definition)
000h
10h
fVCO3_0 range selection:
3Eh
3Fh
004h
00 –
01 –
10 –
11 –
fVCO3_0 < 125 MHz
125 MHz ≤ fVCO3_0 < 150 MHz
150 MHz ≤ fVCO3_0 < 175 MHz
fVCO3_0 ≥ 175 MHz
PLL3_1: 30-Bit Multiplier/Divider value for frequency fVCO3_1
(for more information see paragraph PLL Multiplier/Divider Definition)
000h
10h
fVCO3_1 range selection:
00 –
01 –
10 –
11 –
fVCO3_1 < 125 MHz
125 MHz ≤ fVCO3_1 < 150 MHz
150 MHz ≤ fVCO3_1 < 175 MHz
fVCO3_1 ≥ 175 MHz
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Table 13. PLL4 Configuration Register
OFFSET (1)
Bit (2)
Acronym
Default (3)
40h
7:5
SSC4_7 [2:0]
000b
4:2
SSC4_6 [2:0]
000b
1:0
SSC4_5 [2:1]
7
SSC4_5 [0]
6:4
SSC4_4 [2:0]
000b
3:1
SSC4_3 [2:0]
000b
0
SSC4_2 [2]
7:6
SSC4_2 [1:0]
5:3
SSC4_1 [2:0]
000b
2:0
SSC4_0 [2:0]
000b
7
FS4_7
0b
6
FS4_6
0b
5
FS4_5
0b
4
FS4_4
0b
3
FS4_3
0b
2
FS4_2
0b
1
FS4_1
0b
0
FS4_0
0b
7
MUX4
1b
6
M8
1b
5:4
M9
10b
3:2
Y8Y9_ST1
11b
1:0
Y8Y9_ST0
01b
7
Y8Y9_7
0b
6
Y8Y9_6
0b
5
Y8Y9_5
0b
4
Y8Y9_4
0b
3
Y8Y9_3
0b
2
Y8Y9_2
0b
1
Y8Y9_1
1b
0
Y8Y9_0
0b
7
SSC4DC
0b
6:0
Pdiv8
01h
7
—
0b
6:0
Pdiv9
01h
41h
42h
43h
44h
45h
46h
47h
(1)
(2)
(3)
(4)
24
000b
000b
DESCRIPTION
SSC4: PLL4 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS4_x: PLL4 Frequency Selection(4)
0 – fVCO4_0 (predefined by PLL4_0 – Multiplier/Divider value)
1 – fVCO4_1 (predefined by PLL4_1 – Multiplier/Divider value)
PLL4 Multiplexer:
0 – PLL4
1 – PLL4 Bypass (PLL4 is in power down)
Output Y8 Multiplexer:
0 – Pdiv6
1 – Pdiv8
Output Y9 Multiplexer:
00 –
01 –
10 –
11 –
Y8,
Y9-State0/1definition:
00 – Y8/Y9 disabled to 3-State (PLL4 is in power down)
01 – Y8/Y9 disabled to 3-State (PLL4 on)
10 –Y8/Y9 disabled to low (PLL4 on)
11 – Y8/Y9 enabled (normal operation, PLL4 on)
Pdiv6-Divider
Pdiv8-Divider
Pdiv9-Divider
reserved
Y8Y9_x Output State Selection(4)
0 – state0 (predefined by Y8Y9_ST0)
1 – state1 (predefined by Y8Y9_ST1)
PLL4 SSC down/center selection:
0 – down
1 – center
7-Bit Y8-Output-Divider Pdiv8:
0 – reset and stand-by
1-to-127 – divider value
Reserved – do not write others than 0
7-Bit Y9-Output-Divider Pdiv9:
0 – reset and stand-by
1-to-127 – divider value
Writing data beyond 50h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can pre-define up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 13. PLL4 Configuration Register (continued)
OFFSET (1)
Bit (2)
Acronym
48h
7:0
PLL4_0N [11:4
49h
7:4
PLL4_0N [3:0]
3:0
PLL4_0R [8:5]
7:3
PLL4_0R[4:0]
2:0
PLL4_0Q [5:3]
7:5
PLL4_0Q [2:0]
4:2
PLL4_0P [2:0]
010b
1:0
VCO4_0_RANGE
00b
4Ch
7:0
PLL4_1N [11:4]
4Dh
7:4
PLL4_1N [3:0]
3:0
PLL4_1R [8:5]
7:3
PLL4_1R[4:0]
2:0
PLL4_1Q [5:3]
7:5
PLL4_1Q [2:0]
4:2
PLL4_1P [2:0]
010b
1:0
VCO4_1_RANGE
00b
4Ah
4Bh
Default (3)
004h
DESCRIPTION
PLL4_0: 30-Bit Multiplier/Divider value for frequency fVCO4_0
(for more information see paragraph PLL Multiplier/Divider Definition)
000h
10h
fVCO4_0 range selection:
4Eh
4Fh
004h
00 –
01 –
10 –
11 –
fVCO4_0 < 125 MHz
125 MHz ≤ fVCO4_0 < 150 MHz
150 MHz ≤ fVCO4_0 < 175 MHz
fVCO4_0 ≥ 175 MHz
PLL4_1: 30-Bit Multiplier/Divider value for frequency fVCO4_1
(for more information see paragraph PLL Multiplier/Divider Definition)
000h
10h
fVCO4_1 range selection:
00 –
01 –
10 –
11 –
fVCO4_1 < 125 MHz
125 MHz ≤ fVCO4_1 < 150 MHz
150 MHz ≤ fVCO4_1 < 175 MHz
fVCO4_1 ≥ 175 MHz
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PLL MULTIPLIER/DIVIDER DEFINITION
At a given input frequency (fIN), the output frequency (fOUT) of the CDCE949 can be calculated by:
ƒ
N
ƒ OUT + IN
Pdiv M
where
M (1 to 511) and N (1 to 4095) are the multiplier/divider values of the PLL;
Pdiv (1 to 127) is the output divider.
The target VCO frequency (fVCO) of each PLL can be calculated:
N
ƒ VCO + ƒIN
M
The PLL operates as fractional divider and needs following multiplier/divider settings
N
N
P = 4 - int(log2 )
M {if P < 0 then P = 0}
N'
Q = int( )
M
R = N'-M ´ Q
Where:
N' = N × 2P;
N ≥ M;
80 MHz < fVCO > 230 MHz.
Example 1: for fIN = 27 MHz; M = 1; N = 4; Pdiv = 2;
Example 2: for fIN = 27 MHz; M = 2; N = 11; Pdiv = 2;
→ fOUT = 54 MHz;
→ fOUT = 75.25 MHz;
→ fVCO = 108 MHz;
→ fVCO = 148.50 MHz;
→ P = 4 – int(log24) = 4 –2 = 2;
→ P = 4 – int(log25.5) = 4 – 2 = 2;
2
→ N’ = 4 × 2 = 16;
→ N’ = 11 × 22 = 44;
→ Q = int(16) = 16;
→ Q = int(22) = 22;
→ R = 16 – 16 = 0;
→ R = 44 – 44 = 0;
The values for P, Q, R and N’ are automatically calculated when using TI Pro Clock™ Software.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCE949QPWRQ1
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CDCE949Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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