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CDCI6214
SNAS734D – JULY 2017 – REVISED JUNE 2019
CDCI6214 Ultra-Low Power Clock Generator With PCIe Support, Four Programmable
Outputs and EEPROM
1 Features
3 Description
•
The CDCI6214 device is an ultra-low power clock
generator. The device selects between two
independent reference inputs to a phase-locked loop
and generates up to four different frequencies on
configurable differential output channels and also a
copy of the reference clock on a LVCMOS output
channel.
1
•
•
•
•
•
•
•
•
•
•
•
•
One Configurable High Performance, Low-Power
PLL With 4 Programmable Outputs
RMS Jitter Performance
– Supports PCIe Gen1 with or without Spread
Spectrum Clocking (SSC)
– Supports PCIe Gen2 / Gen3 / Gen4 without
SSC
Typical Power Consumption: 150 mW at 1.8 V(2)
Universal Clock Input
– Differential AC-Coupled or LVCMOS: 1 MHz to
250 MHz
– Crystal: 8 MHz to 50 MHz
Flexible Output Frequencies
– 44.1 kHz to 350 MHz
– Glitchless Output Divider Switching
Four Individually Configurable Outputs
– LVCMOS, LVDS or HCSL
– Differential AC-Coupled With Programmable
Swing (LVDS-, CML-, LVPECL-Compatible)
Fully Integrated PLL, Configurable Loop
Bandwidth: 100 kHz to 3 MHz
Single or Mixed Supply Operation for Level
Translation: 1.8 V, 2.5 V and 3.3 V
Configurable GPIOs
– Status Signals
– Up to 4 Individual Output Enables
– Output Divider Synchronization
Flexible Configuration Options
– I2C-Compatible Interface: Up to 400 kHz
– Integrated EEPROM With Two Pages and
External Select Pin
Only Supports 100 Ω Systems
Industrial Temperature Range: –40ºC to 85ºC
Small Footprint: 24-Pin VQFN (4 mm × 4 mm)
2 Applications
•
•
•
•
•
PCIe Gen 1/2/3/4 clocking
1G / 10G Ethernet Switches, NIC, Accelerators
Test & Measurement , Handheld Equipment
Multi-Function Printers
Broadcast Infrastructure
Each of the four output channels has a configurable
integer / fractional output divider and a dedicated
integer divider. Together with the output muxes, this
allows up to five different frequencies. Clock
distribution dividers are reset in a deterministic way
for clean clock gating and glitch-less update
capability. Flexible power-down options allow to
optimize the device for lowest power consumption in
active and standby operation. Typically four 156.25
MHz LVDS outputs consume 150 mW at 1.8V.
Typical RMS jitter of 386 fs for 100 MHz HCSL output
enhances system margin for PCIe applications.
The CDCI6214 is configured using internal registers
that are accessed by an I2C-compatible serial
interface and internal EEPROM.
The CDCI6214 enables high-performance clock trees
from a single reference at ultra-low power with a
small footprint. The factory- and user-programmable
EEPROM make the CDCI6214 ideal as easy-to-use,
instant-on clocking solution with low power
consumption.
Device Information(1)
PART NUMBER
CDCI6214
PACKAGE
BODY SIZE (NOM)
VQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Four LVDS outputs, 156.25 MHz with crystal reference.
Application Example CDCI6214
Voltage Domain
1.8V / 2.5V / 3.3V
FPGA
DAC
DAC
Crystal
CDCI6214
Voltage Domain
1.8V / 2.5V / 3.3V
MCU
Ethernet
LVCMOS
Crystal Copy
PCIe
Voltage Domain
1.8V / 2.5V / 3.3V
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCI6214
SNAS734D – JULY 2017 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
EEPROM Characteristics.......................................... 6
Reference Input, Single-Ended and Differential Mode
Characteristics (REFP, REFN, FB_P, FB_N) ............ 6
6.7 Reference Input, Crystal Mode Characteristics (XIN,
XOUT) ........................................................................ 6
6.8 General-Purpose Input and Output Characteristics
(GPIO[4:1], SYNC/RESETN) ..................................... 6
6.9 Triple Level Input Characteristics (EEPROMSEL,
REFSEL) .................................................................... 7
6.10 Reference Mux Characteristics .............................. 7
6.11 Phase-Locked Loop Characteristics ....................... 7
6.12 Closed-Loop Output Jitter Characteristics .............. 8
6.13 PCIe Gen1 Spread Spectrum Generator ................ 8
6.14 Output Mux Characteristics .................................... 8
6.15 LVCMOS Output Characteristics ............................ 9
6.16 HCSL Output Characteristics ................................. 9
6.17 LVDS DC-Coupled Output Characteristics ............. 9
6.18 Programmable Differential AC-Coupled Output
Characteristics ......................................................... 10
6.19 Output Skew and Delay Characteristics ............... 10
6.20 Output Synchronization Characteristics................ 10
6.21 Timing Characteristics........................................... 11
6.22 I2C-Compatible Serial Interface Characteristics
(SDA/GPIO2, SCL/GPIO3) ...................................... 11
6.23 Timing Requirements, I2C-Compatible Serial
Interface (SDA/GPIO2, SCL/GPIO3) ....................... 11
6.24 Power Supply Characteristics ............................... 12
6.25 Typical Characteristics .......................................... 13
7
Parameter Measurement Information ................ 14
8
Detailed Description ............................................ 18
7.1 Parameters.............................................................. 14
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps ........................................................
18
18
19
30
31
40
Application and Implementation ........................ 92
9.1
9.2
9.3
9.4
Application Information............................................
Typical Applications ................................................
Do's and Don'ts .......................................................
Initialization Setup ..................................................
92
92
95
95
10 Power Supply Recommendations ..................... 97
10.1 Power-Up Sequence ............................................. 97
10.2 De-Coupling .......................................................... 97
11 Layout................................................................... 97
11.1 Layout Guidelines ................................................. 97
11.2 Layout Examples................................................... 97
12 Device and Documentation Support ................. 99
12.1
12.2
12.3
12.4
12.5
12.6
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
99
99
99
99
99
99
13 Mechanical, Packaging, and Orderable
Information ........................................................... 99
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2018) to Revision D
Page
•
Added VDDREF and tablenote to the output supply voltage parameter in the Recommended Operating Conditions ......... 5
•
Added statement on chX_1p8vdet setting ........................................................................................................................... 21
•
Changed CDCI6214 - Pre-Configured EEPROM Page 0 graphic........................................................................................ 38
Changes from Revision B (April 2018) to Revision C
Page
•
Corrected PCIe compliance statement .................................................................................................................................. 1
•
Changed pin names for pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N. ............................................... 4
•
Changed descriptions for pins 1 and 2................................................................................................................................... 4
•
Changed pin names for pins 1 and 2 in Absolute Maximum Ratings .................................................................................... 5
•
Changed pin names for pins 1 and 2 in Reference Input, Single-Ended and Differential Mode Characteristics
(REFP, REFN, FB_P, FB_N).................................................................................................................................................. 6
•
Changed Input capacitance specification symbols in Reference Input, Single-Ended and Differential Mode
Characteristics (REFP, REFN, FB_P, FB_N) from: CIN_XOUT and CIN_XIN to: CIN_XOUT/FB_P and CIN_XIN/FB_P ........................... 6
2
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•
Changed the test conditions for the fractional RMS Jitter specification in Closed-Loop Output Jitter Characteristics
from: Y1 =122.88 MHz LVDS to: Y1 =133+1/3 MHz LVDS and the typical value from: 2 ps to: 3 ps................................... 8
•
Changed name of the PCIe Spread Spectrum Generator table to PCIe Gen1 Spread Spectrum Generator ....................... 8
•
Changed pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the Functional Block Diagram ................. 18
•
Changed pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the Reference Block graphic ................... 19
•
Changed External (XIN) pin to: FB_P/N in the Phase-Locked Loop Circuit graphic............................................................ 21
•
Changed pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the CDCI6214 - Pre-Configured
EEPROM Page 0 and CDCI6214 - Pre-Configured EEPROM Page 1 graphics ................................................................. 38
•
Changed pins XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the Typical Applications schematics.............................. 92
•
Changed design parameter superscript to a subscript ........................................................................................................ 93
Changes from Revision A (October 2017) to Revision B
Page
•
Changed pinout pins 5 and 6 from NC to REFP, REFN inputs.............................................................................................. 4
•
Changed supply voltage maximum from: 3.6 V to: 3.65 V ..................................................................................................... 5
•
Removed Skew between HCSL maximum from the Output Skew and Delay Characteristics table ................................... 10
Changes from Original (July 2017) to Revision A
Page
•
Changed device status from Advanced Info to Production Data............................................................................................ 1
•
Changed REFSEL pin description to reflext REFMUX control. ........................................................................................... 26
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SNAS734D – JULY 2017 – REVISED JUNE 2019
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5 Pin Configuration and Functions
VDDVCO
EEPROMSEL
Y1P
Y1N
STATUS/GPIO1
SDA/GPIO2
24
23
22
21
20
19
RGE Package
24-Pin VQFN
Top View
XOUT / FB_P
1
18
Y2P
XIN / FB_N
2
17
Y2N
VDDREF
3
16
VDDO12
REFSEL
4
15
VDDO34
REFP
5
14
Y3P
REFN
6
13
Y3N
7
8
9
10
11
12
Y0
RESETN/SYNC
Y4N
Y4P
OE/GPIO4
SCL/GPIO3
25 (GND)
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE
XOUT/FB_P
1
XIN/FB_N
2
I
Crystal Input / Differential Negative Reference
VDDREF
3
P
Power Supply Pin for Input Path, Digital and EEPROM
REFSEL
4
I
Manual Reference Selection MUX for PLL, RPU = 50 kΩ, RPD = 50 kΩ
REFP
5
I
Differential Positive Reference
REFN
6
I
Differential Negative Reference
Y0
7
O
Output 0 Pin
RESETN/SYNC
8
I
Chip Reset. Alternatively, Output Divider Sync, RPU = 50 kΩ (1)
Y4N
9
O
Output 4 Negative Pin
Y4P
10
O
Output 4 Positive Pin
OE/GPIO4
11
IO
Global output enable (default) or programmable GPIO, RPU = 50 kΩ (1)
SCL/GPIO3
12
IO
Serial interface clock (default) or programmable GPIO
Y3N
13
O
Output 3 Negative Pin
Y3P
14
O
Output 3 Positive Pin
VDDO34
15
P
Power Supply for Outputs 3 and 4
VDDO12
16
P
Power Supply for Outputs 1 and 2
Y2N
17
O
Output 2 Negative Pin
Y2P
18
O
Output 2 Positive Pin
SDA/GPIO2
19
IO
Serial interface data (default) or programmable GPIO
STATUS/GPIO1
20
IO
Status (default) or programmable GPIO, RPU = 50 kΩ (1)
Y1N
21
O
Output 1 Negative Pin
Y1P
22
O
Output 1 Positive Pin
EEPROMSEL
23
I
EEPROM Page Mode Select, RPU = 50 kΩ, RPD = 50 kΩ (1)
VDDVCO
24
P
Power Supply Pin for VCO / PLL
GND
25
G
Ground, Thermal Pad
(1)
4
IO
DESCRIPTION
Crystal Driver Output / LVCMOS Input / Differential Positive Reference
RPU is an internal pullup resistor. RPD is an internal pulldown resistor.
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SNAS734D – JULY 2017 – REVISED JUNE 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDDREF, VDDVCO, VDDO12, VDDO34
Supply voltage
–0.3
3.65
V
XIN/FB_P, XOUT/FB_N, REFP, REFN
Input voltage
–0.3
VDDREF +
0.3
V
STATUS/GPIO1, SDA/GPIO2, SCL/GPIO3, OE/GPIO4,
REFSEL, EEPROMSEL, RESETN/SYNC
Input voltage
–0.3
VDDREF +
0.3
V
Y0, Y1P, Y1N, Y2P, Y2N, Y3P, Y3N, Y4P, Y4N
Output voltage
–0.3
VDDO_x +
0.3
V
STATUS/GPIO1, SDA/GPIO2, SCL/GPIO3, OE/GPIO4
Output voltage
–0.3
VDDREF +
0.3
V
TJ
Junction temperature
125
ºC
Tstg
Storage temperature
150
ºC
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
1.71
3.465
V
Output supply voltage
1.71
3.465
V
Output supply voltage
1.71
3.465
V
VDDO3
Output supply voltage
1.71
3.465
V
VDDO4
Output supply voltage
1.71
3.465
V
TA
Ambient temperature
–40ºC
85
ºC
VDDREF,
VDDVCO
Core supply voltage (1)
VDDO1
VDDO2
(1)
NOM
VDDREF and VDDVCO must be powered from the same supply voltage.
6.4 Thermal Information
CDCI6214
THERMAL METRIC (1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
39.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.5
°C/W
RθJB
Junction-to-board thermal resistance
16.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.6
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
16.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 EEPROM Characteristics
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
nEEcyc
EEPROM programming cycles
tEEret
EEPROM data retention
TEST CONDITIONS
MIN
each word
TYP
10
MAX
UNIT
10,000
cycles
10
years
6.6 Reference Input, Single-Ended and Differential Mode Characteristics (REFP, REFN, FB_P,
FB_N)
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
fIN_Ref
Reference frequency
VIH
Input high voltage
LVCMOS input buffer
VIL
Input low voltage
LVCMOS input buffer
VIN_DIFF
Differential input voltage swing,
peak-to-peak
VDDREF = 2.5 V or 3.3 V, ACcoupled differential input buffer
VIN_DIFF
Differential input voltage swing,
peak-to-peak
VDDREF = 1.8 V, AC-coupled
differential input buffer
dVIN/dT
Input slew rate
20% – 80%
IDC
Input duty cycle
MIN
TYP
1
MAX
UNIT
250
MHz
0.8 ×
VDDREF
V
0.2 ×
VDDREF
V
0.5
1.6
V
0.5
1.0
V
3
V/ns
40%
60%
CIN_XOUT/FB_P Input capacitance
No xtal active, on-chip load
disabled, at 25°C
7
pF
CIN_XIN/FB_P
Input capacitance
No xtal active, on-chip load
disabled, at 25°C
5
pF
CIN_REF
Input capacitance
at 25°C
5
pF
6.7 Reference Input, Crystal Mode Characteristics (XIN, XOUT)
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
fIN_Xtal
Crystal frequency
Fundamental mode
ZESR
Crystal equivalent series resistance
A supported crystal is within
CL
PXTAL
MIN
TYP
MAX
UNIT
8
50
MHz
30
100
Ω
Crystal load capacitance
Using on-chip load capacitance. A
supported crystal is within.
5
8
pF
Crystal tolerated drive power
A supported crystal tolerates up to
100
CXIN_LOAD
On-Chip load capacitance
Programmable in typical 200fF steps at room temp
DNLXIN_LOAD
Differential non-linearity
at room temp
uW
3
9.1
200
pF
fF
6.8 General-Purpose Input and Output Characteristics (GPIO[4:1], SYNC/RESETN)
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.8 ×
VDDREF
UNIT
VIH
Input high voltage
VIL
Input low voltage
IIH
Input high level current
VIH = VDDREF
–0.02
μA
IIH
Input high level current
VIH = VDDREF, Pin 12, 19
0.004
μA
IIL
Input low level current
VIL = GND
–50
μA
IIL
Input low level current
VIL = GND, Pin 12, 19
–0.004
μA
dVIN/dT
Input slew rate
20% – 80%
CIN_GPIO
Input Capacitance
6
V
0.2 ×
VDDREF
0.5
V/ns
10
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pF
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General-Purpose Input and Output Characteristics (GPIO[4:1], SYNC/RESETN) (continued)
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.8 ×
VDDREF
VOH
Output high voltage
only capacitive load
V
VOL
Output low voltage
only capacitive load
dVOUT/dT
Output slew rate
20% - 80%, at 10pF
0.3
V/ns
RPU
Pullup resistance
Pin 11, 20
77
kΩ
0.2 ×
VDDREF
V
6.9 Triple Level Input Characteristics (EEPROMSEL, REFSEL)
VDDVCO,VDDO12, VDDO34, VDDREF = 1.8V ±5%, 2.5V ±5%, 3.3V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
Input high voltage
0.8 ×
VDDREF
VIM
Input mid voltage
0.41 ×
VDDREF
VIL
Input low voltage
IIH
Input high level current
VIH = VDDREF
40
μA
IIM
Input mid level current
VIH = VDDREF/2
–1
μA
IIL
Input low level current
VIL = GND
–40
μA
tRIN
input slew rate
10% - 90%
V
0.5 ×
VDDREF
0.58 ×
VDDREF
V
0.2 ×
VDDREF
V
50
ns
CIN_TRI
10
RPDPU
pF
64
kΩ
6.10 Reference Mux Characteristics (1)
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
LREF_MUX
Reference mux isolation
XIN = Crystal 25 MHz, REF = 27
MHz
LREF_MUX
Reference mux isolation
XIN = Crystal 25 MHz, REF =
24.576 MHz
(1)
MIN
TYP
MAX
UNIT
89
dBc
78
dBc
Mux isolation is defined as the attenuation relative to the carrier base harmonic as a positive dBc number.
6.11 Phase-Locked Loop Characteristics
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
1
TYP
100
MHz
2400
2800
MHz
100
3000
kHz
400
700
MHz
fPFD
Phase detector frequency
fVCO
Voltage-controlled oscillator
frequency
fBW
Configurable closed-loop PLL
bandwidth
fCLKDIST
Clock distribution frequency
KVCO
Voltage-controlled oscillator gain
fVCO = 2.4 GHz
62
MHz/V
KVCO
Voltage-controlled oscillator gain
fVCO = 2.5 GHz
62
MHz/V
KVCO
Voltage-controlled oscillator gain
fVCO = 2.8 GHz
92
MHz/V
|ΔTCL|
Allowable temperature drift for
continuous lock
dT/dt ≤ 20 K / min
REF = 25 MHz
125
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6.12 Closed-Loop Output Jitter Characteristics
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
tRJ_CL
RMS phase jitter
TEST CONDITIONS
MIN
TYP
MAX
UNIT
int. Range from 10 kHz to 20 MHz ,
XIN = Crystal 25 MHz, Integer
Output Divider, Yx = 156.25 MHz
LVDS
500
750
fs
int. Range from 10 kHz to 20 MHz ,
XIN = Crystal 25 MHz, Integer
Output Divider, Yx = 100 MHz HCSL
386
800
fs
500
fs
PCIe Gen 3/4 Common Clock
transfer functions applied, XIN =
Crystal 25 MHz, Integer Output
Divider, Yx = 100 MHz HCSL
int. Range from 10 kHz to 20 MHz ,
XIN = Crystal 25 MHz, VCO = 2500
MHz, Fractional Output Divider , Y1
=133+1/3 MHz LVDS (1)
(1)
3
ps
Integrated RMS jitter at other frequencies using fractional output divider may vary. Contact TI for further assistance.
6.13 PCIe Gen1 Spread Spectrum Generator
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C, fVCO = 2.4
GHz, ch[4:1]_iod_mux = 2, ch[4:1]_iod = 3, ch[4:1]_ssc_counter = 4, ch[4:1]_ssc_fmod = 1, ch[4:1]_ssc_type =
1, ch[4:1]_ssc_spread = 0
PARAMETER
fSSC
TEST CONDITIONS
MIN
TYP
SSC deviation
31.25
tSSC_FREQ_ SSC deviation
–0.5%
MAX
UNIT
kHz
DEVIATION
6.14 Output Mux Characteristics (1)
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
LOUT_MUX
LOUT_MUX
LOUT_MUX
LOUT_MUX
LOUT_MUX
(1)
8
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output mux isolation
REF = 27 MHz, XIN = 25 MHz, VCO
= 2500 MHz, PSFB = 4, Y_ODD =
312.5 MHz, Y_EVEN = 208.3 MHz,
LVPECL
65
dBc
Output mux isolation
REF = 27 MHz, XIN = 25 MHz, VCO
= 2500 MHz, PSFB = 4, Y_ODD =
312.5 MHz, Y_EVEN = 250 MHz,
LVPECL
63
dBc
Output mux isolation
REF = 27 MHz, XIN = 25 MHz, VCO
= 2500 MHz, PSFB = 4, Y_ODD =
312.5 MHz, Y_EVEN = 89.3 MHz,
LVPECL
72
dBc
Output mux isolation
REF = 27 MHz, XIN = 25 MHz, VCO
= 2500 MHz, PSFB = 4, IODs =
312.5 MHz, Yx=BYPASS (XIN),
LVPECL
64
dBc
Output mux isolation
REF = 27 MHz, XIN = 25 MHz, VCO
= 2500 MHz, PSFB = 4, Y_ODD =
100 MHz, Y_EVEN = 266.6 MHz,
LVPECL
57
dBc
Mux isolation is defined as the attenuation relative to the carrier base harmonic as a positive dBc number.
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6.15 LVCMOS Output Characteristics
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
fO_LVCMOS
Output frequency
VDDO_x = 2.5 V or 3.3 V, normal
drive
fO_LVCMOS
Output frequency
VDDO_x = 1.8 V, normal drive
VOH_LVCMO
TYP
MAX
UNIT
0.1
350
MHz
0.1
250
MHz
0.8 ×
VDDREF
Output high voltage
Normal mode, only capacitive load
Output low voltage
Normal mode, only capacitive load
Output high voltage
Slow mode, only capacitive load
Output low voltage
Slow mode, only capacitive load
Output impedance
Normal mode
28
Ω
Output impedance
Weak mode
80
Ω
Phase noise floor, single side band
fCARRIER = 100 MHz, fOFFSET = 10
MHz
S
VOL_LVCMO
MIN
V
0.2 ×
VDDREF
S
VOH_LVCMO
S
VOL_LVCMO
0.7 ×
VDDREF
V
0.3 ×
VDDREF
S
RON_LVCMO
V
V
S
RON_LVCMO
S
LLVCMOS_10
0M
–148
dBc/Hz
6.16 HCSL Output Characteristics
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
350
MHz
0.55
V
1.0
V
0.8
2.0
Vpp
250
550
mV
fO_HCSL
Output frequency
VCM_HCSL
Output common mode
VOD
Differential output voltage
fO_HCSL = 100 MHz
0.4
VSS
Differential output voltage, peak to
peak
fO_HCSL = 100 MHz
VCROSS
Absolute crossing point
Rp = 49.9 Ω ±5%, fO_HCSL = 100
MHz
ΔVCROSS
Relative crossing point variation
w.r.t to average crossing
point, fO_HCSL = 100 MHz
dV/dt
Slew rate for rising and falling edge
Differential, at VCROSS ±150 mV,
fO_HCSL = 100 MHz (1)
ΔdV/dt
Slew rate matching
Single-ended, at VCROSS ±75 mV,
fO_HCSL = 100 MHz (1)
ODC
Output duty cycle
Not in PLL bypass mode
RP
Parallel termination
Rp = 49.9 Ω ±5% required
LHCSL_100M Phase noise floor, single side band
(1)
TYP
0.1
0.2
0.34
100
1
mV
4
V/ns
20%
45%
55%
45
55
fCARRIER = 100 MHz, fOFFSET = 10
MHz
-152
Ω
dBc/Hz
PCIe test load slew rate
6.17 LVDS DC-Coupled Output Characteristics
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
0.1
MAX
UNIT
350
MHz
fO_PRG_AC
Output frequency
VCM
Output common mode
VDDO_X = 2.5 V, 3.3 V,
chx_lvds_cmtrim_inc = 2
1.125
1.2
1.375
V
VCM
Output common mode
VDDO_X = 1.8 V,
chx_lvds_cmtrim_inc = 2
0.8
0.9
1
V
VOD
Differential output voltage
LVDS
0.3
0.45
tRF
Output rise/fall times
LVDS (20% to 80%)
0.25
675
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LVDS DC-Coupled Output Characteristics (continued)
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
ODC
LLVDS_DC_1
TEST CONDITIONS
Output duty cycle
Not in PLL bypass mode
Phase noise floor, single side band
fCARRIER = 100MHz, fOFFSET =
10MHz
00M
MIN
TYP
45%
MAX
UNIT
55%
–152
dBc/Hz
6.18 Programmable Differential AC-Coupled Output Characteristics
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C and AC-coupled
outputs
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
350
MHz
Output frequency
VOD
Differential output voltage
LVDS-like
0.45
V
VOD
Differential output voltage
CML-like
0.8
V
VOD
Differential output voltage
LVPECL-like
0.9
V
tRF
Output rise/fall times
LVDS-like (20% to 80%)
675
ps
tRF
Output rise/fall times
CML-like (20% to 80%)
520
ps
tRF
Output rise/fall times
LVPECL-like (20% to 80%)
500
ODC
Output duty cycle
Not in PLL bypass mode
LDIFF_AC_10
Phase noise floor, single side band
fCARRIER = 100 MHz, fOFFSET = 10
MHz
0M
0.1
MAX
fO_PRG_AC
45%
ps
55%
–152
dBc/Hz
6.19 Output Skew and Delay Characteristics
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSK_HCSL
Skew between HCSL
Y[4:1] = HCSL, fOY[4:1] = 100 MHz
140
ps
tSK_DIFFAC
Skew between progr. differential AC
Y[4:1] = programmable output
swing, fOY[4:1] = 100 MHz
150
ps
tSK_LVCMOS Skew between LVCMOS
Y[4:1] = LVCMOS, fOY[4:1] = 100
MHz
100
ps
tSK_LVCMOS
Skew between LVCMOS to Bypass
Y[4:0] = LVCMOS, fOY[4:0] = 100
MHz
3
ns
Propagation delay
REF = 67 MHz, VCO = 2680 MHz,
PSFB = 4, PSAY_ODD = 4,
PSBY_EVEN = 4, IODY_ODD = 10,
IODY_EVEN = 10, YP_ODD = YN_ ODD
= IOD, in ext. ZDM, LVCMOS
_BYP
tPD_ZDM
–600
600
ps
MAX
UNIT
6.20 Output Synchronization Characteristics
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
tSU_SYNC
Setup time SYNC pulse
With respect to PLL reference rising
edge at 100 MHz with R = 1
tH_SYNC
Hold time SYNC pulse
With respect to PLL reference rising
edge at 100 MHz with R = 1
tPWH_SYNC
High pulse width for SYNC
With R = 1, at least 2 PFD periods
+ 24 feedback pre-scaler periods
60
ns
tPWL_SYNC
Low pulse width for SYNC
With R = 1, at least 1 PFD period
6
ns
tEN
Individual output enable time (1)
Tri-state to first rising edge, fY[4:1] <
200 MHz
(1)
10
MIN
TYP
3
ns
3
4
ns
nCK
Output clock cycles of respective output channel. Global output enable handled by digital logic, additional propagation will be added.
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Output Synchronization Characteristics (continued)
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
tDIS
Individual output disable time (1)
TEST CONDITIONS
MIN
TYP
Last falling edge to tri-state, fY[4:1] <
200 MHz
MAX
4
UNIT
nCK
6.21 Timing Characteristics
VDDVCO,VDDO12,VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
tINIT
Initialization time
Initialization time from POR to
device releasing PLL outputs.
tVDD
Power supply ramp
Timing requirement for any VDD pin
while RESETN = LOW
MIN
TYP
50
MAX
UNIT
5
ms
2000
µs
MAX
UNIT
6.22 I2C-Compatible Serial Interface Characteristics (SDA/GPIO2, SCL/GPIO3)
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
0.7 ×
VDDREF
VIH
Input voltage, logic high
V
VIL
Input voltage, logic low
VHYS
Input Schmitt trigger hysteresis
VDDREF = 3.3 V, fSCL = 400 kHz
156
mV
VHYS
Input Schmitt trigger hysteresis
VDDREF = 2.5 V, fSCL = 400 kHz
118
mV
VHYS
Input Schmitt trigger hysteresis
VDDREF = 1.8 V, fSCL = 400 kHz
85
IIH
Input leakage current
VDDREF = 0.17 V..3.12 V
VOL
Low-level output voltage
VOL
0.3 ×
VDDREF
V
mV
–10
10
μA
At 3-mA sink current, VDDREF = 3.3
V – 5%
0.4
V
Low-level output voltage
At 3-mA sink current, VDDREF = 2.5
V – 5%
0.4
V
VOL
Low-level output voltage
At 2-mA sink current, VDDREF = 1.8
V – 5%
0.342
V
IOL
Low-level output current
VOL = 0.4 V
CIN
Input capacitance
3
mA
10
pF
6.23 Timing Requirements, I2C-Compatible Serial Interface (SDA/GPIO2, SCL/GPIO3)
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPW_G
Pulse width of suppressed glitches
fSCL
SCL clock frequency
Standard
100
50
kHz
fSCL
SCL clock frequency
Fast-mode
400
kHz
tSU_STA
Setup time start condition
SCL = VIH before SDA = VIL
0.6
μs
tH_STA
Hold time start condition
SCL = VIL after SCL = VIL. After this
time, the first clock edge is
generated.
0.6
μs
tSU_SDA
Setup time data
SDA valid after SCL = VIL, fSCL =
100 kHz
250
ns
tSU_SDA
Setup time data
SDA valid after SCL = VIL, fSCL =
400 kHz
100
ns
tH_SDA
Hold time data
SDA valid before SCL = VIH
0
μs
tPWH_SCL
Pulse width high, SCL
fSCL = 100 kHz
4
μs
tPWH_SCL
Pulse width high, SCL
fSCL = 400 kHz
0.6
μs
tPWL_SCL
Pulse width low, SCL
fSCL = 100 kHz
4.7
μs
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Timing Requirements, I2C-Compatible Serial Interface (SDA/GPIO2, SCL/GPIO3) (continued)
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
tPWL_SCL
Pulse width low, SCL
fSCL = 400 kHz
tOF
Output fall time
COUT = 10..400 pF
MIN
TYP
MAX
UNIT
250
ns
MAX
UNIT
1.3
μs
6.24 Power Supply Characteristics
VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40ºC to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
IDD_REF
Reference input current
DBL = on
4
mA
IDD_XIN
Crystal input current
Crystal with Pmax = 200 μW
2
mA
IDD_VCO
VCO and PLL current
fVCO = 2500 MHz, PSFB = PSA = 4
and PSB = off
13
mA
IDD_OUT
Output channel current
Activated output channel, 1x LVDS
156.25 MHz
10
mA
IDD_IOD
Output integer divider current
2
mA
IDD_FOD
Output fractional divider current
20
mA
IDD_PDN
Power-down current
Using reset pin / bits
3
mA
IDD_TYP
Typical current
4x 156.25-MHz LVDS case using
crystal input and doubler
83
mA
IDD_TYP
Typical current
2x IODs LVDS/LVCMOS, 1x FOD
LVDS
72
mA
LPSNR
Power supply noise rejection (1)
Yx = 100 MHz LVDS, on one of
VDDx injected sine wave 50 mV at
fINJ = 10 kHz,
–56
dBc
LPSNR
Power supply noise rejection (1)
Yx = 100MHz LVDS, on one of
VDDx injected sine wave 50 mV at
fINJ = 100 kHz
–46
dBc
LPSNR
Power supply noise rejection (1)
Yx = 100MHz LVDS, on one of
VDDx injected sine wave 50 mV at
fINJ = 1 MHz
–49
dBc
LPSNR
Power supply noise rejection (1)
Yx = 100MHz LVDS, on one of
VDDx injected sine wave 50 mV at
fINJ = 10 MHz
–69
dBc
LPSNR
Power supply noise rejection (1)
Yx = 100MHz LVDS, on one of
VDDx injected sine wave 50 mV at
fINJ = 20 MHz
–74
dBc
LPSNR
Power supply noise rejection (1)
Yx = 100MHz LVDS, on one of
VDDx injected sine wave 50 mV at
fINJ = 40 MHz
–73
dBc
(1)
12
dBc with respect to output carrier frequency.
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6.25 Typical Characteristics
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
Power Density in dBc/Hz
Power Density in dBc/Hz
VDDx = 1.8 V at room temperature
-70
-80
-90
-100
-110
-120
-130
-140
-70
-80
-90
-100
-110
-120
-130
-140
-150
-150
-160
-160
-170
-180
102
-170
10
3
4
10
5
10
10
6
7
10
7
4x10
-180
102
103
Frequency in Hz
Reference: Crystal
25 MHz
104
105
106
107
4x107
Frequency in Hz
Closed-Loop Phase Noise 100-MHz HCSL
from 2.4-GHz VCO
Reference: Crystal
25 MHz
Figure 1. 100-MHz Carrier
Closed-Loop Phase Noise 156.25-MHz
LVDS from 2.5-GHz VCO
Figure 2. 156.25-MHz Carrier
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7 Parameter Measurement Information
7.1 Parameters
7.1.1 Reference Inputs
VDD
VDD
R1 = 100 W
RS
ZO = 50 W
RINT
XOUT/FB_P
C = 0.1 mF
XIN/FB_N
R2 = 100 W
Clock Generator:
RINT + RS = 50 W
Figure 3. Single-Ended LVCMOS Crystal Input
Signal
Generator
(1)
< 2 VPP
DUT
100
Applied signal has to stay within VIN_DIFF limits.
Figure 4. Differential AC-Coupled Input
7.1.2 GPIOs
7.1.3 Outputs
Scope
LVCMOS
50
DUT
GND
Figure 5. LVCMOS Output
14
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Parameters (continued)
100 k
100 k
1 pF
33
(1)
< 1 pF
< 1 pF
GND
50
High
Impedance
Probe
Measured using Tektronix DPO75902SX oscilloscope. Recommended to use an oscilloscope bandwidth setting of 4/8
GHz and vertical setting of 50mV/division. Data processed using Clock Jitter Tool: Ver:1.6.7.2.
Figure 14. HCSL PCIe Test Load Setup
7.1.4 Serial Interface
STOP
ACK
START
tIR
tPWL_SCL tPWH_SCL
STOP
tIF
~~
VIH
SCL
~~
VIL
tH_STA
tSU_STA
tBUS
tIR
tSU_SDA
tH_SDA
tIF
tSU_STOP
~~
~~
VIH
SDA
~~
VIL
Figure 15. I2C Timing
7.1.5 Power Supply
Sine
Wave
Modulator
Power Supply
Signal
Generator
DUT
Reference
Input
Device Output
Balun
Phase Noise/
Spectrum
Analyzer
Figure 16. PSNR Setup
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8 Detailed Description
8.1 Overview
The CDCI6214 clock generator is a phase-locked loop with integrated loop filter and selectable input reference.
The output of the integrated voltage-controlled oscillator (VCO) is connected to a clock distribution network,
which includes multiple frequency dividers and feeds four output channels with configurable differential and
single-ended output buffers.
8.2 Functional Block Diagram
VDDVCO
24
CDCI6214
7
Y0
LVCMOS
4
Differential
REFP 5
VCO
x
REFN 6
PSA
Phase Locked Loop
1 MHz
to 250 MHz
FOD1
24 Bit
(+SSC)
PSB
REFSEL 4
BYP
2400 MHz
to 2800 MHz
21
ch2
DS
100 kHz
to 3000 kHz
@25 MHz
1 MHz
to 100 MHz
1 MHz
to 50 MHz
22
DS
IOD1
14 Bit
ch1_mux
PSA
ch1_iod_mux
/4, /5, /6
x2
CP
R
8 MHz
to 50 MHz
16 VDDO12
LF
PFD
x
VCO
DS
8 Bits
OSC
XOUT/FB_P
N
1
PSB
VCO
/4, /5, /6
PSA
PSFB
PSB
/4, /5, /6
14 Bits
ZDM
CL
x
FOD2
24 Bit
(+SSC)
x
DS
IOD2
14 Bit
BYP
ch1
18
ch3
17
Y2P
Y2N
ch2_mux
ch2_iod_mux
2
XIN/FB_N
Y1P
Y1N
3 pF
to 9 pF
x
x
LDOs for Analog
VCO
VDDREF 3
FOD3
24 Bit
(+SSC)
PSA
PSB
LDO for Digital
x
DS
IOD3
14 Bit
ch4
BYP
Osc.
ch3_mux
ch3_iod_mux
M
H
L
Registers
14 Y3P
Y3N
13
ch2
Default
15 VDDO34
x
SCL 12
I2C
Digital
Page 1
SDA 19
VCO
FOD4
24 Bit
(+SSC)
PSA
Page 0
x
GPIO
GPIO
Reset
GPO
Sync
PSB
x
DS
IOD4
14 Bit
BYP
11
20
8
GPIO1
RESETN / SYNC
9
DS
Y4P
Y4N
ch4_mux
EEPROM
GPIO4
10
ch3
ch4_iod_mux
23
x
EEPROMSEL
blockdiag_detailed_pg1p0_v7
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Figure 17. CDCI6214 Clock Generator With Four Outputs
x
18
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8.3 Feature Description
The following sections describe the individual blocks of the CDCI6214 ultra-low power clock generator.
8.3.1 Reference Block
A reference clock to the PLL is fed to pins 1 (XOUT/FB_P) and 2 (XIN/FB_N) or to pins 5 (REFP) and 6 (REFN).
There are multiple input stages available to adapt to many clock references. The bit-fields that control the
reference input type selection are xin_inbuf_ctrl and ref_inbuf_ctrl.
The reference mux selects the reference for the PLL and the PLL-bypass path. For debug purposes ip_byp_mux
allows to connect the reference divider or doubler output to the clock distribution.
The buffers for the PLL-bypass path can be individually enabled and disabled using ip_byp_en_ch[4:1] and
ip_byp_en_y0.
ref_inbuf_ctrl
ch0_lvcmos_drv
REFP 5
ip_byp_en_y0
x
REFN 6
7
Y0
ip_byp_mux
4
REFSEL 4
ip_rdiv = 0
ref_mux
x2
ref_mux_src
PLL
ip_xo_gm
chX
R
ip_xo_gm_fine
ip_rdiv t 1
OSC
chX_iod_mux
ip_byp_en_chX
ip_rdiv
ip_xo_cload
XOUT/FB_P 1
CL
x
PLL
XIN/FB_N 2
xin_inbuf_ctrl
Internal
Zero Delay
Feedback
Figure 18. Reference Block
8.3.1.1 Input Stages
8.3.1.1.1 Crystal Oscillator
The XIN and XOUT pins provide a crystal oscillator stage to drive a fundamental mode crystal in the range of 8
MHz to 50 MHz. The crystal input stage integrates a tunable load capacitor array up to 9 pF using ip_xo_cload.
The drive capability of the oscillator is adjusted using ip_xo_gm.
8.3.1.1.2 LVCMOS
The LVCMOS input buffer threshold voltage follows VDDREF. This helps to use the device as a level shifter as
the outputs have separate supplies.
8.3.1.1.3 Differential AC-Coupled
The differential input stage has an internal bias generator and should only be used with AC-coupled reference
inputs.
8.3.1.2 Reference Mux
Either XIN or REF can be selected as reference to the PLL and clock distribution path. The reference mux is
controlled using the REFSEL pin with ref_mux_src = 0 or the ref_mux bit-field with ref_mux_src = 1.
8.3.1.3 Reference Divider
A reference divider can be used to divide higher input frequencies to the permitted PFD range. It supports
division values of 1 to 255 using ip_rdiv.
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Feature Description (continued)
8.3.1.3.1 Doubler
The reference path contains a doubler circuit. It is used to double the input frequency and can be used to
achieve the highest PFD update frequency of 100 MHz using a 50-MHz crystal. The doubler activates using
ip_rdiv = 0.
8.3.1.4 Bypass-Mux
The input reference or the input to the PFD can be routed to the bypass path using ip_byp_mux.
8.3.1.5 Zero Delay, Internal and External Path
In zero delay mode the REF input clock is used as reference clock at the PFD. The FB_P clock (LVCMOS) or
FB_P/N clock (differential) can be used to feed an external source as feedback clock to the PFD. The external
feedback path is recommended for zero delay operation. Moreover there is an additional internal feedback path
which is sourced by output channel 2.
Table 1. Zero Delay Operation (1)
Operation
Reference
Feedback
REFSEL
ref_mux
ref_mux_
src
Normal PLL, XIN
Reference
L
x
0
1
x
0
0
x
x
x
x
x
x
Normal PLL, REF
Reference
L
x
0
1
x
x
0
x
x
x
x
x
x
Normal PLL, REF
Reference
x
1
1
1
x
x
0
x
x
x
x
x
x
Zero Delay, Internal
Feedback
x
1
1
1
A
A
1
0
1
B
B
C
C
Zero Delay, External
Feedback
x
1
1
1
A
A
1
1
1
B
B
C
C
(1)
(2)
ip_rdiv
ref_inbuf
_ctrl
xin_inbuf
_ctrl
zdm_mo
de
zdm_cloc
ksel
zdm_aut
o
pll_psfb
pll_psa
pll_ndiv
ch2_iod_
div (2)
'x' allows any possible bit-field value. An entry of 'A', 'B' or 'C' indicates the same bit-field value.
For internal feedback channel 2 is required. For external feedback the output clock connected to FB_P/N is recommended to have same
settings as default PLL feedback path.
8.3.2 Phase-Locked Loop
The CDCI6214 contains a fully integrated phase-locked loop circuit. The error between a reference phase and an
internal feedback phase is compared at the phase-frequency-detector. The comparison result is fed to a charge
pump that is connected to an integrated loop filter. The control voltage resulting from the loop filter tunes an
internal voltage-controlled oscillator (VCO). The frequency of the VCO is fed through a pre-scaler feedback
divider (PSFB) and another feedback divider back to the PFD.
The PLL closed-loop bandwidth is configurable using registers PLL0, PLL1, and PLL2.
•
•
•
•
•
•
•
20
Integer PLL
PFD operates 1 MHz to 100 MHz
Live Lock-Detector provides PLL lock status on status pin and bit lock_det (there is an additional sticky bit
unlock_s)
Integrated selectable loop filter components
For 25-MHz PFD bandwidths between 100 kHz and 3000 kHz can be achieved to optimize PLL to input
reference
Voltage-Controlled Oscillator (VCO) tuning range of 2400 to 2800 MHz
VCO is compatible to 0.5% spread spectrum (SSC) references at 100 MHz.
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Clock Distribution
4
DS
pll_cp_dn
Reference Clock
Feedback Clock
pll_lf_res
pll_psa
RRes
Charge
Pump
Phase
Frequency
Detector
/4, /5 /6
Clock Distribution
Pre-Scaler A
Voltage Controlled
Oscillator
pll_cp_up
CPcap
CZcap
pll_lf_pcap
DS
/4, /5 /6
Clock Distribution
Pre-Scaler B
pll_lf_zcap
GND
14 Bit
Feedback Divider
FB_P/N
/4, /5 /6
Feedback Pre-Scaler
pll_ndiv
zdm_clocksel
zdm_mode
pll_psb
DS
Divider
Synchronization
pll_psfb
Internal (CH2)
x
x
Figure 19. Phase-Locked Loop Circuit
Table 2. Common Clock Generator Loop Filter Settings (1)
fVCO in MHz
(1)
(2)
fPFD in MHz
BW in MHz
Phase
Margin in °
Damping
Factor
ICP in mA
pll_cp_up
(2)
CPcap IN pF
RRes IN kΩ
CZcap IN pF
pll_lf_pcap
pll_lf_res
pll_lf_zcap
2400
25
0.51
67
0.9
2.0
17.5
2.5
450
2400
50
0.97
67
1.3
2.0
17.5
2.5
450
2400
100
1.41
68
1.2
2.4
17.5
1.5
450
2457.6
61.44
1.04
67
1.4
1.8
17.5
2.5
450
2500
25
0.49
67
0.9
2.0
17.5
2.5
450
2500
50
0.93
68
1.3
2.0
17.5
2.5
450
2680
67
0.38
67
1.3
0.2
19.5
5.5
480
2688
48
0.93
68
1.3
1.5
17.5
2.5
480
2688
96
0.36
67
1.0
0.2
19.5
3.5
480
2800
50
1.00
68
1.0
2.6
17.5
1.5
450
2800
100
1.00
68
1.0
1.3
17.5
1.5
450
All values typical design targets.
Program same value to pll_cp_dn.
8.3.3 Clock Distribution
The VCO connects to two individually configurable pre-scaler dividers sourcing the on-chip clock distribution.
The clock distribution consists of four output channels. Each output channel contains a divider with integer and
fractional division as well as spread-spectrum and synchronization capabilities.
A mux after each divider allows to feed the generated frequency to the adjacent output buffers. Thus for single
frequency clock generation only a single output divider needs to be active.
The output buffers are compatible to various signaling standards: LVDS, CML-like, LVPECL-like, LVCMOS and
HCSL using ch1_outbuf_ctrl.
• HCSL must be directly connected to a load termination to ground. A series resistance can be used to adapt to
the trace impedance.
• LVDS requires a differential termination connected between the positive and negative output buffer pins. The
termination can be connected directly or using AC-coupling. When using the LVDS output type, set
ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, andch4_1p8vdet to match the VDDO12 and VDDO34.
• CML and LVPECL are only supported in an AC-coupled configuration. The receiver and the termination may
only be connected through AC-coupling capacitors to the device pins.
• LVCMOS outputs are designed for capacitive loads only. A series resistance should be used to adapt the
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driver impedance to the trace impedance. For a typical 50-Ω trace, a resistor between 22 Ω to 33 Ω should be
used. The polarity of the positive and negative pins can be adjusted separately.
The output buffers support a wide frequency range of up to 350 MHz. Higher output frequencies up to 700 MHz
are functional, but are not covered by electrical specifications.
8.3.3.1 Output Channel
Figure 20. Clock Distribution Pre-Scaler Dividers (1)
chX_fod_msb
chX_fod
chX_syn c_en
24 Bit
Fractio nal Divide r
VCO
DS
PSA
5 Bit
Digital Del ay
PSB
chX_iod_div
chX-1
YXP
YXN
14 Bit
Inte ger Divide r
chX+1
chX_syn c_dela y
BYP
chX_mux
chX_iod_mux
chX_outbuf_ctrl
chX_mute_sel
chX_cmo s_pol
Clock Distribu tion
chX_1p8vdet
chx_lvcmos_drv
Figure 21. Clock Distribution, Output Channel
(1)
INSTANCES
DIVISION VALUES
PSA
4, 5, 6
PSB
4, 5, 6
A known phase relationship for divider synchronization with mixed division values is ensured by architecture.
Table 3. Output Buffer Signal Standards
OUTPUT
LVCMOS
Y0
X
Y1
LVDS
AC-CML (2)
AC-LVPECL (2)
X
X
X
X
Y2
X
X
X
X
X
Y3
X
X
X
X
X
x
X
x
X
Y4
(1)
(2)
HCSL (1)
For highest performance it is recommended to use HCSL on output Y1 or Y4.
The common mode shall be provided externally through an external bias source, like a voltage divider or pullup resistor. The output
buffer will provide sufficient swing.
Table 4. Output Channel Signal Selection
NO.
INPUT SOURCE
0
Channel N-1
Y1 (N=1)
Y2 (N=2)
Y3 (N=3)
Y4 (N=4)
x
x
x
x
1
IOD N
x
x
x
2
Channel N+1
x
x
x
Table 5. Integer Divider Input Selection
22
NO.
SOURCE
0
Pre-scaler A
1
Pre-scaler B
2
Fractional Divider
3
Bypass
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Table 6. Output Channel Divider Types and Delay
ABBREVIATION
TYPE
IOD
Integer
FOD
(1)
(2)
(3)
Fractional
DIVIDER
(2)
DELAY
MIN
MAX
PRE-SCALER, CYCLES
1
16383
32 (1)
2/3
4/3
32 (3)
Cycles of the selected pre-scaler PSA or PSB.
with respect to fractional divider input frequency fFOD_IN = fVCO / 8.
Cycles of fVCO/8.
8.3.3.2 Fractional Divider
8.3.3.2.1 Synthesis Mode
A 24-Bit resolution fractional divider synthesizes any frequency between fVCO/12 ≤ fFOD ≤ fVCO/6. The synthesized
frequency fFOD is available on the respective integer divider source mux ch[4:1]_iod_mux for further division when
required.
Please use the TICS Pro software to generate the fractional divider settings for ch[4:1]_fod_msb and ch[4:1]_fod.
In general the following bits should be considered to activate one of the fractional dividers.
• pdn_pll_fodclk = 0
• pdn_ch[4:1] = 0
• pdn_ch[4:1]_fod = 0
• ch[4:1]_iod_mux = 2
For spread spectrum operation the part shall be configured in "bypass-mode" which is basically a fVCO / 8 integer
mode. For bypass mode the settings shall be ch[4:1]_fod_msb = 32768 and ch[4:1]_fod = 0.
8.3.3.2.2 Spread Spectrum Clocking
The device offers a spread spectrum clocking option in each output channel. The following requirements have to
be met for the spread spectrum option to operate:
fY[4:1] = fVCO / (8 · ch[4:1]_iod_div)
where
•
•
•
2400
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