CDCLVP111MVFREP

CDCLVP111-EP www.ti.com SCAS933 – DECEMBER 2012 LOW-VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER Check for Samples: CDCLVP111-EP FEATURES 1 • • • • • • • • • Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL Fully Compatible With LVECL and LVPECL Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V Selectable Clock Input Through CLK_SEL Low-Output Skew (Typ 15 ps) for ClockDistribution Applications – Additive Jitter Less Than 1 ps – Propagation Delay Less Than 355 ps – Open Input Default State – LVDS, CML, SSTL input compatible VBB Reference Voltage Output for SingleEnded Clocking Available in a 32-Pin LQFP Package Frequency Range From DC to 3.5 GHz Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • • • • Controlled Baseline One Assembly and Test Site One Fabrication Site Available in Military (–55°C to 125°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability VF PACKAGE (TOP VIEW) APPLICATIONS • • Designed for Driving 50 Ω Transmission Lines High Performance Clock Distribution (1) Custom temperature ranges available DESCRIPTION The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω. The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor. However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended. The CDCLVP111 is characterized for operation from –55°C to 125°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated CDCLVP111-EP SCAS933 – DECEMBER 2012 www.ti.com Table 1. FUNCTION TABLE CLK_SEL ACTIVE CLOCK INPUT 0 CLK0, CLK0 1 CLK1, CLK1 Table 2. ORDERING INFORMATION (1) TJ PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER –55°C to 125°C LQFP - VF CDCLVP111MVFREP LVP111MEP V62/12624-01XE (1) 2 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :CDCLVP111-EP CDCLVP111-EP www.ti.com SCAS933 – DECEMBER 2012 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DEVICE INFORMATION 31 30 29 28 27 26 24 3 CLK0 CLK0 + 0 4 - CLK1 CLK1 23 22 21 6 + 1 7 - 20 19 - 18 17 CLK_SEL 2 15 14 - 13 12 11 VBB 5 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 PIN FUNCTIONS (1) PIN NAME CLK_SEL DESCRIPTION NO. 2 CLK0, CLK0 3, 4 CLK1, CLK1 6, 7 Clock select. Used to select between CLK0 and CLK1 input pairs. LVTTL/LVCMOS functionality compatible. Differential LVECL/LVPECL input pair Q [9:0] 11, 13, 15, 18, 20, 22, 24, 27, 29, 31 LVECL/LVPECL clock outputs, these outputs provide low-skew copies of CLKn. Q[9:0] 10, 12, 14, 17, 19, 21,23, 26, 28, 30 LVECL/LVPECL complementary clock outputs, these outputs provide copies of CLKn. VBB 5 VCC 1, 9, 16, 25, 32 VEE 8 (1) Reference voltage output for single-ended input operation Supply voltage Device ground or negative supply voltage in ECL mode CLKn, CLK_SEL pull down resistor = 75 kΩ; CLKn pull up resistor = 37.5 kΩ; CLKn pull down resistor = 50 kΩ. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :CDCLVP111-EP 3 CDCLVP111-EP SCAS933 – DECEMBER 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT –0.3 to 4.6 V Input voltage –0.3 to VCC + 0.5 V VO Output voltage –0.3 to VCC + 0.5 V IIN Input current ±20 mA VEE Negative supply voltage (Relative to VCC) IBB Sink/source current IO DC output current Tstg Storage temperature range TJ Maximum operating junction temperature VCC Supply voltage (Relative to VEE) VI (1) –4.6 to 0.3 V –1 to 1 mA –50 mA –65 to 150 °C 150 °C Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VCC Supply voltage (relative to VEE) 2.375 2.5/3.3 3.8 UNIT V TJ Operating junction temperature –55 125 °C PACKAGE THERMAL IMPEDANCE, VF (LQFP) θJA θJC (1) 4 Thermal resistance junction to ambient (1) TEST CONDITION VALUE UNIT 0 LFM 74 °C/W 150 LFM 66 °C/W 250 LFM 64 °C/W 500 LFM 61 °C/W 39 °C/W Thermal resistance junction to case According to JESD 51-7 standard. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :CDCLVP111-EP CDCLVP111-EP www.ti.com SCAS933 – DECEMBER 2012 Estimated Life (Years) 100 Electromigration FailMode 10 Wirebond Voiding Fail Mode 1 105 110 115 120 125 130 135 140 145 150 Continuous T J (°C) (1) See data sheet for absolute maximum and minimum recommended operating conditions. (2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). Figure 1. CDCLVP111 in 32/VF Package Operating Life Derating Chart Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :CDCLVP111-EP 5 CDCLVP111-EP SCAS933 – DECEMBER 2012 www.ti.com LVECL DC ELECTRICAL CHARACTERISTICS Vsupply: VCC = 0 V, VEE = -2.375 V to -3.8 V over operating temperature range TJ = –55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX IEE Supply internal current Absolute value of current ICC Output and internal supply current All outputs terminated 50 Ω to VCC – 2 V IIN Input current Includes pullup/pulldown resistors, VIH = VCC, VIL = VCC - 2 V –55°C, 25°C, 125°C –150 For VEE = –3 to –3.8 V, IBB = –0.2 mA –55°C, 25°C, 125°C –1.45 –1.3 –1.125 VBB Internally generated bias voltage VEE = –2.375 to –2.75 V, IBB = –0.2 mA –55°C, 25°C, 125°C –1.4 –1.25 –1.1 –55°C, 25°C, 125°C 35 85 –55°C, 25°C 385 125°C 405 150 UNIT mA mA μA V VIH High-level input voltage (CLK_SEL) –55°C, 25°C, 125°C –1.165 –0.88 V VIL Low-level input voltage (CLK_SEL) –55°C, 25°C, 125°C –1.81 –1.475 V VID Input amplitude (CLKn, CLKn) Difference of input, See –55°C, 25°C, 125°C 0.5 1.3 V VCM Common-mode voltage (CLKn, CLKn) DC offset relative to VEE –55°C, 25°C, 125°C VEE + 1 –0.3 V –55°C –1.26 –0.85 VOH High-level output voltage IOH = –21 mA 25°C –1.2 –0.85 125°C –1.15 –0.8 25°C –1.85 –1.425 –55°C, 125°C –1.85 –1.25 VOL Low-level output voltage IOL = –5 mA VOD Differential output voltage swing Terminated with 50 Ω to VCC –2 V, See Figure 4 (1) 6 (1) VIH - VIL –55°C, 25°C, 125°C 400 V V mV VID minimum and maximum is required to maintain ac specifications, actual device function tolerates a minimum VID of 100 mV. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :CDCLVP111-EP CDCLVP111-EP www.ti.com SCAS933 – DECEMBER 2012 LVPECL DC ELECTRICAL CHARACTERISTICS Vsupply: VCC = 2.375 V to 3.8 V, VEE= 0 V over operating temperature range TJ = –55°C to 125°C (unless otherwise noted) PARAMETER IEE Supply internal current TEST CONDITIONS Absolute value of current MIN –55°C, 25°C, 125°C TYP MAX 35 UNIT 85 -55°C, 25°C 385 125°C 405 mA ICC Output and internal supply current All outputs terminated 50 Ω to VCC – 2 V IIN Input current Includes pullup/pulldown resistors VIH = VCC, VIL= VCC–2V –55°C, 25°C, 125°C –150 Internally generated bias voltage VCC = 3 to 3.8 V, IBB= –0.2 mA –55°C, 25°C, 125°C VCC – 1.45 VCC – 1.3 VCC – 1.125 VBB VCC = 2.375 to 2.75 V, IBB = –0.2 mA –55°C, 25°C, 125°C VCC – 1.4 VCC – 1.25 VCC – 1.1 VIH High-level input voltage (CLK_SEL) –55°C, 25°C, 125°C VCC – 1.165 VCC – 0.88 V VIL Low-level input voltage (CLK_SEL) –55°C, 25°C, 125°C VCC – 1.81 VCC – 1.475 V VID Input amplitude (CLKn, CLKn) Difference of inpu, see –55°C, 25°C, 125°C 0.5 1.3 V VCM Common-mode voltage (CLKn, CLKn) DC offset relative to VEE –55°C, 25°C, 125°C 1 VCC – 0.3 V –55°C VCC – 1.26 VCC – 0.85 VOH High-level output voltage IOH = –21 mA 25°C VCC – 1.2 VCC – 0.85 125°C VCC – 1.15 VCC – 0.8 25°C VCC – 1.85 VCC – 1.425 –55°C, 125°C VCC – 1.85 VCC – 1.25 (1) VOL Low-level output voltage IOL = –5 mA VOD Differential output voltage swing Terminated with 50 Ω to VCC - 2 V, See Figure 4 (1) , VIH - VIL –55°C, 25°C, 125°C mA μA 150 V V V 400 mV VID minimum and maximum is required to maintain ac specifications, actual device function tolerates a minimum VID of 100 mV. AC ELECTRICAL CHARACTERISTICS Vsupply: VCC = 2.375 V to 3.8 V, VEE = 0 V or LVECL/LVPECL input VCC = 0 V, VEE = -2.375 V to -3.8 V over operating temperature range TJ = –55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP tpd Differential propagation delay CLKn, CLKn to all Q0, Q0… Q9, Q9 See Note D in Figure 2 tsk(o) Output-to-output skew See Notes A and D in Figure 2 15 tsk(pp) Part-to-part skew See Notes B and D in Figure 2 70 taj Additive phase jitter (1) Integration bandwidth of 20 kHz to 20 MHz, fout = 200 MHz at 25°C f(max) Maximum frequency (1) Functional up to 3.5 GHz, see Figure 4 tr/tf Output rise and fall time (20%, 80%) See Note D in Figure 2 (1) 200 0.125 MAX UNIT 355 ps 50 ps ps 0.8 ps 3500 MHz 240 ps Specification is guaranteed by bench characterization and is not tested in production. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :CDCLVP111-EP 7 CDCLVP111-EP SCAS933 – DECEMBER 2012 www.ti.com CLKn CLKn Q0 tPLH0 tPLH0 tPLH1 tPLH1 Q0 Q1 Q1 Q2 tPLH2 tPLH2 Q2 tPLH9 o o o o o tPLH9 Q9 Q9 A. Output skew is calculated as the greater of: The difference between the fastest and the slowest tPLHn (n = 0, 1,...9) or the difference between the fastest and the slowest tPHLn (n = 0, 1,...9). B. Part-to-part skew, is calculated as the greater of: The difference between the fastest and the slowest tPLHn (n = 0, 1,...9) across multiple devices or the difference between the fastest and the slowest tPHLn (n = 0, 1,...9) across multiple devices. C. Typical value measured at ambient when clock input is 155.52 MHz for an integration bandwidth of 20 kHz to 5 MHz. D. Input conditions: VCM = 1 V, VID = 0.5 V and FIN = 1 GHz. Figure 2. Waveform for Calculating Both Output and Part-to-Part Skew VCC ZO = 50 Ω Yn CDCLVP111 Driver LVPECL Receiver ZO = 50 Ω Yn 50 Ω 50 Ω VEE VT = VCC - 2 V Figure 3. Typical Termination for Output Driver (See the Interfacing Between LVPECL, LVDS, and CML Application Note, Literature Number SCAA056) 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :CDCLVP111-EP CDCLVP111-EP www.ti.com SCAS933 – DECEMBER 2012 DIFFERENTIAL OUTPUT VOLTAGE SWING vs FREQUENCY 1000 VODtyp - Differential Output Voltage Swing - mV 900 800 700 600 25°C 500 125°C -55°C 400 300 200 100 0 1 1.5 2 2.5 3 3.5 f - Frequency - GHz Figure 4. LVPECL Input Using CLK0 Pair, VCC = 2.375 V, VCM = 1 V, VID = 0.5 V Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :CDCLVP111-EP 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) CDCLVP111MVFREP ACTIVE LQFP VF 32 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 LVP111MEP V62/12624-01XE ACTIVE LQFP VF 32 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 LVP111MEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of