CDCLVP2102RGTT

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents CDCLVP2102 SCAS881C – AUGUST 2009 – REVISED JANUARY 2016 CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer 1 Features 3 Description • • • The CDCLVP2102 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications. 1 • • • • • • • • • • • • Dual 1:2 Differential Buffer Two Clock Inputs Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL Four LVPECL Outputs Maximum Clock Frequency: 2 GHz Maximum Core Current Consumption: 48 mA Very Low Additive Jitter: