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CDCM1802
SCAS759C – APRIL 2004 – REVISED JULY 2017
CDCM1802 Clock Buffer With Programmable Divider,
LVPECL I/O + Additional LVCMOS Output
1 Features
3 Description
•
The CDCM1802 clock driver distributes one pair of
differential clock input to one LVPECL differential
clock output pair, Y0 and Y0, and one single-ended
LVCMOS output, Y1. It is specifically designed for
driving 50-Ω transmission lines. The LVCMOS output
is delayed by 1.6 ns over the PECL output stage to
minimize noise impact during signal transitions.
1
•
•
•
•
•
•
•
Distributes One Differential Clock Input to One
LVPECL Differential Clock Output and One
LVCMOS Single-Ended Output
Programmable Output Divider for Both LVPECL
and LVCMOS Outputs
1.6-ns Output Skew Between LVCMOS and
LVPECL Transitions Minimizing Noise
3.3-V Power Supply (2.5-V Functional)
Signaling Rate Up to 800-MHz LVPECL and
200-MHz LVCMOS
Differential Input Stage for Wide Common-Mode
Range Also Provides VBB Bias Voltage Output for
Single-Ended Input Signals
Receiver Input Threshold ±75 mV
16-Pin VQFN Package (3.00 mm × 3.00 mm)
The CDCM1802 has two control pins, S0 and S1, to
select different output mode settings. The S[1:0] pins
are 3-level inputs. Additionally, an enable pin EN is
provided to disable or enable all outputs
simultaneously. The CDCM1802 is characterized for
operation from −40°C to 85°C.
For single-ended driver applications, the CDCM1802
provides a VBB output pin that can be directly
connected to the unused input as a common-mode
voltage reference.
Device Information(1)
2 Applications
•
•
•
•
PART NUMBER
Networking and Data Communications
Medical Imaging
Portable Test and Measurement
High-end A/V
CDCM1802
PACKAGE
VQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Example
CDCM1802
250 MHz
125 MHz
IN, IN
Y0,Y0
RS0 = open
S0
Setting for Mode 4:
EN = VDD/2
S1 = 0
S0 = 1
RS1 = 0
S1
125 MHz
Y1
REN = 60lQ
EN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCM1802
SCAS759C – APRIL 2004 – REVISED JULY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
4
4
4
4
5
6
6
6
7
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Jitter Characteristics..................................................
Supply Current Electrical Characteristics .................
Control Input Characteristics.....................................
Timing Requirements .............................................
Bias Voltage VBB....................................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
11
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 17
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 20
11.3 Thermal Considerations ........................................ 21
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2015) to Revision C
Page
•
Changed pin names for pins 3 and 11 from: IN and Y0 to: IN and Y0. ................................................................................. 3
•
Removed duplicate thermal information line from Layout Guidelines. ................................................................................. 19
Changes from Revision A (July 2008) to Revision B
•
2
Page
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
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SCAS759C – APRIL 2004 – REVISED JULY 2017
5 Pin Configuration and Functions
13 S0
S1
15
14 VSS
EN
16
RGT Package
16-Pin VQFN
Top View
IN
3
10
Y0
VBB
4
9
VDD0
8
Y0
VDD1
11
7
2
Y1
IN
6
VDD0
VSS
12
5
1
VSS
VDD PECL
Pin Functions
PIN
NAME
NO.
I/O
I
(with 60-kΩ
pullup)
DESCRIPTION
ENABLE. Enables or disables all outputs simultaneously; The EN pin offers three different
configurations: tie to GND (logic 0), external 60-kΩ pulldown resistor (pull to VDD/2) or left
floating (logic 1); EN = 1: outputs on according to S0 and S1 setting EN = VDD/2: outputs on
according to S0 and S1 setting EN = 0; outputs Y[1:0] off (high-impedance); see Table 1 for
details.
EN
16
IN
2
IN
3
S0
13
I
S1
15
I
(with 60-kΩ
pullup)
Y1
7
O
LVCMOS clock output. This output provides a copy of IN or a divided down copy of clock IN
based on the selected mode of operation: S0, S1, and EN. Also, this output can be disabled
by tying VDD1 to GND.
Y0
10
Y0
11
O
LVPECL
LVPECL clock output. This output provides a copy of IN or a divided down copy of clock IN
based on the selected mode of operation: S1, S0, and EN. If Y0 output is unused, the output
can simply be left open to save power and minimize noise impact to Y1.
VBB
4
O
VDDPECL (1)
1
Supply
Supply voltage PECL input + internal logic
9, 12
Supply
PECL output supply voltage for output Y0;
Y0 can be disabled by pulling VDD0 to GND.
Caution: In this mode no voltage from outside may be forced because internal diodes could
be forced in a forward direction. Thus, it is recommended to leave the output disconnected.
8
Supply
Supply voltage CMOS output; The CMOS output can be disabled by pulling VDD1 to GND.
Caution: In this mode no voltage from outside may be forced, because internal diodes could
be forced in forward direction. Thus, it is recommended to leave Y1 unconnected, tied to
GND, or terminated into GND.
5, 6, 14
Supply
Device ground
VDD0
VDD1
VSS
(1)
(1)
Differential input clock. Input stage is sensitive and has a wide common mode range.
Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS, CML,
HSTL). Since the input is high-impedance, it is recommended to terminate the PCB
transmission line before the input (for example, with 100-Ω across input). The input can also
I
be driven by a single-ended signal, if the complementary input is tied to a dc reference
Differential input voltage (for example, V /2).
CC
The inputs deploy an ESD structure protecting the inputs in case of an input voltage
exceeding the rails by more than ≈0.7 V. Reverse biasing of the IC through this inputs is
possible and must be prevented by limiting the input voltage < VDD.
Select mode of operation. Defines the output configuration of Y0 and Y1. Each pin offers
three different configurations: tied to GND (logic 0), external 60-kΩ pulldown resistor (pull to
VDD/2) or left floating (logic 1); see Table 1 for details.
Output bias voltage used to bias unused complementary input IN for single-ended input
signals. The output voltage of VBB is VDD −1.3 V. When driving a load, the output current
drive is limited to about 1.5 mA.
VDD0, VDD1, and VDDPECL should have the same value.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VDD
Supply voltage
–0.3
3.8
V
VI
Input voltage
–0.2
(VDD + 0.2)
V
VO
Output voltage
–0.2
(VDD + 0.2)
V
Yn, Yn, IOSD
Differential short circuit current
TJ
Maximum junction temperature
125
125
°C
Tstg
Storage temperature
−65
150
°C
(1)
Continuous
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Supply voltage
VDD
Supply voltage (only functionality)
TA
Operating free-air temperature
MIN
NOM
MAX
3
3.3
3.6
UNIT
V
2.375
3.6
V
–40
85
°C
6.4 Thermal Information
CDCM1802
THERMAL METRIC
(1)
RGT (VQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
48.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.9
°C/W
RθJB
Junction-to-board thermal resistance
22.5
°C/W
ψJT
Junction-to-top characterization parameter
1.7
°C/W
ψJB
Junction-to-board characterization parameter
22.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
LVPECL INPUT IN, IN
fclk
Input frequency
0
800
VCM
High-level input common mode
1
VDD − 0.3
VIN
Input voltage swing between IN and IN
IIN
Input current
RIN
Input impedance
CI
Input capacitance at IN, IN
See
(1)
500
1300
See
(2)
150
1300
VI = VDD or 0 V
±10
300
V
mV
µA
kΩ
1
pF
LVPECL OUTPUT DRIVER Y0, Y0
fclk
Output frequency (see Figure 3)
VOH
High-level output voltage
VOL
Low-level output voltage
VO
Output voltage swing between Y and Y
(see Figure 3)
IOZL
Output 3-state
IOZH
CO
Output capacitance
LOAD
Expected output load
0
800
Termination with 50 Ω to VDD − 2 V
VDD − 1.18
VDD – 0.81
V
Termination with 50 Ω to VDD − 2 V
VDD − 1.98
VDD – 1.55
V
Termination with 50 Ω to VDD − 2 V
500
mV
VDD = 3.6 V, VO = 0 V
VDD = 3.6 V, VO = VDD – 0.8 V
VO = VDD or GND
MHz
5
µA
10
µA
1
pF
50
Ω
LVCMOS OUTPUT PARAMETER, Y1
Output frequency (3) (see Figure 4)
fclk
0
VDD = min to max, IOH = −100 µA
VOH
High-level output voltage
VDD = 3 V, IOH = −6 mA
VDD = 3 V, IOH = −12 mA
VOL
Low-level output voltage
200
2.4
V
2
VDD = min to max, IOL = 100 µA
0.1
VDD = 3 V, IOL = 6 mA
0.5
VDD = 3 V, IOL = 12 mA
0.8
IOH
High-level output current
VDD = 3.3 V, VO = 1.65 V
−29
IOL
Low-level output current
VDD = 3.3 V, VO = 1.65 V
37
IOZ
High-impedance state output current
VDD = 3.6 V, VO = VDD or 0 V
CO
Output capacitance
VDD = 3.3 V
Load
Expected output loading (see Figure 9)
(1)
(2)
(3)
MHz
VDD – 0.1
V
mA
mA
±5
µA
2
pF
10
pF
Required to maintain AC specifications
Required to maintain device functionality
Operating the CDCM1802 LVCMOS output above the maximum frequency will not cause a malfunction to the device, but the Y1 output
signal swing will not achieve enough signal swing to meet the output specification. Therefore, the CDCM1802 can be operated at higher
frequencies, while the LVCMOS output Y1 becomes unusable.
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVPECL OUTPUT DRIVER Y0, Y0
tDuty
Output duty cycle distortion (1)
Crossing point-to-crossing point
distortion
tsk(pp)
Part-to-part skew
Any Y0 (see Note A in Figure 7)
tr/tf
Rise and fall time
20% to 80% of VOUTPP
(see Figure 8)
−50
50
ps
50
ps
200
350
ps
LVPECL INPUT-TO-LVPECL OUTPUT PARAMETER
tpd(lh)
Propagation delay rising edge
VOX to VOX
320
600
ps
tpd(hl)
Propagation delay falling edge
VOX to VOX
320
600
ps
tsk(p)
LVPECL pulse skew
(see Note B in Figure 7)
VOX to VOX
100
ps
LVCMOS OUTPUT PARAMETER, Y1
tskLVCMOS(o)
Output skew between the LVCMOS
output Y1 and LVPECL output Y0
VOX to VDD / 2 (see Figure 7)
tDuty
Output duty cycle distortion (2)
Measured at VDD / 2
tsk(pp)
Part-to-part skew
Y1 (see Note A in Figure 7)
tpd(lh)
Propagation delay rising edge from
IN to Y1
VOX to VDD / 2 load (see Figure 9)
1.6
2.6
ns
tpd(hl)
Propagation delay falling edge from
IN to Y1
VOX to VDD / 2 load (see Figure 9)
1.6
2.6
ns
tr
Output rise slew rate
20% to 80% of swing
(see Figure 9)
1.4
2.3
V/ns
tf
Output fall slew rate
80% to 20% of swing
(see Figure 9)
1.4
2.3
V/ns
(1)
(2)
1.6
ns
−150
150
ps
300
ps
For a 800-MHz signal, the 50-ps error would result into a duty cycle distortion of ±4% when driven by an ideal clock input signal.
For a 200-MHz signal, the 150-ps error would result in a duty cycle distortion of ±3% when driven by an ideal clock input signal.
6.7 Jitter Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tjitterLVPECL
tjitterLVCMOS
TEST CONDITIONS
Additive phase jitter from input to
LVPECL output Y0
(see Figure 1)
Additive phase jitter from input to
LVCMOS output Y1
(see Figure 2)
MAX
UNIT
12 kHz to 20 MHz, fout = 250 MHz to 800 MHz,
divide by 1 mode
MIN
TYP
0.15
ps rms
50 kHz to 40 MHz, fout = 250 MHz to 800 MHz,
divide by 1 mode
0.25
ps rms
12 kHz to 20 MHz, fout = 250 MHz, divide by 1
mode
0.25
ps rms
50 kHz to 40 MHz, fout = 250 MHz, divide by 1
mode
0.4
ps rms
6.8 Supply Current Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
IDD
IDDZ
6
TEST CONDITIONS
MIN
TYP MAX
UNIT
Full load
All outputs enabled and terminated with 50 Ω to VDD − 2 V on
LVPECL outputs and 10 pF on LVCMOS output,
f = 800 MHz for LVPECL outputs and 200 MHz for LVCMOS,
VDD = 3.3 V
No load
Outputs enabled, no output load, f = 800 MHz for LVPECL outputs
and 200 MHz for LVCMOS, VDD = 3.6 V
85
mA
All outputs 3-state by control logic, f = 0 Hz, VDD = 3.6 V
0.5
mA
Supply current
Supply current, 3-state
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100
mA
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6.9 Control Input Characteristics
over operating free-air temperature range (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
42
60
78
Rpullup
Internal pullup resistor on S0, S1, and EN input
VIH(H)
Three level input high, S0, S1, and EN pin (1)
0.9 × VDD
VIM(M)
Three level input MID, S0, S1, and EN pin
0.3 × VDD
VIL(L)
Three level low, S0, S1, and EN pin
IIH
Input current, S0, S1, and EN pin
VI = VDD
IIL
Input current, S0, S1, and EN pin
VI = GND
(1)
UNIT
kΩ
V
0.7 × VDD
V
0.1 × VDD
V
–5
µA
85
µA
38
Leaving this pin floating automatically pulse the logic level high to VDD through an internal pullup resistor of 60 kΩ.
6.10 Timing Requirements
MIN
tsu
Setup time, S0, S1, and EN pin before clock IN
th
Hold time, S0, S1, and EN pin after clock IN
t(disable)
Time between latching the EN low transition and when all outputs are
disabled (how much time is required until the outputs turn off)
t(enable)
Time between latching the EN low-to-high transition and when outputs are
enabled based on control settings (how much time passes before the
outputs carry valid signals)
NOM
MAX
UNIT
25
ns
0
ns
10
ns
1
μs
6.11 Bias Voltage VBB
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VBB
Output reference voltage
TEST CONDITIONS
MIN
VDD = 3 V–3.6 V, IBB = –0.2 mA
VDD – 1.4
TYP
MAX
UNIT
VDD – 1.2
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6.12 Typical Characteristics
−110
−100
VDD = 3.3 V
TA = 25°C
f = 622 MHz
÷1 Mode
−120
VDD = 3.3 V
TA = 25°C
f = 250 MHz
÷1 Mode
−105
−110
Additive Phase Noise − dBc/Hz
Additive Phase Noise − dBc/Hz
−115
−125
−130
−135
−140
−145
−150
−115
−120
−125
−130
−135
−140
−145
−150
−155
−155
−160
10
100
1k
10k
100k
1M
10M
−160
10
100M
f − Frequency Offset From Carrier − Hz
100
1k
10k
100k
1M
10M
100M
f − Frequency Offset From Carrier − Hz
G001
G002
Figure 1. Additive Phase Noise vs
Frequency Offset From Carrier − LVPECL
Figure 2. Additive Phase Noise vs
Frequency Offset From Carrier − LVCMOS
0.90
3.5
0.85
VDD = 3.6 V
VDD3 = 3.6 V
3.0
LVCMOS Output Swing − V
LVPECL Output Swing − V
0.80
0.75
0.70
VDD = 3 V
0.65
0.60
0.55
VDD = 3.3 V
2.5
VDD3 = 3 V
2.0
VDD = 3.3 V
1.5
1.0
0.50
TA = 25°C
Load = See Figure 10
0.5
0.45
0.40
0.1
TA = 25°C
Load = 50 W to VDD − 2 V
0.3
0.5
0.7
0.0
0.9
1.1
1.3
1.5
25
75
125 175 225 275 325 375 425 475
f − Frequency − GHz
f − Frequency − MHz
G003
G004
Figure 3. Amplitude PECL Peak-to-Peak vs Frequency
Figure 4. Amplitude CMOS Peak-to-Peak vs Frequency
4.0
110
VDD = 3.3 V
3.5
VBB − Output Reference Voltage − V
ICC - Supply Current - mA
100
CMOS Running, PECL Off (Mode 10)
CMOS and PECL Running, No Load
CMOS Off, PECL Running
CMOS and PECL Running (Mode 3)
90
80
70
60
50
0.1
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.3
0.5
0.7
0.9
1.1
1.3
−5
1.5
5
10
15
20
25
30
35
G006
Figure 5. Supply current vs Frequency
8
0
I − Load − mA
f - Frequency - GHz
Figure 6. Output Reference Voltage (VBB) vs Load
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7 Parameter Measurement Information
IN
IN
Y0
Y0
tPHLO
0.5 x VDD1
Y1
tskLVCMOS(o)
A.
Part-to-part skew, tsk(pp), is calculated as the greater of:
M− The difference between the fastest and the slowest tpd(LH)n across multiple devices
M− The difference between the fastest and the slowest tpd(HL)n across multiple devices
B.
Pulse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL) and
the low-to-high (tpd(LH)) propagation delays when a single switching input causes Y0 to switch,
tsk(p) = | tpd(HL) − tpd(LH) |. Pulse skew is sometimes referred to as pulse width distortion or duty cycle skew.
Figure 7. Waveforms for Calculation of tsk(o) and tsk(pp)
Y0
VOH
Y0
VOL
80%
0V
VOUT(pp)
20%
|Y0 t Y0|
tr
tf
Figure 8. LVPECL Differential Output Voltage and Rise and Fall Time
VDD
CDCM1802
1 lQ
Y1
LVCMOS
1 lQ
10 pF
Figure 9. LVCMOS Output Loading During Device Test
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Parameter Measurement Information (continued)
(VDD t 2 V)
CDCM1802
50 Q
Y0, Y0
LVPECL
Figure 10. LVPECL Output Loading During Device Test
10
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8 Detailed Description
8.1 Overview
The CDCM1802 is a clock buffer with a programmable divider. There is one LVCMOS and one LVPECL output.
The LVCMOS output is specifically designed for driving 50-Ω transmission lines. It is delayed by 1.6 ns over the
PECL output stage to minimize noise impact during signal transitions. Both outputs can be divided individually by
1, 2, 4, and 8. Divider settings can be selected with three 3-level control pins.
8.2 Functional Block Diagram
LVCMOS
Div 1
Div 2
Div 4
Div 8
IN
IN
Y1
Y0
LVPECL
Y0
VBB
Bias Generator
VDD t 1.3 V
(imax < 1.5 mA)
Control
S0
EN
S1
8.3 Feature Description
The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. For singleended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the
unused input as a common-mode voltage reference.
8.4 Device Functional Modes
8.4.1 Control Pin Settings
The CDCM1802 has three control pins, S0, S1, and the enable pin (EN) to select different output mode settings.
All three inputs (S0, S1, EN) are 3-level inputs. In addition, the EN input allows disabling all outputs and place
them into a Hi-Z (or tristate) output state when pulled to GND.
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Device Functional Modes (continued)
Setting for Mode 4:
EN = VDD/2
S1 = 0
S0 = 1
CDCM1802
RS0 = open
S0
RS1 = 0
S1
REN = 60lQ
EN
Figure 11. Control Pin Setting for Example
Each control input incorporates a 60-kΩ pullup resistor. Thus, it is easy to choose the input setting by designing
a resistor pad between the control input and GND. To choose a logic zero, the resistor value must be zero.
Setting the input high requires leaving the resistor pad empty (no resistor installed). For setting the input to
VDD/2, the installed resistor needs a value of 60 kΩ with a tolerance better or equal to 10%.
Table 1. Selection Mode Table
(1)
MODE
EN
S1
S0
0
0
X
1
VDD/2
2
VDD/2
3
1
4
5
LVPECL (1)
LVCMOS
Y0
Y1
X
Off (high-z)
Off (high-z)
0
VDD/2
/1
/1
VDD/2
1
/1
/2
0
0
/1
/4
VDD/2
0
1
/2
/2
1
0
1
/2
/4
6
VDD/2
0
0
/4
/4
7
VDD/2
1
0
/4
/8
8
VDD/2
VDD/2
VDD/2
/8
/1
9
1
1
0
/8
/4
10
1
1
1
Off (high-z)
/4
The LVPECL outputs are open emitter stages. Thus, if you leave the unused LVPECL output Y0
unconnected, then the current consumption is minimized and noise impact to remaining outputs is
neglectable. Also, each output can be individually disabled by connecting the corresponding VDD input
to GND.
8.4.2 Device Behavior During RESET and Control Pin Switching
8.4.2.1 Output Behavior When Enabling the Device (EN = 0 → 1)
In disable mode (EN = 0), all output drivers are switched in high-Z mode. The bandgap, current references, the
amplifier, and the S0 and S1 control inputs are also switched off. In the same mode, all flip-flops will be reset.
The typical current consumption is likely below 500 µA (to be measured).
When the device will be enabled again it takes maximal 1 µs for the settling of the reference voltage and
currents. During this time the output Y0 and Y0 drive a high signal. Y1 is unknown (could be high or low). After
the settle time, the outputs go into the low state. Due to the synchronization of each output driver signal with the
input clock, the state of the waveforms after enabling the device look like those shown in Figure 12. The inverting
input and output signal is not included. The Y:/1 waveform is the undivided output driver state.
12
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1 us
EN
IN
Y:/1 High-Z
Undefined
Y:/2 High-Z
Undefined
Y:/4 High-Z
Undefined
Low
Low
Low
Signal State After the Device is Enabled (IN = Low)
1 us
EN
Undivided State is Valid After the First
Positive Transition of the Input Clock
IN
Y:/1 High-Z
Undefined
Y:/2 High-Z
Undefined
Y:/4 High-Z
Undefined
Low
Low
Low
Signal State After the Device is Enabled (IN = High)
Figure 12. Waveforms
8.4.2.2 Enabling a Single Output Stage
If a single output stage becomes enabled:
• Y0 will either be low or high (undefined).
• Y0 will be the inverted signal of Y0.
With the first positive clock transition, the undivided output becomes the input clock state. If a divide mode is
used, the divided output states are equal to the actual internal divider. The internal divider does not get a reset
while enabling single output drivers.
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ENABLE Yx:
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Disabled
Enabled
Undivided State is Valid After the First
Positive Transition of the Input Clock
IN
Y:/1
High-Z
Undefined
Y:/x
High-Z
Undefined
Divider State
Figure 13. Signal State After an Output Driver Becomes Enabled While IN = 0
ENABLE Yx:
Disabled
Enabled
Undivided State is Valid After the First
Positive Transition of the Input Clock
IN
Y:/1
High-Z
Undefined
Y:/x
High-Z
Undefined
Divider State
Figure 14. Signal State After an Output Driver Becomes Enabled While IN = 1
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 LVPECL Receiver Input Termination
The input of the CDCM1802 has high impedance and comes with a very large common mode voltage range. For
optimized noise performance it is recommended to properly terminate the PCB trace (transmission line).
Additional termination techniques can be found in the following application notes: SCAA062 and SCAA059.
CDCM1802
IN
50 Q
CAC
150 Q
50 Q
LVPECL
50 Q
IN
50 Q
150 Q
CAC
VBB
C
Figure 15. Recommended AC-Coupling LVPECL Receiver Input Termination
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Application Information (continued)
CDCM1802
130 Q
IN
50 Q
83 Q
LVPECL
130 Q
IN
50 Q
83 Q
Figure 16. Recommended DC-Coupling LVPECL Receiver Input Termination
9.1.2 LVCMOS Receiver Input Termination
CDCM1802
LVCMOS
IN
50 Q
CAC
Rdc
IN
VBB
CCT
NOTE: CAC − AC-coupling capacitor (for example, 10 nF)
CCT − Capacitor keeps voltage at IN constant (for example, 10 nF)
Rdc − Load and correct duty cycle (for example, 50 Ω)
VBB − Bias voltage output
Figure 17. Typical Application Setting for Single-Ended Input Signals Driving the CDCM1802
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9.2 Typical Application
Figure 18 shows a fanout buffer application.
3.3 V
PHY
IN
100 MHz LVPECL
Hi-Z
Y1
from backplane
IN
50
VBB
Setting for Mode 3:
EN = 1
RS0 = 0
S1 = 0
S0 = 0
RS1 = 0
ASIC
CDCLVP1802
3.3 V
S0
130
S1
Y0
REN = open
EN
83
Figure 18. Typical Application Schematic, CDCM1802
9.2.1 Design Requirements
The CDCM1802 shown in Figure 18 is configured to be able to select an 100-MHz LVPECL clock from the
backplane. The signal can be fanned out to desired devices, as shown. The CDCM1802 offers internal dividers
for both the LVCMOS and LVPECL output. In the example the LVCMOS output is divided by 4 and the LVPECL
output is divided by 1.
•
•
•
The PHY device receive a single ended 25-MHz signal. Optionally a series resistance can be placed close to
the output to match transmission line impedance and reduce reflections.
The ASIC is capable of DC coupling with a 3.3-V LVPECL driver such as the CDCM1802. This ASIC features
internal termination so no additional components are needed.
S0, S1, EN needs to be set accordingly to ensure the required divider setting.
9.2.2 Detailed Design Procedure
Refer to LVPECL Receiver Input Termination for proper input terminations, dependent on single-ended or
differential inputs.
Refer to Figure 9 and Figure 10 for output termination schemes depending on the receiver application.
Refer to Table 1 for setting the desired divider modes.
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Typical Application (continued)
9.2.3 Application Curve
Input (Vectron C5310A1) = 83 fs, rms
Output (LVPECL, divide 1) = 134 fs, rms
additive jitter = 105 fs, rms (typ)
Figure 19. Additive Jitter Performance
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10 Power Supply Recommendations
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter or phase noise is very critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system
against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required
by the device and must have low equivalent series resistance (ESR). To properly use the bypass capacitors, they
must be placed very close to the power-supply terminals and laid out with short loops to minimize inductance. It
is recommended to add as many high-frequency (for example, 0.1-μF) bypass capacitors as there are supply
terminals in the package. It is recommended, but not required, to insert a ferrite bead between the board power
supply and the chip power supply that isolates the high-frequency switching noises generated by the clock driver;
these beads prevent the switching noise from leaking into the board supply. It is imperative to choose an
appropriate ferrite bead with very low DC resistance to provide adequate isolation between the board supply and
the chip supply, as well as to maintain a voltage at the supply terminals that is greater than the minimum voltage
required for proper operation.
Figure 20 illustrates this recommended power-supply decoupling method.
Board
Supply
VCC
Chip
Supply
Ferrite Bead
C
10 mF
C
1 mF
C
0.1 mF (x3)
Figure 20. Power-Supply Decoupling
11 Layout
11.1 Layout Guidelines
TI recommends taking special care of the PCB design for good thermal flow from the VQFN 16-pin package to
the PCB. The current consumption of the CDCM1802 is fixed. JEDEC JESD51−7 specifies thermal conductivity
for standard PCB boards.
To ensure sufficient thermal flow, it is recommended to design with four thermal vias in applications.
See the SCBA017 and the SLUA271 application notes for further package-related information.
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11.2 Layout Example
Package Thermal Pad
(Underside)
Thermal Via
Dia 0.020 In.
Top Side
Island
Heat
Dissipation
VSS Copper Plane
VSS Copper Plane
Figure 21. Recommended Thermal Via Placement
20
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11.3 Thermal Considerations
Table 2. Package Thermal Resistance
PARAMETER
RθJA
(1)
VQFN−16 package thermal resistance
with thermal vias in PCB (1)
TEST CONDITIONS
MIN
4-layer JEDEC test board (JESD51−7) with four thermal
vias of 22-mil diameter each, airflow = 0 ft/min
TYP MAX
UNIT
48.4
°C/W
It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good
heat sink.
Example:
Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:
TChassis = 85°C (temperature of the chassis)
Peffective = Imax × Vmax = 85 mA × 3.6 V = 306 mW (max power consumption inside the package)
ΔTJunction = RθJA × Peffective = 40.8°C/W × 306 mW = 12.48°C
TJunction = ΔTJunction + TChassis = 12.48°C + 85°C = 97.48°C (the maximum junction temperature of
Tdie−max = 125°C is not violated)
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
SCAA062: DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
SCAA059: AC-Coupling Between Differential LVPECL, LVDC, HSTL, and CML
SCBA017: Quad Flatpack No-Lead Logic Packages
SLUA271: QFN/SON PCB Attachment
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CDCM1802RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AJW
Samples
CDCM1802RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AJW
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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