CDCS503PW

CDCS503 www.ti.com .................................................................................................................................................................................................. SCAS872 – MARCH 2009 Clock Buffer/Clock Multiplier With Optional SSC FEATURES APPLICATIONS • • 1 • • • • • • • Part of a Family of Easy to use Clock Generator Devices With Optional SSC Clock Multiplier With Selectable Output Frequency and Selectable SSC SSC Controllable via 2 External Pins – ±0%, ±0.5%, ±1%, ±2% Center Spread Frequency Multiplication Selectable Between x1 or x4 With One External Control Pin Output Disable via Control Pin Single 3.3V Device Power Supply Wide Temperature Range –40°C to 85°C Low Space Consumption by 8 Pin TSSOP Package Consumer and Industrial Applications requiring EMI reduction through Spread Spectrum Clocking and/ or Clock Multiplication PACKAGE IN SSC_SEL 0 SSC_SEL 1 GND 1 2 3 4 CDCS503 8 7 6 5 VDD OE OUT FS BLOCK DIAGRAM VDD IN LVCMOS SSC_SEL 0 SSC_SEL 1 FS GND x1 or x4 / SSC LV CMOS OUT Control Logic OE DESCRIPTION The CDCS503 is a spread spectrum capable, LVCMOS Input Clock Buffer with selectable frequency multiplication. It shares major functionality with the CDCS502 but utilizes a LVCMOS input stage instead of the crystal input stage of the CDCS502. Also an Output Enable pin has been added to the CDCS503. The device accepts a 3.3V LVCMOS signal at the input. The input signal is processed by a PLL, whose output frequency is either equal to the input frequency or multiplied by the factor of 4. The PLL is also able to spread the clock signal by ±0%, ±0.5%, ±1% or ±2% centered around the output clock frequency with a triangular modulation. By this, the device can generate output frequencies between 8MHz and 108MHz with or without SSC. A separate control pin can be used to enable or disable the output. The CDCS503 operates in 3.3V environment. It is characterized for operation from –40°C to 85°C, and available in an 8-pin TSSOP package. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated CDCS503 SCAS872 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com FUNCTION TABLE OE FS SSC_SEL 0 SSC_SEL 1 SSC AMOUNT fOUT/fIN fOUT at fin = 27 MHz 0 x x x x x 3-state 1 0 0 0 ±0.00% 1 27 MHz 1 0 0 1 ±0.50% 1 27 MHz 1 0 1 0 ±1.00% 1 27 MHz 1 0 1 1 ±2.00% 1 27 MHz 1 1 0 0 ±0.00% 4 108 MHz 1 1 0 1 ±0.50% 4 108 MHz 1 1 1 0 ±1.00% 4 108 MHz 1 1 1 1 ±2.00% 4 108 MHz DEVICE INFORMATION PACKAGE IN SSC_SEL 0 SSC_SEL 1 GND 1 2 3 4 CDCS503 8 7 6 5 VDD OE OUT FS PIN FUNCTIONS SIGNAL PIN TYPE IN 1 I LVCMOS Clock input OUT 6 O LVCMOS Clock Output SSC_SEL 0, 1 DESCRIPTION 2, 3 I Spread Selection Pins, internal pull-up OE 7 I Output Enable, internal pull-up FS 5 I Frequency Multiplication Selection, internal pull-up VDD 8 Power 3.3V Power Supply GND 4 Ground Ground PACKAGE THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE over operating free-air temperature range (unless otherwise noted) (1) THERMAL AIRFLOW (CFM) CDCS503PW 8-PIN TSSOP RθJA RθJC (1) 2 0 150 250 500 High K 149 142 138 132 Low K 230 185 170 150 High K 65 Low K 69 UNIT °C/W °C/W The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CDCS503 CDCS503 www.ti.com .................................................................................................................................................................................................. SCAS872 – MARCH 2009 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE UNIT VDD Supply voltage range –0.5 to 4.6 V VIN Input voltage range (1) –0.5 to 4.6 V (1) Vout Output voltage range –0.5 to 4.6 V IIN Input current (VI < 0, VI > VDD) 20 mA Iout Continuous output current 50 mA TST Storage temperature range –65 to 150 °C TJ Maximum junction temperature 125 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN VDD Supply voltage fIN Input frequency VIL Low level input voltage LVCMOS VIH High level input voltage LVCMOS VI Input voltage threshold LVCMOS CL Output load test LVCMOS IOH/IOL Output current TA Operating free-air temperature NOM MAX 3.0 3.6 FS = 0 8 32 FS = 1 8 27 0.3 VDD 0.7 VDD UNIT V MHz V V 0.5 VDD -40 V 15 pF ±12 mA 85 °C DEVICE CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS fout = 70 MHz; FS = 1, SSC = 2% 22 Device supply current fOUT Output frequency IIH LVCMOS input current VI = VDD; VDD = 3.6 V IIL LVCMOS input current VI = 0 V; VDD = 3.6 V LVCMOS high-level output voltage VOL LVCMOS low-level output voltage MAX 8 32 FS = 1 32 108 IOH = - 0.1mA 2.9 IOH = - 8mA 2.4 IOH = - 12mA 2.2 µA –10 µA V 0.1 IOL = 8mA 0.5 IOL = 12mA 0.8 High- impedance-state output current OE = Low Cycle to cycle jitter (1) fout = 108 MHz; FS = 1, SSC = 1%, 10000 Cycles tr/tf Rise and fall time (1) 20%–80% Odc Output duty cycle fMOD Modulation frequency MHz 10 IOL = 0.1mA tJIT(C-C) UNIT mA FS = 0 IOZ (1) TYP 19 IDD VOH MIN fout = 20 MHz; FS = 0, no SSC –2 2 110 µA ps 0.75 45% V ns 55% 30 kHz Measured with Test Load, see Figure 2. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CDCS503 3 CDCS503 SCAS872 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com 40 35 IDD - Input Current - mA 30 x4 Mode 25 20 x1 Mode 15 10 5 0 0 5 10 15 20 25 fi - Input Frequency - MHz 30 35 Figure 1. IDD vs Input Frequency, VCC = 3.3V, SSC = 2%, Output Loaded With Test Load 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CDCS503 CDCS503 www.ti.com .................................................................................................................................................................................................. SCAS872 – MARCH 2009 APPLICATION INFORMATION SSC MODULATION The exact implementation of the SSC modulation plays a vital role for the EMI reduction. The CDCS503 uses a triangular modulation scheme implemented in a way that the modulation frequency depends on the VCO frequency of the internal PLL and the spread amount is independent from the VCO frequency. The modulation frequency can be calculated by using one of the below formulas chosen by frequency multiplication mode. FS = 0: fmod = fIN / 708 FS = 1: fmod = fIN / 620 PARAMETER MEASUREMENT INFORMATION VDD CDCS503 1 kW LVCMOS 1 kW 10 pF Figure 2. Test Load CDCS503 LVCMOS LVCMOS Typical Driver Series Termination ~ 18 W Impedance ~ 32 W ZL = 50 W Figure 3. Load for 50-Ω Board Environment Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CDCS503 5 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device CDCS503PWR Package Package Pins Type Drawing TSSOP PW 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 7.0 B0 (mm) K0 (mm) P1 (mm) 3.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCS503PWR TSSOP PW 8 2000 356.0 356.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TUBE T - Tube height L - Tube length W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) CDCS503PW PW TSSOP 8 150 530 10.2 3600 3.5 Pack Materials-Page 3 PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP 6.2 SEATING PLANE PIN 1 ID AREA A 0.1 C 6X 0.65 8 1 3.1 2.9 NOTE 3 2X 1.95 4 5 B 4.5 4.3 NOTE 4 SEE DETAIL A 8X 0.30 0.19 0.1 C A 1.2 MAX B (0.15) TYP 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM 1 8 (R0.05) TYP SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) TYP 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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