CDCV304PWG4

Order Now Product Folder Technical Documents Support & Community Tools & Software CDCV304 SCAS643I – SEPTEMBER 2000 – REVISED OCTOBER 2017 CDCV304 200-MHz General-Purpose Clock Buffer, PCI-X Compliant 1 Features 2 Description • • The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-X specifications. 1 • • • • • • General-Purpose and PCI-X 1:4 Clock Buffer Operating Frequency – 0 MHz to 200 MHz General-Purpose Low Output Skew: VDD) –50 50 mA Output clamp current, IOK (VO < 0 or VO > VDD) –50 50 mA Continuous total output current, IO (VO = 0 to VDD) –50 50 mA 230.5 °C/W 125 °C 150 °C Package thermal impedance, θJA: PW package Junction temperature, Tj, max Storage temperature range Tstg (1) (2) (3) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 4.6 V maximum. Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated Product Folder Links: CDCV304 3 CDCV304 SCAS643I – SEPTEMBER 2000 – REVISED OCTOBER 2017 www.ti.com 5.2 Recommended Operating Conditions MIN Supply voltage, VDD NOM MAX 2.3 Low-level input voltage, VIL High-level input voltage, VIH V 0.3 x VDD V 0.7 x VDD Input voltage, VI V 0 High-level output current, IOH Low-level output current, IOL VDD VDD = 2.5 V –12 VDD = 3.3 V –24 VDD = 2.5 V 12 VDD = 3.3 V 24 Operating free-air temperature, TA UNIT 3.6 –40 85 V mA mA °C 5.3 Thermal Information CDCV304 THERMAL AIR FLOW (CFM) THERMAL METRIC (1) PW (TSSOP) UNIT 8 PINS High K RθJA Junction-to-ambient thermal resistance 0 149 150 142 250 138 500 132 230 185 Low K °C/W 170 150 RθJC(top) Junction-to-case (top) thermal resistance 43.7 RθJB Junction-to-board thermal resistance 102 ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (1) 1.8 100.2 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 5.4 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL Input voltage High-level output voltage Low-level output voltage IOH High-level output current IOL Low-level output current (1) 4 TEST CONDITIONS MIN TYP (1) MAX UNIT –1.2 V VDD = 3 V, II = –18 mA VDD = 2.3 V, IOH = –8 mA 1.8 VDD = 2.3 V, IOH = –16 mA 1.5 VDD = min to max, IOH = –1 mA VDD = 3 V, IOH = –24 mA 2 VDD = 3 V, IOH = –12 mA 2.4 VDD = 2.3 V, IOL = 8 mA 0.5 VDD = 2.3 V, IOL = 16 mA 0.7 VDD = min to max, IOL = 1 mA 0.2 VDD = 3 V, IOL = 24 mA 0.8 VDD = 3 V, IOL = 12 mA VDD = 3 V, VO = 1 V VDD = 3.3 V, VO = 1.65 V VDD = 3 V, VO = 2 V VDD = 3.3 V, VO = 1.65 V VDD – 0.2 V V 0.55 –50 –55 60 70 mA mA All typical values are with respect to nominal VDD and TA = 25°C. Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated Product Folder Links: CDCV304 CDCV304 www.ti.com SCAS643I – SEPTEMBER 2000 – REVISED OCTOBER 2017 Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER II Input current TEST CONDITIONS MIN TYP (1) MAX VI = VO or VDD UNIT ±5 f = 67 MHz, VDD = 2.7 V 28 f = 67 MHz, VDD = 3.6 V 37 μA IDD Dynamic current, see Figure 1 mA CI Input capacitance VDD = 3.3 V, VI = 0 V or VDD 3 pF CO Output capacitance VDD = 3.3 V, VI = 0 V or VDD 3.2 pF 5.5 Timing Requirements over operating free-air temperature range (unless otherwise noted) PARAMETER fclk TEST CONDITIONS MIN Clock frequency TYP 0 MAX UNIT 200 MHz 5.6 Switching Characteristics: VDD = 2.5 V ± 10% VDD = 2.5 V ± 10%, CL= 10 pF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 2 2.9 4.5 2 3 4.5 UNIT tPLH Low-to-high propagation delay tPHL High-to-low propagation delay tsk(o) Output skew (2) 50 150 tr Output rise slew rate 1.5 2.2 4 V/ns tf Output fall slew rate 1.5 2.2 4 V/ns MIN TYP (1) MAX UNIT 1.8 2.4 3 1.8 2.5 3 50 100 (1) (2) See Figure 4 and Figure 5 See Figure 6 ns ps All typical values are with respect to nominal VDD. The tsk(o) specification is only valid for equal loading of all outputs. 5.7 Switching Characteristics: VDD = 3.3 V ± 10% VDD = 3.3 V ± 10%, CL= 10 pF (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH Low-to-high propagation delay tPHL High-to-low propagation delay tsk(o) Output skew (2) tjitter Additive phase jitter from input to output 1Y0 tsk(p) Pulse skew tsk(pr) Process skew tsk(pp) Part-to-part skew Clock high time, see Figure 7 tlow Clock low time, see Figure 7 tr Output rise slew rate (3) (1) (2) (3) Output fall slew rate 12 kHz to 5 MHz, fout = 30.72 MHz 63 12 kHz to 20 MHz, fout = 125 MHz 56 VIH = VDD, VIL = 0 V thigh tf See Figure 4 and Figure 5 (3) 66 MHz 6 140 MHz 3 66 MHz 6 140 MHz 3 ns ps fs rms 150 ps 0.2 0.3 ns 0.25 0.4 ns ns ns VO = 0.4 V to 2 V 1.5 2.7 4 V/ns VO = 2 V to 0.4 V 1.5 2.7 4 V/ns All typical values are with respect to nominal VDD. The tsk(o) specification is only valid for equal loading of all outputs. This symbol is according to PCI-X terminology. Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated Product Folder Links: CDCV304 5 CDCV304 SCAS643I – SEPTEMBER 2000 – REVISED OCTOBER 2017 www.ti.com 5.8 Typical Characteristics 60 3.5 VOH − High-Level Output Voltage − V ICC − Supply Current − mA TA = 85°C Output Load: as in Figure 1 50 VDD = 3.6V 40 VDD = 2.7V 30 20 0 20 40 60 80 100 120 140 160 VDD = 3.3 V TA = 25°C 3.0 2.5 2.0 1.5 1.0 0.5 0.0 −100 −90 −80 f − Frequency − MHz −70 −60 −50 −40 −30 −20 −10 0 IOH − High-Level Output Current − mA Figure 1. Supply Current vs Frequency Figure 2. High-Level Output Voltage vs High-Level Output Current VOL − Low-Level Output Voltage − V 3.5 3.0 VDD = 3.3 V TA = 25°C 2.5 2.0 1.5 1.0 0.5 0.0 −20 0 20 40 60 80 100 120 IOL − Low-Level Output Current − mA Figure 3. Low-Level Output Voltage vs Low-Level Output Current 6 Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated Product Folder Links: CDCV304 CDCV304 www.ti.com SCAS643I – SEPTEMBER 2000 – REVISED OCTOBER 2017 6 Parameter Measurement Information VDD 140 Ω Yn 10 pF 140 Ω Figure 4. Test Load Circuit VDD 50% VDD CLKIN 0V tPLH tPHL 0.6 VDD 0.6 VDD 50% VDD 50% VDD 0.2 VDD 1Y0 − 1Y3 VOH 0.2 VDD tr VOL tf Figure 5. Voltage Waveforms Propagation Delay (tpd) Measurements 50% VDD Any Y 50% VDD Any Y tsk(0) Figure 6. Output Skew tcyc PARAMETER VIH(Min) VIL(Max) Vtest VALUE 0.5 VDD thigh UNIT V 0.35 VDD V VIH(Min) 0.4 VDD V Vtest 0.6 VDD VIL(Max) tlow 0.2 VDD 0.4 VDD Peak to Peak (Minimum) A. All parameters in Figure 7 are according to PCI-X 1.0 specifications. Figure 7. Clock Waveform Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated Product Folder Links: CDCV304 7 CDCV304 SCAS643I – SEPTEMBER 2000 – REVISED OCTOBER 2017 www.ti.com 7 Detailed Description 7.1 Functional Block Diagram OE CLKIN Logic Control 2 3 1 1Y0 5 1Y1 7 1Y2 8 1Y3 7.2 Device Functional Modes Table 1. Function Table INPUTS 8 OUTPUTS CLKIN OE 1Y[0:3] L L L H L L L H L H H H Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated Product Folder Links: CDCV304 CDCV304 www.ti.com SCAS643I – SEPTEMBER 2000 – REVISED OCTOBER 2017 8 Device and Documentation Support 8.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 8.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 8.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 8.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated Product Folder Links: CDCV304 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CDCV304PW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CKV304 CDCV304PWG4 ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CKV304 CDCV304PWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CKV304 CDCV304PWRG4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CKV304 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of