CDCV304TPWREP

CDCV304-EP www.ti.com SCAS927A – MARCH 2012 200-MHz GENERAL-PURPOSE CLOCK BUFFER, PCI-X COMPLIANT Check for Samples: CDCV304-EP FEATURES 1 • • • • • • • • General-Purpose and PCI-X 1:4 Clock Buffer Operating Frequency – 0 MHz to 200 MHz General-Purpose Low Output Skew: VDD) ±50 mA Output clamp current, IOK (VO < 0 or VO > VDD) ±50 mA Continuous total output current, IO (VO = 0 to VDD) ±50 mA Storage temperature range Tstg (1) (2) (3) 2 –65°C to 150°C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 4.6 V maximum. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCV304-EP CDCV304-EP www.ti.com SCAS927A – MARCH 2012 THERMAL INFORMATION CDCV304 THERMAL METRIC (1) PW UNITS 8 PINS Junction-to-ambient thermal resistance (2) θJA 175.8 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) ψJT Junction-to-top characterization parameter (5) ψJB Junction-to-board characterization parameter (6) 61.8 104.3 °C/W 7.7 102.6 xxx (1) (2) (3) (4) (5) (6) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VDD NOM 2.3 Low-level input voltage, VIL High-level input voltage, VIH V 0.3 x VDD V V 0 Low-level output current, IOL UNIT 3.6 0.7 x VDD Input voltage, VI High-level output current, IOH MAX VDD VDD = 2.5 V –12 VDD = 3.3 V –24 VDD = 2.5 V 12 VDD = 3.3 V 24 Operating free-air temperature, TA –40 V mA mA 105 °C TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) PARAMETER fclk TEST CONDITIONS Clock frequency MIN 0 TYP MAX UNIT 200 MHz Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCV304-EP 3 CDCV304-EP SCAS927A – MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL Input voltage High-level output voltage Low-level output voltage IOH High-level output current IOL Low-level output current II Input current IDD Dynamic current, see CI CO (1) 4 TEST CONDITIONS MIN TYP (1) MAX UNIT –1.2 V VDD = 3 V, II = –18 mA VDD = min to max, IOH = –1 mA VDD – 0.3 VDD = 2.3 V, IOH = –8 mA 1.78 VDD = 3 V, IOH = –24 mA 1.90 VDD = 3 V, IOH = –12 mA 2.30 VDD = 2.3 V, IOL = 8 mA 0.51 VDD = min to max, IOL = 1 mA 0.20 VDD = 3 V, IOL = 24 mA 0.84 VDD = 3 V, IOL = 12 mA VDD = 3 V, VO = 1 V VDD = 3.3 V, VO = 1.65 V VDD = 3 V, VO = 2 V VDD = 3.3 V, VO = 1.65 V V V 0.60 –45 mA –55 54 mA 70 VI = VO or VDD ±5 μA f = 67 MHz, VDD = 2.7 V 28 f = 67 MHz, VDD = 3.6 V 37 Input capacitance VDD = 3.3 V, VI = 0 V or VDD 3 pF Output capacitance VDD = 3.3 V, VI = 0 V or VDD 3.2 pF mA All typical values are with respect to nominal VDD and TA = 25°C. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCV304-EP CDCV304-EP www.ti.com SCAS927A – MARCH 2012 SWITCHING CHARACTERISTICS VDD = 2.5 V ± 10%, CL= 10 pF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 2 2.9 4.5 2 3 4.5 UNIT tPLH Low-to-high propagation delay tPHL High-to-low propagation delay tsk(o) Output skew (2) 50 150 tr Output rise slew rate (3) 1 2.2 4 V/ns tf Output fall slew rate (3) 1 2.2 4 V/ns MIN TYP (1) MAX UNIT 1.8 2.4 3.8 1.8 2.5 3.8 50 100 (1) (2) (3) See Figure 1 and Figure 2 See Figure 3 ns ps All typical values are with respect to nominal VDD. The tsk(o) specification is only valid for equal loading of all outputs and TA = -40°C to 85°C. This symbol is according to PCI-X terminology. SWITCHING CHARACTERISTICS VDD = 3.3 V ± 10%, CL= 10 pF (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH Low-to-high propagation delay tPHL High-to-low propagation delay tsk(o) Output skew (2) tjitter Additive phase jitter from input to output 1Y0 tsk(p) Pulse skew tsk(pr) Process skew tsk(pp) Part-to-part skew Clock high time, see Figure 4 tlow Clock low time, see Figure 4 tr Output rise slew rate (3) (1) (2) (3) Output fall slew rate 12 kHz to 5 MHz, fout = 30.72 MHz 63 12 kHz to 20 MHz, fout = 125 MHz 56 VIH = VDD, VIL = 0 V thigh tf See Figure 1 and Figure 2 66 MHz 140 MHz 6 3 (3) 180 ps 0.2 ns 0.25 ns ns 2.2 140 MHz ps fs rms 6 66 MHz ns ns 1 2.7 4 V/ns 1 2.7 4 V/ns All typical values are with respect to nominal VDD. The tsk(o) specification is only valid for equal loading of all outputs and and TA = -40°C to 85°C. This symbol is according to PCI-X terminology. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCV304-EP 5 CDCV304-EP SCAS927A – MARCH 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION VDD 140 Ω Yn 10 pF 140 Ω Figure 1. Test Load Circuit VDD 50% VDD CLKIN 0V tPLH tPHL 0.6 VDD 0.6 VDD 50% VDD 50% VDD 0.2 VDD 1Y0 − 1Y3 VOH 0.2 VDD tr VOL tf Figure 2. Voltage Waveforms Propagation Delay (tpd) Measurements 50% VDD Any Y 50% VDD Any Y tsk(0) Figure 3. Output Skew tcyc PARAMETER VIH(Min) VIL(Max) Vtest VALUE 0.5 VDD thigh UNIT V 0.35 VDD V VIH(Min) 0.4 VDD V Vtest 0.6 VDD VIL(Max) tlow 0.2 VDD 0.4 VDD Peak to Peak (Minimum) A. All parameters in Figure 4 are according to PCI-X 1.0 specifications. Figure 4. Clock Waveform 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCV304-EP CDCV304-EP www.ti.com SCAS927A – MARCH 2012 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT VOH − High-Level Output Voltage − V 3.5 3.0 VDD = 3.3 V TA = 25°C 2.5 2.0 1.5 1.0 0.5 0.0 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 IOH − High-Level Output Current − mA Figure 5. LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT VOL − Low-Level Output Voltage − V 3.5 3.0 VDD = 3.3 V TA = 25°C 2.5 2.0 1.5 1.0 0.5 0.0 −20 0 20 40 60 80 100 120 IOL − Low-Level Output Current − mA Figure 6. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCV304-EP 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CDCV304TPWREP ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 C304T V62/12618-01XE ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 C304T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of