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CDCVF2310
SCAS666D – JUNE 2001 – REVISED OCTOBER 2015
CDCVF2310 2.5-V to 3.3-V High-Performance Clock Buffer
1 Features
3 Description
•
•
•
•
•
•
The CDCVF2310 device is a high-performance, lowskew clock buffer that operates up to 200 MHz. Two
banks of five outputs each provide low-skew copies
of CLK. After power up, the default state of the
outputs is low regardless of the state of the control
pins. For normal operation, the outputs of bank
1Y[0:4] or 2Y[0:4] can be placed in a low state when
the control pins (1G or 2G, respectively) are held low
and a negative clock edge is detected on the CLK
input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be
switched into the buffer mode when the control pins
(1G and 2G) are held high and a negative clock edge
is detected on the CLK input. The device operates in
a 2.5-V and 3.3-V environment. The built-in output
enable glitch suppression ensures a synchronized
output enable sequence to distribute full period clock
signals.
1
•
•
•
•
High-Performance 1:10 Clock Driver
Operates up to 200 MHz at VDD 3.3 V
Pin-to-Pin Skew < 100 ps at VDD 3.3 V
VDD Range: 2.3 V to 3.6 V
Operating Temperature Range –40°C to 105°C
Supports 105ºC Ambient Temperature (see
Thermal Considerations)
Output Enable Glitch Suppression
Distributes One Clock Input to Two Banks of Five
Outputs
25-Ω On-Chip Series Damping Resistors
Packaged in 24-Pin TSSOP
2 Applications
•
The CDCVF2310 is characterized for operation from
–40°C to 85°C.
General-Purpose Applications
Device Information
PART NUMBER
CDCVF2310
PACKAGE
TSSOP (24)
(1)
BODY SIZE (NOM)
4.40 mm × 7.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
VDD VDD VDD VDD VDD VDD
1G
Logic
25 Ω
5
25 Ω
5
1Y(4...0)
CLK
2G
2Y(4...0)
Logic
CDCVF2310
GND GND GND GND GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCVF2310
SCAS666D – JUNE 2001 – REVISED OCTOBER 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
3
4
4
4
4
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ...............................................
Jitter Characteristics..................................................
Switching Characteristics .........................................
Switching Characteristics ..........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
11.3 Thermal Considerations ........................................ 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (January 2008) to Revision D
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
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5 Pin Configuration and Functions
PW Package
24-Pin TSSOP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
GND
VDD
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VDD
1G
2Y4
24
23
22
21
20
19
18
17
16
15
14
13
CLK
VDD
VDD
2Y0
2Y1
GND
GND
2Y2
2Y3
VDD
VDD
2G
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1G
11
I
Output enable control for 1Y[0:4] outputs. This output enable is active-high, meaning the
1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
2G
13
I
Output enable control for 2Y[0:4] outputs. This output enable is active-high, meaning the
2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
1Y[0:4]
3, 4, 5, 8, 9
O
Buffered output clocks
2Y[0:4]
21, 20, 17, 16, 12
O
Buffered output clocks
Input reference frequency
CLK
24
I
GND
1, 6, 7, 18, 19
—
Ground
VDD
2, 10, 14, 15, 22,
23
—
DC power supply, 2.3 V – 3.6 V
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VDD
VI
(2) (3)
VO (2)
(3)
MIN
MAX
UNIT
Supply voltage
–0.5
4.6
V
Input voltage
–0.5
VDD + 0.5
V
Output voltage
–0.5
VDD + 0.5
V
IIK
Input clamp current VI < 0 or VI> VDD
±50
mA
IOK
Output clamp
current
VO < 0 or VO > VDD
±50
mA
IO
Continuous total
output current
VO = 0 to VDD
±50
mA
TJ
Maximum junction temperature
125
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 4.6 V maximum.
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6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
UNIT
2000
(2)
V
1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
(1)
See
VDD
Supply voltage
VIL
Low-level input voltage
VIH
High-level input voltage
VI
Input voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
MIN
NOM
2.3
2.5
3.3
MAX UNIT
VDD = 3 V to 3.6 V
0.8
VDD = 2.3 V to 2.7 V
0.7
VDD = 3 V to 3.6 V
V
3.6
V
2
VDD = 2.3 V to 2.7 V
V
1.7
0
VDD
VDD = 3 V to 3.6 V
V
12
VDD = 2.3 V to 2.7 V
mA
6
VDD = 3 V to 3.6 V
12
VDD = 2.3 V to 2.7 V
mA
6
–40
85
°C
Unused inputs must be held high or low to prevent them from floating.
6.4 Thermal Information
CDCVF2310
THERMAL METRIC
(1)
PW (TSSOP)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
91.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31.2
°C/W
RθJB
Junction-to-board thermal resistance
46.4
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
45.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
UNIT
VIK
Input voltage
VDD = 3 V
II
Input current
VI = 0 V or VDD
IDD
Static device current
CLK = 0 V or VDD ,
IO = 0 mA
-40°C to 85°C
CI
Input capacitance
VDD = 2.3 V to 3.6 V
VI = 0 V or VDD
2.5
pF
CO
Output capacitance
VDD = 2.3 V to 3.6 V
VI = 0 V or VDD
2.8
pF
(1)
4
II = –18 mA
MAX
≤105°C
–1.2
V
±5
μA
80
μA
100
μA
All typical values are at respective nominal VDD.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
VDD = 3.3 V ±0.3 V
VDD = min to max
VOH
High-level output voltage
VDD = 3 V
VDD = min to max
VOL
IOH
IOL
Low-level output voltage
High-level output current
Low-level output current
VDD = 3 V
IOH = –100 μA
VDD – 0.2
IOH = –12 mA
2.1
IOH = –6 mA
2.4
V
IOL = –100 μA
0.2
IOL = 12 mA
0.8
IOL = 6 mA
0.55
VDD = 3 V
VO = 1 V
VDD = 3.3 V
VO = 1.65 V
VDD = 3.6 V
VO = 3.135 V
VDD = 3 V
VO = 1.95 V
VDD = 3.3 V
VO = 1.65 V
VDD = 3.6 V
VO = 0.4 V
VDD = min to max
IOH = –100 μA
VDD = 2.3 V
IOH = –6 mA
VDD = min to max
IOL = 100 μA
VDD = 2.3 V
IOL = 6 mA
VDD = 2.3 V
VO = 1 V
VDD = 2.5 V
VO = 1.25 V
VDD = 2.7 V
VO = 2.375 V
VDD = 2.3 V
VO = 1.2 V
VDD = 2.5 V
VO = 1.25 V
VDD = 2.7 V
VO = 0.3 V
V
–28
–36
mA
–14
28
36
mA
14
VDD = 2.5 V ±0.2 V
VOH
High-level output voltage
VOL
Low-level output voltage
IOH
High-level output current
IOL
Low-level output current
VDD – 0.2
V
1.8
0.2
V
0.55
–17
–25
mA
–10
17
25
mA
10
6.6 Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature
fclk
Clock frequency
MIN
MAX
VDD = 3 V to 3.6 V
0
200
VDD = 2.3 V to 2.7 V
0
170
UNIT
MHz
6.7 Jitter Characteristics
Characterized using CDCVF2310 Performance EVM when VDD= 3.3 V. Outputs not under test are terminated to 50 Ω.
PARAMETER
tjitter
TEST CONDITIONS
Additive phase jitter from input to output 1Y0
TYP
12 kHz to 5 MHz, fout = 30.72 MHz
52
12 kHz to 20 MHz, fout = 125 MHz
45
UNIT
fs rms
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6.8 Switching Characteristics
VDD= 3.3V ±0.3V (see Figure 2) and over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
tPLH
CLK to Yn
tPHL
(1)
TEST CONDITIONS
MIN
MAX
f = 0 MHz to 200 MHz
For circuit load, see Figure 2.
1.3
2.8
ns
100
ps
250
ps
tsk(o)
Output skew (Ym to Yn)
tsk(p)
Pulse skew (see Figure 5)
tsk(pp)
Part-to-part skew
tr
Rise time (see Figure 3)
VO = 0.4 V to 2 V
0.7
2
V/ns
tf
Fall time (see Figure 3)
VO = 2 V to 0.4 V
0.7
2
V/ns
tsu(en)
Enable setup time, G_high before CLK ↓
0.1
ns
tsu(dis)
Disable setup time, G_low before CLK ↓
0.1
ns
th(en)
Enable hold time, G_high after CLK ↓
0.4
ns
th(dis)
Disable hold time, G_low after CLK ↓
0.4
ns
(1)
(see Figure 4)
UNIT
500
ps
The tsk(o) specification is only valid for equal loading of all outputs.
6.9 Switching Characteristics
VDD= 2.5V ±0.2V (see Figure 2) and over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
tPLH
CLK to Yn
tPHL
(1)
TEST CONDITIONS
MIN
MAX
f = 0 MHz to 170 MHz
For circuit load, see Figure 2.
1.5
3.5
ns
tsk(o)
Output skew (Ym to Yn)
170
ps
tsk(p)
Pulse skew (see Figure 5)
400
ps
tsk(pp)
Part-to-part skew
600
ps
tr
Rise time (see Figure 3)
VO = 0.4 V to 1.7 V
0.5
1.4
V/ns
tf
Fall time (see Figure 3)
VO = 1.7 V to 0.4 V
0.5
1.4
V/ns
tsu(en)
Enable setup time, G_high before CLK ↓
0.1
ns
tsu(dis)
Disable setup time, G_low before CLK ↓
0.1
ns
th(en)
Enable hold time, G_high after CLK ↓
0.4
ns
th(dis)
Disable hold time, G_low after CLK ↓
0.4
ns
(1)
6
(see Figure 4 )
UNIT
The tsk(o) specification is only valid for equal loading of all outputs.
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6.10 Typical Characteristics
180
ICC 3.3V 25°C
ICC 2.5V 25°C
ICC Supply Current [mA]
160
140
120
100
80
60
40
20
0
20
40
60
80
100
120
140
160
180
200
Frequency [MHz]
Figure 1. Supply Current vs Frequency
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7 Parameter Measurement Information
From Output
Under Test
CL = 25 pF on Y n
500 Ω
A.
CL includes probe and jig capacitance.
B.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 200 MHz, ZO = 50 Ω,
tr < 1.2 ns, tf < 1.2 ns.
Figure 2. Test Load Circuit
VDD
50% VDD
0V
CLK
t PLH
t PHL
1.7 V or 2 V
Yn
0.4 V
0.4 V
tr
VOH
50% VDD
VOL
tf
Figure 3. Voltage Waveforms Propagation Delay Times
VDD
CLK
0V
VOH
50% VDD
Any Y
VOL
VOH
50% VDD
Any Y
VOL
t sk(o)
t sk(o)
Figure 4. Output Skew
VDD
50% VDD
CLK
0V
t PLH
t PHL
VOH
Yn
50% VDD
VOL
NOTE: tsk(p) = | tPLH – tPHL |
Figure 5. Pulse Skew
8
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8 Detailed Description
8.1 Overview
The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five
outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless
of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a
low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on
the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins
(1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable
sequence to distribute full period clock signals.
8.2 Functional Block Diagram
3
1Y0
25 Ω
4
1Y1
25 Ω
5
1Y2
25 Ω
8
1Y3
25 Ω
9
1Y4
25 Ω
1G
2G
11
Logic Control
13
Logic Control
21
CLK
24
2Y0
25 Ω
20
25 Ω
17
25 Ω
16
25 Ω
12
25 Ω
2Y1
2Y2
2Y3
2Y4
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8.3 Feature Description
8.3.1 Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the
clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative
edge triggered by the input clock) (see Figure 6).
The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for
predictable operation.
CLK
Gn
Yn
tsu(en)
th(en)
a) Enable Mode
CLK
Gn
Yn
tsu(dis)
th(dis)
b) Disable Mode
Figure 6. Enable and Disable Mode Relative to CLK↓
10
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8.4 Device Functional Modes
Table 1 lists the functional modes for the CDCVF2310.
Table 1. Function Table
INPUT
(1)
OUTPUT
1G
2G
CLK
1Y[0:4]
2Y[0:4]
L
L
↓
L
L
(1)
H
L
↓
CLK
L
H
↓
L
CLK (1)
H
H
↓
CLK (1)
CLK (1)
L
After detecting one negative edge on the CLK input, the output
follows the input CLK if the control pin is held high.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDCVF2310 is a LVCMOS buffer solution that can operate up to 200 MHz. Low output skew as well as the
ability for glitchless output enable and disable is featured to simultaneously enable or disable buffered clock
outputs as necessary in the application.
9.2 Typical Application
100 MHZ
LVCMOS Oscillator
CLKIN VDD
50 W Trace
Y0
CMOS
CPU Clock
Y1
CMOS
FPGA Clock
100 W
1G
50 W Trace
From CPU
GND
PLL
Reference
Yn
100 W
Figure 7. Example System Configuration
9.2.1 Design Requirements
The CDCVF2310 shown in Figure 7 is configured to fan out a 100-MHz signal from a local LVCMOS oscillator.
The CPU is configured to control the output state through 1G.
The configuration example is driving three LVCMOS receivers in a backplane application with the following
properties:
• The CPU clock can accept a full swing DC-coupled LVCMOS signal. A series resistor is placed near the
CDCVF2310 to closely match the characteristic impedance of the trace to minimize reflections.
• The FPGA clock is similarly DC-coupled with an appropriate series resistor placed near the CDCVF2310.
• The PLL in this example can accept a lower amplitude signal, so a Thevenin's equivalent termination is used.
The PLL receiver features internal biasing, so AC-coupling can be used when common-mode voltage is
mismatched.
9.2.2 Detailed Design Procedure
Refer to Electrical Characteristics table to determine the appropriate series resistance needed for matching the
output impedance of the CDCVF2310 to that of the characteristic impedance of the transmission line.
12
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Typical Application (continued)
9.2.3 Application Curves
Figure 8. CDCVF2310 Output Phase Noise 89.1 fs
(12 kHz to 20 MHz), Reference Phase Noise 76.9 fs, Output
Frequency 125 MHz
Figure 9. CDCVF2310 Output Phase Noise 169.6 fs
(12kHz to 5MHz), Reference Phase Noise 161.5 fs,
Frequency 30.72 MHz
The low-additive jitter of the CDCVF2310 can be seen in the previous application plots. The low-noise, 125-MHz
input source drives the CDCVF2310, resulting in 45-fs RMS additive jitter when integrated from 12 kHz to 20
MHz for this configuration. The low-noise 30.72-MHz input source drives the CDCVF2310, resulting in 52-fs RMS
additive jitter when integrated from 12 kHz to 5 MHz for this configuration.
CLK
GN
YN
Figure 10. CDCVF2310 Configured as Gate Function for Output Clock
The CDCVF2310 can be configured to generate a gated clock using the GN Please refer to Output Enable Glitch
Suppression Circuit for required timings.
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10 Power Supply Recommendations
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter or phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guards the power supply system
against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by
the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they
must be placed very close to the power-supply terminals and laid out with short loops to minimize inductance. TI
recommends adding as many high-frequency (for example, 0.1 µF) bypass capacitors, as there are supply
terminals in the package. TI recommends, but does not require, inserting a ferrite bead between the board power
supply and the chip power supply that isolates the high-frequency switching noises generated by the clock buffer;
these beads prevent the switching noise from leaking into the board supply. It is imperative to choose an
appropriate ferrite bead with very low DC resistance to provide adequate isolation between the board supply and
the chip supply, as well as to maintain a voltage at the supply terminals that is greater than the minimum voltage
required for proper operation.
Figure 12 shows this recommended power supply decoupling method.
Board
Supply
VCC
Chip
Supply
Ferrite Bead
C
10 µF
C
1 µF
C
0.1 µF
Figure 11. Power Supply Decoupling
14
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11 Layout
11.1 Layout Guidelines
Figure 12 shows a conceptual layout detailing recommended placement of power supply bypass capacitors. For
component side mounting, use 0402 body size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low-impedance connection to the ground plane.
11.2 Layout Example
Ground bypass capacitor with low impedance
connection to ground plane
0402 or smaller body size capacitors are
recommended
Place bypass power supply capacitors as short
as possible to device pin
Figure 12. PCB Conceptual Layout
11.3 Thermal Considerations
CDCVF2310 supports high ambient temperature up to 105°C. The system designer needs to ensure that the
maximum junction temperature is not exceeded. Following Equation 1 can be used to calculate the junction
temperature based on the measured case temperature. The case temperature is defined as the hottest
temperature on the top of the device. The case temperature measurement can be performed with (in order of
accuracy) an IR camera, a fluor-optic probe, a thermocouple, or IR gun with a maximum field view of 4-mm
diameter just to name a few techniques. Further information can be found at SPRA953 and SLUA566
Tjunction = Tcase + (ψtj x Power)
(1)
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Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: CDCVF2310
15
CDCVF2310
SCAS666D – JUNE 2001 – REVISED OCTOBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Using Thermal Calculation Tools for Analog Components, SLUA566
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: CDCVF2310
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCVF2310PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV2310
CDCVF2310PWG4
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV2310
CDCVF2310PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV2310
CDCVF2310PWRG4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV2310
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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