Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
SN74LVTH16373-EP
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
SN74LVTH16373-EP 3.3-V ABT 16-Bit Transparent D-Type Latch With Tri-State Outputs
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controlled Baseline
– One Assembly/Test Site, One Fabrication Site
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Member of the Texas Instruments Widebus™
Family
State-of-the-Art Advanced BiCMOS Technology
(ABT) Design for 3.3-V Operation and Low StaticPower Dissipation
Supports Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V VCC)
Supports Unregulated Battery Operation Down to
2.7 V
Typical VOLP (Output Ground Bounce) < 0.8 V at
VCC = 3.3 V, TA = 25°C
Ioff and Power-Up Tri-State Support Hot Insertion
Bus Hold on Data Inputs Eliminates the Need for
External Pullup/Pulldown Resistors
Distributed VCC and GND Pins Minimize HighSpeed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 4000-V Human Body Model (A114-A)
– 200-V Machine Model (A115-A)
Data Buffer
Bus Driver
Display Driver
3 Description
The SN74LVTH16373 is a 16-bit transparent D-type
latch with tri-state outputs designed for low-voltage
(3.3 V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
This device is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers,
and working registers. This device can be used as
two 8-bit latches or one 16-bit latch. When the latchenable (LE) input is high, the Q outputs follow the
data (D) inputs. When LE is taken low, the Q outputs
are latched at the levels set up at the D inputs.
Device Information(2)
PART NUMBER
PACKAGE
SN74LVTH16373-EP
BODY SIZE (NOM)
TSSOP (48)
12.50 mm × 6.10 mm
SSOP (48)
15.88 mm × 7.49 mm
BGA MICROSTAR
JUNIOR (56)
4.50 mm × 7.00 mm
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature
cycle,
autoclave
or
unbiased
HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
(2) For all available packages, see the orderable addendum at
the end of the data sheet.
SN74LVTH16373-EP Single Channel Block Diagram
1OE
1LE
1
48
C1
1D1
47
2
1Q1
1D
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVTH16373-EP
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements (I Version) .............................. 7
Switching Characteristics (I Version) ........................ 7
Timing Requirements (M Version) ............................ 8
Switching Characteristics (M Version) ...................... 8
Typical Characteristics .......................................... 10
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2004) to Revision B
Page
•
Added Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics section, Detailed
Description section, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...... 1
•
Corrected table notes for Absolute Maximum Ratings table .................................................................................................. 4
•
Added new device temperature range to Recommended Operating Conditions table .......................................................... 5
•
Added new device specifications in Timing Requirements (M Version) and Switching Characteristics (M Version) tables.. 8
•
Added Figure 1 to Specifications section ............................................................................................................................... 9
2
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
SN74LVTH16373-EP
www.ti.com
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
5 Pin Configuration and Functions
DGG or DL Package
48-Pin TSSOP or SSOP
Top View
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
GQL Package
56-Pin BGA MICROSTAR JUNIOR
Top View
1
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
Table 1. Pin Assignments (1)
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
1LE
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
VCC
VCC
1D3
1D4
D
1Q6
1Q5
GND
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
VCC
VCC
2D6
2D5
J
2Q7
2Q8
GND
GND
2D8
2D7
K
2OE
NC
NC
NC
NC
2LE
(1)
NC − No internal connection.
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
Submit Documentation Feedback
3
SN74LVTH16373-EP
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
www.ti.com
Pin Functions
PIN
NAME
1Dn (1)
I/O
NO.
DESCRIPTION
37, 38, 49, 41, 43, 44, 46, 47
I
Data input pins
48
I
Latch enable pin to control 1Qn output states
1LE
1OE
1
I
Active low enable pin for 1Qn pins
1Qn (1)
2, 3, 5, 6, 8, 9, 11, 12
O
Output pins
2Dn (1)
26, 27, 29, 30, 32, 33, 35, 36
I
Data input pins
25
I
Latch enable pin to control 2Qn output states
2LE
2Qn
(1)
13, 14, 16, 17, 19, 20, 22, 23
O
Output pins
2OE
24
I
Active low enable pin for 2Qn pins
GND
4, 10, 15, 21, 28, 34, 39, 45
—
VCC
7, 18, 31, 42
I
(1)
Ground
Power supply input for internal circuits
"n" denotes numbering (1 to 8) for data input and output pins.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
4.6
V
VI
Input voltage (2)
–0.5
7
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
–0.5
(2)
VO
Voltage applied to any output in the high state
VCC + 0.5 V
V
IO
Current into any output in the low state
128
mA
IO
Current into any output in the high state (3)
64
mA
IIK
Input clamp current (VI < 0)
–50
IOK
Output clamp current (VO < 0)
–50
Tstg
Storage temperature
–65
(1)
(2)
(3)
mA
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This current flows only when the output is in the high state and VO > VCC.
6.2 ESD Ratings
V(ESD)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per A114-A
±4000
V
Charged device model (CDM), per JEDEC specification JESD22-C101 (1)
±3000
V
200
V
Machine model (MM), per A115-A
(1)
4
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
SN74LVTH16373-EP
www.ti.com
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
2.7
3.6
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
V
VI
Input voltage
5.5
V
IOH
High-level output current
–32
mA
IOL
Low-level output current
64
mA
Δt/Δv
Input transition rise or fall rate, outputs enabled
10
ns/V
Δt/ΔVCC
Power-up ramp rate
TA
(1)
V
2
V
200
Operating ambient temperature
µs/V
I version
–40
85
°C
M version
–55
125
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LVTH16373-EP
THERMAL METRIC
(1) (2)
DGG (TSSOP)
DL (SSOP)
GQL (BGA MICROSTAR
JUNIOR)
48 PINS
48 PINS
56 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
68.9
60.3
62.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
14.6
31
24.7
°C/W
RθJB
Junction-to-board thermal resistance
35.8
32.1
28.9
°C/W
ψJT
Junction-to-top characterization parameter
2.4
9.3
0.9
°C/W
ψJB
Junction-to-board characterization parameter
35.5
31.8
28
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
Submit Documentation Feedback
5
SN74LVTH16373-EP
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
www.ti.com
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted); all typical values are at VCC = 3.3 V, TA = 25°C
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 2.7 V,
II = –18 mA
VCC = 2.7 V to 3.6 V,
IOH = –100 µA
VCC = 2.7 V,
IOH = –8 mA
VCC = 3 V,
IOH = –32 mA
VCC = 2.7 V
VOL
VCC = 3 V,
VCC = 0 or 3.6 V,
Control inputs VCC = 3.6 V,
II
Data inputs
Ioff
Data inputs
TYP
VCC = 3.6 V
–1.2
V
V
V
2
V
IOL = 100 µA
0.2
V
IOL = 24 mA
0.5
V
IOL = 16 mA
0.4
V
IOL = 32 mA
0.5
V
IOL = 64 mA
0.55
V
VI = 5.5 V
10
µA
VI = VCC or GND
±1
µA
1
µA
–5
µA
±100
µA
VI or VO = 0 to 4.5 V
VI = 0.8 V
75
VI = 2 V
VCC = 3.6 V (1),
VI = 0 to 3.6 V
IOZH
VCC = 3.6 V,
VO = 3 V
IOZL
VCC = 3.6 V,
VO = 0.5 V
IOZPU
IOZPD
µA
–75
µA
±650
µA
5
µA
–5
µA
VCC = 0 to 1.5 V, VO = 0.5 to 3 V, OE = don’t care
±100
µA
VCC = 1.5 V to 0, VO = 0.5 to 3 V, OE = don’t care
±100
µA
0.19
mA
Outputs high
VCC = 3.6 V, IO = 0, VI = VCC
or GND
ICC
UNIT
2.4
VI = 0
VCC = 3 V
MAX
VCC – 0.2
VI = VCC
VCC = 0,
II(hold)
MIN
Outputs low
Outputs disabled
5
mA
0.19
mA
0.2
mA
∆ICC (2)
VCC = 3 to 3.6 V, One input at VCC − 0.6 V, Other inputs
at VCC or GND
Ci
VI = 3 V or 0
3
pF
Co
VO = 3 V or 0
9
pF
(1)
(2)
6
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
SN74LVTH16373-EP
www.ti.com
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
6.6 Timing Requirements (I Version)
over recommended operating conditions (unless otherwise noted); TA = –40°C to 85°C
MIN
tw
Pulse duration, LE high
tsu
Setup time, data before LE↓
th
Hold time, data after LE↓
MAX
UNIT
VCC = 3.3 V ± 0.3 V
3
ns
VCC = 2.7 V
3
ns
VCC = 3.3 V ± 0.3 V
1
ns
0.6
ns
1
ns
1.1
ns
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
6.7 Switching Characteristics (I Version)
over recommended operating conditions (unless otherwise noted); TA = –40°C to 85°C; all typical values are at VCC = 3.3 V,
TA = 25°C
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
D
Q
D
LE
Q
tPHL
LE
Q
tPZH
tPZL
tPHZ
tPLZ
OE
OE
OE
OE
VCC = 3.3 V ± 0.3 V
MIN
TYP
MAX
1.5
2.7
3.8
ns
4.2
ns
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
Q
tPLH
TEST CONDITIONS
1.5
2.5
3.6
ns
4
ns
2.1
3
4.3
ns
4.8
ns
4
ns
4
ns
4.3
ns
5.1
ns
4.3
ns
4.7
ns
5
ns
5.4
ns
4.7
ns
4.8
ns
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
2.1
2.9
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
Q
1.5
2.8
1.5
2.8
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
Q
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
Q
2.4
3.5
2
3.2
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
Q
VCC = 2.7 V
tsk(o)
VCC = 3.3 V ± 0.3 V
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
UNIT
0.5
ns
Submit Documentation Feedback
7
SN74LVTH16373-EP
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
www.ti.com
6.8 Timing Requirements (M Version)
over recommended operating conditions (unless otherwise noted); TA = –55°C to 125°C
MIN
tw
Pulse duration, LE high
tsu
Setup time, data before LE↓
th
Hold time, data after LE↓
MAX
UNIT
VCC = 3.3 V ± 0.3 V
3
ns
VCC = 2.7 V
3
ns
1.6
ns
1
ns
VCC = 3.3 V ± 0.3 V
1.4
ns
VCC = 2.7 V
1.5
ns
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
6.9 Switching Characteristics (M Version)
over recommended operating conditions (unless otherwise noted); TA = –55°C to 125°C; all typical values are at VCC = 3.3 V,
TA = 25°C
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
D
Q
D
Q
tPLH
LE
Q
tPHL
LE
Q
tPZH
tPZL
tPHZ
tPLZ
OE
OE
OE
OE
tsk(o)
8
Q
Q
Q
Q
TEST CONDITIONS
VCC = 3.3 V ± 0.3 V
TYP
1.5
2.7
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
1.5
2.5
2.1
3
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
2.1
2.9
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
1.5
2.8
1.5
2.8
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
1.8
3.5
2
3.2
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
Submit Documentation Feedback
MIN
0.5
MAX
UNIT
5
ns
5.5
ns
4.8
ns
5.3
ns
5.4
ns
5.9
ns
4.9
ns
4.9
ns
7
ns
7.9
ns
6.2
ns
7.2
ns
7.2
ns
7.9
ns
5.2
ns
5.4
ns
ns
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
SN74LVTH16373-EP
www.ti.com
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
1M
Electromigration Failure Mode
Estimated Life (hours)
100k
10k
1k
100
80
90
100
110
120
Continuous Junction Temperature, TJ (qC)
130
140
150
D004
(1)
See data sheet for absolute maximum and minimum recommended operating conditions.
(2)
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3)
Enhanced plastic product disclaimer applies.
Figure 1. Derating Chart for SN74LVTH16373-EP
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
Submit Documentation Feedback
9
SN74LVTH16373-EP
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
www.ti.com
6.10 Typical Characteristics
4
0.45
3.5
0.4
3
0.35
0.3
VOL (V)
VOH (V)
2.5
2
1.5
0.25
VOL, VCC = 2.7 V @ 100 PA
VOL, VCC = 2.7 V @ 24 mA
VOL, VCC = 3 V @ 16 mA
VOL, VCC = 3 V @ 32 mA
VOL, VCC = 3 V @ 64 mA
0.2
0.15
1
VOH, VCC = 3.6 V @ -100 PA
VOH, VCC = 2.7 V @ -100 PA
VOH, VCC = 2.7 V @ -8 mA
VOH, VCC = 3 V @ -32 mA
0.5
0.1
0.05
0
0
-55
-40
-20
0
25
40
80
Junction Temperature (°C)
100
125
-55
-40
D001
Figure 2. VOH vs Temperature
10
Submit Documentation Feedback
-20
0
25
40
80
Junction Temperature (°C)
100
125
D002
Figure 3. VOL vs Temperature
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
SN74LVTH16373-EP
www.ti.com
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
7 Parameter Measurement Information
6V
500 Ω
From Output
Under Test
S1
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Open
500 Ω
2.7 V
1.5 V
Timing Input
LOAD CIRCUIT
0V
tw
tsu
2.7 V
Input
1.5 V
1.5 V
th
2.7 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
Output
1.5 V
VOL
tPHL
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPLZ
tPZL
3V
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLH
1.5 V
2.7 V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf ≤ 2.5 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
Figure 4. Load Circuit and Voltage Waveforms
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
Submit Documentation Feedback
11
SN74LVTH16373-EP
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
www.ti.com
8 Detailed Description
8.1 Overview
The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3-V)
VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. This device is
particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
This device can be used as two 8-bit latches or one 16-bit latch. When the latchenable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D
inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high impedance state and the increased drive provide the capability to drive bus lines
without interface or pullup components. OE does not affect internal operations of the latch. Old data can be
retained or new data can be entered while the outputs are in the high-impedance state.
8.2 Functional Block Diagram
1OE
1LE
1
48
47
25
2LE
C1
1D1
24
2OE
C1
2
1Q1
1D
36
2D1
13
1D
2Q1
To Seven Other Channels
To Seven Other Channels
Figure 5. Logic Diagram (Positive Logic)
Figure 6. Logic Diagram (Positive Logic)
8.3 Feature Description
The SN74LVTH16373 included active bus-hold circuitry that holds unused or undriven inputs at a valid logic
state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. Additionally, it features
power up three state that will keep the outputs in high-impedance state during power up or power down when
VCC is between 0 and 1.5 V. This prevents driver conflict during power up.
To ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up tri-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
Table 2. Function Table (Each 8-Bit Section)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
8.4 Device Functional Modes
Device functions as tristatable 8 or 16-bit latch per function table defined in Table 2.
12
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
SN74LVTH16373-EP
www.ti.com
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The specially designed 3-V LVTH family uses the 0.8-µ BiCMOS process technology for bus-interface functions.
Like its 5-V ABT counterpart, LVHT provides up to 64 mA of drive, low propagation delays. The bus-hold feature
eliminates requirements for external pullup resistors and I/Os that can handle up to 7 V, which allows them to act
as 5-V/3-V translators.
9.2 Typical Application
3.3 V or 5 V
3.3 V
3.3 V or 5 V
VCC
.
.
.
uC or
System Logic
3.3-V CMOS or TTL
1OE
1LE
1D1
1D8
.
.
.
2OE
2LE
2D1
2D8
1Q1
.
.
.
uC,
System Logic,
or LEDs
3.3-V CMOS or TTL
1Q8
2Q1
.
.
.
2Q8
GND
Figure 7. Application Diagram
9.2.1 Design Requirements
The SN54LVTH16373 utilizes BiCMOS technology with high-drive currents. Care must be taken to avoid bus
contention that can disrupt system functionality and/or cause violation of absolute maximum ratings.
9.2.2 Detailed Design Procedure
•
•
Recommended input conditions
– Rise time and fall time specifications. See Δt/ΔV in Recommended Operating Conditions.
– Specified high and low levels. See VIH and VIL in Recommended Operating Conditions.
– Inputs are overvoltage tolerant, which allows them to go as high as 5.5 V independent of VCC.
Recommend output conditions
– Avoid buss contention.
– Do not exceed IOH and IOL current limits in Recommended Operating Conditions.
– Outputs that are being driven high may not be pulled above VCC by more they 0.5 V.
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
Submit Documentation Feedback
13
SN74LVTH16373-EP
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
www.ti.com
Typical Application (continued)
9.2.3 Application Curves
3.5
3
ICC (mA)
2.5
2
ICC @ Outputs High
ICC @ Outputs Low
ICC @ Outputs Disabled
1.5
1
0.5
0
-55
-40
-20
0
25
40
80
Junction Temperature (°C)
100
125
D003
Figure 8. ICC vs Temperature
14
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
SN74LVTH16373-EP
www.ti.com
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1
μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible
for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 9 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 9. Layout Diagram
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
Submit Documentation Feedback
15
SN74LVTH16373-EP
SCBS778B – NOVEMBER 2003 – REVISED JUNE 2016
www.ti.com
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
Widebus, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVTH16373-EP
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CLVTH16373IDGGREP
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH16373EP
CLVTH16373IDLREP
ACTIVE
SSOP
DL
48
1000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH16373EP
V62/04712-01XE
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH16373EP
V62/04712-01YE
ACTIVE
SSOP
DL
48
1000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH16373EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
