CSD17322Q5A

CSD17322Q5A SLPS330 – JUNE 2011 www.ti.com 30V, N-Channel NexFET™ Power MOSFETs Check for Samples: CSD17322Q5A FEATURES 1 • • • • • • • • 2 PRODUCT SUMMARY Optimized for 5V Gate Drive Ultralow Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package Notebook Point of Load Point-of-Load Synchronous Buck in Networking, Telecom and Computing Systems DESCRIPTION The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications, and optimized for 5V gate drive applications. Figure 1. Top View S 1 8 D S 2 7 D S 3 G 4 6 30 V Qg Gate Charge Total (4.5V) 3.6 nC Qgd Gate Charge Gate to Drain 1.1 RDS(on) Drain to Source On Resistance VGS(th) Threshold Voltage nC VGS = 4.5V 10 mΩ VGS = 8V 7.3 mΩ 1.6 V Device Package Media CSD17322Q5A SON 5-mm × 6-mm Plastic Package 13-Inch Reel Qty Ship 2500 Tape and Reel ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated VALUE UNIT VDS Drain to Source Voltage 30 V VGS Gate to Source Voltage +10 / –10 V Continuous Drain Current, TC = 25°C 87 A Continuous Drain Current(1) 16 A IDM Pulsed Drain Current, TA = 25°C(2) 104 A PD Power Dissipation(1) 3 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 33A, L = 0.1mH, RG = 25Ω 54 mJ ID (1) Typical RθJA = 41°C/W on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB. (2) Pulse duration ≤300μs, duty cycle ≤2% D D 5 Drain to Source Voltage ORDERING INFORMATION APPLICATIONS • • VDS D P0093-01 RDS(on) vs VGS GATE CHARGE 30 10 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance - mΩ ID = 14A 25 20 15 10 5 0 TC = 25°C TC = 125ºC 0 1 2 3 ID = 14A VDD = 15V 9 8 7 6 5 4 3 2 1 4 5 6 7 VGS - Gate-to- Source Voltage - V 8 9 10 0 0 1 2 3 4 5 6 7 8 Qg - Gate Charge - nC 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated CSD17322Q5A SLPS330 – JUNE 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250μA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 24V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +10 / –10V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250μA RDS(on) Drain to Source On Resistance gfs Transconductance 30 1.1 V 1 μA 100 nA 1.6 2.0 V VGS = 4.5V, ID = 14A 10 12.4 mΩ VGS = 8V, ID = 14A 7.3 8.8 mΩ VDS = 15V, ID = 14A 37 S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Series Gate Resistance 4.7 Qg Gate Charge Total (4.5V) 3.6 Qgd Gate Charge Gate to Drain 1.1 nC Qgs Gate Charge Gate to Source 1.6 nC Qg(th) Gate Charge at Vth 0.9 nC Qoss Output Charge 8.6 nC td(on) Turn On Delay Time 6.7 ns tr Rise Time 12 ns td(off) Turn Off Delay Time 10.5 ns tf Fall Time 3.7 ns VGS = 0V, VDS = 15V, f = 1MHz VDS = 15V, ID = 14A VDS = 13V, VGS = 0V VDS = 15V, VGS = 4.5V, IDS = 14A, RG = 2Ω 580 695 pF 390 470 pF 35 44 pF Ω 4.3 nC Diode Characteristics VSD Diode Forward Voltage ISD = 14A, VGS = 0V 0.85 Qrr Reverse Recovery Charge 19.6 nC trr Reverse Recovery Time VDD= 13V, IF = 14A, di/dt = 300A/μs 1 V 17.8 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) MAX UNIT RθJC Thermal Resistance Junction to Case (1) PARAMETER 1.8 °C/W RθJA Thermal Resistance Junction to Ambient (1) (2) 51 °C/W (1) (2) 2 MIN TYP RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Copyright © 2011, Texas Instruments Incorporated CSD17322Q5A SLPS330 – JUNE 2011 www.ti.com GATE GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 51°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RθJA = 125°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) ZqJA - Normalized Thermal Impedance 10 1 0.5 0.3 0.1 Duty Cycle = t1/t2 0.1 0.05 P 0.02 0.01 0.01 t1 t2 Single Pulse Typical RqJA = 100°C/W (min Cu) TJ = P ´ ZqJA ´ RqJA 0.001 0.001 0.01 0.1 1 tp - Pulse Duration - s 10 100 1k G012 Figure 2. Transient Thermal Impedance Copyright © 2011, Texas Instruments Incorporated 3 CSD17322Q5A SLPS330 – JUNE 2011 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 50 40 30 20 10 0 VGS = 4.0V VGS = 4.5V VGS = 8.0V VDS = 5V 45 IDS - Drain-to-Source Current - A IDS - Drain-to-Source Current - A 50 40 35 30 T C = 125°C 25 T C = 25°C 20 15 T C = -55°C 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1 1.5 2 2.5 VGS - Gate-to-Source Voltage - V VDS - Drain-to-Source Voltage - V Figure 3. Saturation Characteristics TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.8 ID = 14A VDD = 15V VGS - Gate-to-Source Voltage (V) 9 f = 1MHz VGS = 0V 1.6 8 C - Capacitance - nF 1.4 7 6 5 4 3 1.2 Coss = Cds + Cgd 1 Ciss = Cgd + Cgs 0.8 0.6 0.4 2 Crss = Cgd 0.2 1 0 0 1 2 3 4 5 6 7 8 0 5 Qg - Gate Charge - nC 10 15 20 VDS - Drain-to-Source Voltage - V Figure 5. Gate Charge TEXT ADDED FOR SPACING G004 TEXT ADDED FOR SPACING ID = 14A ID = 250µA RDS(on) - On-State Resistance - mΩ VGS(th) - Threshold Voltage - V 30 30 1.4 1.2 1 0.8 0.6 0.4 0.2 25 20 15 10 5 0 -25 25 75 T C - Case Temperature - °C 125 175 Figure 7. Threshold Voltage vs. Temperature 4 25 Figure 6. Capacitance 1.6 0 -75 G002 Figure 4. Transfer Characteristics 10 0 3 G005 TC = 25°C TC = 125ºC 0 1 2 3 4 5 6 7 8 9 10 VGS - Gate-to- Source Voltage - V Figure 8. On-State Resistance vs. Gate-to-Source Voltage Copyright © 2011, Texas Instruments Incorporated CSD17322Q5A SLPS330 – JUNE 2011 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 ID = 14A VGS = 4.5V 1.4 ISD - Source-to-Drain Current - A Normalized On-State Resistance 1.6 1.2 1 0.8 0.6 0.4 0.2 -75 10 1 T C = 125°C 0.1 T C = 25°C 0.01 0.001 0.0001 -25 25 75 T C - Case Temperature - °C 125 0 175 0.2 Figure 9. Normalized On-State Resistance vs. Temperature TEXT ADDED FOR SPACING G008 TEXT ADDED FOR SPACING I(AV) - Peak Avalanche Current - A IDS - Drain-to-Source Current - A 1.2 1k 100 10 1ms 10ms 100ms 11110 1 Area Limited by RDS(on) 0.01 0.01 1 Figure 10. Typical Diode Forward Voltage 1k 0.1 0.4 0.6 0.8 VSD - Source-to-Drain Voltage - V G007 1s Single Pulse Typical R θJA = 100°C/W (min Cu) DC 0.1 1 10 VDS - Drain-to-Source Voltage - V 100 100 T C = 25°C 10 T C = 125°C 1 0.01 G009 Figure 11. Maximum Safe Operating Area 0.1 1 10 t(AV) - Time in Avalanche - ms 100 G010 Figure 12. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING IDS - Drain-to-Source Current - A 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 125 T C - Case Temperature - °C 150 175 G011 Figure 13. Maximum Drain Current vs. Temperature Copyright © 2011, Texas Instruments Incorporated 5 CSD17322Q5A SLPS330 – JUNE 2011 www.ti.com MECHANICAL DATA Q5A Package Dimensions L E2 H K 7 D2 3 4 b 4 5 5 6 3 6 e D1 7 2 2 8 8 1 1 q L1 Top View Bottom View Side View c A q E1 E Front View M0135-01 DIM 6 MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 e 1.17 1.27 1.37 H 0.41 0.56 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 θ 0° 12° Copyright © 2011, Texas Instruments Incorporated CSD17322Q5A SLPS330 – JUNE 2011 www.ti.com Figure 14. Recommended PCB Pattern DIM F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 F8 F4 F10 M0139-01 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket Copyright © 2011, Texas Instruments Incorporated 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD17322Q5A ACTIVE VSONP DQJ 8 2500 RoHS-Exempt & Green SN Level-1-260C-UNLIM -55 to 150 CSD17322 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of